3 -- DOCENTE: CÉSAR VÁZQUEZ CIANCA 4 -- DESCRIPCIÓN: IMPLEMENTACIÓN UART RX 5 ---------------------------------------------------------------------------------- 6 library IEEE; 7 use IEEE.STD_LOGIC_1164.ALL; 8 9 entity UART_RX is 10 Port ( IN_RX : in STD_LOGIC; 11 DATO : out STD_LOGIC_VECTOR (7 downto 0); 12 CLK : in STD_LOGIC); 13 end UART_RX; 14 15 architecture Behavioral of UART_RX is 16 SIGNAL BAUDIOS: INTEGER RANGE 0 TO 5200; 17 SIGNAL NBIT: INTEGER RANGE 0 TO 10; 18 SIGNAL RX_INICIO: STD_LOGIC:='0'; 19 SIGNAL IN_RX_ANT: STD_LOGIC; 20 SIGNAL DATO_BUFFER: STD_LOGIC_VECTOR(7 DOWNTO 0); 21 22 begin 23 24 -- LEER ESTADO DE RX 25 IN_RX_ANT <= IN_RX WHEN CLK'EVENT AND CLK='1'; 26 27 -- INICIAR LA COMUNICACIÓN 28 RX_INICIO <= '0' WHEN NBIT=10 ELSE 29 '1' WHEN (IN_RX_ANT = '1' AND IN_RX='0') AND CLK'EVENT AND CLK='1'; 30 31 BAUDIOS <= 0 WHEN RX_INICIO='0' OR BAUDIOS = 5200 ELSE 32 BAUDIOS + 1 WHEN CLK'EVENT AND CLK='1'; 33 34 NBIT <= 0 WHEN RX_INICIO = '0' ELSE 35 NBIT + 1 WHEN BAUDIOS = 5199 AND CLK'EVENT AND CLK='1'; 36 37 38 DATO_BUFFER(0) <= IN_RX WHEN NBIT = 1 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 39 DATO_BUFFER(1) <= IN_RX WHEN NBIT = 2 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 40 DATO_BUFFER(2) <= IN_RX WHEN NBIT = 3 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 41 DATO_BUFFER(3) <= IN_RX WHEN NBIT = 4 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 42 DATO_BUFFER(4) <= IN_RX WHEN NBIT = 5 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 43 DATO_BUFFER(5) <= IN_RX WHEN NBIT = 6 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 44 DATO_BUFFER(6) <= IN_RX WHEN NBIT = 7 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 45 DATO_BUFFER(7) <= IN_RX WHEN NBIT = 8 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 46 47 DATO <= DATO_BUFFER WHEN NBIT = 9 AND BAUDIOS = 2600 AND CLK'EVENT AND CLK='1'; 48 49 end Behavioral;
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