Hall Ticket No. | L] LI li | Question Paper Code: B1217 CMR COLLEGE OF ENGINEERING & TECHNOLOGY (AUTONOMOUS) M.Tech I Semester Regular Examinations Sept & Oct- 2015 System on Chip Architecture (Embedded Systems) 10.2015 ‘Time: 3 hours Max.Marks:60 ' PART-A Answer all FIVE questions (Compulsory) Each question carries FOUR marks. Sx4=20M 1. Explain the approach steps for SoC design? 2. How to minimize pipe line delays? © 3. Explain need of Vector Instructions? 4, Define contention time in inter connect architectures ? 5. How SoC design helps in Image compression? PART-B 4 Answer any FIVE questions. One question from each unit either A or B (Compulsory) Each question carries EIGHT Marks. Sx8-40M 6.A) Based on architecture, classify the processors, Which architecture is more ideal for Soc? Why? (OR) B) _ Explain components of the system and processor architectures? 7.A) Explain basic concepts in processor Micro Architecture? (OR) a B) Explain i) VLIW Processors ii) Superscalar Processors 8.A) Brief the Strategies for line replacement at miss time in Cache memory? (OR) B) Define Write Policies? Explain SOC Memory system with examples? 9.4) Explain overhead analysis and trade off analysis on reconfigurable parallelism? (OR) B) Explain SOC Standard Buses and effects of Bus transactions? 10.4) Explain AES algorithms with suitable example? 1 (OR) B) Explain SOC design approach with suitable application?