2416
6, DECEMBER 2017
A New DFT-Based Phasor Estimation Algorithm
Using High-Frequency Modulation
Babak Jafarpisheh, Student Member, IEEE, Seyed M. Madani
Abstract—This paper proposes a new fast algorithm to estimate
the fundamental phasor of fault current signals, based on discrete
Fourier transform (DFT). Since fault currents include decaying dc
component (ddc), DFT-based algorithms have inaccuracy in phasor
estimation. The proposed algorithm consists of four steps. First, a
new auxiliary signal is introduced based on a simple high-frequency
modulation of the fault current. Then, DFT of the fault current and
sample-summation of both fault current and auxiliary signal are
calculated, for each one-cycle-length data stream. Next, DFT esti-
mation error due to the ddc is calculated. Finally, by removing this
error, accurate fundamental phasor is obtained. This paper uses
an innovative and accurate formulation based on notations of sig-
nal processing literature. To validate the proposed algorithm, sev-
eral computer-simulated signals and an electromagnetic transient
program-generated signal are employed. The proposed algorithm
is compared with recent phasor estimation methods, using wide
variety of test signals. Standard indices of rise time, settling time,
and percentage overshoot are used for comparison. These compar-
isons show that the proposed algorithm has robust performance
in off-nominal frequency condition, and presence of harmonics,
noise and multiple ddc components. Moreover, it provides faster
convergence speed and lower computation burden.
Index Terms—Damping factor, decaying dc component, discrete
Fourier transform, high-frequency modulation, numerical relays,
phasor estimation.
I. INTRODUCTION
OMPUTER based protection has attracted many
C researches because of its applications in wide area moni-
toring, protection and control (WAMPAC). In this type of protec-
tion, accurate estimation of voltage and current phasors plays an
important role. Therefore, several researches investigate various
algorithms for phasor estimation. The presented algorithms for
this purpose are: discrete Fourier transform (DFT), least square
error (LSE), cosine filters, discrete wavelet transform (DWT),
Kalman filters and intelligent techniques such as artificial neural
Manuscript received June 23, 2016; revised September 16, 2016; accepted
November 4, 2016. Date of publication November 16, 2016; date of current
version October 16, 2017. Paper no. TPWRD-00781-2016.
B. Jafarpisheh is with the Department of Electrical Engineering, Faculty
of Engineering, University of Isfahan, Isfahan 81746-73441, Iran (e-mails:
b.jafarpisheh@eng.ui.ac.ir, babak_jafarpisheh@yahoo.com).
S. M. Madani is with the Department of Electrical Engineering, Faculty
of Engineering, University of Isfahan, Isfahan 81746-73441, Iran (e-mails:
m.madani@eng.ui.ac.ir, madani104@yahoo.com).
S. Mohammad Shahrtash is with the Department of Electrical Engineering,
Center of Excellence for Power System Automation and Operation, Iran Uni-
versity of Science and Technology, Tehran 16844, Iran (e-mail: shahrtash@
iust.ac.ir).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TPWRD.2016.2629762
0885-8977 © 2016 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications standards/publications/rights/index.html for more information.
IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 32, NO.
, Member, IEEE, and S. Mohammad Shahrtash
networks (ANNs) [1]–[8]. The DFT is widely used for phasor
estimation because of its simplicity, high accuracy and speed [9].
The DFT can filter out harmonics and estimate the magni-
tude and phase angle of a periodic signal [1]–[4]. However,
the presence of non-periodic decaying dc component (ddc)
in fault currents causes large error (up to 15%) in estimated
magnitude [10], [11].
Research has been performed in the open literature to reduce
the DFT phasor estimation error in presence of ddc [12], [13].
There are two main groups for this work:
In the first group, the ddc is first filtered out, and then the
DFT is applied on the remaining signal containing the funda-
mental and other harmonics to estimate the fundamental phasor
[10], [14]–[16]. Implementation of mimic filter is one of the con-
ventional solutions for filtering the ddc. However, this high-pass
filter amplifies harmonics and inter-harmonics, which causes os-
cillatory error in estimated magnitude [10]. In [14], a modified
notch filter is performed to filter out the ddc. References [15],
[16] introduce an auxiliary signal containing reduced ddc, based
on fault current. Then, the DFT is applied to the auxiliary sig-
nal to obtain its fundamental component. Finally, fundamental
current phasor is estimated based on fundamental phasor of
the auxiliary signal. The estimated magnitude of this method
severely oscillates, especially in case of small ddc time con-
stants.
The second group estimates the ddc, subtracts it from fault
current signal, and applies DFT to estimate the fundamental
phasor [17]–[29]. The value of ddc is estimated in [17]–[19] by
decomposing samples into odd and even strings and perform-
ing DFT on each of them. These methods suffer from heavy
computational burden. In [20], ddc parameters are obtained by
two partial sums. However, this algorithm cannot completely
filter out all of the harmonic components in fundamental phasor
estimation. In [21], the ddc value is estimated using compli-
cated equations, based on DFT of three consecutive strings of
the sample data. This method takes one cycle plus two ad-
ditional samples to estimate the fundamental phasor. Another
DFT-based method described in [22] suffers from heavy com-
putational burden. It requires computing DFT twice for each
string of data. References [23], [24] presented another DFT-
based method which takes one cycle plus two additional sam-
ples. A long duration method for phasor estimation that takes
one and half cycle is presented in [25]. In [26], ddc parameters
are estimated by integration from fault current signal. However,
due to linear approximation of ddc, it has poor performance for
small values of ddc time constant. In continuation of [26], other
JAFARPISHEH et al.: NEW DFT-BASED PHASOR ESTIMATION ALGORITHM USING HIGH-FREQUENCY MODULATION 2417

DFT-based methods are presented in [27]–[29] for estimation can be rewritten as shown in (2).
of fundamental and sub-synchronous components. Heavy ma-
Δ
trix and logarithmic computations are the main disadvantages i[n] = i(nΔt) = iddc [n] + iac [n]
of these methods.
where :
For most of the mentioned algorithms, the performance of
phasor estimation is acceptable either for small or large ddc iddc [n] = I0 e−n Δ t/τ
time constants. Outside of their specific range, their estimated
N /2−1
  
phasor has oscillatory error. 2πk
This paper presents an algorithm to suppress the ddc for wide iac [n] = |Ik | cos n + θk (2)
N
k =1
range of ddc time constant, avoiding heavy computations. An
innovative, accurate formulation is applied using notations of where N is the number of samples per cycle and Δt is the
signal processing literature [1], [2]. The proposed algorithm sampling interval. It is assumed that harmonic numbers higher
consists of four steps: (1) A new auxiliary signal is intro- than (N/2 − 1) are eliminated by a low-pass filter, to avoid the
duced which is easily generated from high-frequency modu- aliasing phenomenon.
lation of the fault current signal, (2) One-cycle-length strings According to (2), the fault current signal is divided into two
from both fault current and auxiliary signals are acquired. The terms. The first term, which is denoted by iddc [n], is the ddc
sample-summation of the both strings and the DFT of the fault value of fault current signal. The second periodic term, which is
current data stream are calculated, (3) The DFT error due to shown by iac [n], contains the fundamental and other harmonic
the ddc is calculated, (4) The calculated error is subtracted components.
from DFT estimation, which results in accurate fundamental The ddc is generated by any fault or disturbances in power
phasor. systems. It can also be generated by current transformers (CTs)
To validate the proposed algorithm, several computer- [17], [18]. The ddc time constant varies from 0.5 to 5 cycles,
simulated signals and an Electromagnetic Transient Program depends on the system configuration, fault location and fault
(EMTP)-generated signal are employed. The proposed algo- resistance [10]. Since ddc is non-periodic, its presence causes
rithm is compared with recent phasor estimation methods, us- significant error in DFT-based estimated-phasor.
ing wide variety of test signals including different values for The estimated phasor of the fundamental component (Iˆ1 ) by
ddc magnitude and time constant. These comparisons show DFT is:
that the proposed algorithm has robust performance in offnom-
N −1
inal frequency condition, and presence of harmonics, noise Δ 2  2π
Iˆ1 = Iˆ1 < 0 , N −1 > = i[n]e−j N n
and multiple ddc components in fault current signals. It also N n =0
provides faster speed of convergence and lower computation
burden. = I1 + ΔI1ddc< 0,N −1>
The rest of this paper is organized as follows. In Section II, where :
the proposed algorithm is completely described within three
subsections of: a brief review on DFT and ddc; presenting the I1 = |I1 | ej θ 1 (3)
proposed algorithm; and the flowchart of the proposed algo-
rithm. In Section III, the performance of the proposed algorithm where Iˆ1 is the fundamental phasor estimated by DFT using
for both computer-simulated and EMTP-generated signals is N-length string of data stream, in which 0 and N−1 denote
evaluated. Finally in Section IV, some concluding remarks are the first and last sample number of the string. I1 represents
discussed. the exact fundamental phasor, and ΔI1ddc denotes the error in
the estimated fundamental phasor caused by the ddc, which can
II. PROPOSED ALGORITHM be obtained as follows:
A. A Brief Review on DFT and ddc
E = e−Δ t/τ
Δ

Discrete Fourier transform (DFT) is a commonly used al-

Δ 2π
gorithm in numerical relays and phasor measurement units Δθ =
(PMUs), for phasor estimation of any periodic signal. The N
N −1
power system fault currents contain sinusoidal fundamental 2 
I0 e−n Δ t/τ .e−j n Δ θ
Δ
and harmonic components, and also a decaying dc component ΔI1ddc = ΔI1ddc< 0,N −1> =
N n =0
(ddc) [17]:
P
 N −1
2   −j Δ θ n 2 1 − EN
i(t) = I0 e−t/τ + |Ik | cos(kω 1 t + θk ), (1) = I0 Ee = I0 (4)
k =1
N n =0 N 1 − Ee−j Δ θ

where I0 and τ are the magnitude and time constant of the Equation (4) is obtained using geometric series. The damping
ddc, k is the harmonic number, P is the maximum harmonic factor E depends on the sampling interval Δt and ddc time
number, |Ik | and θk are the magnitude and phase angle of the constant τ . ΔΘ is the phase difference between two consecutive
k-th harmonic. The discretization form of the fault current signal samples and can be precalculated.
2418 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 32, NO. 6, DECEMBER 2017

B. Proposed Algorithm Equation (11) is simplified as:

⎡ ⎤
In this subsection, a four-step DFT-based algorithm is pro- N −1 N /2−1
 
posed, to estimate the fundamental current phasor. S̃y ac = (−1)n ⎣ Ik ej k n Δ θ ⎦
Step 1: A new auxiliary signal y[n] is introduced based on a n =0 k =1
simple high-frequency modulation of the fault current signal as
follows: where :
Ik = |Ik | ej θ k (12)
y[n] = (−1)n i[n] = (−1)n [iddc [n] + iac [n]]
Δ
(5)
Using rules of geometric series, (12) can be rewritten as:
In the frequency domain, the high-frequency modulation
N /2−1 N −1
shifts the fundamental and harmonic components. In other  
words, the auxiliary-signal harmonic-components can be ob- S̃y ac = Ik ( − 1)n ej k n Δ θ
k =1 n =0
tained by mirroring the fault current harmonic-components
N /2−1 N −1
around the mid-frequency (harmonic number of N/4).    n
Step 2: N-length sample-summation for both fault current and = Ik ( − 1)ej k Δ θ
auxiliary signals are calculated, which are denoted by Si and k =1 n =0
Sy , respectively. Si is defined as: N /2−1
 1 − ( − 1)N ej N k Δ θ
N −1 N −1 = Ik
Δ
  1 − [( − 1)ej k Δ θ ]
Si = Si < 0 , N −1 > = i[n] = [iddc [n] + iac [n]] (6) k =1

n =0 n =0 N /2−1
 1 − ( − 1)N ej 2π k
= Ik (13)
Since the ac part of the fault current iac [n] is periodic, its 1 + ej k Δ θ
k =1
sample-summation over one cycle is equal to zero:
⎡ ⎤ It is clear that ej 2π k = 1. Since N is an even number,
N
 −1 N
 −1 N/2−1   ( − 1)N = 1. Thus, (13) is rewritten as:
⎣ 2πk
iac [n] = |Ik | cos n + θk ⎦ = 0 (7)
N N /2−1

n =0 n =0 k =1 1−1
S̃y ac = Ik =0 (14)
1 + ej k Δ θ
So, iddc [n] is the only remaining term of the fault current k =1
sample-summation Si . So, high-frequency modulation of iddc [n] is the only remain-
N −1 N −1
ing term of auxiliary signal sample-summation Sy .
  1 − EN
Si = iddc [n] = I0 E n = I0 (8) N
 −1 N
 −1
n =0 n =0
1−E Sy = (−1)n iddc [n] = (−1)n I0 E n
n =0 n =0
Similarly, the sample-summation of auxiliary signal Sy is
N N
defined as: 1 − ( − 1) E 1 − EN
= I0 = I0 (15)
N −1 N −1 1 − ( − 1)E 1 + E
 
(−1)n i[n]
Δ
Sy = Sy < 0 , N −1 > = y[n] = As mentioned previously, Si denotes the summation of N
n =0 n =0 consecutive samples of fault current data stream. Actually, Si
N
 −1 acts as a low-pass filter for fault current. Since the auxiliary-
= ( − 1)n [iddc [n] + iac [n]] (9) signal harmonic-components are obtained by mirroring the fault
n =0 current harmonic-components around the mid-frequency, the
frequency response of Sy can also be obtained by mirroring
It will be proved that the second term in (9) which is called
the Si frequency response around the mid-frequency (harmonic
Sy ac is equal to zero:
number of N/4). Therefore, Sy acts as a high-pass filter. Figure 1
N
 −1 depicts normalized magnitude of the frequency responses for Si
Sy ac  (−1)n iac [n] = 0 (10) and Sy , for N = 16 and fundamental frequency of 60 Hz. Since
n =0 it is assumed that harmonic numbers higher than (N/2 − 1) are
eliminated by an anti-aliasing filter, the frequency responses are
To prove (10), the phasor representation of Sy ac is used:
depicted for maximum frequency of 420 Hz.
⎡ ⎤
N −1 N /2−1 Dividing (8) by (15), results in:
 
S̃y ac  (−1)n ⎣ |Ik | ej 2π k n /N ej θ k ⎦ Si 1 + E
n =0
= (16)
k =1 Sy 1−E
where : Finally, the damping factor is easily obtained as:
 
Si − Sy
Sy ac = Re S̃y ac (11) E= (17)
Si + Sy
JAFARPISHEH et al.: NEW DFT-BASED PHASOR ESTIMATION ALGORITHM USING HIGH-FREQUENCY MODULATION 2419

III. PERFORMANCE EVALUATION

In order to evaluate the performance of the proposed al-
gorithm, several computer-simulated signals and an EMTP-
generated signal are employed. The results are compared with
recent methods of [16], [17] and [28], which are denoted by
S-CharmDFT, Modified DFT and Prony-DFT, in the rest of this
paper. For all the signals, the number of samples per cycle,
fundamental frequency and sampling frequency are 16, 60 Hz
and 960 Hz, respectively. The input signals are pre-processed
by a second order Butterworth low-pass filter with cutoff fre-
quency of 420 Hz (to eliminate harmonic numbers higher than
N/2 − 1), to prevent aliasing errors.
Fig. 1. Normalized magnitude of the frequency responses for S i and S y .
In the following subsections, the performance of the proposed
algorithm is compared to the recent mentioned methods from
the viewpoints of convergence speed, dependency to ddc param-
eters, computation burden and robustness to: harmonics, noise,
multiple ddc components and offnominal frequency condition.

A. Test for Basic Signals

In this subsection, basic signals consisting ddc and funda-
mental component are introduced as follows [17]:

2π
i1 [n] = I0 e−n Δ t/τ − |I1 | cos n + θ1
N

= |I1 | cos (θF )e−n Δ t/τ − |I1 | cos(nΔθ + θ1 ) (21)

where ΘF is the fault inception angle. This basic signal is ap-

plied to the proposed and other mentioned algorithms. Since the
ddc time constant varies from 0.5 to 5 cycles [10], six differ-
ent values are used to cover different power system structures.
Therefore, eighteen different fault current signals are generated
by choosing the ddc time constant of: {5, 25, 50, 100, 150,
Fig. 2. Schematic diagram of the proposed algorithm.
200 ms}, and fault inception angle of: {0°, 45°, 90°}. At zero
fault inception angles, the ddc magnitude is maximum and it
is equal to that of the fundamental component. For ΘF = 45◦ ,
Step 3: The phasor estimation error due to the ddc (ΔI1ddc ) is the ddc magnitude is 0.707 (cos 45°) times |I1 |. In the same
calculated. To estimate ΔI1ddc in (4), the value of I0 (1 − E N ) way, at ΘF = 90◦ , the ddc magnitude is zero; thereby the fault
must be obtained using either (8) or (15): current signals do not contain ddc [17], [18], [29]. In this paper,
the magnitude and phase angle of the fundamental component
I0 (1 − E N ) = (1 − E)Si = (1 + E)Sy (18) are assumed to be 1.0 (p.u.) and 60°, respectively [24], for
computer-simulated signals.
Therefore, ΔI1ddc is obtained by substituting (18) into (4):
For each of the above eighteen signals, the magnitude and
2
N (1 − E)Si 2
(1 + E)Sy phase angle of the fundamental component are estimated by the
ΔI1ddc = −j Δ θ = N (19) proposed algorithm, S-CharmDFT, Modified DFT and Prony-
1 − Ee 1 − Ee−j Δ θ
DFT. Because of the large number of test signals, the estimated
in which, the damping factor E is calculated using (17). fundamental phasor is drawn only for the worst case, in which
Step 4: The phasor estimation error due to the ddc ΔI1ddc is the ddc time constant is 200 (ms) and fault inception angle is
subtracted from the estimated phasor, which results in accurate zero. The fault current and estimated phasors are depicted versus
fundamental phasor. time, in Figs. 3 and 4, respectively.
I1 = Iˆ1 − ΔI1ddc (20) To compare the performance of phasor estimation methods,
three standard indices are used [27]–[29]. (1) Rise time tR is
the time needed for a waveform to rise from 10% to 90% of its
C. Flowchart of the Proposed Algorithm
expected value. (2) Settling time tS is the time duration which
In this subsection, the flowchart of the proposed algorithm is the waveform enters and remains within the 5% error band of the
shown in Fig. 2. expected value. (3) Percentage Overshoot PO is the difference
2420 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 32, NO. 6, DECEMBER 2017

TABLE I
PERFORMANCE INDICES FOR THE CASE OF 90° FAULT INCEPTION ANGLE

Performance Indices

Phasor t R (ms) t S (ms) P O(% )

Magnitude 4.53 8.23 0.1

Phase Angle 4.87 10.62 0.13

Fig. 3. Basic signal with ddc time constant of 200 (ms) and fault inception TABLE II
angle of zero. AVERAGE OF THE INDICES FOR THE EIGHTEEN CASES

Magnitude

Method t R (ms) t S (ms) P O(% )

S-CharmDFT [16] 11.327 16.34 3.208
Modified DFT [17] 9.544 19.236 3.392
Prony-DFT [28] 8.564 15.056 2.723
Proposed Algorithm 5.414 11.719 1.607
Phase Angle
S-CharmDFT [16] 11.907 21.504 3.364
Modified DFT [17] 10.044 20.594 4.112
Prony-DFT [28] 8.911 17.176 2.653
Proposed Algorithm 6.117 12.991 1.717

Fig. 4. Estimated fundamental phasor for the worst case of basic signals.

case for the estimation algorithms, in which the performance of

the proposed algorithm and other algorithms are almost similar,
which are given in Table I.
As an advantage, unlike the other mentioned methods (Figs. 5
and 6), the three indices of the proposed algorithm are small and
almost constant for all the time constant values. Therefore, the
proposed phasor estimation algorithm results in faster conver-
gence speed and less dependency to the ddc parameters. This
is due to the simpler calculations and faster estimation of the
damping factor by the proposed algorithm.
Fig. 5. Result evaluation for zero fault inception angle.
To clarify the comparison, averages of the indices are calcu-
lated and shown in Table II, for eighteen signals generated by
three levels of the ddc magnitude and six time constants.
As seen in Table II, the indices’ averages of the proposed al-
gorithm are significantly smaller, which confirms the mentioned
advantage of the algorithm.

B. Test for Multiple ddc Components

Fig. 6. Result evaluation for 45° fault inception angle.
between the maximum and expected value of the waveform,
normalized by the expected value [29].
As mentioned earlier, for the eighteen basic signals, fun-
damental phasor is estimated by the proposed, S-CharmDFT,
Modified DFT and Prony-DFT algorithms. For each of the es-
timated phasors, rise time tR , settling time tS and percentage
overshoot PO are calculated and depicted in Figs. 5 and 6 for
fault inception angles of 0° and 45°, respectively. For fault in-
ception angle of 90°, the ddc does not exist. This is the easiest
The power-line fault current, which consists of a ddc and
sinusoidal components, is passed through a current transformer
(CT) before applying to the relays. The second ddc is added
to the fault current, due to the burden of CT [17]. Thus, the
CT output current contains two ddc components, during faults.
Since the burden of CTs is usually small, the time constant of
the second ddc becomes large and causes oscillatory error in
estimated phasor.
To evaluate the effect of multiple ddc components, the fol-
lowing test signal is used [17].
i2 [n] = |I1 | cos (θF )e−n Δ t/τ p − 0.1 |I1 | cos (θF )e−n Δ t/τ s
 
2π
− |I1 | cos n + θ1 (22)
N
JAFARPISHEH et al.: NEW DFT-BASED PHASOR ESTIMATION ALGORITHM USING HIGH-FREQUENCY MODULATION
Fig. 7. Fundamental phasor estimation for fault current signal with multiple
ddc components.
Fig. 8. Fault current signal including harmonics and white random noise.
where, the fault inception angle ΘF and first ddc time constant
(τp ) are assumed to be zero and 5 cycles, as the worst condition.
The time constant of the second ddc τs is set to 20 cycles [17].
The estimated fundamental phasors are depicted versus time,
in Fig. 7. Compared to the recent mentioned methods, the pro-
posed algorithm has better performance, in presence of multiple
ddc components (Fig. 7).
C. Test for Harmonics and Noise
In this subsection, the performance of the proposed algorithm
is evaluated in presence of harmonics and white random noise
[17], [24]. As shown in (23), the fault inception angle and ddc
time constant are assumed to be zero and 5 cycles, which is
the worst condition. The signal-to-noise ratio (SNR) for white
random noise is set to 20 dB.
N /2−1

 |I1 | 2πk
−n Δ t/τ
i3 [n] = |I1 | e − cos n + kθ1
k N
k =1
+ White Random Noise
The fault current and estimated phasors are depicted versus
time in Figs. 8 and 9, respectively.
As seen in Fig. 9, the proposed algorithm has better perfor-
mance in fundamental phasor estimation than the other three
methods, in presence of harmonics and noise. This is because,
as shown in Fig. 1, harmonic components and noise with max-
imum frequency of 420 Hz (harmonic number of N/2-1), are
severely suppressed by Si and Sy in the proposed algorithm.
2421
Fig. 9. Fundamental phasor estimation for fault current signal including har-
monics and white random noise.
Fig. 10. Fundamental phasor estimation for fault current signal in offnominal
frequency condition.
D. Test for Offnominal Frequency
During transient condition, the fundamental frequency
slightly deviates from its nominal value, which is called offnom-
inal frequency condition. This deviation causes oscillatory and
steady state error in estimated phasor [29]. To verify the per-
formance of the proposed algorithm, the test signal in previous
subsection is used by changing its power frequency to 59.5 Hz.
The estimated phasors are depicted versus time in Fig. 10.
As shown in Fig. 10, in offnominal frequency condi-
tion, the proposed algorithm estimates the fundamental
phasor faster and more accurate than the other men-
tioned methods. This is because Si and Sy have approxi-
mately the same gain for frequencies around fundamental
frequency of 60 Hz (Fig. 1).
E. Test for EMTP-Generated Signal
At this subsection, the proposed algorithm is evaluated, using
(23) typical electric signals that take place on electric power systems.
An EMTP-generated test signal corresponding to a single-
phase fault at the mid-point of a 103.47 km long, 220-kV trans-
mission line is used to evaluate the performance of the proposed
algorithm [23]. The fault current is shown in Fig. 11. Figure 12
depicts the estimated magnitude and phase angle of the funda-
mental component versus time for the proposed, S-CharmDFT
[16], modified DFT [17] and Prony-DFT [28] algorithms. For
more clarity, Fig. 13 depicts the estimated phasors versus time,
from one cycle after the fault inception time.
2422 IEEE TRANSACTIONS ON POWER DELIVERY, VOL. 32, NO. 6, DECEMBER 2017

TABLE III
COMPARISON OF THE COMPUTATION BURDEN AND NUMBER OF SAMPLES
REQUIRED FOR PHASOR ESTIMATION ALGORITHMS

Algorithm Log/exp × ÷ + − Required number of samples

[26] 2 61 80 N+ 1
[24] 2 61 48 N+ 1
[21] – 182 140 N+ 2
[20] – 151 64 N
[23] – 148 50 N+ 2
[30] – 48 59 N+ 1
[17], [18] – 37 95 N
[31] – 35 94 N+ 2
[16] – 34 76 N+ 1
Fig. 11. EMTP-generated fault current signal. [22] – 30 65 N
Proposed Algorithm – 15 65 N

As seen in Table III, the proposed algorithm significantly de-

Fig. 12. Estimated phasor of fundamental component for EMTP-generated
fault current signal.
creases the computational burden compared to the other phasor
estimation methods. It is notable that the other algorithms in
[27]–[29], which are not mentioned in Table III, suffer from
heavy matrix and logarithmic computations.
Based on Table III and the previous subsections, the pro-
posed algorithm provides lower computation burden and faster
convergence speed than S-CharmDFT [16], modified DFT [17],
and Prony-DFT [28] methods. Other methods of Table III are
not simulated and depicted in previous subsections, to keep fig-
ures clarity. However, a method may achieve fast convergence
in price of high computation burden.

Fig. 13. Estimated phasor from one cycle after the fault inception time for
EMTP-generated fault current signal.
As seen in Figs. 12 and 13, all of the three performance
indices of: rise time, settling time and percentage overshoot of
the proposed algorithm are significantly smaller than the other
phasor estimation methods.
F. Computation Burden
For evaluation of the computation burden, total numbers of
logarithmic, exponentional and basic-mathematical operations
are calculated, for the proposed and several recent phasor esti-
mation methods of [16]–[18], [20], [21], [23], [24], [26], [30],
[31]. It is assumed that some parameters are precalculated and
used in the implementation of the methods. Table III also shows
the required number of samples per data window for each phasor
estimation method. The number of samples per cycle is assumed
to be 16. In this case, each (fast) DFT computation consists of
10 multiplications and 30 summations [4].
IV. CONCLUSION
This paper presents a new DFT-based phasor estimation al-
gorithm, which contains four steps. First, a new auxiliary signal
is introduced based on a simple high-frequency modulation of
the fault current signal. Then, sample-summation of N-length
strings from fault current and auxiliary signals are calculated.
DFT of the fault current string is also calculated. Next, the DFT
error caused by the ddc is calculated. Finally, the fundamental
phasor component is estimated by eliminating the error value.
The performance of the proposed algorithm is compared with
three recent phasor estimation methods, using various types
of computer-simulated signals and an EMTP-generated signal.
Several computer-simulated signals are employed, considering:
different values for ddc magnitude and time constant, offnom-
inal frequency condition, and presence of harmonics, noise
and multiple ddc components. Three performance indices of
rise time, settling time and percentage overshoot are used for
comparison.
Compared to the mentioned recent methods, advantages of
the proposed algorithm are:
1) Faster convergence speed,
2) Less dependency to ddc parameters,
3) Robust performance in presence of multiple ddc compo-
nents in fault current signal,
4) Robust performance in presence of harmonics and noise,
5) Better performance in offnominal frequency condition,
6) Less computation burden.
The low demanding property of the proposed algorithm
makes it applicable for fast protection purposes.
JAFARPISHEH et al.: NEW DFT-BASED PHASOR ESTIMATION ALGORITHM USING HIGH-FREQUENCY MODULATION
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Babak Jafarpisheh (S’16) was born in Isfahan, Iran,
on September 14, 1988. He received the B.Sc. degree
(with hons.) in electrical engineering from Isfahan
University of Technology, Isfahan, Iran, in 2010, the
M.Sc. degree (with hons.) in electrical engineering
from the Bu-Ali Sina University, Hamadan, Iran, in
2012. He is currently working toward the Ph.D. de-
gree in electrical engineering at the University of Is-
fahan, Isfahan, Iran.
Since 2013, he has been a member of the Power
System Planning Center at Esfahan Regional Electric
Company, as a Consultant Engineer. His research interests include the areas of
power system protection, signal processing in power systems, wide area mon-
itoring, protection and control, renewable energies, control and identification
systems, and power quality of power systems.
Seyed M. Madani (S’97–M’03) received the B.Sc.
degree from Sharif University of Technology, Tehran,
Iran, in 1989, the M.Sc. degree from the University of
Tehran, Tehran, in 1991, and the Ph.D. degree from
the Eindhoven University of Technology, Eindhoven,
The Netherlands, in 1999, all in electrical power
engineering.
From 2000 to 2005, he worked with Texas A&M
University, University of Puerto Rico, and University
of Wisconsin at Madison, as an Assistant Professor or
a Visiting Professor. From 2005 to 2011, he worked
with Isfahan University of Technology as an Assistant Professor. He is currently
an Associate Professor at the University of Isfahan, Isfahan, Iran.
His research interests include power system protection and electrical ma-
chine drives. He has published several IEEE, IEE, and IET publications.
S. Mohammad Shahrtash was born in Tehran, Iran,
1960. He received the B.Sc. degree in electrical
engineering from Abadan Institute of Technology,
Abadan, Iran, in 1980, the M.Sc. degree in electrical
engineering from the University of Manchester In-
stitute of Science and Technology, England, U.K., in
1985, and the Ph.D. degree in electrical engineering
from Sharif University of Technology, Tehran, Iran,
in 1995. He is currently a Professor and the Head
of the Center of Excellence for Power System Au-
tomation and Operation, Iran University of Science
and Technology, Tehran. His main research areas include condition monitoring,
protection, electromagnetic transient analysis, and power system studies. He
has published several IEEE and IET publications.