IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 12, NO.
4, JULY 2013
Scalable Electrical Compact Modeling for Graphene
FET Transistors
Sébastien Frégonèse, Maura Magallo, Cristell Maneux, Henri Happy, and Thomas Zimmer, Senior Member, IEEE
Abstract—A new scalable electrical compact model for the
Graphene FET devices is proposed. Starting from Thiele’s quasi-
analytical model, the equations are modified to be fully compati-
ble with SPICE-like circuit simulation. Compared to Meric et al.
model, the charge model is improved. This large signal model has
been implemented in Verilog-A code and can be used for simulation
in a standard circuit design environment such as Cadence or ADS.
This model has been verified using different measurements from
the literature, and furthermore, its scalability is demonstrated.
Index Terms—Circuit, SPICE, compact, electrical, graphene,
large signal, model, transistor.
I. INTRODUCTION
HE physical properties of graphene are of highest inter-
T est for electronic applications and have motivated many
research groups to develop radio frequency and microwave
graphene field effect transistors (GFET) [1]–[6]. Impressive
high frequency performances have been demonstrated so far:
an intrinsic fT of 210 GHz for a 210 nm channel length [7]; an
intrinsic fT of 280 GHz for a 40 nm channel length [8]; an intrin-
sic fT of 300 GHz for a 144 nm channel length [9], while Meric
et al. [10] and Meng et al. [4] have published some devices with
balanced fM AX versus fT performances with interesting extrin-
sic figures of merit. Since the graphene research activities for
electronic applications have started recently, only few analog
and RF circuits have been demonstrated [11]–[16]. In addition
to the measurement of transistors, the evaluation of such devices
for circuit applications within a design environment is desirable.
Most of the developed transistors are evaluated as a single ele-
ment outside of the circuit context that can induce misleading
conclusions about the potentials of such devices in terms of
circuit integration. The evaluation of the circuit performances
Manuscript received September 27, 2012; accepted March 27, 2013. Date of
publication April 12, 2013; date of current version July 3, 2013. This work (part
of the GRADE project) was supported by the European Commission through the
Seventh Framework Program for Research and Technological Development and
by the French National Research Agency (ANR) through the P2 N “GRACY”
project. The review of this paper was arranged by Associate Editor A. Martinez.
S. Frégonèse, M. Magallo, C. Maneux, and T. Zimmer are with the Uni-
versity of Bordeaux, Center National de la Recherche Scientifique (CNRS),
33000 Bordeaux, France (e-mail: sebastien.fregonese@ims-bordeaux.fr;
maura.magallo@ims-bordeaux.fr; cristell.maneux@ims-bordeaux.fr; thomas.
zimmer@ims-bordeaux.fr).
H. Happy is with the University Lille 1, Sciences and Technologies -
IEMN Lab, 59650 Villeneuve d’Ascq, France (e-mail: henri.happy@iemn.univ-
lille1.fr).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TNANO.2013.2257832
1536-125X/$31.00 © 2013 IEEE
539
Fig. 1. Cross-sectional view of the transistor structure.
can be carried out using appropriate electrical compact models.
The electrical compact model must be able to represent prop-
erly the electrical behavior for dc, ac, and transient simulation.
Some works have already been proposed for GFETs modeling,
e.g., finite element studies have been done using drift-diffusion
equation [17] and NEGF simulation [18]. Analytical or com-
pact models have been proposed by Ryhzii et al. [19], Meric
et al. [20], [21], Shepard et al. [22], Scott and Leburton [23],
Wang et al. [24], Jimenez and Moldovan [25], [26], Cham-
plain [27], [28], Habibpour et al. [29], and Thiele et al. [30].
The first one assumes ballistic transport in the graphene layer,
while other works are based on the drift equation. Some of the
models can be easily implemented for SPICE simulation that
includes large signal simulation, while [30] is a quasi-analytical
model for the dc simulation and a compact model for small
signal simulation.
In this paper, we propose a new large signal compact model
based on the work from [21] and [30]. Compared to [21]
and [31], the charge model is improved; it includes the specific
density of states of graphene, and furthermore, we modify equa-
tions proposed in [30] to get Verilog-A-language-compatible
equations for further circuit simulations (SPICE like). The pa-
per has two parts: an improved transistor compact model is
developed and described in the first part; then, the second part
compares compact model results to measurements from the lit-
erature proving its scalability.
II. COMPACT MODEL
The compact model is described in three steps: A) the metal–
insulator–graphene (MIG) structure is modeled; B) we use the
charge of the MIG structure to obtain an expression of the drain
current; C) the large signal equivalent compact model is de-
scribed. Fig. 1 shows a cross-section view of a typical GFET.
A. Metal–Insulator–Graphene Capacitance Modeling
The charge evaluation in a MIG structure requires a different
approach compared to conventional semiconductor. This is due
to the gapless band structure of graphene. Hence, combining the
540 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 12, NO. 4, JULY 2013

calculation

Qnet (x) = βs
  2
−CTOP + CTOP
2 +4β |CTOP (VG S i −V (x))+e Nf |
· .
2β
(4)

B. Drain Current Modeling

Fig. 2. Equivalent circuit of the MIG capacitor. Using the drift equation, the drain current can be expressed
as follows [30]:
VD S i
(|Qnet | + e npuddle ) dV
ID = μW 0

(5)
specific density of states of graphene with the Fermi approach
V
0 D S i v S1A T dV
for the carrier distribution, and simplifying the formula, the
total charge density in MIG capacitor can be approximated as
follows [30]:
 
e2
QSH (x) ≈ e − |VCH (x)| VCH (x) + NA − ND
π (vf )2
 
β homogeneity of the electrostatic potential.
= e − |VCH (x)| VCH (x) + Nf (1)
e We assume that the area of hole and electron puddles are
with  being the reduced Planck constant, vf the Fermi veloc-
ity, e the electronic charge, and VCH (x) the channel potential
along x, NA and ND are the acceptor and donor doping, respec-
tively (NA − ND = Nf ) and β = e3 /π (vf )2 . Also, applying
a drain voltage VD S implies that the channel potential V (x)
and, consequently, the Fermi level is varying along the chan-
nel. Hence, this potential drop induces a charge variation along
the channel that is followed by a change in the conduction and
valence band level in the channel VCH (x) through the Pois-
son equation. In order to model properly both effects, we use
the equivalent circuit proposed by Thiele [30]. This equivalent
circuit is given in Fig. 2, where V (x) models the change in
potential due to VD S i ; VG S i is the internal gate-source voltage;
CTOP is the gate insulator capacitance.
Applying the Kirchhoff’s law to the equivalent circuit, the
following relation between gate voltage, channel potential and
potential variation due to VD S can be established:
(CTOP ) (VCH (x) − VG S i + V (x)) − β |VCH (x)| VCH (x)
+ e Nf = 0.
The zeros of this second degree polynomial can be calculated
and give the following channel potential solution:
L + μ
where μ is the mobility, W the width of the graphene sheet, L
the channel length, and vSAT is the saturation velocity in the
graphene layer. Variable npuddle is the residual carrier density,
which is induced by spatial inhomogeneity within the graphene
layer (npuddle = Δ2 /π2 vf2 ) [32]. Δ represents the spatial in-
equal in size meaning that ne puddle = nh puddle = npuddle /2.
Using this hypothesis, the puddle does not induce a shift of the
Dirac point.
The saturation velocity depends on the carrier concentration
2
as vSAT = ω/ (π (|Qnet (x)|/e + npuddle ))0.5+A V (x) , where
 ω is the surface phonon energy of the substrate [30] and A is
a constant. The term AV 2 (x) represents a second order effect
and is neglected in the further treatment.
Equation (5) cannot be directly implemented in Verilog-A
code due to its integral form. Hence, we need to develop an-
alytical solutions for (5). The integral in the numerator of the
fraction has a direct analytical solution and it is given in the
appendix. At large VD S , one can observe that the saturation
velocity has to be taken into account. The integral in the de-
nominator of (5) has also a solution, but it is not compatible and
suitable for Verilog-A implementation due to its complexity. In
order to come up with a simplified integral solution, we assume
an average value for the saturation velocity vSAT . An average
vSAT AV value can be estimated from (4) assuming an average
charge in the channel taking the half drain potential for V (x) =
(2)
VD S i /2:
Qnet A V = βs
⎡ 
 
⎤2
VCH (x) = s
V

 −C
⎢ TOP + C 2
TOP +4β
CTOP V GS i − D S i/2 +e Nf
⎥
−CTOP + 2
CTOP + 4β |CTOP (VG S i − V (x)) + e Nf | ·⎢
⎣
⎥.
⎦
2β
2β
s = sign (CTOP (VG S i − V (x)) + e Nf ) . (3)
(6)
Combining (1) and (3), the bias dependant mobile carrier
charges Qnet ( = QSH − eNf ) can be computed as a function Using this approximation, the integral in the denominator
of VG S i : this expression will be used for further drain current of (5) can be simplified using the average saturation velocity
FRÉGONÈSE et al.: SCALABLE ELECTRICAL COMPACT MODELING FOR GRAPHENE FET TRANSISTORS 541

Fig. 3. ID S − V D S characteristics for different V G S , computed using numer-

ical solution from (5), approximated analytical solution, and comparison to mea-
surement data [33]. V G S = −2 V to 0 V; N f ∼ 0 cm−2 , μ = 7000 V/(cm2 ·s),
εr = 3.4, th −B N = 8.5 nm, Δ = 66.8 meV,  ω = 56 meV, A = 0, and
R S = R D = 0.
Fig. 4. Normalized charge characteristics versus V G S for different V D S ,
computed using numerical solution from [30] and analytical solution. N f ∼
0 cm−2 , μ = 7000 V/(cm2 ·s), εr = 3.4, th −B N = 8.5 nm, Δ = 66.8 meV,  ω
= 56 meV, A = 0, and R S = R D = 0.

vSAT AV and the solution is given by

(π (|Qnet AV |/e + npuddle ))0.5

L+μ |VD S i |
ω
.
This approximated solution can easily be implemented in
Verilog-A code along with (5) for a more accurate calculation
of the drain current. This approximated solution is compared to
numerical solution in Fig. 3. In order to use realistic parameters,
we have also compared our calculation to measurement data
[33]. Note that within this measurement data, access resistance
effects have been corrected. A good agreement between our
model and numerical solution is observed.

C. Large Signal Equivalent Circuit

In order to develop a small and large signal compact model
that works both in ac and transient modes, one needs to evaluate Fig. 5. Normalized C G S capacitance characteristics versus V G S for different
V D S , computed using numerical solution from [30] and analytical solution. N f
the total charge inside the channel. Assuming an average electric ∼ 0 cm−2 , μ = 7000 V/(cm s), εr = 3.4, th −B N = 8.5 nm, Δ = 66.8 meV,
field within the channel, the total charge in the channel can be  ω = 56 meV, A = 0, and R S = R D = 0.
approximated as follows:
 L
QCH = W (Qnet (x) + e npuddle ) dx imated analytical solution. The concordance is correct for the
0 considered bias range. We used the same parameters than used
 VD S i  
1 β previously.
≈ eW |VCH | VCH + npuddle dV From the channel charge QCH , the gate-source and drain-
EAV 0 e
source capacitances can be directly deduced from the derivative
with of the charge expression as follows:
1

EAV ≈  . dQCH

dQCH

(|Q n e t A V |+e n p u d d l e )μ∗W ) μ CG S = − , CG D = − .

ID S + v S A T AV dVG S
V G D = cste dVD S
V G S = cste
(7) (8)
Fig. 5 presents the comparison between the numerical solu-
This integral has already been solved for the current calcula- tion and the approximated analytical solution of the CG S ca-
tion, and the solution is given in the Appendix. Fig. 4 presents pacitance. These elements can be directly computed using a
the comparison between the numerical solution and the approx- derivative function in Verilog-A language as described in [34].
542
Fig. 6. Equivalent circuit of GFET electrical compact model.
Fig. 7. ID S versus V D S curves for different V G S values (–1.25, –0.75, –0.25,
0.25, and 0.75 V), measurement (symbol) [36], and compact model simulation
(solid line).
The equivalent circuit of the complete compact model is pre-
sented in Fig. 6. In addition to the current source ID S , the gate
source capacitance CG S , and the drain source capacitance CG D ,
the following lumped elements can be observed: RD , RS , and
RG are the drain, source, and gate access resistances; CparGD
and CparGS are the parasitic gate-drain and gate-source capaci-
tors. The current source ID S is implemented using (9) and (11)
and CG S and CG D are implemented using (8), (11), and (12).
III. CHARACTERIZATION AND COMPARISON TO MEASUREMENT
In order to validate our model and to demonstrate its capability
to model some GFETs using different graphene material and
insulator, we have modeled three technologies: the first one is
from HRL Laboratories [35], the second one is from MIT [36],
and the last one is from Columbia University [33].
The transistor described in [36] is a top gated device using
HfO2 insulator for the gate oxide. The graphene is grown by
chemical vapor deposition on Ni substrate and is composed of
about four monolayers. The measurement data and our compact
model simulation are presented in Fig. 7.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 12, NO. 4, JULY 2013
TABLE I
PARAMETERS FROM [36], USED IN SIMULATION [30] AND USED IN THIS STUDY
Fig. 8. ID S versus V D S curves for different V G S values from 3 V with a
step of 0.5 V, measurement (symbol) [35] and compact model simulation (solid
line).
The extracted parameters are compared to physical data from
[36] and also to parameters used in the quasi-analytical model
[30]. The data are compared in Table I and are in good agreement
with [36] and [30].
The second GFET described in [35] is a top-gated graphene
FET and is fabricated with epitaxial graphene layers grown on
Si-face 6 H-SiC substrates on 50-mm wafers, and the graphene
has about one monolayer on the terraces and two monolayers on
the edges. This device has been chosen since it presents remark-
able saturation, as shown in Fig. 8. Output curves, transfer char-
acteristics, and transconductance are presented in Figs. 8 and 9.
A good agreement is observed between measurement and sim-
ulation considering electrical fluctuation of the device. Parame-
ters used in simulation have been directly extracted from [35] or
optimized on measurements. Note that the extracted parameters
are also very close to the work presented in [27]. The parameters
are summarized in Table II.
FRÉGONÈSE et al.: SCALABLE ELECTRICAL COMPACT MODELING FOR GRAPHENE FET TRANSISTORS 543

Fig. 9. ID S versus V G S curves for different V D S values (1.05, 1.55, 2.05,

2.55, and 3.05 V), measurement (symbol) [35] and compact model simulation
(solid line). The associated transconductance is presented in the inset (solid
line).

TABLE II
PARAMETERS FROM PROCESS, USED IN SIMULATION IN [28] AND USED
IN THIS STUDY

Finally, we verify the scalability over the gate length of our

compact model using the measurement data described in [33].
The parameters used for the simulation are described in Table
III. The GFETs under consideration are built utilizing hexagonal
boron nitride (h-BN) as both a gate dielectric and supporting
substrate. Very high mobility is achieved using this material.
Moreover, in this case, the three GFETs are built in a small area
resulting from a very homogeneous process. Hence, these data
can be used to verify our model scalability and using only one set
of parameters; the model is able to accurately describe the three
devices by just changing gate length parameter. Comparison of
experimental and simulation results is presented in Fig. 10. The Fig. 10. ID S versus V D S for different V G S values from −2 to 0 V, measure-
gate length varies from 3 μm to 440 nm. Maximum drain current ment in symbol [33] and compact model simulation in solid line. Lg = 3 μm,
Lg = 1 μm, and Lg = 0.44 μm.
increases conversely with the gate length, as expected.
544 IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 12, NO. 4, JULY 2013

TABLE III This equation has a direct analytical solution and can be
PARAMETERS USED IN COMPACT MODEL SIMULATION AND COMPARISON TO
PARAMETERS FROM [33]
solved using a change in variable (z = CTOP (VG S i − V ) +
e Nf ), and the final solution is given as follows:
1
num = −
12eβ 2 CTOP
⎡ ⎤z 2
2
6βCTOP z1,2 − 6β 2 z1,2
2

⎢  2 3/2 ⎥
⎢ +CTOP CTOP − 4βz1,2 , if z1,2 < 0 ⎥
⎢ ⎥
⎣ 6βCTOP z1,2 + 6β z1,2
2 2 2
⎦
 2 3/2
−CTOP CTOP + 4βz1,2 4
+ 2CTOP , if z1,2 > 0 z 1
(11)
where z1 and z2 are the integral boundaries
z2 = CTOP (VG S i −VD S i )+e Nf z1 = CTOP VG S i + e Nf .
Finally, the charge (7) is solved in the same way than
precedently
 L
QCH = W Qnet (x) + e npuddle dx
0

IV. CONCLUSION 1
≈ eW [χnum + npuddle VD S i ] (12)
EAV
We have developed a new compact model based on the
quasi-analytical physics based model from [30]. This quasi- 1
χnum =− 2
analytical model [30] is more physics based than the first com- 12eβ CTOP
pact model [21], but it is not fully compatible with SPICE sim- ⎡ ⎤z 2
2
6 βCTOP z1,2 − 6 β 2 z1,2
2
ulation. Hence, our model represents a good tradeoff in terms of ⎢  2 3/2 ⎥
physics and implementation compatibility. Our model has been ⎢ +CTOP CTOP − 4 βz1,2 , if z1,2 < 0 ⎥
⎢ ⎥(13)
directly implemented in Verilog-A code. In order to perform ⎣ −6 βCTOP
2
z1,2 − 6 β 2 z1,2
2
⎦
 2 3/2
this implementation, some approximate solutions have been +CTOP CTOP + 4, βz1,2 , if z1,2 > 0 z 1
proposed to solve the integral equations. The approximations
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Sébastien Frégonèse was born in Bordeaux, France,
in 1979. He received the M.Sc. and Ph.D. degrees
in electronics from the University of Bordeaux, Bor-
deaux, in 2002 and 2005, respectively.
He was involved in bulk and thin film SOI SiGe
HBTs, with emphasis on compact modeling. From
2005 to 2006, he was a Postdoctoral Research Fel-
low with the Technical University of Delft, Delft, The
Netherlands, where was involved in the Si strain FET
emerging devices, focusing on process and device
simulation. In 2007, he joined, as a Researcher, the
IMS Laboratory, Center National de la Recherche Scientifique (CNRS), Bor-
deaux. His current research interests include electrical compact modeling and
characterization of HF devices such as the SiGe HBTs and carbon-based transis-
tors. From 2011 to 2012, he was a Visiting Researcher at the IEMN Laboratory,
Lille, France, where he was involved graphene FET device modeling. He is
currently involved in a couple of National and European research projects like
the European FP7 IP DotFive Project, ESF EUROGRAPHENES ELOGRAPH,
MEDEA + programs, ANR ACCENT, ANR PANINI, and ANR Nanograin.
He was a Reviewer of the Physica Status Solidi, the IEEE TRANSACTIONS ON
ELECTRON DEVICES, the Solid State Electronics, and some IEEE conferences.
Maura Magallo was born in Naples, Italy, in 1987. She received the M.Sc.
degree in electronics from the University of Naples “Federico II,” Naples, Italy,
in 2011. She is currently working toward the Ph.D. degree in graphene transistor
compact modeling with the Nanoelectronics Group, Laboratory of the Integra-
tion from Material to System (IMS), Bordeaux, France.
Cristell Maneux received the B.Eng. degree in elec-
tronics engineering, the M.Sc. degree in electronics
engineering, the Ph.D. degree in electronics, and the
Habilitation à Diriger des Recherches (professional
dissertation) degree from the University of Bordeaux,
Bordeaux, France, in 1992, 1994, 1998, and 2007,
respectively.
From 1997 to 1998, she was a Research and
Teaching Assistant with the University of Bordeaux,
where in 1998 she was an Associate Professor in the
Department of Electronics Engineering and is cur-
rently the Head of the Electrical Characterization and Compact Modeling Team
(http://www.ims-bordeaux.fr/spip.php?article95) in the Nanoelectronic Group,
Laboratory of the Integration from Material to System (IMS). Her current re-
search interests include the study of HBT technologies using the finite element
simulation, physical analysis, and low frequency noise characterization for com-
pact modeling purpose as well as reliability concerns. Since 2005, she has ini-
tiated a new research topic on the development of carbon nanotube transistor
(CNTFET) compact modeling. For HBT and CNTFET technologies, she has
authored or coauthored more than 60 journal publications and conference papers
and has gathered significant scientific coordination experience within national
and international collaborative research projects over the past decade, having
been a work package leader or scientific coordinator for several national and
European projects. She is currently the leader of ANR ROBUST collaborative
scientific program (http://extranet.ims-bordeaux.fr/ROBUST).
546
Henri Happy received the Ph.D. degree in electri-
cal engineering from the Université des Sciences et
Technologies de Lille 1 (USTL), Lille, France, in
1992.
In 1988, he joined the USTL Lab Institut
d’Electronique, de Microélectronique et de Nan-
otechnologie (IEMN), where he is currently a
Full Professor of Electronics. His current research
interests include high electron-mobility transistor
(HEMT) modeling, using a quasi-two-dimensional
approach. He is the main coauthor of the software
Hemt ELEctrical properties and Noise Analysis (HELENA), published since
1995. From 1998 to 2003, he was involved in the design, fabrication, and charac-
terization (up to 220 GHz) of monolithic microwave integrated circuits (MMICs)
for optical communications systems, using either planar or three-dimensional
circuit topologies. Since 2004, he has been involved in nanodevices for HF
applications. He has developed successful carbon electronics activities at the
IEMN Lab, based on nanotubes. These activities now also include graphene and
several kinds of 2-D materials. The main objectives are the understanding of
fundamental limitations and improvement of HF performance of nanodevices,
and their applications in emerging fields of RF circuits on flexible substrates.
IEEE TRANSACTIONS ON NANOTECHNOLOGY, VOL. 12, NO. 4, JULY 2013
Thomas Zimmer (M’98–SM’08) received the M.Sc.
degree in physics from the University of Würzburg,
Würzburg, Germany, in 1989, and the Ph.D. degree
in electronics from the University Bordeaux 1, Bor-
deaux, France, in 1992.
From 1989 to 1990, he was with the Fraunhofer In-
stitute, Erlangen, Germany. Since 1992, he has been
with the IMS Institute, University of Bordeaux, Bor-
deaux, France, where he has been a Professor since
2003 and is the Leader of the research group “Na-
noelectronics,” IMS Laboratory. His current research
interests include electrical compact modeling and characterization of HF devices
such as HBT (SiGe, InP), graphene nanotubes, and GFETs. He is a cofounder of
XMOD Technologies. He was a Reviewer for many journals (IEEE ED, EDL,
SSE, etc.) and participated on the Program Committee of several conferences
(BCTM, ESSDERC, etc.). He has authored or coauthored more than 150 peer-
reviewed scientific articles, 1 book, and contributed to 8 book chapters.