EXPERIMENT #14

STUDENT NAME : M.usama saghar Roll NO: 2019-CPE-27

Subject : EDC
Subject Teacher: DR

Muhammad Imran Malik Lab

Engineer: Engr. Muhammad

Ubaidullah Lab Performed In :

DSP LAB
Course Instructor / Lab Engineer

Experiment No. 14

Objective: To Design a Small Signal Common Source JFET Amplifier and Analyze the
performance of Small Signal Common Drain JFET Amplifier

Apparatus: DC power supply, nFET, Multimeter, Breadboard, Resistors

Circuit Diagram:

Theory:
A common source amplifier can provide significant voltage gain to a small signal applied as

input. As gate to source junction is reverse biased, no current except a very small leakage
current flows from Drain to Source. RG can hence be assumed to be very large e.g. 1MΩ.

Output voltage VDS is given for a design problem, hence value of drain resistance RD can be
calculated using output loop equation:

𝑉DD − 𝐼D 𝑅D − 𝑉DS = 0

Device Transconductance gm can be calculated using the following expression:

2𝐼DSS
𝑔 = J D

n 𝑉p

𝐼DSS
Stage voltage gain can be calculated as

= −𝑔

(𝑅

||𝑅

[ 𝑅G ]

Procedure:
vc n D

L) 𝑅
G + 𝑟c

Design the circuit using the following given data:

VDD=20V, VGG=2V, ID=6mA, rs=50Ω, IDSS=30mA, VDS=VDD/2
Connect your designed circuit on breadboard
Apply AC input and vary its magnitude from 500mV to 3V with a uniform step size
Measure output voltage using oscilloscope, your measured stage voltage gain is v L

vc

Compare measured and calculated stage voltage gain and calculate percentage error
CIRUIT: 1
Observations:

Vs VL Avs
Calculated Measured %age Error
500mV 2.21mV 0.34 4.42mV 2.77%
1V 2.21mV 0.34 2.21mV 51%
1.5V 2.21mV 0.34 1.4733mV 66%
2V 2.21mV 0.34 1.105mV 75%
2.5V 2.21mV 0.34 0.884mV 80%
3V 2.21mV 0.34 0.736mV 83.3%

Circuit Diagram:
Theory:
In a JFET connected as a common drain amplifier, the drain terminal is connected directly to
the supply voltage, in this way drain is common in between gate and source. The output
signal is the same as voltage across drain and source.

S gn Rc and taking
tage voltage gain of the amplifier is the unloaded voltage gain i.e.
into account loading
1+ gn Rc

effect:

𝑔n (𝑅S ||𝑅L)

𝑅1||𝑅2

vc = [
𝐴 1+𝑔

]( )
(𝑅 ||𝑅

n S L)

𝑅1||𝑅2 + 𝑟c

While device transconductance gm can be calculated using the following expression:

2𝐼DSS
𝑔 = J D

n 𝑉p

𝐼DSS

Procedure:
Analyze the circuit using following resistor values:
VDD=24V, R1=1.8MΩ, R2=470kΩ, RE=1.5kΩ, RL=3kΩ, VP=3V, IDSS=30mA
Connect this circuit on breadboard
Apply AC input and vary its magnitude from 500mV to 3V with a uniform step size
Measure output voltage using oscilloscope, your measured stage voltage gain is v L

vc

Compare measured and calculated stage voltage gain and calculate percentage error

Observations:

Vs VL Avs
Calculated Measured %age Error
500mV 0.00mV 0.0018V 0.00mV 0.5%
1V 0.02mV 0.0018V 0.02mV 1%
1.5V 0.04mV 0.0018V 0.02mV 1%
2V 0.06mV 0.0018V 0.02mV 1%
2.5V 0.08mV 0.0018V 0.02mV 1%
3V 0.09mV 0.0018V 0.02mV 1%
Conclusion:
• Source amplifier can provide significant voltage gain to a small signal
applied as input. As gate to source junction is reverse biased.
• In a JFET connected as a common drain amplifier, the drain terminal is connected
directly to the supply voltage, in this way drain is common in between gate and
source. The output signal is the same as voltage across drain and source.