REPRINDEREA— INTRODUCERE INTRODUCTION — INDEX DE FUNCTII FUNCTIONAL INDEX —TABEL DE ECHIVALENTE CROSS REFERENCE GUIDE DIGITAL IC'S CHARACTERIZATION — NOTIUNI GENERALE ENERAL NOTIONS — CARACTERISTICI, REGUL] DE UTILIZARE CHARACTERISTICS. NOTE TO THE USER — PARAMETRI. DEFINITII PARA ERS. DEFINITIONS — SIMBOLURI SYMBOLS —INFORMATII GENERALE ‘tice: v.sss3;.98hs denase. cote GENERAL INFORMATION —VALORI LIMITA ABSOLUTA ABSOLUTE MAXIMUM RATINGS RA CODULUI DE MARCARE......... egivieen vee R_ INFORMATION — CIRCUITE INTEGRATE TTL STANDARD... STANDARD TTL ICS — CARACTERIZAREA CIRCUITELOR INTEGRATE LOGICE.... CUPRINS CONTENTS a 4 8 44alee —TRIGGER SCHMITT 120 SCHMITT TRIGGER = MONOSTABIL aie rec silvia ec Pec Srninnba gh +e 124 MONOSTABLE —CIRCUITE BASCULANTE BISTABILE.......--+2+2sereese eens 141 FLIP-FLOPS — NUMA ISH GPE, a ANGLIA... E.Sun a 18 COUNTERS — REGIST RUBIN sa MUMMERS 5 annie <2 34hiom bd to) 0256 REGISTER — DECODIFICATOR 2 DECODER —CIRCUITE ARITMETICE...........+ 279 ARITHMETIC. CIRCUITS SOOM RI irre) te oe ed y= o> o8 doi ole iceman ae 301 MEMORY —CIRCUITE INTEGRATE TTL RAPIDE........ Z 314 HIGH SPEED TTL ICS = OPERATOR. 5. 318 Doi operatori SI-NU cu cite 4 intrari CDB 420 E 78 Dual 4-Input NAND Gate Operator SILNU cu 8 intrari CDB430E © CDB 430 HE 81 8-Input NAND Gate CDB 430 EM 324 Doi operatori SI-NU de putere cu cite 4 intrari CDB 440 E CDB 440 HE 84 Dual 4-Input NAND Power Gate CDB 440 HP 327 OPERATOR! $1 AND GATES Patru operatori $I cu cite 2 intrari CDB 408 E 83 Quadruple 2-Input AND GateOPERATORI SI-NU STANDARD RAPID Pag. NAND GATES HIGH SPEED Page Patru operatori $I cu cite trari, iesiri cu colector CDB 409 E 66 1 (5,5 V) -€DB 408 E 63 le 2-Input AND Gate Open-Collector. Output CDB 411 HE 321 STANDARD RAPID HIGH SPEED CDB 404 E By] . i cu colec- tor in gol (5,5 V) CDB 405 E 54 Hex I ‘s with Open- = in gol CDB 406 E ay ee INVERSOARE, OPERATORI DE PUTERE INVERTERS, POWER GATES STANDARD RAPID HIGH SPEED Pag. Page Sase operatori de putere, iesiri cucolector in gol (30 V) Hex Power Gates with Open- Collector Output (30 V) $ase inversoare de putere, iesiri cu colector in gol (15 V) Hex Power Inverters with Open- Collector Output (15 V) Sase operatori de putere, iesiri cu colector in gol (15 V) Hex Power Gates with Open- Collector Output (15 V) CDB 407 E CDB 416 E CDB 417 E 75 OPERATORI SI-SAU-NU, EXPANDOARE AND-OR-INVERT GATES, EXPANDERS Doi operatori $I-SAU-NU cu cite 2X2 intrari (unul expandabil) Expandable Dual 2-Wide 2-In- put AND-OR-INVERT Gate Doi operatori $I-SAU-NU cu cite 2X2 intrari Dual 2-Wide 2-Input AND-OR- INVERT Gate CDB 450 E CDB 451 E CDB 451 HE CDB 451 HP 87 ny 330 iOPERATORI SI-SAU-NU, EXPANDERE AND-OR-INVERT GATES, EXPANDERS Pag. Page Operator expandabil $I-SAU- NU cu 4X2 intrari Expandable 4-Wide 2-Input AND-OR-INVERT Gate Operator SI-SAU-NU cu 4X2 intrari CDB 454 E 4-Wide 2-Input AND-OR-IN- VERT Gate Doud expandere cu cite 4 intrari CDB 460 E Dual 4-Input Expander CDB 453 E CDB 454 HE 94 98 334 101 TRIGGER SCHMITT SCHMITT TRIGGER STANDARD RAPID HIGH SPEED Doi operatori SI-NU TRIG- GER SCHMITT cu cite 4 intrari CDB 413 E Dual 4-Input NAND SCHMITT TRIGGER 120 CIRCUITE BASCULANTE FLIP-FLOPS Monostabil CDB 4121 E Monostable ss Bistabil JK STAPIN-SCLAV JK MASTER-SLAVE Flip-Flop CDB 472 E CDB 472 EM 12 eee TRIGGER SCHMITT SCHMITT TRIGGER STANDARD RAPID Pag. HIGH SPEED Page Dov’ bistabile JK STAPIN- SCLAV Dual JK MASTER-SLAVE Flip-Flop Doua bistabile tip D cu bascu- lare pe front Duo! D-Type Edge-Triggered Flip-Flop Doua bistabile JK STAPIN- SCLAV Dual JK Flip-Flop MASTER-SLAVE CDB 473 E CDB 473 EM CDB 474 E CDB 476 E 148 155 161 NUMARATOARE COUNTERS Numarator decadic Decade Counter Numarator divizor prin 12 Divide-by-Twelve Counter Numéarator binar de 4 biti 4-Bit Binary Counter Nui itor decadic sincron re- versibil (2 intrari de tact) Synchronous Up/Down Decade Counter (Two Clock Lines) CDB 490 E CDB 492 E CDB 493 E CDB 4192 E 184 198 212 226SR OSA TA SE NUMARATOARE COUNTERS Numarator binar de 4 biti sincron reversibil (doua in- tréri de tact) CDB 4193 E Synchronous Up/Down 4-Bit Bi- nary counter (Two Clock Lines) Pag. Page 240 REGISTRE, DECODIFICATOARE, ELEMENTE ARITMETICE, MEMORII REGISTERS, DECODERS, ARITHMETIC ELEMENTS, MEMORIES Registru de deplasare dreapta/ stinga de 4 biti CDB 495 E 4-Bit Right/Left Shift Register Decodificator ZCB—zecimal CDB 442 E BCD-to-Decimal Decoder Patru operatori SAU-EXCLU- SIV cu cite 2 intrari CDB 486 E Quadruple 2-Input EXCLUSIV- OR Gate Sumator complet de 4 biti CDB 483 4-Bit Binary Full Adder Memorie citeste/scrie de 16 biti CDB 481 £ 16-Bit Random-Access Memory 256 271 279 287 301 Nota: Circuitele integrate logice sint prezentate in logicd pozitiva Note: Positive logic is adopted for Digital ICs’ description 14TABEL DE ECHIVALENTE CROSS REFERENCE GUIDE | SS £ oe LP.R.S. TEXAS Eines SESCOSEM iNet UN ENTS FAIRCHILD Tar. SIEMENS cil CDB 400 E SF.C 400 E SN 7400 N 7400, 9NO0 DC MIC 7400 J, MIC 9002-5D FLH 101 cll 30 Ct CDB 403 E SF.C 403 E SN 7403 N 7403, 9NO3 DC MIC 7403 J, MIC 9012-SD FLH 294 DB 400 EM SF.C 400 EM SN 5400 N 5400, 9NOO DM MIC 5400 J, MIC 9002-1D CDB 404 E SF.C 404 E SN 7404 N 7404, 9NO4 DC MIC 7404 J, MIC 9016-5D FLH 211 CDB 405 E SF.C 405 E SN 7405 N 7405, 9NOS DC MIC 7405 J FLH 271 CDB 406 E SF.C 406 E SN 7406 N 7406, 9NO6 DC MIC 7406 J CDB 407 E SF.C 407 E SN 7407 N3 7407, 9NO7 DC MIC 7407 J CDB 408 E SF.C 408 E SN 7408 N 7408, 9NO8 DC CDB 409 E SF.C 409 E SN 7409 N 7409, 9NO9 DC CDB 409 EM SF.C 409 EM SN 5409 W 5409, 9NO9 FM CDB 410 E SF.C 410 E SN 7410 N 7440, 9N10 DC MIC 7410 J, MIC 9003-5D FLH 411 cil 48 cl CDB 413 E SF.C 413 E SN 7413 N 7413, 9N13 DC MIC 7413 J, FLH 354 CDB 416 E SF.C 416 E SN 7416 N 7416, N16 PC | MIC 7416 J CDB 417 E SF.C 417 E SN 7417 N 7417, 9NI7 PC } MIC 7417 J CDB 420 E SF.C 420 E SN 7420 N 7420, 9N20 PC MIC 7420 J, MIC 9004-5D FLH 121 ch 33 cl CDB 430 E SF.C 430 E SN 7430 N 7430, 9N30 PC MIC 7430 J FLM 131 CDB 430 EM SF.C 430 EM SN 5430 N 5430, 9N30 PM MIC 5430 J cDB 440 E SF.C 440 E SN 7440 N 7440, 9N40 PC MIC 7440 J, MIC 9009-5D FLH 141 cil 32 CI CDB 442 E SF.C 442 E SN 7442 N 7442, 9NS2 PC MIC 7442 J FLH 281 CDB 450 E SF.C 450 E SN 7450 N 7450, 9NSO PC MIC 7450 J, MIC 9005-5D FLH 151 CDB 451 E SF.C 451 E SN 7451 N 7451, 9NS1 PC i MIC 7451 J FLH 161 ci 34 Cl CDB 453 £ SF.C 453 E SN 7453 N 7453, 9NS3 PC MIC 7453 J, MIC 9008-5D FLH 171 CDB 454 E SF.C 454 E SN 7454 N 7454, 9NS4 PC MIC 7454 | FLH 181 Cll 46 Cl COB 460 E SF.C 460 E SN 7460 N 7460, 9N60 PC } MIC 7460 J, MIC 9006-5D FLY 101 CDB 472 E SF.C 472 E SN 7472 N 7472, 9N72 PC Mic 7472 J FL) 111 cul 44cl 16 7LP.R.S. TEXAS Bksese SESCOSEM INSTRUMENTS FAIRCHILD CDB 472 EM SF.C 472 EM SN 5472 N $472, 9N72 PM COB 473 E SE.C 473 E SN 7473 N 7473, 9N73 PC CDB 473 EM SF.C 473 EM SN 5473 N 5473, 9N73 PM CDB 474 E SF.C 474 E SN 7474 N 7474, N74 PC CDB 476 E SF.C 476 E SN 7476 N 7476, N86 PC CDB 481 E SF.C 481 E SN 7481. N 93407 PC CDB 483 E SF.C 483 E SN 7483 N 7483, 99383 PC CDB 486 E SF.C 486 E SN 7486 N 7486, 9390 PC CDB 490 E SF.C 490 E SN 7490 N 7490, 9390 PC CDB 492 E SF.C 492 E SN 7492 N 7492, 9392 PC CDB 493 E SF.C 493 E SN 7493 N 7493, 9393 PC CDB 495 E SF.C 495 E SN 7495 AN 7495, 9395 PC CDB 4121 E SF.C 4121 E SN 74121 N 74121, 9603 PC CDB 4192 E SF.C 4192 E SN 74192 N 74192, 9360 PC CDB 4193 E SF.C 4193 E SN 74193 N 74193, 9366 PC DB 400 HE SF.C 400 HE SN 74H0O N 74H00, 9HOO PC CDB 400 HEM = SF.C 400 HEM = SN_54HOO N 54H00, 9H00 PM CDB 400 HP SF.C 400 HP SN 74HOO N 74H00, 9HOO FC CDB 410 HE SF.C 410 HE SN 74H10 N 74H10, 9H10 PC CDB 411 HE SF.C 411 HE SN 74H11.N 7411, 9H11 PC CDB 430 HE SF.C 430 HE SN 74H30 N 74H30, 9H30 PC CDB 440 HE SF.C 440 HE SN 74H40 N 74H40, 9H40 PC DB 440 HP SF.C 440 HP SN 74H40 W 74H40, 9H40 FC CDB 451 HE SF.C 451 HE SN 74HS1 N 74H51, 9H51 PC CDB 451 HP SF.C 451 HP SN 74H51 W 74H51, 9H51 FC CDB 454 HE S.C 454 HE SN 74HS4 N 74H54, 9H54 PC SN LTT. SIEMENS cit MIC 5472 MIC 7473 | Pa cil 8s cl MIC 5473 | 1 IC 7474 J FLY 141 MIC 7476 J FLJ 134 cll 74 cl MIC 7481 J Mic 7483 J FLH 241 es MIC 7486 J FLH 341 MIC 7490 J FLy 161 MIC 7492 J FLy 174 MIC 7493 ) F MIC 7495 J Fy 151 MIC 74121 J FLK 101 MIC 74192 J FLY 244 MIC 74193 J FLJ 251 cil 50 ct Cll 78 cl Cll 54 Cl cil a2 Cl Cll 58 Cl Cll 83 CI Cll 60 Cl 19CARACTERIZAREA CIRCUITELOR INTEGRATE LOGICE LOGICAL ICs' CARACTERIZATION SS NOTIUNI GENERALE VARIABILA LOGICA: marime fizicad. cu valori apartinind unui numéar finit de game disjuncte de valori. VARIABILA LOGICA BINARA: variabila logica cu doua game disjuncte de valori. SEMNAL LOGIC BINAR: ocu- parea momentana a unei anumite stari logice de catre o variabila logic’ binara. GAMA DE VALORI (STARE) JOS (Lt), GAMA DE VALORI (STARE) SUS (H) ale unei variabile logice binare: se stabilesc doud game disjuncte de valori ale varia- bilei_ logice binare astfel incit orice valoare apartinind gamei de valori JOS este mai mica, in va- loare algebrica, decit orice valoare apartinind gamei de valori SUS. LOGICA POZITIVA: logic in care se atribuie gamei de valori (starii) JOS starea logica 0" si gamei de valori (starii) SUS, sta- rea logicd 1". CIRCUIT LOGIC: circuit care opereazi. cu semnale logice la intrari si iesiri. 20 GENERAL NOTIONS DIGITAL VARIABLE: -a physical quantity having a value within a finit number of non-overlapping ran- ges of values. BINARY DIGITAL VARIABLE: a digital variable with only two non overlapping ranges of values. BINARY DIGITAL SIGNAL: tem- porary digital status of a binary digital variable. LOW (L) RANGE (STATE), HIGH (H) RANGE (STATE) of 2 binary digital variable: two ,non overlapping ranges of values for a binary digital variable are stipu- lated so that any value belonging to the LOW range (state) is smaller, as algebric value, than any other value belonging to the HIGH range (state). POSITIVE LOGIC: logical state 0“ corresponds to the LOW range (state) and logical state .,1" cor- responds to the HIGH range (state). DIGITAL CIRCUIT: circuit which is operating with digital signals at inputs and outputs. Rn OPERATIE LOGICA BINARA; FUNCTIE LOGICA BINARA: ope- catie efectuata asupra unor varia- bile logice binare dupa regulile algebrei binare (Boole) avind ca rezultat o variabila logicd binara care se numeste functie logica binara. TABEL DE ADEVAR: tabel de reprezentare a unei functii logice binare. TABEL DE FUNCTIONARE: tabel de reprezentare a relatiilor necesare sau posibile intre starile variabilelor logice binare de la intrarile si iesirile unui circuit logic binar. UNITATE DE SARCINA: con- sumul de curent al unei intrari aleas’ conventional, dintr-o familie TTL, astfel inctt consumul oricarei alte intrari din aceeasi familie TTL si fie multiplu al consumului intrarii conventionale Nota: se defineste, daca este —¥ I max —lon min > ¥ by min corespunzitoare cazurilor de func- tionare celor mai defavorabile. Fig. 7 ponding to the limits of the permit- ted and guaranteed voltage ranges must be specified (Fig. 8). max and I min for the inputs and Io.max and lowmin for the outputs have algebraic signification with the sign convention that inco- ming currents are positive. In order to associate two or more TTL circuits, the output currents of the driving gate and the input currents of the driven gates have to obey the next rules: lon max > — ¥ hy max lon min > ¥ he min corresponding to the worse case operating conditions. 2Capacitatea de tncarcare a iesirii (fan-out) unui circuit integrat TTL reflecté capacitatea iesirii acestui circuit de a absorbi curent in starea JOS si de a debita curent ‘in starea SUS. Curect de introre Input current Toate circuitele integrate TTL fabricate de 1.P.R.S.-Baneasa sint prevazute cu diode de limitare pe emitorii tranzistorului de intrare. Aceste diode limiteazi excursiile negative ale tensiunii de intrare pina la —1,5 V. Pentru micsorarea sensibilitatii la zgomot si optimizarea duratelor de comutare, intrarile nefolosite ale circuitelor integrate TTL 30 Ttheigh--— = z u £14 tensiune oe introre 4 t Input vollage Coren The fan-out capability of a TTL integrated circuit reflects its ability to sink current in the output LOW state and to source current in the output HIGH state. at de introre Lnpet corrent Fig. 8. 4 Tensiune de ntrore Trout voltege t Corea! oe iesire Output current | Tensiune de esire Output vaitoge All TTL ICs manufactured by 1.P.R.S.-Bdneasa incorporate input diodes. Each clamping diode is capable of limiting negative excursi- ons at the input to a maximum value of —1.5 V below ground. To minimize noise sensitivity and optimize switching times unused inputs of TTL ICs should be held between 2.4 V and the absolute EE ERE EE ES se conecteazé la o tensiune cu valoarea cuprinsa intre 2,4 V si valoarea limita 5,5V. Astfel se elimina efectele capacitatii distri- buite, asociati intrarii flotante si se evita degradarea duratelor de propagare. Moduri de conectare a intrarilor nefolosite: —se conecteaza intrarile nefolo- site la o sursd independenta de tensiune de 2,4V —3,5V; —se conecteaza intrarile nefolo- site la o intrare folosita dac& capacitatea de inc&rcare a iesirii circuitului care comanda nu este depasita. Fiecare intrare aditionala reprezinté o sarcind unitara, in starea SUS, pentru iesirea circui- tului care comanda; —se conecteaza intrarile nefolo- site la Vee printr-un rezistor de 1kQ, pentru a proteja intrarea in cazul’ aparitiei unor virfuri de tensiune mai mari de 5,5V. La fiecare rezistor pot fi conectate 25 de intrari nefolosite, Circuitele integrate TTL pre- vazute cu iesiri cu colectorul in gol permit realizarea functiei logice Sl-cablat. Pentru obtinerea acestei functii logice se conecteazd impreu- na iesirile cu colectorul in gol si apoi se leagi la Vcc printr-un re- zistor de sarcind. Valoarea acestui maximum 5.5 V. This eliminates the effect of the distributed capaci- tance associated with the floating input and ensures that no degrada- tion will occur in the propagation delay times. Possible ways of hand- ling unused inputs are: —connect unused inputs to on independent supply voltage in the range of 2.4 V to 3.5 V; — connect unused inputs to @ used input if fan-out of the driving output will not be exceeded. Each input presents a full load in the HIGH state to the driving output; — connect unused inputs to Vee through a 1 kQ resistor. If a transient exceeding the 5.5 V ma- ximum rating should occur, the impedance will be high enough to protect the input. One to 25 un- used inputs may be connected to each 1 kQ resistor. TTL ICs provided with open col- lector outputs permit the Wired- AND function. This is achieved by connecting open collector outputs together and adding an external pull up resistor. The value of the pull up resistor is determined by considering, the fan out of the 31rezistor depinde de capacitatea de incarcare a conexiunii $I si de numérul circuitelor care reali- zeaza functia considerata. Valoarea rezistorului se alege dintr-un do- meniu limitat de o valoare maxima (stabilita si mentina Voy garantat cind toate iesirile sint in starea SUS) si o valoare minima (stabilita astfel incit capacitatea de incar- care a legaturii $1 si nu fie dep3- gita cind o singura iesire este in starea JOS). Ri (max) AND tie and the number of ICs in the AND tie. The pull up resistor value is chosen from a range be- tween a maximum value (established to maintain the required Vox with all the AND tied outputs HIGH) and a minimum value (established so that the AND tie fan out is not exceeded when only one output is Low). Vcc min — Vou Ny low + Ne lia ‘ V. =v Ry (min) =: —Yeemax— Vou Ny lou — No tic Unde: rezistorul de sarcina numarul iesirilor cu colectorul in gol conectate impreuna numéarul unitatilor de sarcina ale intrérilor comandate curentul de iesire in starea SUS curentul de iesire, al unui ope- rator de comanda, necesar in starea JOS unitatea de sarcina in starea SUS unitatea de sarcina in starea JOS tensiunea de iesire in starea JOS (0,4 V) tensiunea de iesire in starea SUS @4 V) tensiunea de alimentare 32 where: external pull up resistor number of wired AND outputs number of input unit loads being driven output HIGH level current LOW level fan out current of driving circuit input HIGH level U.L. input LOW level U.L. output LOW level voltage (0.4 V) output HIGH level voltage (2.4 V) power supply voltage PARAMETRI. DEFINITII TENSIUNEA DE INTRARE IN STARE SUS: valoare a tensiunii de intrare apartinind gamei de valori SUS de tensiune. Se defi- neste o valoare minima a ten- siunii de intrare in starea SUS ca fiind tensiunea cea mai mica, in valoare algebricé, din gama de valori SUS de tensiune pen- tru care circuitul logic binar functioneaza in limitele specifi- cate. TENSIUNEA DE INTRARE IN STARE JOS: valoare a tensiunii de intrare apartinind gamei de valori JOS de tensiune. Se defi- neste o valoare maxima a ten- siunii de intrare in stare JOS ca fiind tensiunea cea mai mare, in valoare algebrica, din gama de valori JOS de tensiune pentru care circuitul logic binar functio- neaza in limitele specificate. TENSIUNEA PRAGULUI SU- PERIOR: valoare a tensiunii de intrare care, atinsa, la cresterea din starea JOS a semnalului de intrare, produce functionarea cir- cuitului in limitele specificate TENSIUNEA PRAGULUI IN- FERIOR: valoare a tensiunii de intrare care, atinsd, la descres- 3 — Catalog circuite integrate Vins Vi PARAMETERS. DEFINITIONS HIGH LEVEL INPUT VOLTAGE: an input voltage level within the HIGH voltage range. A minimum value of the HIGH level input vol- tage is specified which is the smallest algebraic value of the HIGH voltage range for which operation of the binary digital circuit with specification limits is guaranteed. LOW LEVEL INPUT VOLTAGE: an input voltage level within the LOW voltage range. A maximum value of the LOW level input vol~ tage is specified which is the grea- test algebraic value of the LOW voltage range for which operation of the binary digital circuit within specification limits is guaranteed. POSITIVE-GOING THRESHOLD VOLTAGE: the voltage level at @ transition operated input which, as the input voltage rises from the defined LOW level, causes operation of the digital circuit according to specification. NEGATIVE GOING THRESHOLD VOLTAGE: the voltage level at a transition operated input which, 33terea din starea SUS a semnalu- lui de intrare, produce functio- narea circuitului in limitele spe- cificate. TENSIUNEA DE IESIRE IN STAREA SUS: valoare a tensiunii de iesire pentru un anumit cu- rent de iesire lou si pentru con- ditiile de intrare necesare stabi- lirii starii SUS la iesire. TENSIUNEA DE IESIRE IN STAREA JOS: valoare a tensiunii de jesire pentru un-anumit cu- rent de iesire lo. si pentru conditiile de intrare necesare stabilirii starii JOS la iesire. TENSIUNEA DE IESIRE IN STAREA DE CONDUCTIE: o valoare a tensiunii de iesire pen- tru un anumit curent de iesire si pentru conditiile de intrare necesare aducerii tranzistorului de iesire tn starea de conductie. TENSIUNEA DE IESIRE IN STAREA DE BLOCARE: o va- loare a tensiunii de iesire pentru un anumit curent de iesire si pentru conditiile de intrare ne- cesare aducerii tranzistorului de iesire in starea de blocare. 34 Vou Vou Von Vort as the input voltage falls from the defined HIGH level, causes opera- tion of the digital circuit according to specification. HIGH LEVEL OUTPUT VOL- TAGE: the voltage at an output terminal for a specified output current Io. with input conditions applied which, according to the product specification, will establish @ HIGH level at the output. LOW LEVEL OUTPUT VOL- TAGE: the voltage at an output terminal for a specified output current Io. with input conditions applied which, according to the product specification, will establish a LOW level at the output. ON STATE OUTPUT VOLTAGE: the voltage of output terminal for a specified output current with input conditions applied which, accor- ding to the product specification, will cause the output transistor to be in the on state. OFF STATE OUTPUT VOLTAGE: the voltage at an output terminal for a specified output current with input conditions applied which, ac- cording to the product specifica- tion, will cause the output transis- tor to be in the off state. CURENTUL DE INTRARE IN STAREA SUS: valoare a curen- tului absorbit* de o intrare careia i se aplicé o tensiune apartinind gamei de valori SUS de tensiune. CURENTUL DE INTRARE IN STAREA JOS: valoare a curentu- lui absorbit* de o intrare careia i se aplic’ o tensiune apartinind gamei de valori JOS de tensiune. CURENTUL DE JESIRE IN STAREA SUS: valoare a curentu- lui absorbit* de iesire cind ten- siunea de iesire apartine gamei de valori JOS de tensiune. CURENTUL DE IESIRE IN STAREA JOS: valoare a curentu- lui absorbit* de iesire cind ten- siunea de iesire apartine gamei de valori JOS de tensiune. CURENTUL DE IESIRE IN STAREA DE CONDUCTIE: va- loare a curentului absorbit* de iesire pentru o anumita valoare a tensiunii de iesire si pentru conditiile de intrare necesare aducerii tranzistorului de iesire in starea de conductie. Nis he lou HIGH LEVEL INPUT CURRENT: the current flowing into* an input when a specified HIGH level vol- tage is applied to that input. LOW LEVEL INPUT CURRENT the current flowing into* an input when a specified LOW level. vol- tage is applied to that input. HIGH LEVEL OUTPUT CURRENT the current flowing into* the output with a resulting specified HIGH level output voltage. LOW LEVEL OUTPUT CURRENT: the current flowing into* the output with a resulting specified LOW level output voltage. ON STATE OUTPUT CURRENT: the current flowing into® the output with a specified output voltage applied and input conditions ap- plied which, according to the pro- duct specification will cause the output transistor to be in the on state. * Curentul debitat are valoare nega- tiva 3« * Current flowing out of @ terminal is a negative value 35AS ET CURENTUL DE JESIRE IN STAREA DE BLOCARE: valoare @ curentului absorbit® de iesire pentru o anumita valoare a ten- siunii de iesire si pentru con- ditille de intrare necesare adu- cerii tranzistorului de iesire in starea de blocare. CURENTUL DE SCURTCIR- CUIT LA IESIRE: valoare a curentului absorbit* de iesirea conectaté la mas& pentru con- ditiile de intrare necesare stabi- lirii starii SUS la iesire. CURENTUL DE ALIMENTA- RE PE CAPSULA CU IESIREA IN STAREA SUS: valoare a cu- rentului de alimentare a unui circuit integrat cind iesirea este (toate iesirile sint) in stare SUS CURENTUL DE ALIMEN- TARE PE CAPSULA CU IESI- REA IN STAREA JOS: valoare @ curentului de alimentare a unui circuit integrat cind iesirea este (toate iesirile sint) in starea Jos FRECVENTA MAXIMA DE TACT: valoarea cea mai mare a frecventei semnalului care co- manda, conform unei secvente lore lect OFF STATE OUTPUT CURRENT: the current flowing into* the output with a specified output voltage applied and input conditions ap- plied, which according to the pro- duct specification, will cause the output transistor to be in the off state. SHORT-CIRCUIT | OUTPUT CURRENT: the current flowing into* an output when that output is short-circuited to ground with input conditions applied to establish @ HIGH level at the output. SUPPLY CURRENT, HIGH LE- VEL OUTPUT: the current flowing into* the supply terminal of an IC when the output is (or all outputs are) at a HIGH level voltage. SUPPLY CURRENT, LOW LE- VEL OUTPUT: the current flowing into* the supply terminal of an IC when the output is (or all outputs are) at a LOW level voltage. MAXIMUM CLOCK FREQUEN- CY: the highest rate at which the clock input of a bistable circuit can be driven through its required * Curentul debitat are valoare nega- tiva 36 * Current flowing out of @ terminal is @ negotive value TE ate Rs NC CARNE anime Ay ye ne 1 1 SS cerute intrarea de tact a unui bistabil, mentinind tranzitii sta- bile ale starilor logice la iesire si respectind tabelul de functio- nare sau regulile logice speci- ficate. TIMPUL DE TRANZITIE DIN STAREA JOS IN STAREA SUS: intervalul de timp intre puncte de referinta specificate pe fron- tul unei forme de unda care evolueazi din starea JOS in starea SUS. TIMPUL DE TRANZITIE DIN STAREA SUS IN STAREA JOS: intervalul de timp intre puncte de referinta specificate pe fron- tul unei forme de unda care evolueazi din starea SUS in starea JOS. TIMPUL DE PROPAGARE LA TRANZITIA SEMNALULUI DE IESIRE DIN STAREA JOS iN STAREA SUS: intervalul de timp intre puncte de referinta spe- cificate pe formele de unda de intrare si de iesire cind semnalul de iesire evolueazé din starea JOS jin starea SUS. TIMPUL DE PROPAGARE LA TRANZITIA SEMNALULUI DE IESIRE DIN STAREA SUS iN STAREA JOS: intervalul de timp intre puncte de referinta spe- thy tet te tera: sequence while maintaining stable transitions of logic level at the output in accordance with the functional table or specified logic rules. LOW TO HIGH LEVEL TRAN- SITION TIME; the time interval between specified reference points on the edge of a waveform chan- ging from the defined LOW level to the defined HIGH level. HIGH TO LOW LEVEL TRAN- SITION TIME: the time interval between specified reference points on the edge of a waveform chan- ging from the defined HIGH level to the defined LOW level. LOW TO HIGH LEVEL OUTPUT PROPAGATION TIME: the time interval between specified refe- rence points on the input and output waveforms with the output signal changing from the defined LOW level to the defined HIGH level. HIGH TO LOW LEVEL OUTPUT PROPAGATION TIME: the time interval between specified reference points on the input and output waveforms with the output signal 37LE cificate pe formele de unda de intrare si de iesire cind semnalu de iesire evolueazi din starea SUS in starea JOS. DURATA MEDIE A IMPULSU- LUI: intervalul de timp intre punctele de referinta situate la 50% din amplitudinea impulsu- lui pe frontul anterior si pe frontul posterior al acestuia. TIMPUL DE MENTINERE: in- tervalul de timp pe durata caruia se mentine un semnal la o anu- mita intrare dupa ce s-a produs © tranzitie activa la o alta intrare specificata. Se specifica o valoare minima a timpului de mentinere ca fiind cel mai scurt interval de timp pentru care este garantata functionarea corecta a circuitului logic. TIMPUL DE PRESTABILIRE: intervalul de timp pe durata c4ruia se mentine semnalul apli- cat la o anumita intrare pina la producerea tranzitiei active la o alta intrare specificat’. Se spe- cific 0 valoare minima a timpu- lui de prestabilire, ca fiind cel mai scurt interval de timp pentru care este garantata functionarea corecta a circuitului logic. 38 tw teetup, changing from the defined HIGH level to the defined LOW level. AVERAGE PULSE WIDTH: the time interval between 50% ampli- tude points on the leading and trailing edges of a pulse. HOLD TIME: the time interval during a signal is retained at a specified input terminal after an active transition occurs at another specified input terminal. A mini- mum value of the hold time is specified which is the shortest interval for which correct opera- tion of the logical circuit is gua- ranteed. SET-UP TIME: the time interval between the application of a signal which is maintained at a specified input terminal and a consecutive active transition at another spe- cified input terminal. A minimum value of the set-up time is specified which is the shortest interval for which correct operation of the logical circuit is guaranteed. eam PE ince SIMBOLURI Tensiunea de intrare tn starea Sus. Tensiunea de intrare in starea Jos. Tensiunea pragului superior. Tensiunea pragului inferior. Tensiunea de iesire in starea sus. Tensiunea de iesire in starea Jos. Tensiunea de iesire in starea de conductie. Tensiunea de iesire in starea de blocare. Tensiunea de intrare inversa maxima. Tensiunea de alimentare. Tensiunea baza-emitor. Curentul de intrare in starea SUS. Curentul de intrare tn starea Jos Curentul de iesire in starea sus. Curentul de iesire in starea JOS. Vox Vou Von Vor Vi Vee SYMBOLS HIGH level input voltage. LOW level input voltage. Positive-going threshold voltage. Negative-going threshold voltage. HIGH level output voltage. LOW level output voltage. On state output voltage. Off state output voltage. Moximum reverse input voltage. Supply voltage. Base-emitter voltage. HIGH level input current. LOW level input current. HIGH level output current. LOW level output current. 39Curentul de iesire in starea de conductie. Curentul de iesire in starea de blocare. Curentul de scurtcircuit la iesire. Curentul de alimentare pe capsula. Curentul de alimentare pe capsul cu iegirea in starea SUS. Curentul de alimentare pe capsula cu iesirea in starea JOS. Curentul de expandare. Frecventa maxima de tact. Timpul de tranzitie din starea JOS in starea SUS. Timpul de tranzitie din starea SUS in starea JOS. Timpul de propagare la tran- zitia semnalului de iesire din starea JOS in starea SUS. Timpul de propagare la tran- zitia semnalului de iesire din starea SUS in starea JOS. Durata medie a impulsului. Timpul de mentinere. Timpul de prestabilire. 40 lon lost los lee Too try. teu, toot tw thoig teetup On state output current. Off state output current. Short-circuit output current. Supply current per package. Supply current per package, HIGH level output. Supply current per package, LOW level output. Expander current. Maximum clock frequency. LOW to HIGH level transition time. HIGH to LOW level transition time. LOW to HIGH level output propagation time. HIGH to LOW level output propagation time. Average pulse width. Hold-time. Set-up time. INFORMATII GENERALE GENERAL INFORMATIONSs Seria circuitelor integrate TTL produse de 1.P.R.S.-Baneasa este caracterizaté prin vitezd mare, imunitate ridicataé la zgomot, con- sum relativ mic de putere. Circuitele integrate din seria TTL standard oferé o buna combi- natie de viteza si disipare de putere (timp de intirziere pe operator: 10 ns; disipare de putere pe opera- tor: 10 mW). Seria cuprinde: operatori, circuite basculante, re- gistre de deplasare, numaratoare, decodificatoare, memorii si ele- mente aritmetice. Operatorii sint disponibili intr-o gama larga: ope- ratori $l, operatori SI-NU, inver- soare, operatori $I-SAU-NU, ex- pandere si operatori cu iesiri cu colectorul in gol. Seria include mai multe tipuri de circuite bista- bile (simple sau duble, cu bascu- lare pe front sau stapin-sclav, cu intrare tip D sau J-K) precum si un circuit monostabil. Sint incluse de asemenea numéaratoare asin- crone si sincrone (numératoare binare, divizoare prin 10, divi- zoare prin 12 si numéaratoare re- versibile). Seria circuitelor integrate TTL rapide include operatori caracte- rizati prin vitezi mare (timp de The 1.P.R.S.-Bdneasa’s TTL IC serie is characterized by a high speed, high noise immunity and relatively low power dissipation. The TTL standard ICs offer a good speed-power relationship (delay time per gate: 10 ns; power dissipation per gate: 10 mW). The series inclu- des: gates, flip-flops, shift registers, counters, decoders, memories and arithmetic elements. A broad selec- tion of gates is offered: AND gates, NAND gates, inverters, AND-OR- INVERT gates, expanders and gates with open collector outputs. The serie contains several flip-flops (single or dual, edge triggered or master-slave, with D type or J-K inputs) and a monostable circuit. Also included are asynchronous and synchronous counters (binary, divi- de-by-ten, divide-by-twelve and up] down counters). The TTL high speed serie includes gates having an improved delay time per gate (6 ns) achieved by the 4intirziere pe operator: 6 ns) asi- gurata de configuratia Darlington a etajului de iesire. Consumul de putere pe operator este de 22 mW. Circuitele integrate din ambele serii sint prevazute cu diode de limitare la intrari pentru a reduce efectele liniei de transmisiune. Gama de temperatura pentru aplicatiile circuitelor integrate TTL fabricate de |.P.R.S.-Baneasa este cea comercialé (0° C...-+70°C) iar unii operatori pot fi. livrati pentru folosirea in gama de tem- peratura militara. (—55° C +125° C). Circuitele sint incapsulate in capsula DIL din plastic (TO-116) iar unii operatori pot fi livrati si in capsula plata din ceramicd (TO-85). 42 Darlington output stage. The power dissipation per gate is of 22 mW. Both TTL standard and TTL high speed ICs are provided with clam- ping diodes at the inputs to minimize the transmission line effects. The TTL ICs manufactured by I.P.R.S.-Béneasa are available for use in comercial temperature range (0° C... +70° C) applications and several gates are available for use in military temperature range (—55° C.., +125° C) applications. These ICs are offered in DIL package (TO-116) and some of them also in Flat-package (TO-85). VALORI LIMITA ABSOLUTA ABSOLUTE MAXIMUM RATINGS ee ET VALORI LIMITA ABSOLUTA PENTRU SERIILE CDB 400 $1 CDB 400 H ABSOLUTE MAXIMUM RATINGS FOR CDB 400 AND CDB 400 H SERIES Tensiunea de alimentare 2. Tensiunea de intrare 55 Vi Gama temperaturii de lucru: sufix E si P 0° C...-70° C sufix EM si PM 55° C...4-125° C Gama temperaturii de sto- care: sufix E si P sufix EM si PM —55°C...-125° C Supply voltage Input voltage Operating temperature range: E and P suffix EM and PM suffix Storage temperature range: E and P suffix EM and PM suffix 43; STRUCTURA CODULUI DE MARCARE PATRU OPERATORI SI-NU CDB 400 FE ORDER INFORMATION CU CITE 2 INTRARI QUADRUPLE 2-INPUT NAND GATE CDB 400 EM ) Tap ba 0 an oe ye CONDITH DE LuCcRU Geo 6B | | | OPERATING CONDITIONS LI * high speed Tipul capsulei i | : DIL pl Package type DIL plastic fe we Fan-out | ae Le blias tet | 1a | Sama gemzeratri | Vel Ace ine Fetkage | Operating teres: | sain | pray sres 105] stares SUS ran-in| Peet pre: | | ee tee : Tae | Hesttane pentru circuite integrate 2, 3, 4 cifre definesc tipul C.I condo E| tots loca7ec fas visas) 40 | ae 1 logice vet a ms oo Ne 2, 3, 4 characters define the type | Standard prefix I.P.R.S. for of ic fi ” | CDB 400 EM| TO-116 | —55°C...4125°C|4.5 V [5.5 V | 10 20 1 paeies fees Toate intrarile ei sD pepe eres ea | All. inputs DLs eee +———__| Nimic | ates || | | SCHEMA ELECTRICA a Nothing * Standar | | | SCHEMATIC 4 rapid f ; H aye | | capsula plata: es * flat package 4 li ie sal he | eye ay CONFIGURATIA TERMINALELOR de lucru : | : 4h | PIN CONFIGURATION Opera ing temperature Nothing * OC...+ 70°C | ' FORgE ; 5 Capsula ro 446 Vedere de sus lt M 2 —55°C...+125° C Pockage Top view q “A 18 Mt 2A 2B = CWO 44 oss > &COB 400 £ CDB 400 £ COB 400 EM CDB 400 EM andino j9aaj wo; 03 y8jy ‘awn Aojap uonoBodorg suGEL sug Fauisal ap injnjeuwas e . 8 00F =u sof-sns eilizuea v} aieSedoud ap duty G andano_ aaa) sd gp= 7 y81y 01 Moy ‘own Ao/9p uo!oBodorg suqZ SU LL Hid asjgo! ap Injnjeuwas & sns-sof wiizues 2] aueedoud ap duty ‘ol xvid ¢AL SNOILIGNOD 1534 stoswWAs suaiawye! diz NIM SS23aIIGNeD — hinTOuhs Nignvuve OE RANE (oA Sa Araceae, SOIUSIYSLIVYVHD _DIWYNAG 3DINVNIG IDILSIYZLVYVD D St = Hey yu or— =" *bky aBoyor andy) asiovas wnw)xow L AsesSlial su A AL “dy MA BWIXBW Bsu@AU] 942I}U) Bp koUNIsUD) st AO='A “dh andino jana} y8/y aBoy204 yu g >>| ‘xem A yw» ‘dy HD) sns aueys ul vauiga! sad qwuasno Ajddns fa AS=IA “bh indino jansy Mo} —‘pinsde> od asey J vu 7 > “xew A oyu ZL “dix 199} sof aueys uy wauséa} -uausje ap yudun>, js ‘ duessn> S wussSlOlSvwor Ao=1A W3 00r 80D Indino ynd4j>-40Ys wuss Sywge, “xew A, vu Of oi 3 00F gad 31Nd419-3unds e{ alga] ap quaun> 5 SNOIIQNOD 1834 S3NIVA —_stoawas aL aww (2a1]120ds as}auayio seajun) Bus aimoradwer 4110-301) Buno1edo 4949 SDUSIYSLIVYVH * TVDINL9373 (22243409 ajyfeopuy puydarxa) nasn| ap tunyesadwied ewe wyPOD uj —3DMLDIIa IDLLSIAL WY = 7 10 ap sanjoa jo21dAi ry * ast = AS= PA 3B] UIs. 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SDUSMFLIVYVHD TWI1IIIF 391193749 ID1LsIwaLOVUVD 70°C |4,75 48 TO-116 k &, The maximum voltage which should be applied to any output in the off state. SCHEMA ELECTRICA *Tensiunea maxima care poate fi aplicata pe orice iesire OPERATING CONDITIONS CONDITH DE LUCRU Se 407 E SCHEMAT! TO-116 CONFIGURATIA TERMINALELOR PIN CONFIGURATION Capsula| J wz 3 | . = gs a BE lo > S ibis se Oo 3] e: eg = ion 3 2 - 2 sa gi- Sy SB} > w se < = SB& © 2 8 i Sec ere z z <8 ZOR Bo ae = 2 os > a (os 6 Ss ES 22 Seat 2 i Ez zo < r¢ = eZg ye = 9 a> oe 28 2 E ra ese ws ee ee o ee Owe a uw a a RS z SER =o a 5, iu 23 ° ZOG Es og | 2 | £8 Bama one ao of O.. | 2S > BS Zz 22 3 oe : oS Oz Fs va oa yndino jana mol 0 ySty ‘ousya oBodoxd sugz su LL vou=w Way ap ininy -pulas Rasopers Bedoud op dusty €s dino. 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B4e4;U! ap eaUNIsUDL AS= "A “dh andino jaray_ysiy 2804204 se vw st > “xew A yuoL “diz HOD] sns eases uy wastsa! 40d quassna Ajddng o='A “dh andino jaa} moj — ‘insde> ad auey se yu oz S| ‘xew 2, yug, ‘dit 129) sof voueys Uy Raujga! -vouije ep quesnD i SNOILIGNO> 1534 sania snoswas suaianvuvd 4531 30 NLIGNOD eOTVA TNTIORNIS Mawel SIUSMBLIVYVHD TWI193979 3919193913 IDNLSIWaLOVYVS (parjrads asimiaygo ssajun) aBuos amosaduiar 4/0-201} Bunosado 4940, (G4es}U0> 9}1/4e21pu! pulada>xe) nudn| ap 1jngesadwiay EWeE ¥E0r Uy" 10 340 sanjon 102104 Wy Ds7= '‘AS=>A sR] WUys a2IdIy ai4ojea eyeoy y AS = IA quasin> andino 3yn24)2-10ys be yusgS}OlSvue, | “xew 2, yw of $0, y4nd4j>4unds e| oaisa! ap yuaun> ASS=IA 3D quasin> ynduy wnuyxow fe yw st *xew >A yu 4 A S'S &] wyxew asesqu! ep yueinD ATS IA 3 2uasn> indus winwsxoy €€ vior Ss 4 sxe A, ve ob Cul) cur HO, ey wixew asenu! ap quaun>. ArO='A 3 quawand anduy wnuxoy ze yu ott Sh] sxew AQ yu gtt— — (-xew 7) ty) *xew TO, ey wyxew aueuzu! ap yuain>, 3 quasin> yndino wnusjuy ww g'o— =% yur gto— (rum yy) ujpwHO, ey wiusw ouisa! ap quaun> 80y0n mndino yaaa] yB}y winutusyy te A¥TEM At= Ave w HOA, SMS Radeys UL Byequeses eWiuW auige! ep eunisual. aBoxon anduy jana y3iy wnwruiyy sup >,, Ate sun HIA SMS easeIS UL rwJad eujUIW euez.U! ap aunIsuay 3D quayunD indyno wnwUW yu p= % yu ge (Kew a)9} *xeW 1A ey oulga} ap wHUIW quBIN> ‘a80xJ0n andino jana Moy wnw)xoW Of A ¥'0 > SA A 8'0 = 'A A v0 sxew TO, sof easeys ub mequrse8 pwyxew aaa} ep ounisual 380304 anduy jana} Moy winui)xoy suys A, A8'0 xew MA, sof waseys UL gsjuuad puyxew auesul ap eounisual ‘ou SNOLLIONOD 1S31 sanivA —sToaWas suaLawyuve 4531 30 NLIGNOD eOIWA = WMTOSWIS NLGW (pay)j2ads asrmsayio ssajun) aBuos asmosadwiay 110-094) Bunosedo 1940 SILSIYFLIVYVHD TWIMLIIIA (218134109 9}114e21pu! puyydedxe) naan} op Hunyesadwiay ewes ey07 Uy 3D1WL93973 |D1LSIWaLIVYVD 64 5 — Catalog circuite integrateCDB 409 £ PATRU OPERATORI $I CU CITE 2 INTRARI, IESIRI CU COLECTOR IN GOL (5,5 V) QUADRUPLE 2-INPUT AND GATE WITH OPEN COLLECTOR OUTPUT (5,5 V) TER EE RST CONDITI DE LucRU OPERATING CONDITIONS v, Gama temperaturii |. wea Tip Gappula | Ode lucra 7 Tree package | Obmating tomers | arn. | 4, | | cos 409 £ | To-116 | oc, 470°C [4.75 v/5,25 v] 5.5.V | 16 mA [4 55.v | 16 ma | 1 icDB 409 PM| To-85 |—Ss°c, + 125°Cl4,75 v'5,25 VI *Tensiunea maxima care poate fi aplicata pe orice iesire in starea blocats The moximum voltoge which should be opplied to any output in the off state. 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S 4 en ws a a5 ze =! ee oe =9 oF <4 So ro CONDITII DE LUCRU OPERATING CONDITIONS | in starea jos Low stote outpui Sg Min, Gama_temperaturii de lucru Operating tempera- ture range Package Capsula Tip Type 4,75, 4 +70° C v & ~~ < = 9 3} = F 5 a w ct 0 WO. a JY GND WY ZA OY SA 72Fan-in| 1 | Curent de iesire in starea JOs Low: state output current 40mA CDB 417 E Tensiune de iesire® Output voltage 15V | Mex. v, 4.75 ee y Min. +70 C de lueru Operating -tempero- | ture range Gama temperaturii oc... *Tensiunea maxima care poate fi aplicata pe orice iesire in starea blocata. Copsula Packore Type | cB 417 | TO-A16 Tip The maximum voltage which should be opplied to any output in the off state. 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WIXeW @sjS9! 9p yUeIND ‘8802/04 yndino wnw)xow 9025-4 atjanpuo> ep ly Ar'o>”A A v0 WA paeys ul PUIXeW du!se! Op auUNisuE) aBoron anduy jaro] moj wnwixow a A8'0 *XeW NA sof vauRys Uy a4eszU! ep puIL in i. raport cu masa, Arrows jedicate octual direction of current flow, voltoges ore measured ogainst_ ground fermin« 13OPERATORI GATES CIRCUITE DE TEST TEST CIRCUITS h. i> iL Pe = Fig. 41 Fiecare intrare este tes- Fig. 42 Fiecare operator tatd separat este testat separat Each input is tested sepa- Each gote is tested rately separately Sagetile indicd sensul real al curentului, tensinnile sint masurate in raport cu masa. Arrows indicate actual direction of current flow, voltages are measured against ground terminal 14 OPERATORI GATES SS: CIRCUITE DE TEST TEST CIRCUITS Fig. 47 Toate intrarile sint testate simultan All inputs are tested simultaneously Sagetile indicd sensul real al curentului, tansiunile sint masurate tn raport cu masa. Arrows indicate actual di Aras rection of current flow, voltoges ore measured against ground c 115OPERATOR! GATES pepe RN EE EE ES CIRCUITE DE TEST TEST CIRCUITS y 4 Meg y - Ingol Open [ae 4 J Xe ‘on = R ‘ h Fig. 48 Fiecare intrare este tes- Fig. 49 tatd separat Each input is tested sepa- rately he Ke de 4 Ingo! | ‘oc ge y Open pen 4 y Fig. 50 Fiecare intrare este testata Fig. 51. Fiecare operator este testat | separat separat ' Each input is tested separa Each gate is tested sepora- tely tely ile indi i, tensiuni In raport cu masa. Sigetile indic& sensu! real al curentului, tensiunile sint masurate Artons indicate actual direction of current flow, voltages are. measured against: ground terminal 116 OPERATOR! GATES Fig. 52 Note: Notes: $2 aw w tps « Generatorul are urmatoarele caracteristici: The generator has the following characteristic te = Sons; t, = 10 ns; tw =0,5us; f=1 MHz; Z=50 0 Toate diodele sint 1 N 3064 All diodes are 1 N 3064 tem + tou Cy include capacitatile sondei si ale montajului Cy includes probe and jig capacitance . Toate intrarile neutilizate la testarea circuitelor CDB 400... CDB 440 sint conectate la 2,4 V. Pentru circ le CDB 450... CDB 454 impulsul de intrare se aplic’ pe una dintre intrarile unei sectiuni SI, celelalte intrari fiind la 2,4 V, Toate intrarile sectiunilor SI neutilizate sint la masa. When testing the CDB 400 through CDB 440 connect all unused inputs to 2.4 V. When testing the CDB 450 through CDB 454 apply the input pulse to one input of one AND section and 2,4 V to all unused inputs of that section. All inputs of unused AND sections are grounded. uzOPERATORI GATES lesire Output goles | | neering | ! ae 6 Operators | PtH eiversot | Won inverting gates | lesire Fig 53 pet Note: 1. Generatorul are urmitoarele caracteris Notes: The generator hos the following characteristics: ty =5 ns; t. =10 ns; ty = 05s; f=1 MHz; Z=50 2 t ty 2. ty = eat PL 3. C, include capacitatile sondei si ale montajului Ci includes probe and jig copacitance 118 OPERATOR! GATES lesire tmpuisur! (vezinota f) Lxponder testot 7 Liponder inder test Fig. 54 Note: 1. Generatorul are urmatoarele caracteristici: Notes: The generator has the following characteristics: t =5 ns; t. = 10 ns; t, = 0.5us; f=1 MHz; Z=50 9 t + ty 2. tg = tebe teu > ‘ 3. Cy include capacitatile sondei si ale montajului Cx includes probe and jig capacitance 119