GANPAT UNIVERSITY

FACULTY OF ENGINEERING AND TECHNOLOGY

Programme Bachelor of Technology Branch/Spec. Information and Communication
Technology
Semester V Version 1.0.0.0
Effective from Academic Year 2019-20 Effective for the batch Admitted in 2017-18
Subject code 2ICT504 Subject Name Digital Design using HDL
Teaching scheme Examination scheme (Marks)
Lecture Practical
(Per week) Total CE SEE Total
(DT) (Lab.)
L TU P TW
Credit -- -- 2 -- 2 Theory -- -- --
Hours -- -- 4 -- 4 Practical 60 40 100
Pre-requisites:
Digital Electronics
Learning Outcome:
After successful completion of course students will be able to:
 Describe, design, simulates, and synthesizes computer hardware using the Verilog
Hardware description language.
 Design combinational and sequential logic that works.
 Design complex state machines (present in all practical computers) that work.
 Synthesize logic and state machines using an Automatic Logic Synthesis program.
 Implement state machines using Field-Programmable Gate Arrays, high-speed computer
arithmetic circuits, computer to be fault-tolerant, computer memory using error-correcting
codes, computer so that it can test itself with built-in circuitry, finite state machines.
Laboratory Contents :
Unit Content Hrs
Overview of Digital Design with Verilog® HDL
1 2
Emergence of HDLs, typical HDL-based design flow, Importance of HDL, trends in HDLs.
Hierarchical Modelling Concepts
2 Top-down and bottom-up design methodology, differences between modules and module 2
instances, parts of a simulation, design block, stimulus block.
Basic concepts
3 Lexical convention, number specification, strings, identifiers data types, system tasks and 3
compiler directives.
Modules and Ports
4 Module definition, port declaration, connecting ports, hierarchical name referencing. 4
Gate-Level Modelling
5 Modelling using basic Verilog gate primitives, description of and/or and buf/not type gates, 3
rise, fall and turn-off delays, min, max, and typical delays.
Dataflow Modelling
6 3
Continuous assignments, delay specification, expressions, operators, operands, operator types.
Behavioural Modelling
Structured procedures, initial and always, blocking and non-blocking statements, delay control,
7 6
generate statement, event control, conditional statements, multi-way branching, loops,
sequential and parallel blocks.
Tasks and Functions
8 3
Differences between tasks and functions, declaration, invocation, automatic tasks and
 functions.
Useful Modelling Techniques
9 Procedural continuous assignments, overriding parameters, conditional compilation and 2
execution, useful system tasks.
Timing and Delays
10 Distributed, lumped and pin-to-pin delays, specify blocks, parallel and full connection, timing 2
checks, delay back-annotation.
Tentative List of Practicals :
Write a Verilog code for Elementary Digital Logic Circuits, compile, synthesis and simulate the design and
writing of test bench for each block. Also download the same in CPLD and Test the operation.
1. Adder and Subtractor (data flow, behavioural and structural modelling).
2. 2:1 and 4:1 Multiplexer and 1:2 and 1:4 De multiplexer.
3. 2 to 4 and 3 to 8 Decoder.
4. 8 bit parity generator.
5. 3 bit adder which can also perform subtraction.
6. 4 bit magnitude comparator.
7. 5 bit binary divider
8. Synchronous and asynchronous D-FF, SR-FF and JK-FF.
9. Master slave JK flip flop using JK flip flop.
10. 4 bit synchronous up/down counter.
11. 4-bit ripple carry full adder and ripple carry counter using structural modelling.
12. 8 to 3 priority encoder.
13. 8 bit BCD to excess-3 code converter.
14. 4 bit parallel loading shift register.
15. 3 bit sequence detector (sequence is 100).
Text Book:
1 Verilog HDL By Samir Palnitkar (Pearson Education).
Reference Books:
1 Verilog HDL Primer By Bhasker J. (B.S.P., Hyderabad).
2 Verilog HDL Synthesis By Bhasker J. (B. S. P., Hyderabad).
3 Verilog Quick start By Lee James M. (Springer, New Delhi).
Mooc :
1 https://nptel.ac.in/courses/106105083/