Audio   Effect:   Haas   Delay 
Christopher   Hogan   &  PJ   O’Sullivan 
Final   Report   ENGS   31 
 

   

 
  
 
 
2 

Abstract 

The   haas   delay   effect   is   a  sound   engineering   technique   used   to   increase   a  track’s   width   in   the 

stereo   field   of   a  mix.   Our   device   receives   12­bit   mono   audio   and   outputs   12­bit   stereo   audio. 

With   two   buttons,   the   user   controls   the   delay   amount,   reflected   in   ms   on   the   device’s   display.   The 

incoming   audio   is   duplicated   into   a  left   and   right   channel,   and   the   resulting   right   channel   is 

delayed   by   the   specified   amount   before   output,   creating   the   audible   haas   effect.   
  
 
 
3 

Table   of   Contents 

1. Introduction 4 
2. Design   Solution 4 
2.1. Specifications 4 
2.2. Operating   Instructions 5 
2.3. Theory   of  O
  peration 5 
2.4. Construction   and   Debugging 8 
3. Evaluation 9 
4. Conclusions 10 
5. Acknowledgements 10 
6. References 11 
7. Appendices 12 
7.1. Appendix   A:   Front   Panel 
7.2. Appendix   B:   Block   Diagrams 
7.3. Appendix   C:   State   Diagrams 
7.4. Appendix   D:   Simulation   Waveforms 
7.5. Appendix   E:   Parts   List 
7.6. Appendix   F:   VHDL   Code 
7.7. Appendix   G:   VHDL   Testbench   Code 
7.8. Appendix   H:   Resource   Utilization 
7.9. Appendix   I:   Analysis   of   Residul   Warnings 
7.10. Appendix   J:   Datasheets 
 
 
   
  
 
 
4 

1. Introduction 

Our   project   was   to   create   a  hardware   implementation   of   haas   delay,   an   integral   production 

technique   in   contemporary   sound   engineering.   The   haas   effect   as   implemented   here   involves 

taking   a  mono   input   signal,   duplicating   it,   and   delaying   one   of   the   resulting   channels   by   a  small 

amount,   creating   the   illusion   of   distance   attenuation.   This   illusion   makes   the   signal   appear   to   be 

emanating   from   multiple   sources   surrounding   you,   affording   the   sound   a  much   wider   space   in   the 

stereo   field.   By   gradually   increasing   the   intensity   of   the   effect   through   incrementation   of   the 

delay   time,   the   user   is   able   to   better   understand   the   nature   of   this   omnipresent   yet   often   subtle 

effect.  

2. Design   Solution 

2.1. Specifications 

Our   design   takes   an   auxiliary   audio   input   and   routes   it   through   a  transformer,   balancing   the   audio 

and   translating   only   the   left   channel,   resulting   in   a  12­bit   mono   audio   signal   that   is   then   routed 

into   the   FPGA   via   a  dual­RCA   port   and   a  PMOD   AD1.   The   amount   of   haas   delay   implemented 

is   a  user   selected   amount   from   0  to   20ms   than   can   be   incremented   or   decremented   by   pressing   an 

“up”  b  utton   or   a  “down”  b  utton;   the   amount   of   delay   is   displayed   on   the   Basys   3  seven   segment 

display.   The   processed   audio   is   output   from   the   board   in   stereo   through   two   dual_RCA   ports   and 

two   PMOD   DA2’s   before   being   funneled   through   another   transformer   and   into   headphones   via   a 

TRS   quarter   inch   output.  T
  hus,   an   audio   source   and   two   buttons   are   required   for   input,   and   a 

display   engine   and   headphones   are   required   for   output.   See   Appendices   A  and   B  for   more   detail 

 
  
 
 
5 
2.2. Operating   Instructions 

● Connect   a  Basys   3  FPGA   (with   a  PMOD   AD1,   two   PMOD   DA2’s,   and   respective   RCA 

ports   connected)   and   program   the   haas   bitstream.   Ensure   that   the   off   board   components 

(transformers   and   necessary   audio   connections)   are   assembled   properly.   See   Appendix   A 

● Connect   an   audio  s  ource   to   the   3.5mm   auxiliary   jack   and  h  eadphones   to   the   3.5mm   port 

converted   from   the   RCA   outputs   of   the   post­DAC   transformer.   You   should   hear 

undistorted   audio   when   your   source   plays.   If   the   output   is   clipping,   turn   down   the   volume 

of   the   input. 

○ Note:   The   haas   delay   effect   is   best   demonstrated   using   simpler   signals   (e.g.   single 

instruments,   pure   tones)   than   complex   ones   (e.g.   full   band   recordings).   Further, 

haas   delay   is   most   easily   observed   using   headphones.   If   you   choose   to   connect 

speakers   instead,   make   sure   to   use   two   and   spread   them   apart   at   least   four   feet. 

● Use   the   up   and   down   buttons   on   the   Basys   3  to   control   the   amount   of   haas   delay   affecting 

your   input.   The   startup   default   is   the   maximum   amount,   20ms,   of   delay.   0ms   of   delay   is 

the   minimum   amount,   effectively   turning   off   the   haas   effect. 

2.3. Theory   of  O
  peration 

Our   device   takes   a  mono   audio   signal   and   channels   it   through   an   analog   to   digital   converter, 

converting   serial   bits   in   to   parallel   vectors   out.   The   single   12­bit   std_logic_vector   output   from 

the   ADC   is   then   split   into   two   signals;   the   first   runs   directly   to   the   left   channel   digital   to   analog 

converter,   and   the   second   runs   into   the   haas   engine,   the   source   of   our   delay.   The   haas   engine 

enacts   delay   by   continuously   writing   the   input   data   to   a  dual   ported   RAM   with   a  simple   11­bit 
  
 
 
6 
write   address   counter   and   reading   previously   written   bits   according   to   desired   delay   time. 

Desired   delay   time   is   defaulted   to   a  maximum   20ms   and   controlled   from   there   by   two   input 

buttons,   up   and   down.   These   inputs   cause   state   changes   within   the  b
  uttons 
  controller, 

updating   the   delay   amount   sent   to   the   haas   engine’s   subtractor   for   figuring   which   RAM   address 

will   be   read.   The   12­bit   output  d
  ata_bus_out 
  from   the   haas   engine   is   connected   to   the   input 

of   the   right   channel   digital   to   analog   converter.   Each   DAC   takes   12­bit   vector   inputs   and   outputs 

a   stream   of   serial   information   through   two   PMOD   DA2’s,   creating   stereo   imaged   audio   with 

haas   delay. 

ADC   Block 

The   Analog   to   Digital   Converter   block   takes   in   two   streams   of   single   bit   audio   information   from 

the   balanced   (positive   channel   and   negative   channel)   mono   input  v  ia   the   PMOD   AD1.   Our 

sample   rate   trigger  t
  ake_sample_sig 
  activates   a  load   cycle   44,100   times   per   second,   each 

cycle   taking   a  series   of   input   bits.   Each   load   cycle   is   fifteen   counts   as   dictated   in   the   ADC   state 

machine,   taking   the   incoming   bit   information   (ignoring   three   prefix   bits)   and   sending   it   to   the 

ADC   shift   register.   The   shift   register   loads   and   shifts   twelve   bits,   producing   12­bit 

std_logic_vectors   to   be   passed   along   to   ADC   out   registers.    Before   output,   the   ADC   subtracts   the 

negative   vector   from   the  p  ositive   vector   and   yields   a  single   output   signal    ,  eliminating 

bal_out 

power   supply   noise.  

Haas   Engine   Block 

The   haas   engine   block   uses   a  counter,   a  dual   ported   ram,   and   a  subtractor   to   intake   12­bit   vectors 

and   output   them   after   a  specified   delay   time.   The   counter   increments   from   0  to   1023   and   writes 

incoming   information   into   the   dual   ported   ram,   instantiated   as   a  1024   address   array   of   12­bit 
  
 
 
7 
vectors.   The   block   takes   in  d
  elay_amount 
 f rom   the   controller   and   feeds   it   to   the   subtractor, 

which   subtracts   the   number   of   addresses   correlating   with   desired   delay   Y  from   the   current   write 

address,   providing   a  read   address   that   outputs   the   vector   from   Y  ms   ago. 

DAC   Block 

Two  D
  AC’s   are   instantiated,   one   for   stereo   left   output   and   one   for   stereo   right   output.   The   DAC’s 

serve   the   opposite   function   of   the   ADC’s,   taking   in   12­bit   std_logic_vectors   and   outputting   a 

serial   stream   of   bits   to   PMOD   DA2   headers   using   shift   registers.   Before   input   to   the   DAC   shift 

registers,   incoming   vectors   are   duplicated.   One   of   the   two   vectors   is   inverted,   yielding   one 

positive   and   one   negative   vector   for   balanced   output   to   each   channel’s   RCA   ports.   1024   is   added 

to   both   vectors   (through   a  cast   to   unsigned   and   back)   to   account   for   the   earlier   balancing   and   DC 

offset,   and   both   vectors   are   affixed   with   two   prefix   bits:   “00”.   These   14­bit   vectors   are   passed 

into   the   DAC   shift   registers   once   every  t
  ake_sample_sig 
  assertion   before   the   latter   12­bits 

are   shifted   out   serially   according   to   the   15   count   cycle   as   detailed   by   the   DAC   state   machine. 

Controller:   Delay   Buttons 

The   controller   keeps   track   of   the   desired   delay   in   ms   as   determined   by   the   user,   and   it   calculates 

the   number   of   addresses   to   be   subtracted   in   the   haas   engine   block,  a
  ddress 
.  address 
   is   a 

product   of   constant  S
  AMPLE_PER_MS 
  (set   to   44   in   our   case   for   44.1KHz   sampling   rate)   and 

integer   delay_ms 
.  The   controller   takes   inputs   from   up   and   down   buttons,   and   it   outputs 

address 
  to  h
  aas_engine 
  as   well   as   numeric   information   to   the   display. 

Display:   Mux   7  Seg 

The   controller   outputs   two   4­bit   signals,  t
  ens 
  and  o
  nes 
,  to   the  M
  UX   7  segment   display,   which 

in   turn   communicates   which   digits   and   segments   on   the   Basys   3’s   display   to   activate   based   on 
  
 
 
8 
the   user   selected   delay   amount  d
  elay_ms 
.  Because   the   maximum   delay   is   20ms,   the   hundreds 

and   thousands   places   are   assigned   to   “0000.” 

Minor   Processes 

The   following   minor   processes   were   implemented   in   the   top   level: 

Monopulsers:  b
  utton_up 
  and  b
  utton_down 
  inputs   are   monopulsed,   or   returned   to 

low   only   one   clock   cycle   after   being   asserted,   before   being   sent   to   the   buttons 

controller. 

Clock   Dividers:   The   serial_clock 
  signal   is   divided   down   2.38MHz   out   of   mclk 

from   Basys   3,   and   in   turn   the  t
  ake_sample_sig 
  signal   is   divided   to   44.1Khz   out   of 

  (and   monopulsed). 
serial_clock 

2.4. Construction   and   Debugging 

When   it   came   time   to   construct   a  hardware   version   of   this   effect,   we   knew   a  few   key   things 

needed   to   be   present:   a  ADC/DAC   for   getting   audio   into   and   out   of   the   effect,   a  display   to   show 

the   delay   amount,   and   buttons   to   increase   or   decrease   the   delay   amount.   The   meat   and   bones   of 

the   project   is   of   course,   the   haas   engine   itself,   which   we   ultimately   decided   to   model   after   a  large 

shift   register.    In   deciding   how   to   instantiate   the   RAM,   we   chose   to   create   a  large   enough   array 

and   let   Vivado   decide   how   to   best   construct   RAM   as   opposed   to   manually   selecting   a  RAM   from 

the   IP   catalog. 

Testbenching   the   controller   and   haas   delay   was   easy   and   straightforward.   The   biggest 

challenge   of   the   project   was   simulating   and   debugging   the   ADC/DAC   portion   of   the   circuit.   It 

was   difficult   just   to   get   the   right   stream   of   bits   being   sent   to   the   ADC/DAC,   and   timing   issues 
  
 
 
9 
made   up   for   about   half   the   debugging   time.   In   addition   to   the   tricky   timing   issues,   we   also   had   to 

handle   a  DC   offset   issue.   The   chips   only   wanted   to   see   audio   above   0  volts,   however   audio 

comes   in   a  form   that   is   centered   around   0  volts.   To   solve   this   issue,   we   used   a  subtraction 

technique   that   balances   audio.   By   subtracting   the   inverted   from   the   original   signal,   we   were   able 

to   manipulate   the   result   to   be   above   0  volts   coming   out   of   the   ADC,   and   then   convert   it   back   in 

the   DACs   after   the   delay   process.   Additionally,   even   after   we   got   the   conversion   process   going, 

we   were   still   faced   with   massive   noise   and   distortion.   To   solve   this   problem,   we   connected   the 

positive   and   negative   pins   to   VCC   and   ground   respectively   with   1k   resistors,   which   almost 

completely   took   away   the   distortion   problem.   After   that,   implementing   the   haas   engine   was   very 

straightforward.   We   tied   in   all   the   code   in   the   port   maps   and   debugged   minimal   errors.   It 

performed   perfectly,   a  welcome   relief   after   the   long   (and   painful)   debug   process   of   the 

ADC/DAC.  

3. Evaluation 

In   general,   our   implementation   of   the   haas   delay   is   clean   and   simple.   We   think   our   design   for   the 

shifting   register   was   a  simple   elegant   solution   to   the   problem   of   instantiating   ram.   Our   initial 

plan   was   to   manually   instantiate   a  dual   ported   RAM   to   handle   the   delay   module,   but   we   quickly 

realized   that   would   have  b  een   more   complicated   than   a  simple   (albeit   large)   shift   register.   If   we 

had   to   do   this   again   with   unlimited   resources,   we   would   change   the   way   we   handled   the 

analog­digital­analog   conversion   by   using   different   chips   that   didn't   require   the   workarounds   we 

had   to   implement,   such   as   tying   resistors    around   the   legs   of   the   pins   on   the   AD1.  

 
  
 
 
10 

4. Conclusions 

At   the   end   of   this   project,   we’ve   accomplished   our   goal   of   creating   a  working   haas   delay 

effect   module   complete   with   display   and   user   input   buttons.   Our  f  inal   device   is   identical   in 

behavior   to   our   proposed   device   despite   various   minor   design   adjustments.  

Although   we   came   out   strong   with   a  well   drafted   implementation   of   our   design,   we   made 

the   unfortunate   mistake   of   bypassing   bottom   up   simulation   in   an   attempt   to   patch   everything 

together   first   try.   This   was   a  lesson   learned   week   after   week   in   lab,   yet   in   our   end­of­term 

excitement,   ignored   one   final   time.   In   the   end,   we   had   to   start   a  clean   Vivado   project,   building 

and   testing   each   component   ground   up   as   we   should   have   done   all   along.   What   could   have   been 

a   casual   week   or   two   of   design   and   testing   turned   into   a  grueling   pair   of   nine   hour   work   nights. 

For   groups   potentially   interested   in   recreating   our   project,   we   would   strongly   suggest   creating   a 

functional   AD   to   DA   path   before   pursuing   any   other   implementation. 

5. Acknowledgements 

We   would   like   to   thank   Professor   Hansen,   Dave   Picard,   and   Liam   Feeney   for   their   time 

consulting   and   aiding   in   the   execution   of   our   project.   We   would   also   like   to   thank   William 

Hogan   for   helping   us   improve   the   sound   quality   through   our   device   and   for   treating   us   to   lab 

refreshments   during   our   final   debugging   session.  

 
  
 
 
11 
PJ   would   like   to   thank   his   parents   Cheryl   and   Joseph   O’Sullivan   for   showing   him   enough 

attention   as   a  child,   allowing   him   to   flourish   in   his   young   adulthood   without   the   burden   of 

unconscious   insecurity. 

Chris   would   like   to   thank   his   sponsors,   Pioneer   DJ   and   Orgain.   Drink   Orgain;  c  lean,   great   tasting 

and   convenient   protein   and   nutrition   made   with   the   highest   quality   ingredients. 

6. References 

We   heavily   implemented   ADC   code   from   Chris   Hogan   and   Max   Wieland’s   ENGS   31   Lab   5. 

Further,   we   directly   used   the   code   for   the   MUX   7  segment   display   as   written   by   Professor 

Hansen   and   included   in   several   previous   labs.   Other   references   were   limited   to   previous   labs   and 

lectures   from   ENGS   31. 

   
  
 
 
12 

7. Appendices 
Appendix A: Front Panel
Appendix B: Block Diagrams
Appendix C: State Diagrams
Appendix D: Simulation Waveforms
Appendix E: Parts List

Parts List:

1x Audio source (Apple iPhone 5S)

1x 3.5mm Stereo to Dual RCA Adapter Cable (“Aux” Cable)
2x ARTccesories DTI Dual Transformer / Isolator
3x Stereo XLR to RCA Cable
3x CON4
1x PMOD AD1
2x PMOD DA2
1x Basys 3 FPGA
1x Dual RCA to 3.5mm Female Adapter cable
1x 3.5mm male to 1/4 inch TRS female adapter
1x 1/4 inch TRS male to stereo mini XLR
1x Pioneer HDJ-2000 Headphones
Appendix F: VHDL Code
1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: adc_out_reg.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21
22 -----------------------------------------------------------------------
23 ------------------------Library Declaration----------------------------
24
25 library IEEE;
26 use IEEE.STD_LOGIC_1164.ALL;
27 use ieee.numeric_std.all;
28
29 -----------------------------------------------------------------------
30 ------------------------Entity Declaration-----------------------------
31
32
33 entity adc_out_reg is
34 port(
35 clk: in std_logic; --clock
36 enable: in std_logic; --enable
37 d: in std_logic_vector(11 downto 0); --data bus coming in
38 q: out std_logic_vector(11 downto 0) --data bus going out
39 );
40 end adc_out_reg;
41
42 -----------------------------------------------------------------------
43 ------------------------Architecture Declaration-----------------------
44
45 architecture behavior of adc_out_reg is
46
47 -----------------------------------------------------------------------
48 -------------------------------Logic-----------------------------------
49 begin
50 process (clk, enable)
51 begin
52 if rising_edge (clk) then -- on the rising edge of the clock
53 if (enable = '1') then -- if enable is high
54 q <= d; -- copy the incoming data bus to the outgoing data bus
55 end if;
56 end if;
57 end process;
58
59 end behavior;
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: adc_shift_reg.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21 -----------------------------------------------------------------------
22 ------------------------Library Declaration----------------------------
23
24 library IEEE;
25 use IEEE.STD_LOGIC_1164.ALL;
26 use ieee.numeric_std.all;
27
28 -----------------------------------------------------------------------
29 ------------------------Entity Declaration-----------------------------
30
31 entity adc_shift_reg is
32 port(
33 clk: in std_logic; --clock
34 data_bit_in: in std_logic; --incoming data bit
35 enable: in std_logic; --enable for shifting
36 data_bus_out: out std_logic_vector(11 downto 0) --bus output
37 );
38
39 end adc_shift_reg;
40
41 -----------------------------------------------------------------------
42 ------------------------Architecture Declaration-----------------------
43
44 architecture behavior of adc_shift_reg is
45
46 -----------------------------------------------------------------------
47 ------------------------Signal Declarations----------------------------
48
49 signal data_bus: std_logic_vector(11 downto 0); --data bus signal
50
51 -----------------------------------------------------------------------
52 -------------------------------Logic-----------------------------------
53 begin
54
55 process (clk, enable)
56 begin
57 if enable = '1' then -- if enable is one, and
58 if (rising_edge(clk)) then -- if there's a rising edge of clock
59 data_bus(11 downto 1) <= data_bus(10 downto 0); -- left shift
60 data_bus(0) <= data_bit_in; --LSB gets a 0
61 end if;
62 end if;
63
64 if (falling_edge(clk)) then -- on the falling edge
65 data_bus_out <= data_bus; -- data bus out gets the internal data bus
66 end if;
67 end process;
68 end behavior;
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: adc_sm.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21
22 -----------------------------------------------------------------------
23 ------------------------Library Declaration----------------------------
24
25 library IEEE;
26 use IEEE.STD_LOGIC_1164.ALL;
27 use ieee.numeric_std.all;
28
29 -----------------------------------------------------------------------
30 ------------------------Entity Declaration-----------------------------
31
32 entity adc_sm is
33 port(
34 clk: in std_logic;
35 take_sample: in std_logic;
36 load_enable: out std_logic;
37 shift_enable: out std_logic;
38 spi_cs: out std_logic
39 );
40 end entity;
41
42 -----------------------------------------------------------------------
43 ------------------------Architecture Declaration-----------------------
44
45 architecture behavior of adc_sm IS
46
47 TYPE adc_bit_count_type IS (count_kickoff, count_14, count_13, count_12, count_11,
count_10, count_9, count_8, count_7, count_6, count_5, count_4, count_3, count_2,
count_1, count_0, count_idle);
48
49
50 -----------------------------------------------------------------------
51 ------------------------Signal Declarations----------------------------
52
53 SIGNAL bit_count_present_state:adc_bit_count_type;
54
55 SIGNAL bit_count_next_state:adc_bit_count_type;
56
57 SIGNAL cs_next_state: std_logic;
58
59 SIGNAL load_enable_next_state: std_logic;
60
61
62
63 -----------------------------------------------------------------------
64 -------------------------------Logic-----------------------------------
65
66 BEGIN
67 adc_bit_counter:
 68 PROCESS (clk,take_sample, bit_count_present_state, bit_count_next_state)
69 BEGIN
70 -- clocked state changes
71 --sclk changing to '1' always clocks next state and also clocks next output states
72
73 IF rising_edge(clk) THEN
74 bit_count_present_state <= bit_count_next_state;
75
76 spi_cs <= cs_next_state;
77 load_enable <= load_enable_next_state;
78 shift_enable <= NOT(cs_next_state);
79
80 end if;
81
82 -- when state is idle & sclk changed to 0 with & take_sample is 1
83 --and change the next output state to match
84
85 --IF ((sclk'EVENT) AND (sclk = '0') AND (take_sample = '1') AND
(bit_count_present_state = count_idle)) THEN
86
87 IF (falling_edge (clk)) then
88 IF (take_sample = '1') THEN
89 bit_count_present_state <= count_kickoff;
90 cs_next_state <= '0';
91 load_enable_next_state <= '0';
92 end if;
93 end if;
94
95 -- combinatorial logic
96 --compute next state & next output from present state and inputs as required
97
98 --If rising_edge(clk) then
99 CASE bit_count_present_state IS
100 WHEN count_kickoff =>
101 bit_count_next_state <= count_14;
102 cs_next_state <= '0';
103 load_enable_next_state <= '0';
104 WHEN count_14 =>
105 bit_count_next_state <= count_13;
106 cs_next_state <= '0';
107 load_enable_next_state <= '0';
108 WHEN count_13 =>
109 bit_count_next_state <= count_12;
110 cs_next_state <= '0';
111 load_enable_next_state <= '0';
112 WHEN count_12 =>
113 bit_count_next_state <= count_11;
114 cs_next_state <= '0';
115 load_enable_next_state <= '0';
116 WHEN count_11 =>
117 bit_count_next_state <= count_10;
118 cs_next_state <= '0';
119 load_enable_next_state <= '0';
120 WHEN count_10 =>
121 bit_count_next_state <= count_9;
122 cs_next_state <= '0';
123 load_enable_next_state <= '0';
124 WHEN count_9 =>
125 bit_count_next_state <= count_8;
126 cs_next_state <= '0';
127 load_enable_next_state <= '0';
128 WHEN count_8 =>
129 bit_count_next_state <= count_7;
130 cs_next_state <= '0';
131 load_enable_next_state <= '0';
132 WHEN count_7 =>
133 bit_count_next_state <= count_6;
134 cs_next_state <= '0';
135 load_enable_next_state <= '0';
136 WHEN count_6 =>
137 bit_count_next_state <= count_5;
138 cs_next_state <= '0';
139 load_enable_next_state <= '0';
140 WHEN count_5 =>
141 bit_count_next_state <= count_4;
142 cs_next_state <= '0';
143 load_enable_next_state <= '0';
144 WHEN count_4 =>
145 bit_count_next_state <= count_3;
146 cs_next_state <= '0';
147 load_enable_next_state <= '0';
148 WHEN count_3 =>
149 bit_count_next_state <= count_2;
150 cs_next_state <= '0';
151 load_enable_next_state <= '0';
152 WHEN count_2 =>
153 bit_count_next_state <= count_1;
154 cs_next_state <= '0';
155 load_enable_next_state <= '0';
156 WHEN count_1 =>
157 bit_count_next_state <= count_0;
158 cs_next_state <= '0';
159 load_enable_next_state <= '0';
160 WHEN count_0 =>
161 bit_count_next_state <= count_idle;
162 cs_next_state <= '1';
163 load_enable_next_state <= '1';
164 WHEN count_idle =>
165 bit_count_next_state <= count_idle;
166 cs_next_state <= '1';
167 load_enable_next_state <= '0';
168 end case;
169 --end if;
170
171 end process;
172 END behavior;
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: ADC.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21 -----------------------------------------------------------------------
22 ------------------------Library Declaration----------------------------
23
24 library IEEE;
25 use IEEE.STD_LOGIC_1164.ALL;
26 use ieee.numeric_std.all;
27
28 -----------------------------------------------------------------------
29 ------------------------Entity Declaration-----------------------------
30
31 entity ADC is
32 port(
33 serial_clock: in std_logic; -- 3.8 mghz serial clock
34 take_sample: in std_logic; -- 44 khz sampling clock
35 spi_sdata_pos: in std_logic; --incoming data positive
36 spi_sdata_neg: in std_logic; --inverted incoming data
37 spi_cs: out std_logic; -- chip select to pins
38 spi_sclk: out std_logic; -- sclk to pins
39 bal_out: out std_logic_vector (11 downto 0) --mono balanced output
40 );
41 end entity;
42
43
44 -----------------------------------------------------------------------
45 ------------------------Architecture Declaration-----------------------
46
47 architecture behavior of ADC is
48
49 -----------------------------------------------------------------------
50 ------------------------Signal Declarations----------------------------
51
52 signal load_enable: std_logic; --enables loading
53 signal shift_enable: std_logic; --enables shifting
54 signal data_bus_int_pos: std_logic_vector (11 downto 0); --internal wiring
55 signal data_bus_int_neg: std_logic_vector (11 downto 0); --internal wiring
56 signal spi_cs_internal :std_logic; -- internal wiring
57 signal preflip_pos: std_logic_vector (11 downto 0); -- internal wiring
58 signal preflip_neg: std_logic_vector (11 downto 0); -- internal wiring
59 signal sub_pos: unsigned (12 downto 0); -- internal wiring
60 signal sub_neg: unsigned (12 downto 0); -- internal wiring
61 signal difference: unsigned (12 downto 0); -- internal wiring
62
63 -----------------------------------------------------------------------
64 -------------------------------Logic-----------------------------------
65
66
67
68
69 -----------------------------Components--------------------------------
 70
71 component adc_sm is
72 port(
73 clk: in std_logic; --clock
74 take_sample: in std_logic; --take sample strobe
75 load_enable: out std_logic; --bus load enable for data
76 shift_enable: out std_logic; --enables shifting of data
77 spi_cs: out std_logic -- chip select
78 );
79 end component;
80
81 -----------------------------------------------------------------------
82
83 component adc_shift_reg is
84 port(
85 clk: in std_logic; --clock
86 data_bit_in: in std_logic; --incoming data bits
87 enable: in std_logic; --enable for shifting
88 data_bus_out: out std_logic_vector(11 downto 0) --bus output
89 );
90
91 end component;
92
93 -----------------------------------------------------------------------
94
95 component adc_out_reg is
96 port(
97 clk: in std_logic; --clock
98 enable: in std_logic; --enable output
99 d: in std_logic_vector(11 downto 0); --incoming bus
100 q: out std_logic_vector(11 downto 0) --output bus (copy of incoming bus)
101 );
102 end component;
103
104 ---------------------------Port Mappings-------------------------------
105
106 begin
107
108 adc_sm1: adc_sm port map(
109 clk => serial_clock,
110 take_sample => take_sample,
111 load_enable => load_enable,
112 shift_enable => shift_enable,
113 spi_cs => spi_cs_internal
114 );
115
116 adc_shift_reg_pos: adc_shift_reg port map(
117 clk => serial_clock,
118 data_bit_in => spi_sdata_pos,
119 enable => shift_enable,
120 data_bus_out => data_bus_int_pos
121 );
122
123 adc_shift_reg_neg: adc_shift_reg port map(
124 clk => serial_clock,
125 data_bit_in => spi_sdata_neg,
126 enable => shift_enable,
127 data_bus_out => data_bus_int_neg
128 );
129
130 adc_out_reg_pos: adc_out_reg port map(
131 clk => serial_clock,
132 enable => load_enable,
133 d => data_bus_int_pos,
134 q => preflip_pos
135 );
136
137 adc_out_reg_neg: adc_out_reg port map(
138 clk => serial_clock,
139 enable => load_enable,
140 d => data_bus_int_neg,
141 q => preflip_neg
142 );
143
144 spi_sclk <= serial_clock;
145 spi_cs <= spi_cs_internal;
146
147 sub_pos <= '0' & unsigned(preflip_pos);
148 sub_neg <= '0' & unsigned(preflip_neg);
149 difference <= sub_pos - sub_neg;
150 bal_out <= std_logic_vector(difference(11 downto 0));
151
152
153
154
155 end behavior;
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: address_sub.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --subtracts the write from the delay, and outputs the read
19
20
21 -----------------------------------------------------------------------
22 ------------------------Library Declaration----------------------------
23
24 library IEEE;
25 use IEEE.STD_LOGIC_1164.ALL;
26 use ieee.numeric_std.all;
27 --use ieee.numeric_std_unsigned.all;
28
29 -----------------------------------------------------------------------
30 ------------------------Entity Declaration-----------------------------
31
32 entity address_sub is
33 port(
34 pos: in integer; --write address from wa_counter
35 neg: in integer; --delay amount from delay_buttons
36 diff: out integer
37 );
38 end address_sub;
39
40 -----------------------------------------------------------------------
41 ------------------------Architecture Declaration-----------------------
42
43 architecture behavior of address_sub is
44
45 -----------------------------------------------------------------------
46 ------------------------Signal Declarations----------------------------
47
48 signal intermediate_result: integer;
49
50 -----------------------------------------------------------------------
51 -------------------------------Logic-----------------------------------
52
53 begin
54 process (pos, neg, intermediate_result)
55 begin
56 intermediate_result <= pos - neg;
57 diff <= intermediate_result;
58 end process;
59 end behavior;
60 --------------------------------End------------------------------------
 1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 08/23/2017 11:43:07 AM
6 -- Design Name:
7 -- Module Name: top_level_tb - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 LIBRARY ieee;
21 USE ieee.std_logic_1164.ALL;
22
23 ENTITY delay_buttons_tb IS
24 END delay_buttons_tb;
25
26 ARCHITECTURE testbench OF delay_buttons_tb IS
27
28 -- Component Declaration for the Unit Under Test (UUT)
29 component buttons is
30 port( serial_clock: in std_logic;
31 up: in std_logic;
32 down: in std_logic;
33 address: out integer;
34 tens: out std_logic_vector(3 downto 0);
35 ones: out std_logic_vector(3 downto 0)
36 );
37 end component;
38
39 --Inputs
40 signal sclk : std_logic := '0';
41 signal take_sample : std_logic := '0';
42 signal button_up : std_logic := '0';
43 signal button_down : std_logic := '0';
44
45 --Outputs
46 signal tens, ones: std_logic_vector(3 downto 0);
47 signal addr: integer := 0;
48
49 -- Clock period definitions
50 constant clk_period : time := 10 ns;
51
52 BEGIN
53 -- Instantiate the Unit Under Test (UUT)
54 dut: buttons port map(
55 serial_clock=>sclk, up=>button_up, down=>button_down,
56 address=>addr, tens=>tens, ones=>ones) ;
57
58 -- Clock process definitions
59 clk_process :process
60 begin
61 sclk <= '0';
62 wait for clk_period/2;
63 sclk <= '1';
64 wait for clk_period/2;
65 end process;
66
67 -- Stimulus process
68 stim_proc: process
69 begin
70 wait for 10*clk_period;
71
72 button_down <= '1'; -- run
73 wait for clk_period; -- monopulsed
74 button_down <= '0';
75 --wait for 19 * clk_period;
76
77 wait;
78 end process;
79
80 END;
81
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: buttons.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21 --interfaces with buttons, outputs delay in addresses/samples as well as numbers which
are sent to mux7seg
22
23 -----------------------------------------------------------------------
24 ------------------------Library Declaration----------------------------
25
26 library IEEE;
27 use IEEE.STD_LOGIC_1164.ALL;
28 use ieee.numeric_std.all;
29
30 -----------------------------------------------------------------------
31 ------------------------Entity Declaration-----------------------------
32
33 entity buttons is
34 port(
35 serial_clock: in std_logic; --serial clock 2.38MHz
36 up: in std_logic; -- up button
37 down: in std_logic; -- down button
38 address: out integer; -- output the address in samples or address -- same
unit 1:1 conversion
39 tens: out std_logic_vector(3 downto 0); -- tens digit to mux7seg
40 ones: out std_logic_vector(3 downto 0) -- ones digit to mux7seg
41 );
42
43 end buttons;
44
45 -----------------------------------------------------------------------
46 ------------------------Architecture Declaration-----------------------
47
48 architecture behavior of buttons is
49
50 -----------------------------------------------------------------------
51 ------------------------Constant Declarations--------------------------
52
53 constant SAMPLE_PER_MS: integer:= 44; -- 44.1 khz
54
55 -----------------------------------------------------------------------
56 ------------------------Signal Declarations----------------------------
57
58 signal delay_ms: integer := 20;
59
60
61 -----------------------------------------------------------------------
62 -------------------------------Logic-----------------------------------
63
64 begin
65
66
67
 68 -----------------------------------------------------------------------
69
70
71 --7seg display process
72 display: process (delay_ms) is
73 begin
74 CASE delay_ms IS
75 WHEN 0 =>
76 tens <= "0000";
77 ones <= "0000";
78 WHEN 1 =>
79 tens <= "0000";
80 ones <= "0001";
81 WHEN 2 =>
82 tens <= "0000";
83 ones <= "0010";
84 WHEN 3 =>
85 tens <= "0000";
86 ones <= "0011";
87 WHEN 4 =>
88 tens <= "0000";
89 ones <= "0100";
90 WHEN 5 =>
91 tens <= "0000";
92 ones <= "0101";
93 WHEN 6 =>
94 tens <= "0000";
95 ones <= "0110";
96 WHEN 7 =>
97 tens <= "0000";
98 ones <= "0111";
99 WHEN 8 =>
100 tens <= "0000";
101 ones <= "1000";
102 WHEN 9 =>
103 tens <= "0000";
104 ones <= "1001";
105 WHEN 10 =>
106 tens <= "0001";
107 ones <= "0000";
108 WHEN 11 =>
109 tens <= "0001";
110 ones <= "0001";
111 WHEN 12 =>
112 tens <= "0001";
113 ones <= "0010";
114 WHEN 13 =>
115 tens <= "0001";
116 ones <= "0011";
117 WHEN 14 =>
118 tens <= "0001";
119 ones <= "0100";
120 WHEN 15 =>
121 tens <= "0001";
122 ones <= "0101";
123 WHEN 16 =>
124 tens <= "0001";
125 ones <= "0110";
126 WHEN 17 =>
127 tens <= "0001";
128 ones <= "0111";
129 WHEN 18 =>
130 tens <= "0001";
131 ones <= "1000";
132 WHEN 19 =>
133 tens <= "0001";
134 ones <= "1001";
135 WHEN 20 =>
136 tens <= "0010";
137 ones <= "0000";
138 WHEN others =>
139 tens <= "0110";
140 ones <= "1001";
141 end case;
142 end process;
143
144 --delay amount & address eval
145 delay_update: process (serial_clock) is
146 begin
147 if rising_edge(serial_clock) then
148 address <= SAMPLE_PER_MS * delay_ms;
149 if up = '1' then
150 if delay_ms < 20 then
151 delay_ms <= delay_ms+ 1;
152 else
153 delay_ms <= delay_ms;
154 end if;
155 elsif down = '1' then
156 if delay_ms > 0 then
157 delay_ms <= delay_ms -1 ;
158 else
159 delay_ms <= delay_ms;
160 end if;
161 end if;
162 end if;
163 end process;
164
165 end behavior;
 1 -----------------------------------------------------------------------
2 ------------------------Library Declaration----------------------------
3
4 library IEEE;
5 use IEEE.STD_LOGIC_1164.ALL;
6 use ieee.numeric_std.all;
7
8 -----------------------------------------------------------------------
9 ------------------------Entity Declaration-----------------------------
10
11 entity dac_shift_reg is
12 port(
13 clk: in std_logic;
14 data_bus_in: in std_logic_vector(13 downto 0);
15 load_enable: in std_logic;
16 shift_enable: in std_logic;
17 data_bit_out: out std_logic
18 );
19
20 end dac_shift_reg;
21
22 -----------------------------------------------------------------------
23 ------------------------Architecture Declaration-----------------------
24
25 architecture behavior of dac_shift_reg is
26
27 -----------------------------------------------------------------------
28 ------------------------Signal Declarations----------------------------
29
30 signal data_bus: std_logic_vector(13 downto 0);
31
32 -----------------------------------------------------------------------
33 -------------------------------Logic-----------------------------------
34 begin
35
36 process (clk, shift_enable, load_enable, data_bus_in)
37 begin
38 if load_enable = '1' then
39 data_bus <= data_bus_in;
40 end if;
41
42 if rising_edge(clk) then
43 if shift_enable = '1' then
44 data_bit_out <= data_bus(13);
45 data_bus (13 downto 1)<= data_bus(12 downto 0);
46 data_bus(0) <= '0';
47 end if;
48 end if;
49 end process;
50 end behavior;
 1 -----------------------------------------------------------------------
2 ------------------------Library Declaration----------------------------
3
4 library IEEE;
5 use IEEE.STD_LOGIC_1164.ALL;
6 use ieee.numeric_std.all;
7
8 -----------------------------------------------------------------------
9 ------------------------Entity Declaration-----------------------------
10
11 entity dac_sm is
12 port(
13 clk: in std_logic; --clock
14 take_sample: in std_logic; --take sample 44.1
15 load_enable: out std_logic; --load loading of bus data
16 shift_enable: out std_logic; --enables shifting of bus data
17 spi_cs: out std_logic -- chip select
18 );
19 end entity;
20
21 -----------------------------------------------------------------------
22 ------------------------Architecture Declaration-----------------------
23
24 architecture behavior of dac_sm IS
25
26 TYPE dac_bit_count_type IS (count_kickoff, count_14, count_13, count_12, count_11,
count_10, count_9, count_8, count_7, count_6, count_5, count_4, count_3, count_2,
count_1, count_0, count_idle);
27
28 --sets up a data type for all the different states in the state machine
29 -----------------------------------------------------------------------
30 ------------------------Signal Declarations----------------------------
31
32 SIGNAL bit_count_present_state:dac_bit_count_type; --signal for the current state
33
34 SIGNAL bit_count_next_state:dac_bit_count_type; -- signal for the next state
35
36 SIGNAL cs_next_state: std_logic; --siganl for chip selects next state
37
38 SIGNAL load_enable_next_state: std_logic; --siganl for load enables next state
39 SIGNAL shift_enable_next_state: std_logic; --siganl for shift enabls next state
40
41
42
43 -----------------------------------------------------------------------
44 -------------------------------Logic-----------------------------------
45
46 BEGIN
47 dac_bit_counter:
48 PROCESS (clk,take_sample, bit_count_present_state, bit_count_next_state)
49 BEGIN
50 -- clocked state changes
51 --sclk changing to '1' always clocks next state and also clocks next output states
52
53 IF rising_edge(clk) THEN
54 bit_count_present_state <= bit_count_next_state;
55 spi_cs <= cs_next_state;
56 load_enable <= load_enable_next_state;
57 shift_enable <= shift_enable_next_state;
58
59 end if;
60
61 -- when state is idle & sclk changed to 0 with & take_sample is 1
62 --and change the next output state to match
63
64 --IF ((sclk'EVENT) AND (sclk = '0') AND (take_sample = '1') AND
(bit_count_present_state = count_idle)) THEN
65
66 IF (falling_edge (clk)) then
 67 IF (take_sample = '1') THEN
68 bit_count_present_state <= count_kickoff;
69 cs_next_state <= '0';
70 spi_cs <= '0';
71 load_enable_next_state <= '1';
72 shift_enable_next_state <= '0';
73 end if;
74 end if;
75
76 -- combinatorial logic
77 --compute next state & next output from present state and inputs as required
78 --if rising_edge(clk) then
79
80 CASE bit_count_present_state IS
81 WHEN count_kickoff =>
82 bit_count_next_state <= count_14;
83 cs_next_state <= '0';
84 load_enable_next_state <= '1';
85 shift_enable_next_state <= '0';
86 WHEN count_14 =>
87 bit_count_next_state <= count_13;
88 cs_next_state <= '0';
89 load_enable_next_state <= '0';
90 shift_enable_next_state <= '1';
91 WHEN count_13 =>
92 bit_count_next_state <= count_12;
93 cs_next_state <= '0';
94 load_enable_next_state <= '0';
95 shift_enable_next_state <= '1';
96 WHEN count_12 =>
97 bit_count_next_state <= count_11;
98 cs_next_state <= '0';
99 load_enable_next_state <= '0';
100 shift_enable_next_state <= '1';
101 WHEN count_11 =>
102 bit_count_next_state <= count_10;
103 cs_next_state <= '0';
104 load_enable_next_state <= '0';
105 shift_enable_next_state <= '1';
106 WHEN count_10 =>
107 bit_count_next_state <= count_9;
108 cs_next_state <= '0';
109 load_enable_next_state <= '0';
110 shift_enable_next_state <= '1';
111 WHEN count_9 =>
112 bit_count_next_state <= count_8;
113 cs_next_state <= '0';
114 load_enable_next_state <= '0';
115 shift_enable_next_state <= '1';
116 WHEN count_8 =>
117 bit_count_next_state <= count_7;
118 cs_next_state <= '0';
119 load_enable_next_state <= '0';
120 shift_enable_next_state <= '1';
121 WHEN count_7 =>
122 bit_count_next_state <= count_6;
123 cs_next_state <= '0';
124 load_enable_next_state <= '0';
125 shift_enable_next_state <= '1';
126 WHEN count_6 =>
127 bit_count_next_state <= count_5;
128 cs_next_state <= '0';
129 load_enable_next_state <= '0';
130 shift_enable_next_state <= '1';
131 WHEN count_5 =>
132 bit_count_next_state <= count_4;
133 cs_next_state <= '0';
134 load_enable_next_state <= '0';
135 shift_enable_next_state <= '1';
136 WHEN count_4 =>
137 bit_count_next_state <= count_3;
138 cs_next_state <= '0';
139 load_enable_next_state <= '0';
140 shift_enable_next_state <= '1';
141 WHEN count_3 =>
142 bit_count_next_state <= count_2;
143 cs_next_state <= '0';
144 load_enable_next_state <= '0';
145 shift_enable_next_state <= '1';
146 WHEN count_2 =>
147 bit_count_next_state <= count_1;
148 cs_next_state <= '0';
149 load_enable_next_state <= '0';
150 shift_enable_next_state <= '1';
151 WHEN count_1 =>
152 bit_count_next_state <= count_0;
153 cs_next_state <= '0';
154 load_enable_next_state <= '0';
155 shift_enable_next_state <= '1';
156 WHEN count_0 =>
157 bit_count_next_state <= count_idle;
158 cs_next_state <= '0';
159 load_enable_next_state <= '0';
160 shift_enable_next_state <= '0';
161 WHEN count_idle =>
162 bit_count_next_state <= count_idle;
163 cs_next_state <= '1';
164 load_enable_next_state <= '0';
165 shift_enable_next_state <= '0';
166 end case;
167
168 --end if;
169 end process;
170 END behavior;
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: DAC.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21 library IEEE;
22 use IEEE.STD_LOGIC_1164.ALL;
23 use ieee.numeric_std.all;
24
25
26 entity DAC is
27 port(
28 serial_clock: in std_logic;
29 take_sample: in std_logic;
30 dac_data_preflip: in std_logic_vector(11 downto 0);
31 spi_sdata_pos: out std_logic;
32 spi_sdata_neg: out std_logic;
33 spi_cs: out std_logic;
34 spi_sclk: out std_logic
35 );
36 end entity;
37
38 -----------------------------------------------------------------------
39 ------------------------Architecture Declaration-----------------------
40
41 architecture behavior of DAC is
42
43 -----------------------------------------------------------------------
44 ------------------------Signal Declarations----------------------------
45 signal dac_data_pre_pos : unsigned (11 downto 0);
46 signal dac_data_pre_neg : unsigned (11 downto 0);
47 signal dac_data_pos: std_logic_vector(13 downto 0);
48 signal dac_data_neg: std_logic_vector(13 downto 0);
49 signal load_enable : std_logic;
50 signal shift_enable : std_logic;
51
52
53 -----------------------------------------------------------------------
54 -------------------------------Logic-----------------------------------
55
56
57
58 -----------------------------------------------------------------------
59 -----------------------------Components--------------------------------
60
61 component dac_sm is
62 port(
63 clk: in std_logic;
64 take_sample: in std_logic;
65 load_enable: out std_logic;
66 shift_enable: out std_logic;
67 spi_cs: out std_logic
68 );
69 end component;
 70
71 -----------------------------------------------------------------------
72
73 component dac_shift_reg is
74 port(
75 clk: in std_logic;
76 data_bus_in: in std_logic_vector(13 downto 0);
77 load_enable: in std_logic;
78 shift_enable: in std_logic;
79 data_bit_out: out std_logic
80 );
81
82 end component;
83
84 -----------------------------------------------------------------------
85 ---------------------------Port Mappings-------------------------------
86 begin
87
88 dac_sm1: dac_sm port map(
89 clk => serial_clock,
90 take_sample => take_sample,
91 load_enable => load_enable,
92 shift_enable => shift_enable,
93 spi_cs => spi_cs
94
95 );
96
97 dac_shift_reg_L: dac_shift_reg port map(
98 data_bit_out => spi_sdata_pos,
99 clk => serial_clock,
100 shift_enable => shift_enable,
101 load_enable => load_enable,
102 data_bus_in => dac_data_pos
103 );
104
105 dac_shift_reg_R: dac_shift_reg port map(
106 data_bit_out => spi_sdata_neg,
107 clk => serial_clock,
108 shift_enable => shift_enable,
109 load_enable => load_enable,
110 data_bus_in => dac_data_neg
111
112 );
113
114 spi_sclk <= serial_clock;
115
116 dac_data_pre_pos <= unsigned(dac_data_preflip) + "1000000000";
117 dac_data_pre_neg <= unsigned((not(dac_data_preflip))) + "1000000000";
118
119
120
121 dac_data_pos(13 downto 12) <= "00";
122 dac_data_pos(11 downto 0) <= std_logic_vector(dac_data_pre_pos);
123
124 dac_data_neg(13 downto 12) <= "00";
125 dac_data_neg(11 downto 0) <= std_logic_vector(dac_data_pre_neg);
126
127 end behavior;
128
129
 1 -----------------------------------------------------------------------
2 ------------------------Library Declaration----------------------------
3
4 library IEEE;
5 use IEEE.std_logic_1164.all;
6 use ieee.numeric_std.all;
7
8
9 -----------------------------------------------------------------------
10 ------------------------Entity Declaration-----------------------------
11
12 entity dp_ram is
13 port(
14 ram_clk: in std_logic; --44.1khz sampling clock
15 write_address: in integer; -- write address, taken from the write address counter
16 read_address: in integer; --read address, taken from the subtractor's dff
17 write_data: in std_logic_vector (11 downto 0); --incoming audio samples from the AD
process
18 read_data: out std_logic_vector (11 downto 0)); -- delayed audio samples
19 end entity dp_ram;
20
21 -----------------------------------------------------------------------
22 ------------------------Architecture Declaration-----------------------
23
24 architecture behavior of dp_ram is
25
26 -----------------------------------------------------------------------
27 ------------------------Signal Declarations----------------------------
28
29 --signal read_enable: std_logic;
30 --signal write_enable: std_logic;
31
32 type RAM_type is array (0 to 1023) of std_logic_vector (11 downto 0);
33 --makes an array, will be instuatiated as some form of memory by vivado
34 signal RAM : RAM_type;
35
36
37 -----------------------------------------------------------------------
38 -------------------------------Logic-----------------------------------
39 begin
40 process (ram_clk, read_address, write_address)
41 begin
42 if rising_edge (ram_clk) then -- on the rising edge,
43 RAM(write_address) <= write_data; --write the current sample into memory. always.
44 if read_address = write_address then --you can't read back what you just wrote
from the ram itself because of timing issues, so if the write and the read
address are identical, just pass the write_data onto the read data (effectively
bypassing the RAM.
45 read_data <= write_data; -- this is bypass statement to avoid address
collision
46 else
47 read_data <= RAM(read_address); -- otherwise, read from the ram
48 end if;
49 end if;
50 end process;
51 end behavior;
52
53
54 --------------------------------End------------------------------------
 1 -- high level component, ties together write address counter, dual ported ram, and
addresss subtractor
2 -- duplicates the incoming signal, sending one copy left and one copy right.
3 -- the right copy is then delayed, which gives the appearance of stereo width.
4
5
6 -----------------------------------------------------------------------
7 ------------------------Library Declaration----------------------------
8
9 library IEEE;
10 use IEEE.STD_LOGIC_1164.ALL;
11 use ieee.numeric_std.all;
12 --use ieee.numeric_std_unsigned.all;
13
14 -----------------------------------------------------------------------
15 ------------------------Entity Declaration-----------------------------
16
17 entity haas_engine is
18 port(
19 take_sample: in std_logic; --44.1khz. divided down from mclk in top_level
20 data_bus_in_mono: in std_logic_vector(11 downto 0); --from the A to D converter
process
21 delay_amount: in integer; --units are samples, comes from the delay_buttons.vhd
22 data_bus_out: out std_logic_vector(11 downto 0) --delayed signal, sent to DA
23 );
24 end entity haas_engine;
25
26 -----------------------------------------------------------------------
27 ------------------------Architecture Declaration-----------------------
28
29 architecture behavior of haas_engine is
30
31 -----------------------------------------------------------------------
32 ------------------------Signal Declarations----------------------------
33
34 signal read_address: integer; --runs behind write address, signal used for wiring
35 signal write_address: integer; --where the current sample is sent to memory, signal
used for wiring
36
37
38 -----------------------------------------------------------------------
39 -----------------------------Components--------------------------------
40
41 component write_counter is
42 port(
43 clk: in std_logic; --get the same 44.1 khz sample clock
44 count: out integer --counting upwards, rolls over after 1024; note: we are aware
that passing integers is "bad form;" however,
45 --our current project is working, and we are reluctant to change
code given our limited time remaining. we
46 --should be converting integers to to std_logic_vector for
passing between blocks and reconverting within
47
48 );
49 end component;
50
51 component dp_ram is
52 port(
53 ram_clk: in std_logic; --get the same 44.1 khz sample clock
54 write_address: in integer; --address that sample is written to from A-D
55 read_address: in integer; --address that is read from, used in the right channel
and then sent to DA
56 write_data: in std_logic_vector (11 downto 0); -- incoming samples, sent to DA left
directly
57 read_data: out std_logic_vector (11 downto 0) --outgoing samples, which are the
samples in write data that are delayed using the address subtractor.
58 );
59 end component;
60
 61 component address_sub is
62 port(
63 pos: in integer; --write address
64 neg: in integer; -- delay amount in samples. **1 address = 1 sample**
65 diff: out integer --read address
66 );
67 end component;
68
69
70
71 -----------------------------------------------------------------------
72 -------------------------------Logic-----------------------------------
73
74 begin
75
76
77 -----------------------------------------------------------------------
78 ---------------------------Port Mappings-------------------------------
79
80
81 write_address_counter: write_counter port map(
82 clk => take_sample,
83 count => write_address
84 );
85
86
87 dual_ported_ram: dp_ram port map(
88 ram_clk => take_sample,
89 write_address => write_address,
90 read_address => read_address,
91 write_data => data_bus_in_mono,
92 read_data => data_bus_out
93 );
94
95
96 address_subtractor: address_sub port map(
97 pos => write_address,
98 neg => delay_amount,
99 diff => read_address
100 );
101
102
103
104
105 end behavior;
106 --------------------------------End------------------------------------
107
 1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 08/23/2017 12:57:19 PM
6 -- Design Name:
7 -- Module Name: monopulser - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24
25 -- Uncomment the following library declaration if using
26 -- arithmetic functions with Signed or Unsigned values
27 use IEEE.NUMERIC_STD.ALL;
28
29 -- Uncomment the following library declaration if instantiating
30 -- any Xilinx leaf cells in this code.
31 --library UNISIM;
32 --use UNISIM.VComponents.all;
33
34 entity monopulser is
35 Port ( clk : in std_logic; --clock
36 button_in : in std_logic; --button in from hardware
37 output : out std_logic --output monopulsed
38
39 );
40 end monopulser;
41
42 architecture Behavioral of monopulser is
43
44 type state_type is (waiting, press, wait_rel);
45 signal curr_s, next_s: state_type;
46
47
48 begin
49
50
51 process(clk) is
52 begin
53 if rising_edge(clk) then -- on the rising edge of clock
54 curr_s <= next_s; --curent state gets next state
55 end if;
56 end process;
57
58 process(curr_s, button_in) is
59 begin
60
61 next_s <= curr_s; --next state gets curent state
62 output <= '0'; --output is 0
63
64 case curr_s is
65 when waiting =>
66 if button_in = '1' then
67 next_s <= press;
68 end if;
69 when press =>
70 output <= '1';
71 next_s <= wait_rel;
72 when wait_rel =>
73 if button_in = '0' then
74 next_s <= waiting;
75 end if;
76 end case;
77 end process;
78
79
80 end Behavioral;
81
 1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 08/25/2017 09:49:42 PM
6 -- Design Name:
7 -- Module Name: top_level - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21
22 library IEEE;
23 use IEEE.STD_LOGIC_1164.ALL;
24 use IEEE.NUMERIC_STD.ALL;
25 library UNISIM;
26 use UNISIM.VComponents.all;
27
28 -- Uncomment the following library declaration if instantiating
29 -- any Xilinx leaf cells in this code.
30 --library UNISIM;
31 --use UNISIM.VComponents.all;
32
33 -----------------------------------------------------------------------
34 ------------------------Entity Declaration-----------------------------
35
36 entity top_level is
37 Port (
38 mclk: in std_logic;
39
40 --ADC in
41 adc_in_pos: in std_logic;
42 adc_in_neg: in std_logic;
43 adc_spi_sclk: out std_logic;
44 adc_spi_cs: out std_logic;
45
46 --DAC out left
47 dac_spi_sclk_L: out std_logic;
48 dac_spi_cs_L: out std_logic;
49 dac_out_L_pos: out std_logic;
50 dac_out_L_neg: out std_logic;
51
52 --DAC out right
53 dac_spi_sclk_R: out std_logic;
54 dac_spi_cs_R: out std_logic;
55 dac_out_R_pos: out std_logic;
56 dac_out_R_neg: out std_logic;
57
58 --buttons
59 button_up: in std_logic;
60 button_down: in std_logic;
61
62 --multiplexed seven segment display
63 seg : out std_logic_vector(0 to 6);
64 an : out std_logic_vector(3 downto 0)
65
66 );
67 end top_level;
68
69 -----------------------------------------------------------------------
 70 ------------------------Architecture Declaration-----------------------
71
72 architecture behavior of top_level is
73
74 -----------------------------------------------------------------------
75 -----------------------------Components--------------------------------
76
77 component ADC is
78 port(
79 serial_clock: in std_logic;
80 take_sample: in std_logic;
81 spi_sdata_pos: in std_logic;
82 spi_sdata_neg: in std_logic;
83 spi_cs: out std_logic;
84 spi_sclk: out std_logic;
85 bal_out: out std_logic_vector (11 downto 0)
86 );
87 end component;
88
89 component haas_engine is
90 port(
91 take_sample: in std_logic; --44.1khz. divided down from mclk in top_level
92 data_bus_in_mono: in std_logic_vector(11 downto 0); --from the A to D converter
process
93 delay_amount: in integer; --units are samples, comes from the delay_buttons.vhd
94 data_bus_out: out std_logic_vector(11 downto 0) --delayed signal, sent to DA
95 );
96 end component;
97
98 component DAC is
99 port(
100 serial_clock: in std_logic;
101 take_sample: in std_logic;
102 dac_data_preflip: in std_logic_vector(11 downto 0);
103 spi_sdata_pos: out std_logic;
104 spi_sdata_neg: out std_logic;
105 spi_cs: out std_logic;
106 spi_sclk: out std_logic
107 );
108 end component;
109
110 component mux7seg is
111 Port ( clk : in STD_LOGIC;
112 y0, y1, y2, y3 : in STD_LOGIC_VECTOR (3 downto 0);
113 seg : out STD_LOGIC_VECTOR(0 to 6);
114 an : out STD_LOGIC_VECTOR (3 downto 0) );
115 end component;
116
117 component monopulser is
118 Port ( clk : in std_logic;
119 button_in : in std_logic;
120 output : out std_logic
121
122 );
123 end component;
124
125 component buttons is
126 port(
127 serial_clock: in std_logic; --serial clock 2.38MHz
128 up: in std_logic; -- up button
129 down: in std_logic; -- down button
130 address: out integer; -- output the address in samples or address -- same
unit 1:1 conversion
131 tens: out std_logic_vector(3 downto 0); -- tens digit to mux7seg
132 ones: out std_logic_vector(3 downto 0) -- ones digit to mux7seg
133 );
134
135 end component;
136
137
138 -----------------------------------------------------------------------
139 ------------------------Signal Declarations----------------------------
140 constant SCLK_DIVIDER_VALUE: integer := 21; --serial clock divider
141 constant SCLK_COUNT_LEN: integer := 5;
142 signal sclkdiv: unsigned(SCLK_COUNT_LEN-1 downto 0) := (others => '0');
143 signal sclk_unbuf: std_logic := '0';
144
145 constant TS_DIVIDER_VALUE: unsigned := "110101"; --take sample generator (53; 54-1)
146 --signal ts_divider_val: unsigned := "110110";
147 constant TS_COUNT_LEN: integer := 5;
148 signal tsdiv: unsigned(TS_COUNT_LEN downto 0) := (others => '0');
149 signal take_sample_sig : std_logic := '0';
150
151 signal serial_clock: std_logic := '0';
152
153 signal data_temp: std_logic_vector(11 downto 0) := (others => '0');
154
155 signal up: std_logic := '0';
156 signal down: std_logic := '0';
157
158 signal tens: std_logic_vector(3 downto 0) := "0000";
159 signal ones: std_logic_vector(3 downto 0) := "0000";
160
161 signal delay_amount: integer := 0;
162
163 signal haas_to_dac: std_logic_vector(11 downto 0) := (others => '0');
164
165 -----------------------------------------------------------------------
166 ---------------------------Port Mappings-------------------------------
167 begin
168
169 ADC1: ADC port map(
170 serial_clock => serial_clock,
171 take_sample => take_sample_sig,
172 spi_sdata_pos => adc_in_pos,
173 spi_sdata_neg => adc_in_neg,
174 spi_cs => adc_spi_cs,
175 spi_sclk => adc_spi_sclk,
176 bal_out => data_temp
177 );
178
179 haas: haas_engine
180 port map(
181 take_sample => take_sample_sig,
182 data_bus_in_mono => data_temp,
183 delay_amount => delay_amount,
184 data_bus_out => haas_to_dac
185 );
186
187
188
189 DAC_L: DAC port map(
190 serial_clock => serial_clock,
191 take_sample => take_sample_sig,
192 dac_data_preflip => data_temp,
193 spi_sdata_pos => dac_out_L_pos,
194 spi_sdata_neg => dac_out_L_neg,
195 spi_cs => dac_spi_cs_L,
196 spi_sclk => dac_spi_sclk_L
197 );
198
199 DAC_R: DAC port map(
200 serial_clock => serial_clock,
201 take_sample => take_sample_sig,
202 dac_data_preflip => haas_to_dac,
203 spi_sdata_pos => dac_out_R_pos,
204 spi_sdata_neg => dac_out_R_neg,
205 spi_cs => dac_spi_cs_R,
206 spi_sclk => dac_spi_sclk_R
207 );
208
209 up_mono: monopulser port map(
210 clk=>serial_clock, button_in=>button_up, output=>up
211 );
212
213 down_mono: monopulser port map(
214 clk=>serial_clock, button_in=>button_down, output=>down
215 );
216
217
218 delay_buttons: buttons port map(
219
220 serial_clock => serial_clock,
221 up=> up,
222 down=> down,
223 address=> delay_amount,
224 tens=> tens,
225 ones=> ones
226 );
227
228 display: mux7seg port map(
229 clk => serial_clock,
230 y3 => "0000",
231 y2 => "0000",
232 y1 => tens,
233 y0 => ones,
234 seg => seg,
235 an => an
236 );
237
238
239 -----------------------------------------------------------------------
240 -------------------------------Logic-----------------------------------
241
242 sclk_buffer: BUFG
243 port map (I => sclk_unbuf,
244 O => serial_clock );
245
246 Serial_clock_divider: process(mclk) is
247 begin
248 if rising_edge(mclk) then
249 if sclkdiv = SCLK_DIVIDER_VALUE-1 then
250 sclkdiv <= (others => '0');
251 sclk_unbuf <= NOT(sclk_unbuf);
252 else
253 sclkdiv <= sclkdiv + 1;
254 end if;
255 end if;
256 end process Serial_clock_divider;
257
258 take_sample_generator: process(serial_clock)
259 begin
260 if rising_edge(serial_clock) then
261 if tsdiv = TS_DIVIDER_VALUE then
262 tsdiv <= (others => '0');
263 --take_sample <= NOT(take_sample);
264 take_sample_sig <= '1';
265 else
266 tsdiv <= tsdiv + 1;
267 take_sample_sig <= '0';
268 end if;
269 end if;
270 end process take_sample_generator;
271
272
273 end behavior;
274
 1 --counter that generates the write address. note that the READ addrss is
2 ---generated by the subtraction process, not this counter
3
4 -----------------------------------------------------------------------
5 ------------------------Library Declaration----------------------------
6
7 library IEEE;
8 use IEEE.std_logic_1164.all;
9 use ieee.numeric_std.all;
10
11
12 -----------------------------------------------------------------------
13 ------------------------Entity Declaration-----------------------------
14
15 entity write_counter is
16 port(
17 clk: in std_logic; --the clock. gets the 44.1 sample clock
18 count: out integer --numerical output,outputed value is the write address.
19 );
20 end entity;
21
22
23 -----------------------------------------------------------------------
24 ------------------------Architecture Declaration-----------------------
25
26 architecture behavior of write_counter is
27
28 -----------------------------------------------------------------------
29 ------------------------Signal Declarations----------------------------
30
31 signal int_count: integer := 0; --internal signal for the counteres register.
32
33 --to_int(unsigned(count_in));
34
35 -----------------------------------------------------------------------
36 -------------------------------Logic-----------------------------------
37
38 --simple counting process, counts to 1023 and then rolls to 0, and if it gets a
39 --reset is goes to 0 as well
40 begin
41 count <= int_count;
42 process(clk, int_count)
43 begin
44 if rising_edge(clk) then
45 if int_count = 1023 then
46 int_count <= 0 ;
47 else
48 int_count <= int_count+1;
49 end if;
50 end if;
51 end process;
52 end behavior;
53
54
55 --------------------------------End------------------------------------
Appendix G: VHDL Testbench Code
1 --------------------------------------------------------------------------------
2 -- Engineer: Eric Hansen
3 -- Course: Engs 31 16X
4 --
5 -- Create Date: 07/22/2016
6 -- Design Name:
7 -- Module Name: pmod_ad1_tb.vhd
8 -- Project Name: Lab5
9 -- Target Device:
10 -- Tool versions:
11 -- Description: VHDL Test Bench for module: pmod_ad1
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18
19 --------------------------------------------------------------------------------
20 LIBRARY ieee;
21 USE ieee.std_logic_1164.ALL;
22 USE ieee.numeric_std.all;
23 use IEEE.MATH_REAL.ALL;
24
25 ENTITY ADC_tb IS
26 END ADC_tb;
27
28 ARCHITECTURE behavior OF ADC_tb IS
29
30 component ADC
31 port (-- interface to top level
32 serial_clock: in std_logic; -- serial clock
33 take_sample : in STD_LOGIC;
34 bal_out : out STD_LOGIC_VECTOR (11 downto 0);
35
36 -- SPI bus interface to ADC
37 spi_sclk : out std_logic;
38 spi_cs : out std_logic;
39 spi_sdata_pos : in std_logic;
40 spi_sdata_neg : in std_logic );
41 end component;
42
43 --Inputs
44 signal serial_clock : std_logic := '0';
45 signal take_sample : std_logic := '0';
46 signal spi_sdata_pos : std_logic := '0' ;
47 signal spi_sdata_neg : std_logic := '0' ;
48
49 --Outputs
50 signal spi_sclk : std_logic := '0' ;
51 signal spi_cs : std_logic := '1';
52 signal bal_out : std_logic_vector(11 downto 0) := (others => '0');
53
54 -- Clock period definitions
55 constant sclk_period : time := 1 us; -- 1 MHz serial clock
56 constant sampling_count_tc : integer := 25; -- to achieve a 40 kHz sampling
rate, for testing
57
58 -- Data definitions
59 constant TxData : std_logic_vector(14 downto 0) := "111000001101001";
60 signal bit_count : integer := 14;
61
62 -- Internal definitions
63 signal sampling_count : integer := 0;
64
65 BEGIN
66 -- Instantiate the Unit Under Test (UUT)
67
68 uut: ADC port map(
 69 serial_clock => serial_clock,
70 take_sample => take_sample,
71 bal_out => bal_out,
72
73 -- SPI bus interface to Pmod AD1
74 spi_sclk => spi_sclk,
75 spi_cs => spi_cs,
76 spi_sdata_pos => spi_sdata_pos,
77 spi_sdata_neg => spi_sdata_neg );
78
79 -- Clock process definitions
80 clk_process: process
81 begin
82 serial_clock <= '0';
83 wait for sclk_period/2;
84 serial_clock <= '1';
85 wait for sclk_period/2;
86 end process;
87
88
89 stim_proc_2: process(spi_sclk)
90 begin
91 if rising_edge(spi_sclk) then
92 if sampling_count < sampling_count_tc-1 then
93 sampling_count <= sampling_count + 1;
94 take_sample <= '0';
95 else
96 sampling_count <= 0;
97 take_sample <= '1'; -- push take_sample to interface to initiate a
conversion
98 end if;
99 end if;
100
101
102
103 if falling_edge(spi_sclk) then -- clock data out on falling edge, MSB first
104 if spi_cs = '0' then -- watch for SPI interface to activate the A/D
105 spi_sdata_pos <= TxData(bit_count);
106 spi_sdata_neg <= not(TxData(bit_count));
107 if bit_count = 0 then bit_count <= 14;
108 else bit_count <= bit_count - 1;
109 end if;
110 end if;
111 end if;
112 end process stim_proc_2;
113 END;
114
 1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.all;
4 use IEEE.MATH_REAL.ALL;
5
6 ENTITY DAC_tb IS
7 END DAC_tb;
8
9 ARCHITECTURE behavior OF DAC_tb IS
10
11 component DAC
12 port (
13 serial_clock: in std_logic;
14 take_sample : in STD_LOGIC;
15 dac_data_preflip : in STD_LOGIC_VECTOR (11 downto 0);
16 spi_sdata_pos : out std_logic;
17 spi_sdata_neg : out std_logic;
18 spi_cs : out std_logic;
19 spi_sclk : out std_logic
20 );
21
22
23 end component;
24
25 --Inputs
26 signal serial_clock : std_logic := '0';
27 signal take_sample : std_logic := '0';
28 signal dac_data_preflip : std_logic_vector(11 downto 0) := (others => '0');
29
30 --Outputs
31 signal spi_sclk : std_logic := '0' ;
32 signal spi_cs : std_logic := '1';
33 signal spi_sdata_pos : std_logic := '0' ;
34 signal spi_sdata_neg : std_logic := '0' ;
35
36 -- Clock period definitions
37 constant sclk_period : time := 1 us; -- 1 MHz serial clock
38 constant sampling_count_tc : integer := 25; -- to achieve a 40 kHz sampling
rate, for testing
39
40 -- Data definitions
41 signal bit_count : integer := 14;
42 signal txData : std_logic_vector(11 downto 0):= "101010101010";
43
44 -- 0 1 0 0 1 0 1 0 1 0 1 0 1 0
45
46 -- Internal definitions
47 signal sampling_count : integer := 0;
48
49 BEGIN
50 -- Instantiate the Unit Under Test (UUT)
51
52 uut: DAC port map(
53 serial_clock => serial_clock,
54 take_sample => take_sample,
55 dac_data_preflip => dac_data_preflip,
56 spi_sdata_pos => spi_sdata_pos,
57 spi_sdata_neg => spi_sdata_neg,
58 spi_cs => spi_cs,
59 spi_sclk => spi_sclk
60 );
61
62 -- Clock process definitions
63 clk_process: process
64 begin
65 serial_clock <= '0';
66 wait for sclk_period/2;
67 serial_clock <= '1';
68 wait for sclk_period/2;
69 end process;
70
71
72 -- Stimulus process: testbench pretends to be the D/A converter
73 stim_proc_2: process
74 begin
75 dac_data_preflip <= txData;
76
77 wait for 100*sclk_period;
78 take_sample <= '1';
79 wait for sclk_period;
80 take_sample <= '0';
81
82
83 end process stim_proc_2;
84
85 END;
86
87
 1 ----------------------------------------------------------------------------------
2 -- Company: ENGS 031 17X
3 -- Engineer: Christopher Hogan & PJ O'Sullivan
4 --
5 -- Create Date:
6 -- Design Name: haas delay
7 -- Module Name: haas_tb.vhd
8 -- Project Name:
9 -- Target Devices:
10 -- Tool Versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 USE ieee.numeric_std.all;
24 use IEEE.MATH_REAL.ALL;
25
26 ENTITY haas_tb IS
27 END haas_tb;
28
29 ARCHITECTURE behavior OF haas_tb IS
30
31 component haas_engine is
32 port(
33 take_sample: in std_logic; --44.1khz. divided down from mclk in top_level
34 data_bus_in_mono: in std_logic_vector(11 downto 0); --from the A to D converter
process
35 delay_amount: in integer; --units are samples, comes from the delay_buttons.vhd
36 data_bus_out: out std_logic_vector(11 downto 0) --delayed signal, sent to DA
37 );
38
39
40 end component;
41
42 --Inputs
43 signal take_sample : std_logic := '0';
44 signal data_bus_in_mono : std_logic_vector(11 downto 0) := "101010101010";
45 signal delay_amount: integer := 20;
46
47 --Outputs
48 signal data_bus_out: std_logic_vector(11 downto 0);
49
50
51 -- Internal definitions
52 signal sampling_count : integer := 0;
53
54 -- Clock
55 signal sclk_period : time := 1 us;
56
57 BEGIN
58 -- Instantiate the Unit Under Test (UUT)
59
60 uut: haas_engine
61 port map(
62 take_sample => take_sample,
63 data_bus_in_mono => data_bus_in_mono,
64 delay_amount => delay_amount,
65 data_bus_out => data_bus_out
66 );
67
68 -- Clock process definitions
69 clk_process: process
70 begin
71 wait for 10*sclk_period;
72 take_sample <= '1';
73 wait for sclk_period;
74 take_sample <= '0';
75 wait;
76
77 end process;
78
79
80 -- Stimulus process: testbench pretends to be the haas effect
81 stim_proc_2: process
82 begin
83
84
85
86
87
88 end process stim_proc_2;
89
90 END;
91
92
Appendix H: Resource Utilization
Appendix I: Analysis of Residual Warnings
Appendix J: Data Sheets

Dual Transformer / Isolator

Artcessories

User's Manual
 Signal Flow Chart

SPECIFICATIONS:
Frequency Response: 10Hz-50kHz +/-.5dB@
+4dBu
THD: .01% Typical @ 1kHz,
+18dBu, <.05% @ 100Hz,
+24dBu
Insertion Loss: .4dB@100k Ohm load,
5.5dB @ 600 Ohm load
Input Connections: XLR female balanced,
1/4-inch TRS balanced /
unbalanced, and RCA jacks
Output Connection: XLR male balanced, 1/4-inch
TRS balanced / unbalanced
and RCA jacks
Power requirement: Passive
Dimensions HxWxD(in): 1.75 x 4.2 x 3.5
HxWxD(mm) : 44.5 x 107 x 89

Weight (lbs/kg): .75 / .34