aa | Microprocessor ig o Singla TC CIntegvoted civeuit), Copoble of [Performing avithmetic and Losicak opervotione dadined by |the Programming - [poss net | OLSA 78 oN BbIE microProcasor (MP) Suitable for wide range OF APPUicetions. Tt is a Gingle-chip,jmog device implowanted with approximetely 6 200 brYengistors On a e4ni22 milichip Contained in & 40 Pin dusl-in-Line (DIP) Pacteage - 2085 Featuves ¢ ee ae 4: 80BS 16 & BBIL micvoprocssor. | #T4 7S o 4oPin Dip Couct mitna Package ) TC oPpevotea in | ysv DC Supply . ATE Con oferate vith 3mu2 cleck greauancy (9085) For 8O2SA-2 VErwSTon Com operate at mouxinauws of Sma TE hog 16 oddvess lings, 8 dotolimes Ond 64kKb Memovy HTL hosEbIe GPR Coenerat Purpose Registers) and two lb bit registers (SP oma PC). ae ide Give haxdwove Interreets | 4 Deane) eeraesresr GS. BSIS:'S ond TnTR Ik Con SuPPort 74 Tratmection | & Provides Control Sigvele (LolM,RB,aR D to Control the bus Cycles ond hence extermat bus contvollay not revived | & Tt algo hag Geviat Elo Control which oews | Beviak Communication CSod, $TD) | ARCHITECTURE OF BOBS Microprocessor oe oe eek The architecture OF BoRS consist aP the Following blocs 4 Registe~s * Tncvementev nee Piet | ae Artitnmetic and losic cunt t |p Jalepvenestavertlereteconlbe & Tntervert Contvol and mechina cycle Brody 4 Jevial Ts Contvol | a Address bugter 4 padvess budiev ond deta | buster | A Timing and Control Civceitory +) [AecuitecwRe OF BOSS [A pee )Geweror perpose REaisters + A enter SPURPe SE. REQTSRS, > BCD E,Hamd Lave Sbit Registers Canbe ugedos a Seperate Bbit Reg. ov OS 16 bTE Register Poivs, gc, DE amd HL. ? Wiz ary Capaimmieise Ganction of af CBI polneey ov memory Pointer Fig. 12.4 Architocture of 8085 2) SPECIAL Purpose REGISTERS - Ae EE ee Astumnaoror CARegister) sAccumuatoy if tvistate 8 bit Regtster. STbIs the Part of the Avithmatic [Logic unit , which 75 used to Stove Bit deta during the Arithmetic amet be gicat OPewattons: Cmost of the Lime Regutt wilt Store in A Reg) Flag Regtster > Flag Register fs an Bbit Register - > During Avithmartc oPewotions Flogs ave set ov Reset (1 ove)Addwess | Doto. Budiey + 2 Bere ee Seer 2 | & Addvess [Data buster 1S am EWE Reaister 4 The Content o& the Stock Pointer (ov) Presram Counter Combe oadad in to the oddveas budjer anc adaras dota onder: #¥ The Zbit Internal deta bus addvess data buster - Inte rrert Contyot ¢ Ro 4 Interrupt control a capes the intermet Signals Comming kya external devias and it.contvol dre interrupt activity of Be85MP* BT has Rie Mntecrvet Signal, nawely TRAP, RSTTS, RSTES: ASTSS ane INTR- is algo cowected €o the Te gesior Ele Contwet + ; & Tt Provictes Lwe lives, SoD avd 3 for Serial Conn orion whe gevial OMtPut dake(g on) ling is o3e te Send dote- gevially ond eviol input dake (S 1D) Une fs Uged to veatve doke Sevially - RLOSOeSNa AR RESD |W e Te algo a gbit vedistey Used to Stove the dake | Lempormvily , when ALv Performs tha Competing BSunctions natanaction Reatstesc Y rgumction Registev is an Bbit Nesistey Used Fo (ood Ere Ingtruction 1S Retcved | ingtructton Copcede ), when on Grom memoyy - | 4) ltnatrmction Decoder! |" Decodas the content Of tre 7 nsteuttton Register (ie ot Gund aceominaly Qives Information boty Efealitg and canbe ‘ Axithmetic cod Cogic yale as aontthmetic logic Unit PertForms the arithmetic Opercekions Suchag addition, Swotvec tom ,inCveman | and logit operations CAND, ORaMA Ex-oRD ee APPLcATION oF O85 MP & Used im Colcutotoy A Usedt tw Pro@ss Controt + Used In home apPlianas Sere > ir a USELIM PRowm used tn date acquistion stems Boel werk 4 USeA In militorry applicaaions | # LSet Im ComPuking appliccions | ® Used in Tndustny cont-roliers> Tt has Five. Flags Ui) Stan Flaxs) (i) ZexoPlage) (Aw Corrs Gloag (AC)iv) Parity Ploa(P) WV) Cannd Plog(cy) De_ 95 Dy 93 Do Ps Scores Sealer? SignPles <— sn denin . oe lag) Coors Fes (Al Parity Cl-fP) Sign flea G) 2 a ARLET execution of Atithmeric OPerakion , 1f bit Pa of | the vresult 16 °)', tro sigh Flag is set otherwise FETS veret | Zev Flas) A TE bre DS oFthe Resttis zero ( During Avithee ls ow, | dhe zeve Bleg Is setiothawise ie 1S Reseto> Auxiliary comm Flog (AC) a TR Corry fs generated by aiait Da ond Ped to pisit D4, tha AC Plog ts Sek otherwise Reset - | Party &lea(P) | 8TH awithnete Operation, TS the vesuit hag an Even number of 1's, the Parity lag is Set. TH the vesutt hag an odd number O8 I's fhe Slegis reset co): | CARRY Fle3(ce | HK TN avithmetiC SPEVEKION when Carry 15 gererated, Lhe Corts Plas 1S See CI) Othanwise ie Ts Reset §kock Pointer (SP) ee memory Pointer: C SFR) * Used to hold Lhe address of the bop elawent of tne | Stack Cwhich Potlosg LiFfo Clost in Bivst out) bosis) Program Counter(PC) | + Pwodtaw, Counter 1S a I6bit SER REgistey & Used to hold the memory oddvess of the noxt instyuction to be @xecuted - ‘* DePends onthe execution Program Counter HenCvewantey /Decementer, + Incevementer/Deeremertey 5S an 16-bit register # TA is used €0 add (ory Subtract one Prom the content oP any of the lbbit register . CSP oy PC) % Stack Pointer 15 & Ib bit TEQSter to be UBEd og ov | |oF 8085 mP Pin Detans eA MPSS DARe U -—S ae. 10/7% } Sate | ia5 | sone }—- WR 1 Recetot owe veces, 28 oe Fig. 1.31 (a) Pin configuration Fig. 1.3.1 (b) Functional pin diagram VEC &VSS2 Te Requives +5V DC Supely with Ground | KramaX. 2 A tuned Civeuit Lixe LO, RC ov crystar is Connected at those two Pins. The interned Clk Jenevator divides ogCietoy Frequency by 2, Cie internat Clk Freq. is gmnz, theve Gore Crystal osc. must“ ak Breq .of Smad Clk OUTS Used os a System Clock For other davies .Tts Frequency is hol@ the oSciuate+ Prequency. Dorvbus and Addvessgus SThe BbIe cletabus (Do-Dr) 75 multiplexed with the ener) hag (Ao-Ar) of the obit oddvess bas. DS During 3t Part oF the machine Cycle (Ti) , lower sbits of Mamors acldvess appear on the bus and remaining Port of De mochima Cycle (T2 ond Tz) these limes ove used as @ bidivecttoral data bus5 | AgtoAis : The wppey hal of tre 16bit addwess | appears on the addvess lines As toAis (mse of | tb bit ody) Contvol and States Signals + DAN AS A (a) ALE! Addwess (etch enable ls active high Signet used to damuttiple, Ma addveszs and deotebus seperately daving T, wet 4b TeAines exterrnar lech Ta Tg mochine cycles Cx bo SePevate addy. ond dot= bea) | ee ae =o | QO) RD LGR : A be on RB indicates that tha date must! be dead Gre te Gelacted wersrilecstions ov Tle Port vie date bus A lew on WR indicates thar the data must be writtey inte the selacted memory lecotion ov T lo Ports vie datebus (C) To] , $0 nds Tradiceees whathaw Tlo operation ‘ We OT mamery oPerekion Tol +0 , memory oPeration TolM =1 ,Tlo operextens Gots) | indicates the type of mechne Cycle in Progyeks. (WP) READY T Te Ts usecl by tha MicwePwecasser to Sense wlethey & Peripheral 15 weady ov not €or doty trometer, TE not, the Promeser Woes Tt is thug Used CO Synchronize Slowey Peripherals to he microproGsser: Interrupts SiGwers the $085 hag five havduarve intevvust SPonats | RST+S RSTbS, RST SS , TRAP ANA TNR. Tha micvopracaasey Yecognilos Intertepe Vequegts on loge Lines at the ent o€ the Cuvveht InStyactiom execution The INTA CIntevruet Acxnowledge) Signal *5 used to indi RVG tne) Seema MN oe cote ledlne lite Tenet cet reeeSeviet Tlo Stgnat ® (A) HeLD: Tndtcotes that anothey master is Vequesting Pov the Use of addvessbus, clatabus and Cont~at bus (B)HLDA! This active high Signet Msused te atknow -ledge Hold Reqwest. eset Signa A) RESETINIA low on this pi DSets the Progvam Counter te 2evo(oeecH) and Ckovs INTE Plog ie the Trtewrupe enable ana HULDA Glip_Slees 3) Tri- states the dota fae Shr contol bug S 4) A ¢tect s the © bo ener eta ee i ee f | OReser sy y a | a aaa OUTS This active high Signet t Poca ing ¥ * | opens: ey This Signal fs synchvoniaed to the pins cK amd i€ Can be used to veset other Ib vides Covmected in the $ygtem - NSTRUCTION ExEcUTION AND DATA Flaw Iw goss dy in order bo execute Prograwn, tha Stovting addwess o8 Cra Prozvom $8 Conded jneo tha Progam counter (PC) « \ FAD ats: qoas sends tra Camas ob pc on om oddvets/on-tht-odd woes is and | * acuveses RB contrat signet | xuPpon yealvine the addvess ona Bd Signet memory Pues the Contents| of adbtessed memory Lacation on Une dake lous Which |s am oPcode of Of cenatraction, Mearwainte PC 1S incvemented to Poiht tha naxt amary Lecation in the Program seqnenet | oN ts daactiveseA ond opceda. 78 Loaded into the Instruction syegister via tatevnel bus of microproassoy |e Tha Ingernction dacoding unit decodes tne instruction amd TaRermosion £0 the Uming ond control unit to # ®D sisi ovides : wee Teaser SignlS oy Tngtyaction execetion - \ eae = ve ¢, 0% gee MNT C,08K Coa ascaset ore Ewo OPevation convert. ID oP es ae inte Nex J0e0 TSE l opcede eee! 28 | date AdT C,08H