GaN Device Technology: Manufacturing,
Characterization, Modelling and Verification
W. CICCOGNANI_, F. GIANNINI', E. LIMIT] , P.E. L ONGHI_, A. NANNI_, A. SERINO', C. LANZIERI2,
M PERONI2, P. ROMANINI2, V CAMARCHIA3, M PIROLA3, G. GHIONE3
Dipartimento di Ingegneria Elettronica, Universit'a di Roma 'Tor Vergata', via del Politecnico, 1, 00133 Roma, Italy
2
SELEX Sistemi Integrati S.p.A., via Tiburtina Km 12,400, 00131 Roma, Italy
3Dipartimento di Elettronica, Politecnico di Torino, Corso Duca degli Abruzzi, 24, 10129 Torino, Italy
Abstract. Gallium Nitride , superior physical
properties, in comparison with other semiconductors,
make GaN HEMT active devices a prime candidate in the
implementation of next generation transmitters for radar
systems, 3G/4G base stations and WiMAX In this
contribution, the characterization, modelling and
verification of di,ferent families of high efficiency, high-
power devices manufactured at SELEX Sistemi Integrati
are reported. Process, characterization and modelling
phases are analyzed to improve and refine the
technology
s fabrication techniques, thermal degradation
issues and dispersion phenomena.
Keywords
GaN Technology, FETs characterization, load pull.
1. Introduction
Next generation wireless communication systems will
offer better telecommunication services with higher data
rate and bandwidth. The microwave active device in the
front-end high power amplifier (HPA) delivers large RF
power levels at high frequency operating at elevated
temperature. Linearity should be optimized to meet the
requirements of high capacity and quality of service in
these systems, in addition to large RF output power and
power added efficiency (PAB).
Nowadays, electronic devices based on Gallium
Nitride (GaN) are becoming increasingly attractive for
high power applications. The key advantages offered by
GaN technology for RF power electronics consists in the
combination of higher output power density (even at high
frequency), larger bandwidth and increased linearity
compared with other existing technologies. These
features directly derive from the semiconductor's
physical properties: the large band-gap generates a
breakdown electrical field ten times larger than Si. This
allows transistor operation at high bias voltages. The
increased saturation velocity, combined with greater
current density in the two-dimensional electron gas,
ensures high power handling up to mm-wave
frequencies.
The most successful GaN device still remains the
AlGaN/GaN high electron mobility transistor (HEMT).
One of the key challenges for the widespread of this
technology is however the control of the thermal
degradation and the trap effects (essentially surface traps
resulting from the piezoelectric nature of the devices) on
978-1-4244-2138-1/08/$25.00 ©)2008 IEEE
the RF characteristics, often known as frequency
dispersion effects in Nitrides. In such context,
AlGaN/GaN HEMTs require a precise device technology
optimization, a critical characterization phase and an
accurate and verified large-signal modelling. All these
three aspects are analyzed in this contribution.
In Section II, GaN HEMT technology is presented,
together with the resulting physical structure. In Section
III, active device characterization and modelling steps are
described in detail. Finally, to validate the modelling
approach, the experimental results of active load-pull
measurements on a GaN HEMT are presented in Section
IV.
2. Device Technology
The technology currently developed in SELEX Sistemi
Integrati enables two different solutions for MMIC
realisation, i.e. Coplanar Wave-Guide (CPW) and
microstrip (MS) guiding structure. This process is based
on aepi-laytrc
on ofGa/sa/a
semi insulating SiC substrate by either N Deos or
MOCVD
M
MBE techniques. The mask levels for MMIC fabrication
are based on a mix and match procedure using both I-
Line Stepper and Electron Beam Lithography (EBL)
techniques. The latter is only used for the fabrication of
the high resolution 0.25ptm gate length to obtain higher
cut-off frequencies. The device's drain and source
electrodes are realised by ohmic contact formation of a
Ti/Al/Ni/Au metallisation to the GaN/AlGaN epi-layer
via a high temperature alloying cycle. Wafer passivation
for surface protection is carried out by SiN plasma-
enhanced chemical vapour deposition (PE-CVD), while
the active device isolation is achieved via Fluorine ion
implantation. The SiN passivation film deposition has
been optimised in order to minimise the carrier trap
concentration at the interface with the semiconductor in
order to conceal the detrimental active devices' drain
dispersion phenomenon. Besides active device
development the MMIC fabrication process comprises:
NiCr thin-film resistors, Metal-Insulator-Metal (MIM)
capacitors, electro-plated inductors, interconnected
trnmiso lie n i-rdesweencsay
Microstrip MMIC fabrication process is ended with
back-side wafer processing for via-hole interconnections.
Such process incorporates: wafer thinning, via-hole
etching by means of an Inductively Coupled Plasma
(ICP) dry etch process and finally back-side (substrate summarised in Table 1. The DC I-V characteristics
and via-hole) metallisation with a thick electro-plated Au however do not allow assessing completely the RF
film deposited on an appropriate barrier metal layer. The dynamic electrical behaviour of GaN microwave devices.
technology's Process Design Kits (PDKs) are available 1000- - --

for AWR's Microwave Office platform. The non-linear 900 - VGS=+0V

active device models are based on state-of the art power 800 _ -VGS=-1 .5 V
VGS=-2.0 V
performance for large gate periphery devices (> 1mm 700 i- VGS=-2.5V
VGS=-3.5 V
total gate width) as confirmed by appropriate source-load 600_ VGS=-45V - VGS=-5.0 V
pull measurements, in Section III and IV. 500 E=; -VGSV-5.5V
400 - T -VGS=-7.5VI
/ - VGS=-8. V
300 -

100 ~- ------ -
-- -

0 2 4 6 8 10 12 14 1~6 18 20 22 24
VDS (V
Fig. 2 DC IV measurements for Imm device in microstrip
technology with 0.5 ur channel length.
Device Technology Microstrip Coplanar
vs. gate length
channel length IMAX=0.75 A/mm IMAX=0.91 A/mm
0.5 pm
~~~Pdc,max=6 W/mm Pdc,max= 11
W/mm
channel length IMAX0.7 A/mm IMAX=O.95 A/mm
0.25 1pm Pdc,max=5 W/mm Pdc,max= 8 W/mm

Table 1 Maximum DC Current and Dissipated Power measured

for each GaN technology.

Fig. 1 Microstrip Device detail (upper) and via hole SEM
photograph after back side gold plating (lower)
Typical GaN-HEMT power density performance is in
the range of 5-6 W/mm with power added efficiency
better that 4500 right up to X-band. Performance for low
noise applications is comparable with the best GaAs
pHEMT results (i.e. N.F. < 1 dB at X-Band). A family of
different MMICs have been designed, fabricated and
tested with this process. In particular: S-Band power bars
and combiners, an X-Band HPA, a 2-6 GHz wideband
HPA and X-Band power switches.
3. Characterization and Modelling
An extensive characterization campaign was carried
out by the University of Rome Tor Vergata on several
SELEX Sistemi Integrati GaN HEMT devices having 0.5
or 0.25ptm gate length. Both microstrip and coplanar
guiding structures were analysed and the total gate
periphery varied from 0.1 mm to 1.2 mm. Several
measurement techniques (DC I-V, pulsed I-V and
hot/cold S-parameters) were employed to select the kind
of device exhibiting the best performance and to select
the device sample better representing the electrical
behaviour of the considered family of devices.
DC IV mesureentshavebeenperfrmedby mans
of a curve tracer. The drain-source voltage was swept
from 0 to 24 V while the gate-source voltage was varied
1 V. Such measurements allow deter-
firom -8 up. to. .
minngth man C araetrs suh s MAxmman
Pdc max/mm, for each guiding structure and gate length, as
RF GaN performance is affected by dispersion and
thermal phenomena. Such effects cause dispersion in the
transistor's I-V characteristics as well as in the
transconductance gm and output conductance gds. I-V
measurements under short (1 to 2 pis) pulse conditions
provide a useful method to investigate dispersion and
thermal effects in microwave devices and are a helpful
tool to evaluate semiconductor process improvement
efforts. Pulsed I-V measurements have been performed
using an on-wafer measurement setup essentially
composed by a probe station and a GaAsCode [1] pulsed
measurement system. Many quiescent bias points have
been investigated applying pulses at the device terminals
having an interval of 0.5ts with a separation of 0.5ms,
[2-4]. The pulsed drain-source voltage was swept from 0
to 24 V, while pulse gate-source voltage was varied from
-8 up to 1 V. To highlight any frequency dispersion
effects, as seen in Fig. 3, pulsed I-V curves have been
compared at two representative bias points:
1)
2)
VDS=2 V, VGS=O V
VDS=25 V, VGS=7 V
Bias 1) is relative to no DC electric field applied to the
active device. In such condition traps are not activated.
On the other hand, for a high electric field at drain and
gate terminals, as in bias 2), the traps play a determinant
rol on teIVdnmc urs.C paig uh
mesrmns as seni 'i.3 ti osbet bev
@ bias 2) a reduced ID,MAX and a higher Vknee. When
~~~~~~~~~~~driving
GaN devices with a high drain voltage, the knee
voltage increases with a degradation of the output power
 Onteohr,wdcs
and a drop in the efficiency due to the higher DC power
dissipation as seen in Fig. 3.

<E
1000

D
900

500
100
400

200 /

Fig. 3
8

0
i
/
§'
.g* - F

4
(

6 8
0t

300 -gX O't <-> 600

10
-
-

100c currentforeachGaNtechnology1Sreportedm|technology.
2 12
Pulsed VDS (V)
t
r-

14
X-

16

Pulsed I-V measurements of Imm device at two bias

Vg--1

7) (doffed line); on microstrip technology with 0.5gm

channel length.

On the other hand, when decreasing the drain voltage

to 20 V, pulsed measurements show a moderate
dependence from the quiescent bias point thus
demonstrating that traps do not seriously affect the
device dynamic response in this condition. The maximum
dynamic current for each GaN technology is reported in
Table 2 when the quiescent bias point is fixed @ 20 V
and the drain current is equal to 300o Of IDSS,
demonstrating that pulsed currents are comparable to the
DC currents in Table 1.
18

points (VDS=OV, VGS=OV) (solid line) and (VDs=25 VGS=-

T-+ .T0V--

20
~ ~
vgs=+1.0
9008VgS=+0.0V

Vgs=-3.0 V
--Vgs=-4.0 V
t 7008 0Vg=-5.0 V
15

u ~~~~~~~~~~~~~~~~~Vgs=-6.0
Vgs=-7.0 V
V
-~~~~~~~~~~~~~~~Vgs=-8.0
-
V

L = X =

300 -0.1

22 24
~ ~

1T5

_
c
25
20 20\

-5

20
20
01

Iep

.101
\

101
(L)
~~~ustrip SLX

10.1
L
co-planar SLX
VDS=20E) V, ID= 0.3IDS

VDse2e V, ID 0.31DSS, for the 0.5gim gate length

-~~~~~~

11.0.
-i(R)(L)
201
(R)
ustrip SLX 3

(R)
co-planar SLX
for the 0.-Vgs=-2.0

20.1
Fig. 4 S parameters measurements for the Imm device biased at

co-planar SLX

~~(L)
ustrip SLX

(G Hz)
0

20131

Fig. 5 S parameter measurements for the 0.6 mm device biased at

VDso2t V, ID= 0.3 IDSS 0.25g5mgate length technology.
l2

301
V

30.1

co-planar SLX

(R)24SLX
ustrip
36
30

24

12

1o
6

0
-

<
E

4040

32

16th
.

<

Device Technology Mistr Coplanar The active devices have been modelled using a second
vs channel length Mcotp Cplnr generation Angelov model [6]. For this purpose, DC and
channel length O.5pm ImAx=0.82 A/mm IMAX=0.95 A/mm pulsed I-V measurements and bias dependent 5-
parameters measurements have been performed on the
charametlengthrs
channelqlengthcy .25pm
251-im 'MAX=O.75 A/mm
ImAx=0.75A/mm 'MAX=O.96
IMAX=0.96 A/mm most representative 1mm devices. A bias-dependent
Table=20VMaximum dynamic current VDs= VV and
small-signal equivalent circuit model of each selected
table
2.dMaximumidynamicfcurrenterentS~2O and ID=0.31DSS
'D0.3IDSS device was preliminarily extracted using the measured 5-
Finceally, theion parameters have been measuredto parameters, [7], to obtain the value of the linear elements
Finally,the s-parmtsihav be nmeasured of the Angelov model and the voltage dependence of its
ealuatedevices ' smllsinal perforan (gain and non-linear part. The large signal equivalent circuit model
maximumed operati rncy) using neon-waferysetu
inludein eprob topology, adopted for the microstrip 0.5Rm gate length
device is illustrated in Fig. 6.
Taking into account the device's power ratings, the 5-
parameters have been measured with a maximum test
frequency of 40 GHz and a typical bias point of G LG RG Rgd RD LD D

VDS=2OV andlD=0S31DSS toucompare the performance of

the different measured device samples. Results of this gr Dg d,Cd
characterization activity are shown in Fig. 4 and Fig. 5 in C~CD
which respectively 0.5 and 0.25cum gate length microstrip Rb
devices are compared with coplanar ones. As result of the erCPG
described characterization work, the most representative Rs
1mm device for each guiding structure and gate length
has been selected and consequently the non linear model L

reported 6al Non lineaequvlenothesalsga

Fig. circuit'moel

ones.
 Rg Rs Rd
Parasitic Lg Ls Ld Cpg Cpgd Cpd 900

Element Q |Q |Q pH pH pH fF fF fF 800
700
0.5 urn
1.4 1 1.8 55 2 115 110 0 45 E 600 Meas
CWG
p500 X-11 =Sim (mA)
0.5pm40
3.8 1.3 1.8 55 10 26 30 0 130 400
pstrip c= 0

0.25pm 200
CG 0.5 0.9 1.3 15 2 90 130 0 55
CWG 0100
0.25,um 0 2.5 5 7.5 10 12.5 15 17.5 20 22.5 25
5 2.6 6 56 14 55 33 0 44 pulsed VDS
pstrip Fig. 8 Measured (circle) and modelled (line) pulsed I-V
characteristics of the 0.5 MS device @ 300% IDSS, VDS =20
Table 3 Extracted parasitic elements for each best representing Vc
Imm device.
The intrinsic nonlinear elements (Ids, Cgs and Cgd) have 40 8
been represented through analytical functions 35_ _0 ° ° 0 XX 0X 7
implemented in the model. The values of the intrinsic
resistances Ri and Rgd and the intrinsic capacitance Cds 30 -
_ f

\° 1 6
were obtained from the small signal model. Finally, the 25- NO
, 5
parameters of the diodes (Dgs, Dgd) have been determined I 2X
by DC I-V gate measurements performed during the 0 1
Cold-FET characterization. 15 II I3
Fig. 7 shows the measured an modelled S-parameters 10- 2
at VDS=20V and VGS=-3V, while a comparison between 5- - 1
measured and simulated device I-V characteristics, o lo
obtained by pulsing the same bias point, is shown in Fig. o 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34
Pav,in (dBm)
8.
Fig. 9: Measured (circle) and simulated (line) power performance
Swp Max of 0.5 MS device in optimum power load condition (FL=
/ 20.1GHz 0.56, 127°), measured by Politecnico di Torino @ 30%
- S(1,1) V S(1,1) \IDSS, VDS = 20 V.
Sim Meas \ The non linear models have been implemented in a
-5S(2,2) 5(2,2) .commercial CAD tool (AWR's Microwave Office) and
have been verified by power sweeps measurements, Fig.
9, and by an extensive load pull campaigns described in
Section IV.

4. Load Pull Verification

The active load-pull bench from Politecnico di Torino
[8], shown in Fig. 10, has been exploited in this work to
wp Mn Pinvestigate thermal effects on GaN devices. This setup is
(a)
~
0.1GHZ a real-time active load-pull test bench, based on the
active loop technique; the system enables to measure in
28 X DB(IS(21)I) (L) 0 real-time both the amplitude and phase of the incident
24 t \ Sim
Ang(S(2,1)) (R, Deg)
-
150 and reflected power waves at the DUT reference plane,
20 DB(IS(2,1 (L)
MeLs
120Sim bench atis fundamental
both
able to derive
and harmonic frequencies. The
device relevant figures of merit
16o Ang(5(2,1))(R, Deg 90 such as PouT, Gain, Power Added Efficiency (PAE), 17N,
12 60 rL and operates in the 0.5-18 GHz band. The incident and
80 S X~~~ 30 reflected power waves at the input and output ports (port
4
k X 0 ~~~~~~~~~~~1
and 2) are measured (sampler 1 and 2) with a Vector
Network Analyzer (VNA). The VNA is standard
00. 2.1 calibrated at the on-wafer reference planes and power
0214.1 6.1 8.1 10.1 12.1 14.1 16.1 18.1 20.1 calibration with a power meter is added for power
FreqUenCY (GHZ) measurements capabilities [9].
(b)
Fig. 7 MeaSUred (CirCle) and mOdelled (line) device S-ParameterS
Ofthe 0.5 MS device @R300% IDSS, VDS =20 V.
 sampler 2

C3sampler 1 a1 as icga1
input variable b; || A
attenuator port 1 port 2
microwave
source DUT
al~ a2
b . b2
(a)
variable phase tunbl
attenuator shifter tfitaer

port 3

bias T
output loop
amplifier
(b)
Fig. 10 (a) Real-time harmonic active load-pull set-up with intermodulation capability and (b) active implementation of the output load..
Details on test-set and calibration can be found in [8]

40
The characterization of SELEX Sistemi Integrati F,
devices has shown promising output power performance, 35
Gain(dB)
in the order of 4 W/mm at 3 dB gain compression, as 30
demonstrated in Section III. The scaling properties are 25
respected going from 0.4ptm periphery up to 1.2 mm. The
nonlinear characterization has been performed at 4 GHz 20
for small and large periphery devices (4x100 ptm and 15
12xlO0 pm) up to VDS 40 V and from 30% IDSS UP to
=
10
roughly 50% IDSS (Class A operation) to stress eventual 5
thermal effects. Such characterisation shows high power
densities in the order of 3.6 W/mm and 4 W/mm at 3 dB 20 -10 0 10 20 30
gain compression, for the 4xlO0 ptm and 12xlO00 m Pin,dBrn
devices respectively. The corresponding efficiency is also (a)
satisfactory (in the order of 34 00 and 32 0/O). An example
of power sweep POUT VS. PIN, gain and PAE in optimum
power load condition (FL= 0.17, 990) for a 12x100 jim
device biased in class AB is shown in Fig. 1. Despite
the quite demanding bias conditions (from Class AB to 3

Class A with high VDS voltage up to 40 V) it is worth 33.5

noticing that the characterized devices have shown a

robust behaviour, not affected from leakage or stress also
after RF stressing consisting over several power sweeps. 32

(b)
Fig. 11 (a) Power sweep POUT VS PIN, gain and PAE in optimum
power load condition (FL= 0.17, 99°) for a l2xlOQim
device biased in class AB, 30%o IDSS, VDS =40 V at 4 GHZ
(upper).

(b) POUT contour plot for 3dB of gain compression in the

FL plane for the same device biased in class AB, 3000 IDSS,
VDS =30 V at 4 GHZ; squares show the loads synthesized
by the load-pull set-up, while the yellow square represent
the optimal load (lower).
5. Conclusion
A set of SELEX Sistemi Integrati GaN HEMTs on
different guiding structures, the various steps adopted for
their characterization, modelling and model validation
have been presented. The entire process flow and the
relevant results demonstrate that the development of GaN
process and devices is rapidly progressing towards
reliability, confirning the initial and challenging results
promised by wide band-gap semiconductors for high
frequency applications.

Acknowledgment
This work was supported by the European project
Key Organization for Research on Integrated circuits in
GaN Technology (Korrigan), RTP N° 102.052 funded
within the EUROPA framework in the CEPA2 priority
area.

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