Electronics & ICT Academy

(An Initiative of Ministry of Electronics & Information Technology (MeitY), Government of India)

Please read the Instructions carefully

Instruction Set to be followed for the enrollment and attending the Online FDP Jointly
Organized by Electronics & ICT Academies at IIT Guwahati and MNIT Jaipur

 A WhatsApp Group will also be Joint FDP by respective coordinator (2-3 days before the
commencement of the session after the last day of registration) where every participant will be
asked to join. The link for joining the WhatsApp group will be shared through Email by the
coordinator.
 All information regarding the online FDP will be updated in both Google Classroom and the
Whatsapp Group.
 The session will be held using the Video Conferencing (VC) Application “Cisco WebEx Event”
for first 900 participants. Rest of the participants can attend the sessions live through YouTube.
The link for YouTube will be shared with the participants in WhatsApp Group.
 The participants need to ensure proper data connectivity and sufficient bandwidth to run the
WebEx Event Platform smoothly. The system should have the minimum system requirement.
E&ICT Academy IIT Guwahati is not responsible for any query related to system malfunctioning.
 A WebEx Event invitation mail will be shared with participants prior to the beginning of the
sessions. Participants need to join each session with their Full Name and registered E-mail id for
daily attendance.
 Continuous Monitoring and Assessment will be conducted by E&ICT Academies and respective
coordinators.
 The theory assessment will be through Google Quiz.
 Incase of any query/problem/issue regarding the registration, you may email us at
eictacad@iitg.ac.in/eictiitg.nkn@gmail.com

Protocols to be followed while attending the session through Video Conferencing Application

 The participants need to input their Full Name and registered Email ID while joining to the VC
application.
 The participants should attend the sessions individually. Two or more participants attending the
sessions via a single system will not be allowed.
 The participants are requested to mute themselves for the session while the Resource Person is
delivering.
 Incase of any doubt/query, the participants may raise their issue in the Chat Box / Q&A section of
the VC application or in the Whatsapp Group.
 The participants are requested to make a good practice of using the Chat Box / Q&A section to
maintain the decorum of the session.
 Electronics & ICT Academy
(An Initiative of Ministry of Electronics & Information Technology (MeitY), Government of India)

Pre-requisites for the Course

 Course Pre-requisite: Digital Logic, Hardware Modeling in Verilog/VHDL (basics)

 Hardware Requirement: Linux Machine with a minimum 2GB RAM (preferably 4GB)
 Tools: Quartus, Icarus Verilog, EUVM, Gtkwave, Qemu with ARM Ubuntu Image, EUVM
Note: Code for all the LABS will be provided on Github
 Please find the below pre-requisite online training links.
1. Basics of Programmable Logic: FPGA Architecture
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1006.html
2. Introduction to Verilog HDL
https://www.intel.com/content/www/us/en/programmable/support/training/course/ihdl120.html
3. University Self-Guided Lab: Introduction to FPGAs and the Intel® Quartus® Software
https://www.intel.com/content/www/us/en/programmable/support/training/course/ouwintro.html
4. University Self-Guided Lab: Become an FPGA Designer in 4 Hours
https://www.intel.com/content/www/us/en/programmable/support/training/course/odswbecome.ht
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5. Introduction to Platform Designer
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsys1000.htm
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6. Creating a System Design with Platform Designer: Getting Started
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsyscreate.ht
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7. Creating a System Design with Platform Designer: Finish the System
https://www.intel.com/content/www/us/en/programmable/support/training/course/oqsysfinish.ht
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8. SoC Hardware Overview: the Microprocessor Unit
https://www.intel.com/content/www/us/en/programmable/support/training/course/oemb5500.html
9. Hardware Design Flow for an Arm*-based Intel® SoC FPGA
https://www.intel.com/content/www/us/en/programmable/support/training/course/osoc1000.html
10. Software Design Flow for an Arm*-based Intel® SoC FPGA
https://www.intel.com/content/www/us/en/programmable/support/training/course/osoc2000.html
11. Using the Intel® Quartus® Prime Standard Edition Software: An Introduction
https://www.intel.com/content/www/us/en/programmable/support/training/course/odsw1100.html
12. Introduction to Parallel Computing with OpenCL™ Programs on FPGAs
https://www.intel.com/content/www/us/en/programmable/support/training/course/oopncl100.html