Vlsi Design Techniques For Analog and Digital Circuits PDF

VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Randall L. Geiger Department of Electrical Engineering Texas A&M University Phillip E. Allen Department of Electrical Engineering Georgia Institute of Technology Noel R. Strader MCC Austin, Texas McGraw-Hill Publishing Company New York St. Louis San Francisco Auckland Bogota Caracas Hamburg Lisbon London Madrid Mexico Milan Montreal New Delhi Oklahoma City Paris San Juan Sao Paulo Singapore Sydney Tokyo TorontoThis book was set in Times Roman by Publication Services, Inc. ‘The editors were Alar E. Elken and John M. Morriss; the production supervisor was Janelle S. Travers. ‘The cover was designed by Robin Hessel. Project supervision was done by Publication Services, Inc. Arcata Graphics/Halliday was printer and binder. VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Copyright © 1990 by McGraw-Hill, Inc. All rights reserved. Printed in the United States of America. Except as permitted under the United States Copyright Act of 1976, no part of this publication may be reproduced or distributed in any form or by any means, or stored in a data base or retrieval system, without the prior written permission of the publisher. 1234567890 HALHAL 89432109 ISBN 0-0?-023253-4 Library of Congress Cataloging-in-Publication Data Geiger, Randall L. VLSI design techniques for analog and digital circuits. (McGraw-Hill series in electrical engineering) Includes index 1, Integrated circuits-Very large scale integration-Design and construction. I. Allen, P. E. @hillip E.) IL. Strader, Noel R, Il. Title. IV. Series. TK7874,G43 1990 621.381°73 88-3737 ISBN 0-07-023253-9VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITSMcGraw-Hill Series in Electrical Engineering Consulting Editor Stephen W. Director, Carnegie-Mellon University CIRCUITS AND SYSTEMS COMMUNICATIONS AND SIGNAL PROCESSING CONTROL THEORY ELECTRONICS AND ELECTRONIC CIRCUITS POWER AND ENERGY ELECTROMAGNETICS COMPUTER ENGINEERING INTRODUCTORY RADAR AND ANTENNAS VLSI Previous Consulting Editors Ronald N. Bracewell, Colin Cherry, James F. Gibbons, Willis W. Harman, Hubert Heffner, Edward W. Herold, John G. Linvill, Simon Ramo, Ronald A. Rohrer, Anthony E. Siegman, Charles Susskind, Frederick E. Terman, John G. Truxal, Emst Weber, and John R. Whinnery VLSI Consulting Editor Stephen W. Director, Carnegie-Mellon University Elliott: Microlithography: Process Technology for IC Fabrication Geiger, Allen, and Strader: VLSI Design Techniques for Analog and Digital Circuits Offen: VLSI Image Processing Ruska: Microelectronic Processing: An Introduction to the Manufacture of Integrated Circuits Seraphim: Principles of Electronic Packaging Sze: VLSI Technology Tsividis: Operation and Modeling of the MOS Transistor Walsh: Choosing and Using CMOSCONTENTS RURBRES = 2.3 24 2A 2B Preface Practical Considerations Introduction Size and Complexity of Integrated Circuits The Microelectronics Field IC Design Process Economics Yield Trends in VLSI Design References Problems Technology Introduction IC Production Process 2.1.1 Processing Steps 2.1.2 Packaging and Testing Semiconductor Processes 2.2.1 MOS Processes 2.2.1a_ NMOS Process 2.2.1b CMOS Process 2.2.1¢ Practical Process Considerations 2.2.2. Bipolar Technology 2.2.3 Hybrid Technology Design Rules and Process Parameters Layout Techniques and Practical Considerations References Problems Appendixes Process Characterization of a Generic NMOS Process Process Characterization of a Generic CMOS Process xiii 10 12 16 19 28 29 Px) ae 32 ep 33 41 42 46 49 55 59 64 68 oP 78 85 85 95 i. 108vi CONTENTS 2c 2D. 2B 3 3.0 Ey 3.2 a. 3.4 3.5 4.0 41 42 43 44 Process Characterization of a Generic Bipolar Process Process Characterization of a Generic Thick Film Process Process Characterization of a Generic Thin Film Process Device Modeling Modeling 3.0.1 de Models 3.0.2 Small Signal Models 3.0.3 Use of Device Models in Circuit Analysis MOS Models dc MOSFET Model Small Signal MOSFET Model High Frequency MOSFET Model Measurement of MOSFET Model Parameters Short Channel Devices Subthreshold Operation Operation in the Third Quadrant of the Ip — Vos Plane Modeling Noise Sources in MOSFETs Simple MOSFET Models for Digital Applications Diode Models 3.2.1. de Diode Model 3.2.2 Small Signal Diode Model 3.2.3. High-Frequency Diode Model Bipolar Models 3.3.1 de BJT Model 3.3.2. Small Signal BJT Model 3.3.3 High-Frequency BJT Model 3.3.4 Measurement of BJT Model Parameters Passive Component Models 3.4.1 Monolithic Capacitors 3.4.2. Monolithic Resistors Summary References Problems Ee Ei 1 1 Ae 1 1 a is weehaurobe Circuit Simulation Introduction Circuit Simulation Using Spice MOSFET Model 4.2.1 Level 1 Large Signal Model 4.2.2. Level 2 Large Signal Model 4.5.3 High-Frequency Model 4.2.4 Noise Model of the MOSFET 4.2.5 Temperature Dependence of the MOSFET Diode Model 4.3.1 Large Signal Diode Current 4.3.2 High-Frequency Diode Model BIT Model 4.4.1. Large Signal BIT Model 4.4.2 High-Frequency BIT Model 118 ipa 130 132 kee 134 134 139 143 144 158 161 167 i 174 177 180 185 187 187 190 190 191 192 202 205 208 210 211 213 221 a 222 237 237 237 240 24L 244 246 251 251 252 253 254 255 256 26145 4a 4B 4c 5.0 a. heed 5.3 5.4 5.5 5.6 6.2 63 6.4 6.5 4.4.3 BIT Noise Model 4.4.4 Temperature Dependence of the BJT Summary References Problems Appendixes Mosfet Parameter Definitions Diode Parameter Definitions BJT Parameter Definitions Basic Integrated Circuit Building Blocks Introduction Switches Active Resistors Current Sources and Sinks Current Mirrors/Amplifiers Voltage and Current References Summary References Problems Design Problems Amplifiers Introduction Inverting Amplifiers 6.1.1 General Concepts of Inverting Amplifiers 6.1.2 MOS Inverting Amplifiers 6.1.3 BIT Inverting Amplifiers Improving the Performance of Inverting Amplifiers 6.2.1 Current-Driven CMOS Cascode Amplifier 6.2.2 Voltage-Driven CMOS Cascode Amplifier 6.2.3 Improving the Gain of the CMOS Cascode Amplifier 6.2.4 The BJT Cascode Amplifier Differential Amplifiers 6.3.1 CMOS Differential Amplifiers 6.3.2 BJT Differential Amplifiers 6.3.3 Frequency Response of Differential Amplifiers 6.3.4 Noise Performance of Differential Amplifiers Output Amplifiers 6.4.1 Output Amplifiers without Feedback 6.4.2 Output Amplifiers with Feedback Operational Amplifiers 6.5.1 Characterization of Op Amps 6.5.2 The BIT Two-Stage Op Amp 6.5.3 The CMOS Two-Stage Op Amp Cascode Op Amps Op Amps with an Output Stage Simulation and Measurement of Op Amps CONTENTS Vii 262 263 264 265 271 2m 280 282 287 287 289 302 318 333 354 372 372 373 376 378 378 379 379 389 407 414 416 418 419 426 431 432 449 452 454 455 466, 473 473 481 485 488 491 494viii CONTENTS 6.6 Comparators 6.6.1 Characterization of Comparators 6.6.2 High-Gain Comparators 6.6.3 Propagation Delay of Two-Stage Comparators 6.6.4 Comparators Using Positive Feedback 6.6.5 Autozeroing 6.7 Summary EES References Problems Design Problems Digital Circuits Introduction Design Abstraction Characteristics of Digital Circuits 7.2.1 Logic Level Standards 7.2.2. Inverter Pair Characteristics 7.2.3 Logic Fan-out Characteristics 7.2.4 Digital Logic Analysis Single-Channel MOS Inverters 7.3.1 Basic Inverter 7.3.2 Inverter Device Sizing 7.3.3 Enhancement-Load versus Depletion-Load Inverters 7.4 NMOS NOR and NAND Logic Circuits 75 7.4.1 Basic NMOS NOR Logic Circuits 7.4.2. Basic NMOS NAND Logic Circuits 7.4.3. Multi-Input NAND and NOR Logic Circuits Complementary MOS Inverters 7.5.1 A Basic CMOS Inverter 7.5.2 CMOS Inverter Logic Levels 7.5.3. Inverter Device Sizing 7.6 CMOS Logic Gates 1d 7.6.1 CMOS NOR Logic Gate 7.6.2. CMOS NAND Logic Gate 7.6.3 Multi-Input CMOS Logic Gates ‘Transmission Gates 7.7.1 | NMOS Pass Transistor 7.7.2 CMOS Transmission Gate 7.8 Signal Propagation Delays 7.8.1 Ratio-Logie Model Process Characteristic Time Constant Inverter-Pair Delay Superbuffers NMOS NAND and NOR Delays Enhancement versus Depletion Loads .8.7 CMOS Logic Delays 7.8.8 Interconnection Characteristics 7.9 Capacitive Loading Considerations 7.9.1 Capacitive Loading 7.9.2 Logic Fan-out Delays 499 499 502 507 Sil 514 518 518 bt) 524 525 a 526 528 528 530 532 532 534 534 ae ae 540, 540 542 543 544 546, 546 548 aa. 551 553 556 558 559 562 564 565 570 570 = 575 578 579 582 584 584 585712 8.0 8.1 8.2 8.3 8.4 8.5, 8.6 8.7 CONTENTS: 7.9.3 Distributed Drivers 7.9.4 Driving Off-Chip Loads 7.9.5 Cascaded Drivers Power Dissipation 7.10.1 | NMOS Power Dissipation 7.10.2 CMOS Power Dissipation Noise in Digital Logic Circuits 7.11.1 _ Resistive Noise Coupling 7.11.2. Capacitive Noise Coupling 7.11.3 Definition of Noise Margins 7.11.4 NMOS Noise Margins 7.11.5 CMOS Noise Margins Summary References Problems Analog Systems Introduction Analog Signal Processing Digital-to-Analog Converters 8.2.1 Current-Scaling D/A Converters 8.2.2 Voltage-Scaling D/A Converters 8.2.3 Charge-Scaling D/A Converters 8.2.4 D/A Converters Using Combinations of Scaling Approaches 8.2.5 Serial D/A Converters Analog-to-Digital Converters 8.3.1 Serial A/D Converters 8.3.2. Successive Approximation A/D Converters 3.3 Parallel A/D Converters 8.3.4 High-Performance A/D Converters 8.3.5 Summary Continuous-Time Filters 8.4.1 Low-Pass Filters 8.4.2. High-Pass Filters 8.4.3 Bandpass Filters Switched Capacitor Filters 8.5.1 Resistor Realization 8.5.2 Passive RLC Prototype Switched Capacitor Filters 8.5.3 Z-Domain Synthesis Techniques Analog Signal Processing Circuits 8.6.1 Precision Breakpoint Circuits 8.6.2 Modulators and Multipliers 8.6.3. Oscillators 8.6.4 Phase-Locked Loops Summary References Problems Structured Digital Circuits and Systems Introduction Random Logic versus Structured Logic Forms ix 587 588 590 593 a 597 599 599 602 603 605 607 608 608 612 612 612 615 623 626 629 633 638 642 648 651 659 664 671 673 674 685 688 692 693, 703 716 ae — 735 747 162 765 710 773 TB TB 719X CONTENTS = 9.3 9.4 95 9.6 97 98 9.9 9.16 9.17 10 10.0 10.1 10.2 Programmable Logic Arrays 9.2.1 PLA Organization 9.2.2 Automatic PLA Generation 9.2.3 Folded PLAs 9.2.4 Large PLAs Structured Gate Layout 9.3.1 Weinberger Arrays 9.3.2 Gate Matrix Layout Logic Gate Arrays MOS Clocking Schemes Dynamic MOS Storage Circuits 9.6.1 Dynamic Charge Storage 9.6.2 Simple Shift Register 9.6.3 Other Shift Registers Clocked CMOS Logic 9.7.1 C#MOS 9.7.2. Precharge-Evaluate Logic 9.7.3 Domino CMOS Semiconductor Memories 9.8.1 Memory Organization Read-Only Memory 9.9.1 Erasable Programmable Read-Only Memory 9.9.2 Electrically Erasable Programmable Read-Only Memory Static RAM Memories Dynamic RAM Memory Register Storage Circuits 9.12.1 Quasi-Static Register Cells 9.12.2 A Static Register Cell PLA-Based Finite-State Machines Microcoded Controllers Microprocessor Design 9.15.1 Data Path Description 9.15.2 Barrel Shifter 9.15.3 Arithmetic Logic Unit 9.15.4 Microcoded Controller Systolic Arrays 9.16.1 Systolic Matrix Multiplication 9.16.2 General Linear System Solver 9.16.3 Bit-Serial Processing Elements Summary References Problems Design Automation and Verification Introduction Integrated Circuit Layout 10.1.1 Geometrical Specification Languages 10.1.2 Layout Styles Symbolic Circuit Representation 10.2.1. Parameterized Layout Representation 10.2.2 Parameterized Module Generation 783 784 790 791 792 793 794 796 799 805 808 808 811 814 815 815 817 819 821 822 824 825 826 827 835 839 840 842 845, 848. 853 856 857 858 860 861 861 862 863 866, 866, 867 872 872 873 875 878 880 880 88310.3 10.4 10.5 10.6 10.7 10.8 10.9 10.10 10.11 10.12 10.2.3 Graphical Symbolic Layout 10.2.4 Logic Equation Symbology Computer Check Plots Design Rule Checks 10.4.1 Geometrical Design Rules 10.4.2 Computer Design Rule Checks 10.4.3 _ Design Rule Checker Output cuit Extraction 10.5.1 A Simple Circuit Extraction Algorithm 10.5.2 Circuit Extractor Output 10.5.3 Interface to Other Programs Digital Circuit Simulation Logic and Switch Simulation 10.7.1 Logic-level Simulation 10.7.2 Switch-level Simulation 10.7.3 Hardware Logic Simulation Timing Analysis 10.8.1 Timing Analysis Methodology 10.8.2 Timing Analysis Tools Register-Transfer-Level Simulation 10.9.1 Simple RTL 10.9.2 ISPS Specification and Simulation 10.9.3 RTL Simulation with LISP Hardware Design Languages 10.10.1 EDIF Design Description 10.10.2 EDIF Net List View of Full Adder 10.10.3 EDIF Mask Layout View of Full Adder 10.10.4 VHDL Design Description Algorithmic Layout Generation 10.11.1 Bristle Blocks Silicon Compiler 1.11.2 MacPitts Silicon Compiler 10.1.3 Commercial Silicon Compilers Summary References Problems Index CONTENTS Xi 884 885 889 894 894 897 898 901 902 903 908 908 913 917 918 918 919 923 923 cp) 926 929 930 a 931 935 938 938 941 943 944 945 946 951PREFACE Growing technological requirements and the widespread acceptance of sophisticated electronic devices have created an unprecedented demand for large-scale, complex, integrated circuits. Meeting these demands has required technological advances in materials and processing equipment, significant increases in the number of individuals involved in integrated circuit design, and an increased emphasis on effectively utilizing the computer to aid in the design. ‘Advances in growing fields, such as Very Large Scale Integrated Cir- cuits (VLSI), generally parallel “graduate level” academic and industrial research efforts. As a result, these concents quite naturally appear initially in university curricula at the graduate level. However, one must inevitably consider how to present this new material to a wider range of students with less sophsticated backgrounds. Integrated circuit design of LSI and VLSI systems is an area where both the required technical background and demand indicate that the material can and should be introduced at the undergraduate level. It is the purpose of this text to accomplish this objective. The textbook has grown out of notes prepared for a one-semester senior level course that presents the fundamentals of integrated circuit design. This course has been offered every semester at Texas A&M University since the fall of 1981. Sufficient technical background for this text can be provided by an introductory level circuits course and an introductory digital logic course. Limited knowledge of material covered in an introductory electronics course is also assumed, but those sections requiring this knowledge can be either skipped or be augmented by the instructor without a major loss of continuity. Each semester, students in the course participate in an integrated circuit design project using the multiproject chip (MPC) approach. Both NMOS and CMOS technologies have been used for the MPC, Process discussions closely parallel those available through the MOSIS program, thus facilitating participation in the MOSIS fabrication program by students who have MOSIS access. Past design projects have been intentionally limited in scope to keep the student’s time xiiiXIV PREFACE commitments at a reasonable level. Past projects have included ring oscillators, PLAs, flip-flops, simple comparators and operational amplifiers, and 16-bit static RAMs. Although the availability of the processing capability helps provide an appreciation of all the details involved in the design of an integrated circuit, the material in this text is designed to be useful with or without access to foundary services. The text includes a qualitative discussion of semiconductor processing in order to make the student cognizant of the processing steps required. Beyond this, a set of process parameters used in device modeling are assumed to serve as the interface between the process and the design engineers. The physical relationship between circuit design and actual silicon layout and area is strongly emphasized as is the anticipated performance of the circuit as affected by typical variations in the process parameters, temperature, and so on. This book adopts the philosophy that the design engineer should be com- fortable with either analog or digital circuitry and that the basic differences in the fundamental blocks are minimal. Integrated circuit design is presented as a systematic merging of a set of design rules, device models, and process parameters in a personnel- and area-efficient manner to develop a circuit that meets required electrical specifications. With this approach, the NMOS, CMOS, Bipo- lar, thick film, and thin film technologies are introduced in parallel. Each of these maintains a uniqueness through a specific set of design rules and device models. Advantages and tradeoffs in regard to area, performance, and processing costs among the technologies are considered. A typical set of design rules and a list of process parameters, sufficient for actual design, are given for each of the processes. These characteristics are used to maintain proper performance perspectives and to make that crucial link between circuit schematic and silicon layout. Since the size of components has been steadily decreasing, the design rules are given in terms of a variable, A, whenever practical. Although design rules for the MOS and Bipolar processes scale quite well for typical 3, 5, and 8 micron processes, it is emphasized that the actual design rules and process parameters corresponding to the specific fabrication process employed should be adopted. The ultimate goal of the circuit designer is not a clever circuit schematic or a computer simulation that predicts the circuit works as anticipated, but an efficiently designed physical piece of silicon that satisfies the original specifications. To this end, practical considerations are discussed including limitations of device models, parasitic and nonlinear effects, and clever component placement on the circuit layout, along with their effects on performance. This book is directed to individuals with no previous integrated circuit design experience who need a working understanding of the subject. The text will also provide a broadened perspective for experienced designers. In addition to the university classroom, this text should find application in industrial training programs, as an interface for groups using or planning to use silicon foundries, and as a resource for the non-semiconductor-based industries that use electronic circuitry and must make the decision of when, if, and how to integrate their systems. It may also serve as a reference book on the subject of integrated circuit designPREFACE XV Chapter | presents an overview of the field of integrated circuit design while focusing on past and present techniques, trends, and performance along with the technological challenges. A discussion of both yield and economics is included in this chapter. Technology is discussed in Chapter 2. Processing steps are presented from a qualitative point of view, followed by detailed discussions of the NMOS, CMOS, and Bipolar processes along with the thick and thin film technologies. Design rules, layout techniques, and the role of the computer are discussed. Models for the MOS and Bipolar transistors suitable for design are presented in Chapter 3, as are more sophisticated models necessary for computer simulation. The characteristics of various types of semiconductor passive components are also investigated. Computer-aided circuit analysis is discussed in Chapter 4. Use of the widely available SPICE program for this purpose is investigated. Chapter 5 is used to introduce basic analog building blocks. Building blocks that are useful for constructing analog circuits are discussed in Chapter 6, Both MOS and Bipolar versions are developed in parallel because of the similarity of the circuit topologies. A digital counterpart to Chapter 5 is presented in Chapter 7. This discussion originates with the inverter, followed by the generation of basic logic gates. Methods of driving large external loads while maintaining acceptable speed are investigated. The emphasis in Chapter 7 is on the MOS technologies because of their widespread acceptance for large digital systems. In Chapter 8, the design of analog systems is considered. These systems employ some of the basic building blocks discussed in Chapters 5 and 6. Systems considered include A/D and D/A converters, continuous-time filters, switched- capacitor filters, oscillators, multipliers, and modulators. Digital systems are discussed in Chapter 9. These include PLAs, gate arrays, static and dynamic memories, microprocessors, and systolic arrays. Design automation is addressed in Chapter 10. The variety of design aids necessary for layout verification is discussed. Much of the material in the book comes as an outgrowth of the design and testing of integrated circuits that have been included on past MPCs as well as the instruction that has been necessary to prepare students to participate in these designs. The fabrication of the MPCs by Texas Instruments, Inc., and the MOSIS Program is gratefully acknowledged. McGraw-Hill and the authors would like to thank the following reviewers for their many helpful comments and suggestions: Jorge J. Santiago-Avilés; Steven Bibyk, Ohio State University; David J. Dumin, Clemson University; Yu Hen Hu, University of Wisconsin; David L. Landis, University of South Florida; H.C. Lin, University of Maryland; M.A. Littlejohn, North Carolina State University; R.A. Saleh, University of Illinois; S.M. Sze, AT&T Bell Laboratories; and Herbert Taub, City College of the City University of New York. Randall L. Geiger Phillip E. Allen Noel R. StraderCHAPTER 1 PRACTICAL CONSIDERATIONS The field of VLSI design is a resource-intense engineering discipline. Project and product definitions are economically motivated, and competition on a worldwide basis is very keen, The market potential for innovative designs is very large, but the market window is often short due to both competition and changing consumer demands. Financial gain potential for both individuals and companies in this field is phenomenal, but the risks can also be very large. Some of the most advanced equipment and CAD resources available in any discipline are focused toward VLSI design and production; this focus makes the field very dynamic but also necessitates a continuing training and learning effort on the part of the design engineers to remain current and productive in this field. It is our goal in this book to introduce basic electronic principles needed by the integrated circuit designer and to discuss engineering tradeoffs and practical considerations that are necessary for the student to make the transition from the classroom to industry as an integrated circuit designer. Although it is impossible to discuss all the practical aspects considered by experienced designers, it is our hope that through the discussions and comments presented in this book, the student will develop a sense of what types of practical questions must be addressed throughout the design process This chapter gives a brief historical overview, followed by a discussion of some of the terminology and jargon specific to the VLSI design field. (We have chosen to adopt the jargon used in the field because this is the language used by VLSI designers to communicate.) Size and complexity perspectives of VLSI circuits are discussed, and the basic types of processes used in IC and VLSI design are qualitatively summarized. The design process itself and the tools available to the designer are covered. Finally, a brief discussion of economics is presented to give the reader a basic appreciation of design costs and fabrication costs of 12. VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS integrated circuits. Included is a simple discussion of the relationship between yield and chip area, which often is the key factor in determining whether a design will be economically viable. 1.0 INTRODUCTION Historically, several events trace the evolution of what is currently termed VLSI technology. In the early 1930s, theoretical developments by Lilienfeld! and Heil” discussed the predecessor to what is now commonly called the field effect transistor (FET). Technological challenges delayed the practical utilization of this device for nearly three decades. In 1947 and 1948, three researchers at Bell Laboratories—Brattin, Bardeen, and Schockley—introduced the bipolar junction transistor (BJT). This development marked the practical beginning of the microelectronics industry. For the next 15 years, large numbers of different BJTs were produced and applied in a wide range of instrumentation systems. The BJTs replaced vacuum tubes in many applications and provided the impetus for a host of new electronic systems. In the summer of 1958 Jack Kilby, an engineer at Texas Instruments, invented the first integrated circuit. Early the following year Robert Noyce of Fairchild independently reported on a procedure that more closely resembles integrated circuits of today. The specific details of Kilby’s circuit are inconsequential, but the impact of his approach has been phenomenal.?** The work of Kilby and Noyce marked the beginning of what has become the field of VLSI design. Germanium was widely used as a semiconductor in some of the early discrete devices. Silicon has been the dominant semiconductor material used for integrated circuit fabrication for the past two decades, and most experts agree that it will remain dominant for the next decade. Since over 25% of the earth’s crust is made of silicon, a real silicon shortage is highly unlikely! Other materials, such as gallium arsenide, are gaining acceptance in niche markets, which may be quite profitable. Improvements in technology —ranging from improvements in materials and photolithography to advancements in processing —have been propelled by the significant financial gains offered to groups that excel in this area. Many integrated circuits of today contain a very large number of transistors, over | million in some designs. Conventional methods for circuit design that involved iteration at the breadboard level proved impractical for designing integrated circuits. This is due to poor designer productivity and the high cost associated with fabricating ICs. Methods of efficiently handling large quantities of design data were needed. Models of transistors that accurately predict experimental performance were required. Methods were needed for increasing designer productivity and reducing the design cycle time as the size and complexity of circuits increased. The tools available now to the IC designer are very powerful and dynamic. Most require the use of large computers or, more recently, powerful graphics- intense workstations. The continued investment in both hardware and software needed for current integrated circuit design is high but is also crucial to remaining competitive. As powerful and dynamic as these tools may be, the fierce competition in the marketplace has resulted in the evolution of user-friendly softwarePRACTICAL CONSIDERATIONS 3 with which the engineer can establish proficiency with a modest investment of time and effort. In the following chapters the tools needed to design VLSI circuits are investigated. In spite of the sophistication and cost of both the hardware and software necessary to remain competitive in the field of VLSI design, most major contri- butions to this field are based upon relatively simple and basic innovations by the engineer. These innovations occur in circuit design, processing, and modeling as well as in the evolution of the CAD tools themselves. They are often made by young engineers. Because of the economic impact of innovations in the VLSI design field, advancement potential and rewards for talented and ambitious engineers are essentially unlimited. This potential exists for both young and old in institutions ranging from small start-up companies to the giants of the industry. Integrated circuit fabrication requires the use of mechanical and optical equipment and materials capable of precisely maintaining close tolerances and small geometries. As with any high-technology field, a large amount of technical jargon has evolved, which must be mastered by anyone wishing to be conversant with those working in the area. The balance of this chapter is devoted to practical considerations and an introduction of terminology associated with the field of integrated circuit design. An integrated circuit (IC) is a combination of interconnected circuit elements inseparably associated on or within a continuous substrate. The substrate is the supporting material upon or within which an IC is fabricated or to which an IC is attached. A monolithic IC is an IC whose elements are formed in place upon or within a semiconductor substrate with at least one of the elements formed within the substrate. A hybrid IC consists of a combination of two or more IC types or an IC with some discrete elements. A wafer (or slice) is the basic physical unit used in processing. It generally contains a large number of identical ICs. Typically, the wafer is circular; production wafers have a diameter of 4, 5, or 6 in. The chip is one of the repeated ICs on a wafer. A typical production wafer may contain as few as 20 or 30 ICs or as many as several hundred or even several thousand, depending upon the complexity and size of the circuit being fabricated. The terms die and bar are used interchangeably for chip in some companies. A test plug, or process control bar (PCB), or process control monitor (PCM), is a special chip that is repeated only a few times on each wafer. It is used to monitor the process parameters of the technology. After processing, the validity of the process is verified by measuring, at the wafer probe level, the characteristics of devices and/or circuits on the test plug. If the measurements of key parameters at the test plug level are not acceptable, the wafer is discarded. A test cell, ot test lead, is a special chip repeated only a few times on each wafer. It differs from the test plug in that the circuit designer includes this cell specifically to monitor the performance of elementary subcircuits or subcomponents.4 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS: Considerable effort has been expended toward using the entire wafer as a single IC, but this approach is challenged by defects in processing and the associated decline in yield and by the inherent delay in signals that must transverse the wafer. Those efforts are in the field termed wafer scale integration (WSI)*"°. 1.1 SIZE AND COMPLEXITY OF INTEGRATED CIRCUITS Integrated circuits are typically classified in terms of the number of devices or potential devices used in the design of the circuit and in terms of the feature size of the process. The device count is generally restricted to the number of active devices (either FETs or BJTS). As will be seen later, most integrated circuits contain large numbers of BJTs or FETs but contain few, if any, passive components. The classification of integrated circuits by device count is summarized in Table Lit Classifications based upon feature size are also common. This classification is in terms of a typical minimum feature size (such as minimum gate length or minimum polysilicon width or minimum metal width) or in terms of the pitch (minimum of the sum of the minimum width of a feature and minimum spacing between similar features). The pitch is often nearly twice the minimum feature size. In the early to middle 1970s, the minimum feature size was typically 7 4 to 10 1. In the late 1970s and early 1980s feature sizes to 5 px were popular. In the mid-1980s, the minimum feature size had shrunk to under 2 1, with some groups producing 1 and 14 p circuits. The early 1990s should see practical submicron processes in production with feature sizes between 0.75 and 0.25 The impact of shrinking the feature size on silicon warrants discussion. For reference purposes, a sketch of a FET appears in Fig. 1.1-1. The FET is composed of a conductive gate region, which is separated from the surface of the substrate by a very thin insulating layer. Diffusions on either side of the gate form what are termed the drain and source regions. The minimum feature size of this, TABLE 1.1-1 Classification of integrated circuits by device count —— Nomenclature Active device Typical count functions SSI 1-100 Gates, op amps, many linear applications MSI 100-1000 Registers, filters, etc. LSI 1000-100,000 Microprocessors, A/D, etc. VLSI 105-108 Memories, computers, signal processors SSPRACTICAL CONSIDERATIONS 5 Channel Gate region oxide P™ substrate Drain FIGURE 1.1-1 Simplified 3-dimensional view of a FET. process is roughly the minimum allowable value for L and W. For example, in a 5 x process the minimum permissible value of L and W would be 5 jz. The area required for the gate of the transistor in such a process would be 25 2. Even though the lateral dimensions of the FET (x and y directions in Fig. 1.1-1) are small, the vertical dimensions are typically much smaller. For example, the thin insulating layer under the gate in a typical 5. process is about 1000 A thick. The relative perspective of the lateral and vertical (z direction) dimensions is grossly underemphasized in Fig. 1.1-1, Because of the large differences in lateral and vertical dimensions of FETs, the lateral dimensions are generally expressed in microns (or occasionally mils) and the vertical dimensions in angstroms. It is very important that the designer have an appreciation for both lateral and vertical feature sizes in any process. Conversions from meters to angstroms as well as a comparison with English units are given in Table 1.1-2. In this table, and throughout this book, the term micron and the abbreviation 1, which corresponds to the industry-accepted jargon for the micrometer, will be used. We are now in a position to develop a realistic perspective for the number of devices (transistors) that can be fabricated on a given piece of silicon. Assume initially that the area required for a single FET is essentially equal to the area TABLE 1.1-2 Conversion of parameters used for device characterization in semiconductor industry Conversion Unit Symbol Angstroms —_-Microns Mils Meters Inches Angstrom A i 107* we 3.94 x 1076 mil 107!° m 3.94 x 1079 in Micron 108A - 0.0394 mil 10-6 m 3.94 x 1075 in Mil mil 2.54x 105A 25.4 p - 2.54 1075 m 0,001 in Meter m 10 A 0° 3.9 10 mil — 39 in ul Inch in 2.54% 108A 2.54 104 p10 mil 2.54 10-7 ms —6 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS required for the gate (i.e., W-Z in Fig. 1.1-1), With this assumption, a 4 inch wafer used in a 5 2 process can accommodate m(2 in)? (2.54 x 104 IN cea esas Su 35 ue | in } transistors. Actually, due to spacing restrictions and interconnection requirements, the number of transistors that can be placed on this wafer will be from one to two orders of magnitude less. Regardless, it should be apparent that a very large number of transistors can be fabricated on such a wafer. The impact of shrinking the feature size can now be appreciated. If we could build transistors that were 0.5 10.54, the number of transistors that could be accommodated by the same 4 inch wafer in the 0.5 w process becomes 3.24 x 108 4 \2 G54 x10 HY" 3 94 x 1910 subject to the same reduction for spacing and interconnections as in the 5 je process. Nonetheless, the 100-fold increase in device count is very significant. To obtain an appreciation for the significance of a 100-fold increase in device count, assume one piece of silicon was used to design a small computer system. The same piece of silicon could be used to build 100 identical computer systems if a 100-fold increase in device count were obtained. Correspondingly, with a fixed chip area, the high-density circuit could perform the work of 100 of the small computer systems. In addition, from an economics viewpoint, the cost of fabricating wafers has increased only modestly as the device geometries have decreased. Beyond the increase in device count, two other major benefits are derived by shrinking device sizes. First, as the device sizes decrease, the speed of circuits increases approximately linearly with feature size reduction. In the previous “small computer” example, it can be observed that in addition to obtaining a significant increase in the number of “equivalent computers” with decreasing device sizes, each of the smaller computers will work much faster! The other major benefit relates to yield, size, and complexity. It will be seen later that the yield depends primarily upon the silicon area (more precisely, active silicon area) of a chip and is relatively independent of the number or size of transistors in this area, Correspondingly, decreasing feature size makes possible some useful designs, which were either physically too large or which had low yields in a large feature size process. ‘There are some limitations associated with shrinking the feature size. These include a deterioration in matching characteristics, increased cost of equipment required for processing the wafers, additional capability requirements for software design aids, and an increased impact of interconnection delays. Concerns about increased power dissipation density and processing complications associated with heat cycling limitations during fabrication also exist. It is generally agreed,PRACTICAL CONSIDERATIONS 7 however, that the benefits of shrinking the minimum feature size far outweigh the limitations, and a major worldwide research effort is ongoing to further shrink device sizes. The number of devices that could potentially be placed on a wafer (calcu- lated above) is strongly dependent upon the wafer size. Of more importance is the number of devices that can be placed on a chip, which represents a small portion of the area of a wafer as indicated in Fig. 1.1-2. From a practical viewpoint, the chip size seldom is (reference 1989) much in excess of 1 cm?. The chip area of Texas Instruments’ (TI) 1M DRAM is 0.54 cm’. That of the Motorola 68020 microprocessor is 0.85 cm?. Even in 1 cm?, a large number of devices can be utilized. For example, in a 5 u process, the 1 cm? chip can accommodate the gates of about 4 million 5 yz x 5 transistors. As mentioned previously, the realistic number of practical devices is from one to two orders of magnitude smaller. For example, the 68020 microprocessor has about 200,000 transistor sites and was designed in a 1.8 process. The TI IM DRAM, designed in a 1p process, has 1,048,576 transistors and an equal number of capacitors in the basic memory array, along with about 52,000 transistors in the control circuit. The TI 16M DRAM, which should be in volume production in 1991, will have a die area of nearly 1 cm?, will have 16,770,000 transistors and an equal number of capacitors in the basic array along with over 150,000 transistors in the control circuit, and will be fabricated in a 0.6 4x process. An analogy between the features on an integrated circuit and the features on the map of a large city is often drawn to obtain a realistic appreciation of the complexity of existing integrated circuits. This is motivated, in part, by the observation that under a high-power microscope, a dense integrated circuit shows a resemblance to a street map of a city with the interconnections corresponding to the city streets. Assuming that the pitch of a process maps to one city block, that a city block is 200 meters on a side, and that the pitch equals twice the minimum feature size, it follows that the magnification factor is 10°:x where x Wafer FIGURE 1.1-2 —~Lit Sketch of a wafer showing repeated “chips.” Chip —>} (See Plate 1 in the color insert of this book for a color photograph of a commercial wafer.)8 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS is the minimum feature size of the process in microns. For the 10 » processes of the early 1970s with a typical die 2.5 mm on a side, this magnification would map the die to a city about 14 miles on a side, which corresponds to a city about the size of Tulsa, Oklahoma. For a 5 j1 process with a die 5 mm ona side, which was popular in the late 1970s, the map increases to that of a city nearly 60 miles on a side. This corresponds to a city the size of the greater Chicago metropolitan area. For the 1 2 processes of the late 1980s, with a 1 cm? die size, the mapping is to a city 600 miles on a side, which would correspond to a city that is 30% larger than the entire state of Texas. Finally, for the projected 0.25 1. processes with a die 2 cm on a side, this same mapping would be to a city nearly 5,000 miles on a side. This would correspond to a city with an area equal to nearly half the earth’s land surface. Many integrated circuits require a silicon area that is considerably less than the maximum practical chip size. Several advantages are offered by using smaller- sized die. First, since the cost of processing a wafer is essentially independent of the size of the die, a smaller chip size will result in fabrication of more chips per wafer and, thus, a reduction in the effective cost per chip. Second, the yield (percentage of chips that are good) decreases rapidly with increasing chip size; details of this are discussed in Sec. 1.5. In addition, since rectangular chips are fabricated on round wafers, the amount of wafer wasted around the periphery is reduced with smaller chips. Example 1.1-1, Assume an operational amplifier (op amp) requires an area 100 mil X 100 mil and a microprocessor requires an area 1 om X 1 cm. (a) How many of each type of chip can be fabricated on a 5 inch wafer? (b) If the yield for the op amp is 98% and that for the microprocessor is 30%, compare the average number of good chips per wafer of each device that can be anticipated. (c) If the fabrication cost per wafer is $400, what is the effective cost per good chip for each device? Solution. (a) Neglecting the area loss on the periphery of the wafer, we calculate the number of op amps and microprocessors as, Nopamp = 2st = 1963 2 pproe = 705) = 126 o Nopampetfecive = (0.98)(1963) = 1923 P pproc effective = (0.3)(126) = 37 © Copamp =m = 20.8¢ Cyproe = $10.53 One naturally poses the question: How small will device sizes ultimately become? Although we will not quantitatively answer this question, we will address some of the major factors which place limits on decreasing device dimensions.PRACTICAL CONSIDERATIONS 9 Up to now, limitations were imposed primarily by limitations in resolution of processing equipment. We are approaching the point, however, where the physics of the semiconductors themselves are starting to cause problems. Gate oxides (the insulating layer under the gate) below 100 A thick are being investigated in conjunction with submicron research efforts. The density of silicon atoms in single crystal silicon is 5 x 10° atoms/em3. This corresponds to an “average” atom spacing of 2.71 A. The nearest-neighbor distance is 1.18 A and the lattice constant is 5.43 A. It should be apparent that the sub-100 A gate oxide layers have dimensions approaching the dimensions of the atomic structure of the semiconductor crystalline structure itself. Silicon dioxide, which is typically used as the insulating layer, is even coarser than silicon. The silicon dioxide density is about 2.3 x 10?? molecules/em3, with an “average” molecular spacing of 3.52 A. It should be apparent that irregularities in surfaces of the order of magnitude of a few molecules become significant in sub-100 A oxide layers. Quantum mechanical tunneling occurs if oxide thicknesses become thinner than about 50 A, thus placing a practical lower bound on oxide thicknesses.!! High electric field strengths, which may cause device failures, also are of concern. Voltages up to 5 V are regularly applied across the 1000 A silicon dioxide insulating layers. This corresponds to electric fields of the order of magnitude of Dat S00ky, wm 1000 A ~~ em This electric field is very large but still less than the breakdown field of silicon dioxide, which is in the 5~10 MV/cm range depending on how the oxide was grown. If, however, the same 5 V were applied to the 100 A oxide layer, the electric field strength would be in the neighborhood of the breakdown field for the oxide. Furthermore, the irregularities in the very thin oxide layers can cause further significant local increases in field strength. The only option is to decrease the voltage applied to the oxide layer, but this is unattractive for two reasons. First, as the voltage across this oxide decreases, noise effects become more significant, thus increasing the chance of occasional errors in circuits using these devices. Second, existing systems have well-defined voltage levels, which a large number of manufacturers adhere to. Since parts made by various manufacturers are often interconnected to form complex systems, interfacing parts with nonstandard signal levels causes a significant increase in design complexity. It is generally desirable to scale the vertical as well as the lateral dimensions when decreasing device sizes. The method under which this scaling occurs affects both the reliability and performance specifications of the process. Various scaling strategies are possible as the lateral dimensions of the MOSFETs decrease. In the constant field scaling strategy, the vertical dimensions typically decrease at the same rate as the lateral dimensions. To maintain a fixed electric field, the operating voltage also decreases at the same rate. The constant voltage scaling strategy is attractive because electrical compatibility with existing circuits is maintained. In a constant voltage scaling strategy that has been proposed, the vertical dimensions decrease quadratically relative to the lateral dimensions. !210 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Obviously tradeoffs among performance, yield, compatibility with existing technology, reliability, process complexity, device performance, and impact of parasitics must be made when selecting a scaling strategy. 1.2. THE MICROELECTRONICS FIELD The microelectronics field is quite broad. Many different types of processes and approaches have found niches in the microelectronics market place. Figure 1.2-1 depicts the major processes that have received a reasonable degree of acceptance. The first division in process types occurs between active and inert substrates. The high-volume integrated circuits typically utilize the active substrates. Some of the more demanding requirements as well as specialized and/or low-volume circuits use the inert substrates. The inert substrates are also used in most hybrid ICs. These latter circuits are often noted for requiring relatively modest investments in processing equipment, but the consumer cost of the hybrid ICs themselves is quite high. ‘Two types of processes that utilize inert substrates are particularly important. These are the thin and thick film processes. These processes are capable of producing good resistors with attractive temperature characteristics. This is difficult to achieve with the standard active substrate processes. The active substrate is generally silicon or doped silicon although considerable research effort has been expended over the last decade in using gallium arsenide (GaAs). Two primary separate types of silicon processes have evolved. The bipolar process uses the BJT as the basic active device whereas the MOS processes use the metal oxide semiconductor field effect transistor, or MOSFET (sometimes termed IGFET for insulated gate FET), as the basic active device. The bipolar process was the most popular through the 1960s and early 1970s. The bipolar process offers potential for operation at very high frequencies and offers some performance advantages such as large transconductances, which are of benefit in many linear applications. The power dissipation in bipolar integrated circuits is, however, often quite high, and the device density is not as high as that attainable with the MOS processes. The popular TTL logic family, ECL, and PL all fall under the bipolar label. Many linear ICs also are fabricated in the bipolar processes. Although the relative amount of research effort in the bipolar area is small compared to that focusing on the MOS processes, the production volume of bipolar ICs is still very large, and some new developments still use the bipolar process. There is, however, considerable development work ongoing in the design of smart bipolar power devices, which contain the control circuitry along with the power devices. The MOS process is often divided into three categories: NMOS, PMOS, and CMOS. The basic devices in MOS processes are the p-channel and n- channel MOSFETs discussed in Chapter 2. The term PMOS refers to a MOS process that uses only p-channel FETs. The PMOS process was used in some of the earlier MOS designs, but is rarely used today primarily because the electrical characteristics of p-channel MOSFETs are not as attractive as those of n-channel MOSFETs. This is because the mobility (discussed in Chapter 3) of p-type material is considerably poorer than that of the n-type material. The termsol seauy Aue “uonearigey D1 ut pasn sossoaoid sofewl Jo soda rel aaa SOW-!a, ereasqns annoy eqeasqns EU SOIUOIDE|0101W oa12 Visi DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS NMOS refers to a MOS process using only n-channel FETs. Excellent density and reasonable performance characterize the NMOS process. The term CMOS (complementary MOS) refers to a MOS process that simultaneously provides both n-channel and p-channel devices. The availability of both types of FETs offers the designer considerable additional flexibility over that attainable with either an NMOS or PMOS process. In digital applications, the availability of complementary devices offers potential for very low static power consumption. In analog applications, the circuit complexity can often be reduced in the CMOS process relative to what is attainable with either the NMOS or PMOS processes. The increased flexibility of CMOS is partially offset by increased fabrication costs and an increase in the silicon area required to implement basic digital functions. The tradeoffs generally favor the CMOS process over NMOS in most new designs. MOS processes are used for most VLSI scale circuits. Applications include memories, interfacing, microprocessors, basic logic functions, and a host of linear and mixed linear and digital applications. Recently there has been a major effort toward combining both bipolar and MOS devices in a single process. This more complex and expensive process, termed Bi-MOS, is becoming cost-effective in a growing class of applications. Some processes also include thin film components with MOS and/or bipolar devices, but the expense associated with adding the thin film layer is justifiable only in specialized applications. 1.3. IC DESIGN PROCESS It is generally the goal of the IC designer to design an integrated circuit that meets a given set of specifications while expending minimal labor and physical resources in a short time frame. Furthermore, the production yield should be high, the process simple, and the die area small. The conventional approach to circuit design often involves much iteration at the breadboard level. Because of the complexity of many VLSI designs and the cost of resources associated with IC design and fabrication, the conventional approach is totally unacceptable. A simple example is useful for obtaining an appreciation for the magnitude of the task facing the VLSI designer. Example 1.3-1. Assume that the productivity of a “conventional” discrete component circuit designer is measured in terms of the average number of transistors per day that the designer produces for a circuit and that the productivity is independent of the complexity of the circuit. If it is assumed that a two person-month effort is required to design a 20-transistor circuit following a conventional approach, how long will it take the same designer to design a circuit that has 500,000 transistors using the same design approach? How large will the circuit schematic be if it requires an average of 2 cm? of space for each transistor in the circuit? Solution. The productivity rate of the designer is 20 transistors/2 person-months = 10 transistors/person-month. Thus, the 500,000-transistor VLSI circuit would require 50,000 person-months, or about 4200 person-years. Note that 4200 person-years is equivalent to about 105 productive person-lifetimes! The schematic would occupy (500,000)(2) cm? = 10° cm? of area. This is the area of a square 10 mon a side!PRACTICAL CONSIDERATIONS 13 From Example 1.3-1, two things should be apparent. First, designer effi- ciency must be improved in the field of VLSI design. Second, much more efficient methods of handling large amounts of design data associated with schematic drafting, layout, and simulation are required. At the outset, one might suspect that designer productivity will actually decrease with circuit complexity. Although this is typically the case for unstruc- tured designs, most existing VLSI circuits are regularly structured and utilize a smail number of basic circuits a large number of times. Powerful design aids, mostly in the form of powerful computer programs, are crucial for the successful design of VLSI circuits. Two approaches to IC design are philosophically identifiable. In the first, called a bottom-up approach, the designer starts at the transistor or gate level and designs subcircuits of increasing complexity, which are then interconnected to realize the required functionality. In the second, termed the top-down approach, the designer repeatedly decomposes the system-level specifications into groups and subgroups of simpler tasks. The lowest-level tasks are ultimately implemented in silicon, either with standard circuits that have been previously designed and tested (often termed standard cells) or with low-level circuits designed to meet the required specifications. In the extreme case, the top-down approach results in a silicon compiler, discussed later, in which all blocks are automatically designed with a computer. The top-down approach is used for some digital designs and often results in a significant increase in designer productivity. Considerable effort has been expended at following the top-down approach for analog design, but analog design requirements are sufficiently specialized that the top-down approach is currently practical only in certain classes of analog designs. It is often the case that both analog and digital system designs use varying combinations of top-down and bottom-up design concepts. A block diagram of the conventional IC design process is shown in Fig. 1.3-1. The starting point is a set of design specifications. On complicated designs, a major effort is required to obtain a complete set of circuit and system specifications. Preliminary designs are based upon simple models of devices or subcircuits. These are typically at the behavioral or logic level for digital circuits and at the component or device level for analog circuits. A preliminary computer simulation using more accurate models is used to verify the performance of the preliminary design. Good device and subcircuit models are crucial. A model is “good” if it accurately predicts experimental performance after fabrication and is sufficiently simple to avoid the requirement of excessive computer time during the simulation. Considerable time is often invested in the initial computer simulation and preliminary design loop. Once the preliminary design is deemed acceptable, the actual layout takes place. The layout phase is often entered on subcircuits prior to the completion of the preliminary design phase. A good overall floorplan is obtained early in the design after a good estimate of the overall architecture and size of the subcircuits is obtained. The floorplan contains all major busing and cell (subcircuit) placement information as well as /O pad designations.14 _ Visi DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS ‘Specifications Preliminary design Computer simulation Computer simulation Yes Initial fabrication Test & evaluation No FIGURE 1.3-1 Block diagram of conventional IC Production bi design process. Additional computer simulation is undertaken on subcircuits after layout and ultimately: on the entire circuit. These simulations are crucial since parasitic effects associated with the layout play a significant role in both analog and digital circuits. In analog circuits the parasitics tend to degrade performance specifications whereas in digital circuits the parasitics generally cause additional unwanted delays or potentially disastrous race conditions. Software also exists at this level in the design for verifying that the layout violates no major design rules and that the circuit in the layout corresponds to the initial circuit schematic. The results of the computer simulation often necessitate changes in the layout or changes in the design itself if the effects of the parasitics cannot be resolved with changes in the layout. Following an acceptable computer simulation of the entire circuit, the circuit is committed to fabrication. In evolving processes or complicated designs,PRACTICAL CONSIDERATIONS 15 subcircuits and/or test structures are often fabricated early in the design process to provide modeling information and/or verify functionality of subcircuits. The commitment “of the design to fabrication is an expensive proposition. Dollar costs for a single fabrication run of $20,000 to $40,000 are common, and delays of 1 to 4 months from submission of the design for fabrication to physical silicon for testing are typical. A single error in the circuit design, simulation, or layout generally makes the circuit either partially or totally nonfunctional. Based upon the experimental evaluation, either the circuit is released to production or the appropriate step of the design process is re-entered. Although first silicon is often not acceptable for production, the timeliness of the market window and the costs associated with fabrication make repeated iteration at the silicon level unacceptable. Improvements in design tools and methodologies are, however, producing a rapidly growing trend toward fully functional first silicon. Significant resources have been invested on a worldwide basis at increasing the effectiveness of the computer-based design aids. A common goal is to auto- mate repetitive and tedious tasks and minimize the amount of human interaction required in the design process. The rationale for this goal is twofold. First, it helps improve designer productivity, and second, it helps reduce errors that are often directly attributable to the designer. Additional information about the CAD tools available to the IC designer is provided throughout this text. Some of the tools and alternative approaches available to the designer deserve mention at this point. Gate arrays and “seas of gates” are becoming quite popular for certain applications such as replacing large number of SSI chips with a single IC. Such arrays are integrated circuits containing a large number (several hundred) of digital gates or transistor cells, which can be used to implement complicated logic functions. These circuits are initially processed up to but not including the interconnection layers to form a versatile and generic building block. Computer programs that determine the interconnections necessary to implement customer- specific logic functions are widely available and are used to determine the required interconnections. One or more interconnection layers are then added to the generic array circuit, resulting in an economical, production-ready integrated circuit that can be fabricated in a few days. These mask programmable arrays are most practical in low- to medium-volume applications where custom design and production costs cannot be justified or in applications that require very quick turn-around. Silicon area is not, however, efficiently utilized in these arrays, making them less attractive for high-volume applications, in which silicon costs become a major factor in overall fabrication costs. Some groups have been successful at automating the design process in restricted applications to the extent that the input to a computer program is the system specification and the output is a layout that should yield production-ready silicon. These programs are called silicon compilers, and they partially remove the conventional IC designer from the design cycle. The resulting simplification on the typical block diagram of Fig. 1.3-1 should be apparent. These programs support the premise that the circuits will be correct by construction, thus min-16 Vist DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS imizing the need for verification by simulation. Although it might appear that silicon compilers will eventually make the IC designer obsolete, this is highly unlikely. These types of CAD tools will, rather, provide the experienced designer with additional capability for meeting more complicated and challenging design goals and provide basic silicon access to other design engineers. 1.4. ECONOMICS Although the field of VLSI design is challenging from both engineering and sci- entific viewpoints, neither government nor industry is willing to support its evolution on these merits alone. Both research and developmental efforts are generally focused toward areas where investments can be recouped in the marketplace within a relatively short time. It is thus crucial that the designer be familiar with the economics of IC production. Two questions naturally arise prior to developmental efforts on any VLSI circuit. First, does a sufficiently large market exist to justify development? Sec- ond, can a product be developed and produced so that a reasonable profit will be realized over the expected life of the product? We will not attempt to consider the first question in this text, but the second question is easier to address. On a product that is anticipated to have a relatively small total sales volume, the developmental costs will typically dominate. On a product with a large projected sales volume over the life of the product, the actual production costs dominate. The developmental costs can be estimated once the amount of engineering effort required to bring a product into production is known. It should be pointed out that even for seemingly simple designs, the developmental costs may become quite large. For example, a design that requires a 12-month effort by an experienced designer may accrue a total project development cost of $350,000 to $450,000 or more even though the base salary of the designer may be only $40,000/year. The burden (multiplier on the base salary of the designer) is quite high because of various expenses: standard fringe benefits the employer generally provides, technician support, applications engineering, computer time charges, equipment amortization, documentation preparation, test procedure development, mask generation, pilot production, and so on. The burden factor varies considerably from project to project and from company to company. Detailed estimates of the specific costs will generally be made because of differing project requirements. Information about design costs within a company is highly proprietary. Nevertheless, it should be apparent that IC design is a very expensive proposition. The production costs are somewhat easier to estimate. These can be grossly decomposed into the costs listed in Table 1.4-1; typical values are listed in Table 1.4-2. The wafer fabrication costs are dependent on the size of the wafer, the number of mask steps, and the type of processing done at each step. These costs are determined by labor costs, materials and maintenance costs, and amortization costs of the processing equipment. Correspondingly, the wafer probe and final test results are dependent on both type and complexity of the circuit itself. Because good testers are quite expensive ($500,000 to $1.5 million for good digital testersPRACTICAL CONSIDERATIONS 17 TABLE 1.4-1 Major costs associated with wafer processing and fabrication Cost Per wafer Per die Wafer fabrication Blank wafer xy v Wafer processing 2 a) Wafer probe av Wafer sawing sa Die attach, bonding, and packaging = Packaging x6 v Final test x7 v TABLE 1.4-2 Typical processing and packaging costs for 12-mask, 3'« CMOS process (1988) based upon volume production Processing costs 4” process 5” process Wafer fabrication Blank wafer Wafer processing Water probe (per wafer) Wafer sawing (per wafer) Die attach and bonding (per wafer) x5 =83 x5 = 85 Packaging 6 (see below) xg (see below) Final test (per package) x7 = 30g/em? x7 = 30¢/em? Package costst Plastic DIP 8 pin $0.032 Plastic DIP 16 pin 0.048 Plastic DIP 24 pin 0.091 Plastic DIP 64 pin 0.70 Ceramic side brazed 16 pin 1.05 Ceramic side brazed 24 pin 1.50 Ceramic side brazed 64 pin 4.95 Ceramic CERDIP 16 pin 0.096 Ceramic CERDIP 24 pin 0.26 Ceramic CERDIP 40 pin 0.64 Ceramic pin grid array 68 pin 6.40 Ceramic array, 84 pin 7.50 ‘Ceramic array 132 pin 10.15 Ceramic pin grid array 224 pin 18.00 ‘Packaging cost estimates courtesy Dr. W.E. Loeb of W.E. Loeb and Associates.”18 Vist DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS in 1989), these costs become significant if much time on the tester is required. The die attach and bonding costs shown in Table 1.4-1 are listed as a per-wafer cost. Some groups prefer to figure these as per-die costs instead. The packaging costs depend on both the type and size of the package. As is shown in Table 1.4-2, low pin count plastic packages cost a few cents, whereas ceramic packages with a large number of pins could cost several dollars. Pin styles also differ. The standard dual inline packages (DIP) have recently been replaced, in some applications, with pin grid arrays and surface mount packages. The plastic surface mount small outline integrated circuit (SOIC) packages are a little less expensive than the DIP structures shown in Table 1.4-2, as are the plastic lead chip carriers (PLCC). For example, a 68-pin PLCC would cost about $0.30 compared to $0.70 for the 64-pin plastic DIP. Since the processing equipment is quite expensive (a single line for processing standard CMOS 5 inch wafers in a 2 2 process may cost $30 million) and the labor costs to keep a line operational are quite high, the amortization costs are also dependent on the accounting procedures used by the individual companies. For example, during periods when the demand for semiconductors is high and the production facilities are running near capacity, the fabrication costs per wafer are reduced if the costs are based upon instantaneous amortization costs. Correspondingly, when the demand for semiconductors is soft, this method of accounting results in significant increases in the per-wafer fabrication costs, which may be somewhat misleading. These economy-dependent variances could be as much as 2:1 or more. It may appear from the information presented in Table 1.4-2 that elimination of the wafer probe step could reduce system costs. In general, this is far from true, as indicated by Example 1.4-1. Example 1.4-1, Compare the costs of producing an integrated circuit in a conventional 3 1, 12-mask CMOS process with the options for processing, testing, and packaging as shown in Table 1.4-3. Assume the die size is 0.5 cm X 0.5 cm, the yield at wafer probe is 50%, the packaging yield (sawing, die attach, bonding, and packaging) is 90%, and that Table 1.4-2 gives realistic values for both fabrication and packaging costs. Approximate the number of potential dies by the wafer/die- area ratio, and assume that dies are discarded as soon as they are determined to be defective. TABLE 1.4-3 Processing, testing, and packaging options for Example 1.4-1 Option Wafer size. Wafer probe Type of package 1 4in Yes in plastic 2 Sin Yes plastic 3 4in Yes in sidebrazed ceramic 4 4in No plastic 5 4in No. sidebrazed ceramicPRACTICAL CONSIDERATIONS 19 Solution. The number of potential dies for the 4 inch and 5 inch wafers are approximately ar(2 in)? en Na= 5 emx05om) i Mg = 5 iy — ~(0.5emx0.5 cm) The actual number of potential dies is somewhat smaller since all potential dies around the perimeter of the wafer are incomplete and hence useless. These effects become more significant as the die size increases and as the wafer size decreases. For options 1, 2, and 3, the production cost per good package becomes u _ ooo | tact lio (14-1) N O probe [xy txgtxz+x4tx. c= at xyt x4 _ where Oprove aNd Opactage Fepresent probe and package yields respectively, x y—r7 are as in Table 1.4-1, Aw is the wafer area, and N is the number of potential dies. For options 4 and 5, the production cost per good package becomes ita tua tis Aw\[_1 \f_4 ej eeeeactiea es | Aw (1 Ae G ( W xe tary lala) (14-2) Substituting from Table 1.4-2, we obtain the following costs for options 1-5 respectively, C, = $1.38, Cy = $1.07, Cy = $2.49, Cy = $1.34, and Cs = $3.57. This example clearly demonstrates several points. First, very significant differences in packaging costs exist. The ceramic packages are much more expensive than plastic. Ceramic packages do, however, provide better isolation from the ambient external environment and are necessary in some high-reliability applications. The importance of the wafer probe step for low-yield parts packaged in expensive packages should be apparent. This allows defective dies to be identified and culled prior to packaging, thus avoiding the expensive proposition of packaging defective dies. The wafer fabrication and packaging costs considered in the example are reasonably independent of circuit complexity. The fabrication yield, however, is strongly a function of die size; it decreases rapidly with increasing die size, as will be demonstrated later in this chapter. In this example, the value of the die itself constitutes a relatively small portion of the overall IC cost. This is typical for small dies. For large dies, the die value generally dominates because of the significant decrease in yield. The probe and final test costs were also relatively small in this example, but testing costs become very significant for larger complicated circuits. 1.5 YIELD Generally, some of the dies on any wafer do not meet the performance specifications, The percentage of dies that do meet performance specifications is termed the wafer yield. In general, the yield decreases rapidly with increasing die area, Consequently, die area plays a major role in the economics of IC design, to20 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS the extent that estimates about the die area and yield are almost always considered when making decisions about whether IC development for specific needs will be economically justifiable. A basic understanding about the economic impact of yield is very important, and since some of the terminology needed to discuss yield is first introduced in Chapters 2 and 3, the reader may need to make an occasional forward reference to those chapters while reading this section. Accurate IC yield prediction is difficult to obtain due to the variety of factors that impact yield. Yield is dependent on the specific type of circuit, the design methodology followed by the designer, the layout itself, and the physical fabrication process. The factors that affect yield include dust particles (by definition, any unwanted foreign objects in solid, liquid, or gaseous state), crystal defects, mask defects, alignment errors, breakage and human handling errors, and parameter drifts. The dust particles on wafers, which introduce local defects, are foreign particles that adversely affect either the photolithographic process or the subsequent processing steps. If large enough, these dust particles will cause problems such as failure of a transistor, breaks in an interconnection, or shorting of two adjacent devices, levels, or interconnections. These types of defects are generally assumed to be randomly distributed over the surface of the wafer and from wafer to wafer. Dust particles on a mask or reticle, if large enough, will also cause failures that are repeated every time that portion of the reticle or mask is used. These defects typically occur at the same geometrical position on all wafers in a lot. Crystal defects are present in the wafer prior to fabrication and cause local circuit defects such as failure of transistors. Mask defects may be local or global, depending on the cause. Alignment errors will typically be limited to a single wafer. It is, however, often the case that all dies on the wafer will be defective if alignment errors occur. Parameter drifts will cause transistors to have characteristics different from those desired. These parameter drifts are introduced during processing and are attributable to the inherent practical and physical limitations associated with processing steps such as photolithography, deposition, and diffusion. These changes may affect all wafers in a lot or may affect individual transistors on a wafer. The average values of key parameters at the lot level are closely monitored. Lots are rejected if these values lie outside a predefined acceptability region. On a single wafer, the parameters are considered to vary statistically from transistor to transistor. Statistical circuit parameter variations large enough to cause circuit failures are more common in analog circuits than in digital circuits. Failures due to parameter variations are termed soft faults, and those failures that cause complete transistor failure or interconnection errors are termed hard faults. Whereas a hard fault generally results in nonfunctionality of part or all of the circuit, circuits with soft faults may well be functional but fail to meet specifications. A single hard fault or soft fault will often cause rejection of a die. Most digital circuits are designed so that they are unaffected by all but the most serious parameter variations. Thus, failures in digital circuits generally result from hard faults. Both soft faults and hard faults are of concern in analog circuits. Faults are bad for two reasons. First, since they cause failure of the die, they drive up the effective costs of a good die. Second, they are often difficult andPRACTICAL CONSIDERATIONS 21 expensive to detect. In fact, questions about whether some complicated circuits are even testable arise. It is now an accepted responsibility of the designers to address the testing problem at the design stage. ICs often contain additional circuitry, which is used in the testing of the circuit itself. The testing question is definitely not trivial for complicated designs, and it represents an active area of research. Related to this problem is the field of fault-tolerant technology, also an active area of research, in which circuits are designed so that they remain functional even if some faults do exist. The probability of having one or more hard faults on any die associated with particulate material or crystal defects generally increases with both die area and circuit complexity. The reason for the increase with die area should be apparent; it is more likely that a die will contact some fixed defects on a wafer if the die area is increased. This is illustrated in simplified form in Fig. 1.5-1, where varying die sizes are considered with a fixed defect distribution. It should be apparent from this example that with 52 potential dies, 45 will be free of defects (Fig. 1,5-1b), With 12 potential dies (Fig. 1.5-1c), 7 will be free of defects, and with 4 potential dies none will be free of defects (Fig. 1.5-1d). In this example, yield decreases from 86% to 0% as the die size increases. Although not accounted for in the previous example, the density of defects which will cause die failure also increases with die complexity. If a die is fa) () | 2 VT 3 ew (c) @ FIGURE 1.5-1 Effects of defects on yield: (a) Defect locations, (b) Small die size, (c) Larger die size, (4) Die size with zero yield.22. VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS not heavily utilized, some defects may occur in areas where no components or interconnections exist, so die failure will not result. Likewise, some types of defects are more likely to cause a fault if they occur where a transistor is located than where interconnections are made. It can be shown, however, that for a fixed circuit schematic overall yield decreases with increasing die size and increases if the devices are densely packed on the die. The reader is thus cautioned not to draw the conclusion that the yield can be improved by decreasing the density if more silicon area for a given circuit is used. In general, the decrease in failure density on a die with a loosely packed circuit will be more than offset by the total number of defects anticipated in the die with larger area. Several models are used to predict yield associated with crystal- and particulate-related defects. A simple model based upon using the Poisson distribution to predict the probability of K defects in a die area, A, with an average defect density of D defects per unit area results in the expression for the probability that a given die of area A has zero defects: P=e4? (5-1) The defect density, D, is typically in the range of 1 to 2/cm?. Since many defects cause a failure only if the defect occurs in an active area, it may be preferable to use the active area and the corresponding average active area defect density in Eq. 1.5-1, Alternatively, even better results should be obtainable if the active and interconnection defects are considered separately. If Aq and A; denote the active and interconnect areas, respectively, and Da and Dy denote the average defect densities in those two regions, then the probability that a die is good can be obtained by modifying Eq. 1.5-1 P = e7AaDat Aw) (1.5-2) Example 1.5-1. If the average defect density is 1/cm?, what is the average cost per good die for a 4” wafer if the die size is 1 cm*? 0.2 cm?? What would be the price per good die if the average defect density increased to 2/em?? Neglect die losses associated with the wafer edges. Assume the cost for the 4” wafer and processing is $200 and that Eq. 1.5-1 models the probability that a device is good. Solution. The average cost per good die is 200/NP where P is the probability the die is good and N is the number of potential dies per wafer. The number of potential 1 cm? dies in a 4” wafer is (neglecting edge losses) 2 (2 in)(2.5 cm/in)|" Tem? . Nem = Likewise No.em = 405 For a I/em? defect density, it follows from Eq. 1.5-1 that the probability that the 1 cm? die is good is 36%, whereas the probability that the 0.2 cm? die is good is 82%. The corresponding cost per good 1 cm? die is thus $6.86. The cost per good 0.2 cm? die is 60¢. If the defect density were to increase to 2/cm?, the averagePRACTICAL CONSIDERATIONS 23 cost per good 1 cm? die increases to $18.24 and the 0.2 cm? die increases to 74¢. From this example it should be apparent that increasing either the defect density or die area significantly increases the average die cost once the product of A and D exceeds unity. Example 1.5-2. If the average defect density is 1.5/cm?, what is the yield if the die size is increased to that of an entire 4” wafer? On the average, how many such wafers must be fabricated to give one good die? If the cost of each wafer is $200, what would be the average cost per good die? Use the simple model of Eq. 1.5-1 to predict yield. Solution, From Eq. 1.5-1, the probability that the die is good is P= e772 im)*2.54 emvin)%(1.5)/em? P = 1,53x 10" It thus requires, on the average, 1/P = 6.5 x 10 wafers to yield one good die. Ata cost of $200/wafer, the average cost per good die would be $1.3 x 10°. Two important observations can be made from the simplified calculations of the previous example. First, the effective cost of good large die is very high. Second, the concept of using the entire wafer as a single IC is totally impractical if the circuit is not tolerant of any faults. The concept of using the entire wafer as a single IC (termed wafer scale integration or WSJ), is sufficiently attractive, however, that considerable effort has been devoted to research in this area. These circuits must, of course, provide for a mechanism of repair—either through inherent redundancy or some form of mechanical reconfiguration (e.g., laser trimming)—to be viable, since some defects will occur during processing. For large devices the yield predicted by Eq. 1.5-1 is somewhat pessimistic. Two other models used are the Seeds model! and Murphy model', which are characterized respectively by the following expressions for the probability that a given die is good: P =e VAD (1.5-3) [1 = e742)? P| AD Additional information about yield prediction can be found in references 16-19. Soft faults due to parameter drifts also affect yield in a statistical sense. The soft faults play a major role in yield of analog circuits. The effects of parameter drifts can best be appreciated by considering Fig. 1.5-2, in which the statistical distributions of the parameter X are shown. In Fig. 1.5-2a the statistical distribution of the average of the parameter over repeated processing runs is shown. Xax and Xyqv define a process window within which the average value of the parameter must reside. Both design and processing groups must agree on an acceptable process window. The cost of fabricating an IC increases with a decreasing process window and approaches infinity as the width of the process window converges to zero. It is often the case that Xyax and Xyw differ from (1.5-4)24 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS ' 5 i z 3 3 Process window a 1 ' Ly — Xvnn center Xaax. x Parameter (a) 5 g = 8 i — }—~ Xun Xoenren Xacrua. Xuax ae ) FIGURE 1.5-2 Statistical parameter spreads in a variable X: (a) Process window, (b) Wafer level variations. Xcenter by 10% to 50% for most of the major process parameters. More details about parameter spreads can be found in Chapter 2. Good designs will meet specifications over a wide process window. It often requires considerable effort on the part of the designer to produce designs that meet specifications over a wide process window. This is particularly true of analog designs. Even at the wafer level, statistical variations in the paratheter occur across the wafer. These variations are somewhat dependent on proximity of devices and, because of the way parameters are defined, the symmetry in layout. This variation, not including either device proximity or layout, is shown in Fig. 1.5-2b, where XactuaL represents the average value of the parameter X on a given wafer. Xacruat is thus considered a random variable relative to processing but a fixed parameter once processing is complete. The statistical variance at the wafer level is generally much smaller than the variance at the processing level.PRACTICAL CONSIDERATIONS 25 For example, the capacitance density of oxide capacitors may have a processing variation (variance) of 10% of the mean whereas the wafer-level variation may be less than 0.1% of the mean. Two interesting observations can be made from the curves in Fig. 1.5-2. First, after fabrication the parameters are distributed around Xacruat rather than the process center, Xcenrer. In fact, after processing the probability that a parameter is close to Xcenter may be quite small. Second, it should be apparent that designs should meet specifications over both process window and wafer-level variations. Most good digital designs are functionally tolerant to large process parameter variations of all key parameters and are quite insensitive to wafer-level variations. This insensitivity is inherent in most of the basic digital circuit structures. These variations, however, play a major role in the speed specifications of digital circuits, with faster circuits commanding a premium price in the marketplace. The analog designer, on the other hand, must pay considerable attention to both process window and wafer-level variations. The process window variations are actually so large that many design approaches used in discrete component design are totally impractical in monolithic designs. For reasons that will become apparent in later chapters, the performance of many analog designs is strongly dependent on close matching of devices and device characteristics and relatively tolerant of nominal parameter variations within the process window. Consequently, the curve of Fig. 1.5-2b plays a key role in many analog designs. Although the exact shape of the parameter distributions shown in Fig. 1.5-2 is of interest, that information is not widely distributed. Rather, a single parameter that in some sense characterizes the parameter distribution is more commonly available. For example, a comment about the threshold voltage, Vr, such as Vz = 0.5 V + 20% means that the value of Vy after processing will “usually” be within +20% of 0.5 V. Actually, depending on the process acceptance criteria, the average value of Vy may be within this window for all accepted wafers. Correspondingly, a comment such as “V7 matching is to 5 mV" means that the wafer-level parameter variations such as those shown in Fig. 1.5-2b typically differ by less than 5 mV from the measured average value. Whereas the bounds on the process window may be fixed due to rejection of wafers that do not meet the acceptance criterion, the wafer-level variations are essentially not bounded. Unless stated differently, it will be assumed throughout this text that a wafer- level or process window distribution as specified above corresponds to a window within which 99.73% of the devices will fall. This corresponds to a +3 standard deviation window if the random variable is normally distributed—an assumption that is often made. Example 1.5-3. Assume the die of a circuit is 6 mm on a side with a defect density of 0.7/cm?. Assume also that the die includes an analog section, which includes 100 transistors in which the characteristics must all be matched to within 0.5% of the die average value to meet specifications. Assume that the matching characteristics of the transistor are dominated by a single parameter that is normally distributed with a +3 standard deviation window, characterized by a variation from the die average of + 0.5%.26 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS (a) Using the Seeds model for defect density, determine the approximate yield if potential soft faults in the analog section are neglected. (b) Estimate the yield if both hard and soft faults are considered. (c) Repeat (b) if matching to 0.25% is required in the analog section. Solution. (a) From (Eq. 1.5-3), the hard yield is the probability that a die is good, which is given by Py = oD = 9 Vigmmrx yenm? — 60.5% (b) The probability that a die has no soft faults is equal to the probability that all 100 transistors meet the matching specifications. The probability that each transistor meets the matching requirements is P = .9973. Thus, the probability that all 100 transistors meet the specifications is Ps = (.9973)'® = .763 ‘The overall yield is thus the product of the hard and soft fault yield, which is P = PyPs = 46% (©) For a matching to 0.25%, it follows from a standard investigation of the normal distribution that the probability that a given transistor meets the specifications is equal to the probability that the normal random variable is within + 1.5 standard deviations of the mean. From a probability density table for the normal distribution, it follows that the probability that any one transistor meets the specifications is 0.8664. Thus, the probability that all 100 transistors meet specifications is Ps = (0.8664)! = 5.9 x 1077 Thus, from part (a), the overall yield is P = PsPy = 3.5 X 10-6 = 3.5 x 10°% Note that this modest increase in matching requirement from 0.5% to 0.25% results in a yield that is so small as to make such a design totally impractical. The previous example demonstrates a very important point. If very much matching is required in analog circuit design, then the matching requirements must not be too severe if the yield is to be high enough to make the circuit economically feasible. Since considerable variation from the process center occurs, as indicated in Fig, 1.5-2a, one naturally asks the question: What value should be used for the parameters at the design stage? Stated alternately, the problem is to find the design target, or the design center, for each parameter. The process center is widely used for the design center. It can, however, be shown that in some cases, the yield can be improved if something other than the process center is used for the design center. The field of design centering and yield optimization addresses these questions. Unless stated otherwise, it will be assumed throughout this book that the desired design center corresponds to the process center. The reader should be cautioned to avoid the temptation of using experimental parameter centers obtained from measurements made on one or two wafer lotsPRACTICAL CONSIDERATIONS 27 in lieu of the design center that has evolved with the process itself. It should be apparent from Fig. 1.5-2 that using experimentally measured parameters rather than the process center as design centers will statistically bias designs in a way that will often be accompanied by a decrease in yield. Industry is keenly aware of the relationship among the specified process window (which dictates the design specification range), the actual wafer-level variations, and the corresponding yield. A capability index, which relates these variables for any process parameter, is defined by the expression” Design specification width Process width Ce where the process width is generally defined to be +3 standard deviations (o) about the mean. Assuming a normally distributed process around the mean in which the process width is characterized by the 3a window, it follows that if the process window is centered in the design specification window, then the probability that a parameter of a device lies inside the design specification window is Gy P | eM dx (1.5-6) 3p Vir This error function, erf (x), integral is readily obtainable from tables of the normal probability distribution, which appear in most elementary statistics texts. If C, is small, the probability that a device parameter is actually within the process window is small; the yield will be poor and will deteriorate even more if the mean of a parameter for a wafer is not centered within the design specification window. Correspondingly, if C, is large, the yield will be high and the process will be reasonably tolerant to small shifts in the wafer-level parameter center from the design specification center. Setting the design specification width so that C, = 2 will result in reasonable yield in many applications, although this may place unrealistic performance demands on the designer for some design Projects. Example 1.5-4 clearly demonstrates the yield implications associated with properly establishing the capability index. Example 1.5-4. If 1000 devices on a chip must have a specific parameter within the specified design process window, determine the soft yield if the process has been characterized by a capability index of (a) Cp = 0.5, (b) Cy = 1.0, (c) Cp = 1.5, and (d) C = 2.0. Solution. With C, = 0.5, it follows from Eq. 1.5-6 and a normal random variable table that P = .8664. Thus, the probability that all 1000 devices have a parameter within the design specification window is Pig = (.8664)' ~ 0. If C = 1.0, .9973 and Pio = .067, which represents about a 6.7% yield. If C, = 1.5, 999993 and Pio) ~ .993. Finally, if C, = 2.0, P = 999999998 and Piooo ~ 1.0, indicating essentially a 100% yield.28 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS 1.6 TRENDS IN VLSI DESIGN Several trends in the production of VLSI circuits are readily identifiable. Some of these have already been discussed in this chapter. The most visible is the continual shrinking of the minimum geometrical feature size. Although this trend will continue, the rate at which the minimum feature size decreases is slowing. This slowing is partially attributable to inherent physical limitations in the photolithographic process and the rapidly increasing costs associated with very fine resolution processing equipment. Problems associated with power dissipation density, the effects of additional diffusion in small devices due to subsequent heat cycle steps during processing, and concerns about a practical alternative to the widely used standard local oxidation (LOCOS) processing step are all becoming significant in submicron processes. The size of the silicon atom and the silicon dioxide molecule will also be of increasing concern in submicron processes. These concerns about size place very real lower bounds on the conventional approach to integrated circuit design. A trend in increasing speed in digital circuits is readily identifiable. Some research efforts with gallium arsenide (GaAs) suggest that this material may ultimately supplant silicon at very high frequencies. GaAs is attractive because of higher electron mobility and, in some applications, because of reduced sensitivity to radiation. Continual improvement in the performance of silicon circuits raises doubts, however, about when and if a transition to GaAs will occur. The increase in speed and increase in circuit complexity are direct results of the reduction in feature size. A third trend is the increasing complexity of circuit function and device count on a die. This trend is crucial for the development of new markets for integrated circuits. A fourth trend is toward increased designer productivity and an ever-growing dependence on the computer in the design process. Design methods that were standard a decade ago would be totally unworkable in many current design projects. A fifth trend is the continual shift of where design, production, and markets are geographically located. A decade ago most major and innovative design efforts and a significant portion of the production were done in the United States and Western Europe, with more mature technologies being transferred to the Far East. Production was generally most profitable in countries where labor costs were low. An increasing shift in the design efforts to the more developed Far Eastern countries has occurred in recent years, with the mature production shifting more into the less-developed Far Eastern countries, where labor costs remain low. The marketplace is also shifting, with a large number of less-developed countries now experiencing the data processing and telecommunications revolution that swept the West a decade earlier. A trend of the design and production activities geographically following the marketplace is also observable. A sixth trend is a growing coupling of a specific process and its processing equipment. As feature sizes shrink and processes become more complex, the process is becoming increasingly dependent on the performance of specific pieces of equipment.PRACTICAL CONSIDERATIONS 29 Other trends include the use of more powerful CAD tools, which extends VLSI design to the realm of the systems designer, and increasing the complexity of processes by using silicon on insulator (SOI) or combining both MOS and bipolar technologies into a single process. REFERENCES 1. J. E. Lilienfeld, U.S. Patent 1,745,175; 1930. 2. O. Heil, British Patent 439,457; 1935. 3. T. R. Reid, The Chip, Simon & Schuster, New York, 1985. 4. 5, J. 0. T. . J.D, Ryder and D. G. Fink, “Engineers and Electrons”, IEEE Press, New York, 1984. . 1. Catt, “Wafer-Scale Integration,” Wireless World (GB), vol. 87, no. 1546, pp. 57-59, July 1981. . W. R. Moore, “Introducing Wafer-Scale Integration,” Silicon Design, vol. 6, p. 9, January 1986. 7. R. Aubusson and I. Catt, “Wafer-Scale Integration—A Fault Tolerant Procedure,” IEEE J. Solid State Circuits, vol. SC-13, no. 3, pp. 339-344, June 1978. 8. D. L. Peltzer, “Wafer-Scale Integration: The Limits of VLSI?" VLSI Design, vol. IV, no. 5, pp. 43-47, September 1983. 9. R. R. Johnson, “The Significance of Wafer-Scale Integration in Computer Design,” presented at the IEEE Int. Conf. on Computer Design: VLSI in Computers, Port Chester, NY, pp. 101- 105, October 1984, 10. IEBE, “Whatever Happened to Wafer-Scale Integration?,” IEEE Spectrum, vol. 19, n0. 6, p. 18, June 1982. 11. R. H, Dennarg, E. H. Gaensslen, H. -N. Ya, V. L. Rideant, E, Bassous, and A. R. LeBlanc, “Design of Ion-Implanted MOSFETS with Very Small Physical Dimensions,” IEEE J. Solid State Circuits, vol. SC-9, pp. 256-268, October 1974, 12, Erie Demoulin, “Fabrication Technology of MOS ICs for Telecommunications,” Design of MOS VLSI Circuits for Telecommunications, ed. Y. Tsividis and P. Antognetti, Prentice-Hall, Englewood Cliffs, N.J. 1985, Chapter 1. 13. W. E. Loeb, “IC Packages, Costs, Trends and Forecasts,” W. E. Loeb and Associates, Soquel, Calif., June 1987. 14, R. B. Seeds, “Yield and Cost Analysis of Bipolar LSI,” IEEE Int. Electron Devices Meeting, Washington, D.C., p. 12, 1967. 15. B. T. Murphy, “Cost-Size Optima of Monolithic Integrated Circuits,” Proc, IEEE, vol. 52, pp. 1537-1545, December 1964. 16. D. G. Ong, Modern MOS Technology, Processes, Devices and Design, McGraw-Hill, New York, 1984. 17, W. E, Ham, “Yield-Area Analysis: Part I—Diagnostic Tool for Fundamental Integrated Circuit Process Problems,” RCA Review, vol. 39, pp. 231-249, June 1978. 18, T. Okabe, M. Nagata and S. Shimada, “Analysis on Yield of Integrated Circuits and a New Expression for Yield,” Electrical Engineering in Japan, vol. 92, pp. 135-141, 1972. 19. C. H. Stapper, A. N. McLaren, and M. Dreckmann, “Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product,” IBM J. Res. Develop., vol. 24, pp. 398-409, 1980. 20. V. E. Kane, “Process Capability Indices,” Journal of Quality Technology, vol. 18, pp. 44-51, January 1986. PROBLEMS Section 1.1 1.1, How many SiOz molecules will be required to form the insulating layer under the gate of a MOSFET that has a 3. X 3 p. gate area if the silicon dioxide thickness is 800 A? Repeat if the gate is 0.5 zx 0.5 yz with a 100 A SiO> layer.30 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS 1.2. What is the average number of vertically stacked SiO) molecules in an 80 A gate oxide layer? Section 1.4 1.3. If the average resistance density (resistance/unit area) is 1.2 Q/q? and the capacitance density is 0.7 fF/u?(1 fF = 10~? pf = 10-5 F) and if a 5 inch wafer costs $250 to produce, what is the cost (based upon area) of a 250 kM resistor? What is the cost of a 100 pF capacitor? How many 2 4 x 2 w transistors can be placed in the area required for the 250 kQ resistor? For the 100 pF capacitor? What is the cost per transistor if spacing and interconnection area are neglected? What is the cost per transistor if spacing and interconnection increase the area per transistor by a factor of 10? Section 1.5 1.4, If a 4 inch wafer costs $200 and the defect density is D = 2/cm?, what is the maximum permissible die area that can be used if the effective die cost (cost per good die) must not exceed 45¢? Assume the Seeds model characterizes the yield of the process and neglect area losses associated with placing square dies on a round wafer. 1.5. If an 8-bit flash A/D converter has 2° comparators and all must have an offset voltage less than 40 mV (—40 mV < Vertue < 40 mV) for the device to operate properly, and if the offset voltage for the comparators in this process is 20 mV, what percentage of the dies will fail due to soft faults associated with the offset voltage? If the same approach is used to build a 10-bit converter, the offset voltage requirement is more stringent (10 mV). If the same process is used, what percentage of the dies will now fail due to soft faults associated with the process? 1.6. Derive an expression for and plot the effective die cost (cost per good die) versus die area if the defect density is 2/cm? for both the simple model of Eq, 1.5-1 and Seeds model. Also obtain an expression for and plot the cost per unit area and the cost per good unit area versus die area for both models. Assume the wafer size is 4 inch and the wafer cost after processing is $200. 1.7. What is the average cost per good 24-pin plastic DIP package of a die that is 0.1 inch on a side if it is fabricated on a 5 inch wafer and the average defect density is 1.5/em?? Assume that wafer probing is used to eliminate defective dies and that the packaging yield is 85%. Use the typical processing costs listed in Table 1.4-2 for your calculations. 1.8. Repeat Example 1.4-1 if the die size is decreased to 0.2 cm X 0.2 em and the defect density is 1.5/em*, Assume the yield model of Eq. 1.5-1 and a.packaging yield of 95%. 1.9. Assume an integrated circuit has a die size of 0.8 cm X 0.8 cm, defect density of 2fem?, a wafer size of 4 inch, a package requirement of 64 pins, and a packaging yield of 90%. (@) Calculate the average cost per good package if wafer probing is used and parts are packaged in plastic DIP packages. (b) Compare the results of part (a) with the average cost per good package if wafer probing is omitted and parts are packaged in ceramic side brazed packages. Use the processing and packaging cost estimates of Table 1.4-2. 1.10. A 5 inch wafer is yielding 85% at wafer probe with a die size of 0.2 em x 0.2 cm. Determine the defect density assuming the process is characterized by the Seeds model.11. 1.12. PRACTICAL CONSIDERATIONS 31. Assume an area overhead per die of 250,000 y? to allow for interconnection of a die to the outside world. Assume that a minimum size transistor is 3p? and an additional 60 4? is needed for spacing and internal interconnection for each transistor. Assume also that the die is fabricated on a 4 inch wafer and that production costs are characterized by the values given in Table 1.4-2. (a) Calculate and plot the average cost of fabrication per transistor on this die as the number of transistors on the die ranges between 1 and 100,000. (b) Calculate and plot the average cost per good transistor on good dies if the fatal defect density in the external interconnection area is 0.1/cm? and that in the area devoted to transistors (transistor, spacing, and interconnection) is 1.5/em?. Use the model of Eq. 1.5-2. Determine the minimum acceptable capability index for characterizing a process if a soft yield of 95% must be maintained on a die that contains 2000 devices.CHAPTER 2 TECHNOLOGY 2.0 INTRODUCTION A good understanding of processing and fabrication technology on the part of the circuit designer is necessary to provide the flexibility needed to optimize integrated circuit designs. With this knowledge the actual layout can be considered during design and the appropriate parasitics can be included in the analysis. Innovative techniques that improve performance often involve circuits or geometries that are dependent on and applicable to a particular process, Knowledge of processing characteristics enables the designer to make yield calculations during design and consider tradeoffs between yield, performance and design simplicity. In this chapter processing technology is discussed from a qualitative viewpoint. This is followed by a detailed discussion of typical NMOS, CMOS, bipolar, thick film, and thin film processes. Most processes in industry can be viewed as either a straightforward variant or extension of these processes. These processes are summarized in the appendices of this chapter. Included in the appendices are process scenarios, graphical process descriptions, design rules, process parameters, and some computer simulation model parameters. These appendices should provide a useful reference for material that is presented in later chapters of this book. This chapter is concluded with a discussion of practical layout considerations and comments about some CAD tools that have become an integral part of the IC design process. 2.1 IC PRODUCTION PROCESS The major steps involved in producing integrated circuits are considered from a qualitative viewpoint in this section. These steps are used in the MOS and/or bipolar processes that will be discussed later in this chapter. 32TECHNOLOGY 33 2.1.1 Processing Steps CRYSTAL PREPARATION. The substrate of bipolar and MOS integrated circuits is generally a single crystal of silicon that is lightly doped with either n- or p- type impurities. The substrate serves both as the physical medium upon and within which the IC is built and as part of the electrical circuit itself. These crystals are sliced from large right-circular cylinders of crystalline silicon, which are carefully grown to lengths up to 2 m and which vary in diameter from 1 to several inches. The slices are typically 250 pz to 400 p thick. From an electrical viewpoint much thinner slices would be acceptable; however, the thicker slices have been adopted because they are more practical to handle (less breakage) and are less likely to warp during processing. The size of the wafers has been increasing rapidly with time to allow for both large chips and a larger number of chips per wafer. As of 1989, many of the older processing lines were using 4 inch wafers, but the newer lines are typically using 5 and 6 inch wafers. The crystals are often cut so that the surface is oriented approximately in the <100> direction. MASKING. IC masks are high-contrast (black on clear) photographic positives or negatives. They are used to selectively prevent light from striking a photosensi- tized wafer during the photolithographic process. The masks are typically made of glass covered with a thin film of opaque metal, although less costly and less durable emulsion masks are sometimes used. The masks are produced from a digitized description of the desired mask geometries. There are several different methods of generating the masks (called pattern generation) from the digitized circuit description. One method involves photographically reducing large copies of the desired patterns that have been generated with a computer-controlled drafting machine. This method was used widely in the past but has largely been replaced by the next two. A second uses a laser beam as a pattern generator in a raster-scan mode. Both of these methods generally also require a high-resolution step and repeat and/or reduction camera to make the final masks that will be used. The intermediate image that is created is called a reticle and is usually 5 or 10 times real size. A third method uses an electron beam (E-beam) to generate the actual patterns directly onto the final masks. This method produces the best quality masks and is used extensively for very small geometries, but it requires considerable time and expensive equipment. PHOTOLITHOGRAPHIC PROCESS. Photoresist is a viscous liquid. It is applied ina thin, uniform layer (about | 42 thick by spinning the wafer) to the entire surface of a wafer following cleaning. After application the photoresist is hardened by baking. The physical characteristics of the photoresist can be changed by exposure to light. The photoresist thus acts as a film emulsion and can be exposed by light through the transparent areas of a mask (either by contact printing or projection), by a projection of light through a reticle containing the same information (called direct step on wafer), or by an electron beam (E-beam) that scans the desired regions. Following exposure, the resist is developed to selectively remove the resist from unwanted areas. This step is often followed by another baking to further harden the remaining photoresist.34 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Both positive and negative photoresists are available. With negative photoresist the unexposed areas are removed during development, and with positive resist the exposed areas are removed. Negative resists are noted for being quite unaffected by etchants used in processing, but finer resolution can typically be obtained with positive resists. Photoresists serve as protective layers to many etchants and oxidizing agents, and as a barrier to ion implants. Proper mask alignment is essential to maintain device operation, characteristics, and yield. Alignment markings are generally included with the circuit information when the masks are made so that these marks will appear on the wafer during and after processing. A machine called a mask aligner is used to align and expose the wafers. Figure 2.1-1 shows typical alignment characteristics. The physical size and geometry of the masks used for fabrication is governed by the particular technique used by the mask aligner to expose the wafer. Mask aligners that use contact printing have multiple copies of the individual circuits at actual size (j.e., 1X) accurately patterned on the mask. These aligners have a large throughput and are relatively inexpensive. The large masks, however, have a very short lifetime (typically 3 to 10 exposures) because of damage incurred when the mask contacts the photoresist for exposure. This increases effective mask costs. The direct step on wafer aligners typically use a 5X mask (often called a reticle) as a negative. It typically will contain only a single copy of the circuit, though several copies may be used for small ICs. The image is optically reduced to 1X upon exposure. The wafer must be repeatedly moved to the next location after each exposure until the entire wafer is exposed. The lifetime of the mask is very long since no physical contact is made, but the throughput has been decreased considerably to allow for the successive wafer movements. The bk ~54— Pe) (a) oy “at be] FeeemoMneetl Alignment marks: (a) Mask marks, (b) Simulated positioning of alignment marks (o) after fabrication,ecunoLocy 35 equipment is also considerably more expensive because of the precision needed to maintain consistent and repeated uniform stepping of the wafer. Both types of aligners are widely used in industry. One of the most practical and popular methods of exposure actually combines the mechanical economics of the | x aligners and the mask life of the steppers. In this approach, a thin protective membrane, called a pelicle, is placed above the emulsion of 1X chrome masks for protection of the mask and long mask life. Although the membrane itself may get dirty or scratched, it is placed far enough away from the mask so as to remain out of focus and thus not project defects onto the wafer when columniated light is focused through the mask onto the wafer. A fourth method of exposure actually uses no masks at all. Instead, a narrow electron beam (E-beam) is selectively focused on the wafer in a raster-scan manner in small regions, with wafer stepping to position successive portions of the wafer under the beam. The same digital database that is used to generate masks can be used to drive the E-beam system. This approach gives better resolution than any of the previously discussed methods but involves very expensive equipment and has a much smaller throughput. It is practical for only the most demanding applications. DEPOSITION. Films of various materials must be applied to the wafer during processing for most existing semiconductor processes. Often these films are very thin (200 A or less for some SiO» layers) but may be as thick as 20 w for “thick film” circuits. Films that are deposited include insulators, resistive films, conductive films, dielectrics, n- and p-type semiconductor materials, and dopants that are subsequently forced deeper into the substrate. Deposition techniques include physical vapor deposition (evaporation and sputtering), chemical vapor deposition (CVD), and screen printing for the thick films. With the exception of the screen-printed films, the depositions are nonselective and are placed uniformly over the entire wafer. Evaporation refers to evaporating the material that is to be deposited by controlling the temperature and pressure of the host material environment. A film is formed when the material condenses. A continuous evaporation—condensation process is established that allows for a controlled growth rate of the film. Sputtering involves bombardment of the host material with high energy ions to dislodge molecules, which will reattach themselves to the surface of the wafer (as well as to other surfaces in the sputtering apparatus). Often two different host materials are simultaneously bombarded at different rates to establish the characteristics of the sputtered material. This dual host bombardment is termed. cosputtering. With some materials, sputtering offers advantages over evaporation in host material integrity on the deposition surface. Chemical vapor deposition (CVD) is achieved in two ways: (1) by causing a reaction of two gases near the substrate, a reaction occurs that creates solid molecules, which subsequently adhere to the substrate surface; or (2) by pyrolytic decomposition (a decomposition caused by heating) of a single gas, which also frees the desired molecules for reattachment.36 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS ETCHING. Etching refers to selectively removing unwanted material from the surface of the substrate. Photoresist and masks are used to selectively pattern (expose) the surface of the substrate. Following this patterning, the physical characteristics of the surface are changed by etching. A single IC will generally undergo several different etches during processing. The chemicals used for etching are chosen to selectively react with unprotected areas on the wafer while not affecting the protected areas. A summary of the effects of some commonly used etchants on typical semiconductor materials is shown in Table 2.1-1. There are two types of etches used in production: wet and dry. The wer etches, often called chemical etches, use liquid etching agents, which are applied to the substrate surface. Although they have received widespread application in the past, they etch horizontally as well as vertically into the surface of the substrate. This horizontal etching causes undercutting of the patterned areas. Unless the width of the nonetched regions is orders of magnitude greater than the thickness of the material being etched, the nonuniformity of the horizontal etching causes significant changes in desired device characteristics. TABLE 2.1-1 Characteristics of commonly used fabrication materials I. Materials used in IC fabrication Purpose Materials Comments Silicon crystal substrates SiCly Silicon source for growth of single crystal silicon SiHCI, Silicon source for growth of single crystal silicon SiO, (Sand) Silicon source for growth of single crystal silicon Silicon layers (both SiCl, and Hy The hydrogen gas strips the Cl atoms single crystalline to form solid silicon, and polysilicon) SiH, Heat causes the release (pyrolysis) of Hy gas. SiH;Cl, Heat causes the release (pyrolysis) of HCI gas. Oxides 02 Used to grow SiO» by thermal oxidation 0 (Steam) Used to grow SiO} by thermal oxidation SiH and O> Used for CVD deposition of SiO, and to grow protective “glass” (SiO) Nitride layers Sig and NH3 ‘The ammonia causes the release of hnydrogen gas and leaves SisNy. SiClg and NH3 The ammonia causes the release of HCI and leaves Si3Ns. Etches, wet Pls Hydrofluoric acid etches SiO, but not Si, SisNg, or photoresist HF and HNO3 Etches SiTECHNOLOGY 37 TABLE 2.1-1 (Continued) Purpose Materials Comments HPO, Hot phosphoric acid etches SisNy but not SiO. Removes some types of photoresist. Etches, dry CHF; Etches SiO, GFs Etches SiOz SF¢ Etches silicon CF, Etches Si3Ny cc Etches aluminum Patterning Photoresist Used as barrier to ion implants. Also used to pattern SiO> since photoresist is not affected by HF, a common SiO) etchant. SiO Acts as a barrier to some p- and n- type impurities SigNy Used as protective layer over silicon or SiO, to prevent thermal growth of SiOz. Also serves as a barrier to low-energy ion implants although thin layers can be and are penetrated with higher-energy implants. Also serves as a diffusion barrier to impurities such as Ga, Al, Zn, and Na. Il. Sources of impurities Impurities Source mtype Arsenic As,03, AsH3 Antimony Sb205, Sb:0, Phosphorus P20s, POC] (liquid), PH3 (gas— implant or diffusion) p-type Gallium Aluminum Boron BN (solid), BBrs (liquid), B03 (gas), BCI3, (gas), BoHe (gs), BF; (for implants) IIL. Impurity migration in silicon Impurity Silicon SiO, Arsenicf(n) moderate very slow Antiznony (n) moderate very slow Phosphorus (n) fast slow Gallium (p) moderate fast Aluminum (p) fast fast Boron (p) fast slow ‘Arsenic is often preferred to the other n-type impurities because it gives more abrupt junction gradienis, ‘which yield better frequency response and improved current gain in bipolar transistors. Due to environmental concems, however, the use of arsenic in the semiconductor industry is limited.38 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Dry etching, also termed ion etching, is directional and thus much less susceptible to the undesirable horizontal undercutting. Dry etching techniques include sputter etching, ion-beam etching, and plasma etching. Since no liquid chemicals are involved, a significant reduction of costs associated with disposal of spent chemicals is realized when dry etches are used. The etch rate for dry etches is generally lower than the wet etch rate. Dry etching is recognized as a practical alternative to wet etching and is widely used. The characteristics of an ideal wet etch and an ideal directional etch are shown in Fig. 2.1-2. The nondirectional etch is termed an isotropic etch. The edge profile appears approximately circular, with radius r and center at point A. If the etch is stopped precisely when the underlying layer is exposed the radius r will be T,, the thickness of the layer, and the undercut of the protective layer, X,, will be also T. If the etch is not stopped precisely when the underlying layer is exposed, the radius will be T,, which is greater than 7’, and both the effective opening and the undercut will thus be larger than desired. ‘An ideal directional etch is termed an anisotropic etch. Note that an anisotropic etch has a very abrupt edge, which causes problems for applying subsequent layers uniformly and reliably across this edge. protective layer : os fo underlying ‘over etched layer under etched Sealy etched fa) protective layer underlying layer protective protective layer layer underlying FIGURE 2.1-2 layer Characteristics of etches: @ Isotropic etch, (6) Anisotropic (ec) etch, (c) Preferential etch.TecHnoLocy 39 The term preferential etch characterizes an etch that prefers one direction but is less directional than an anisotropic etch. A preferential etch is depicted in Fig. 2.1-2c. The preferential etch may be preferable where subsequent layer coverage of an anisotropic etch is problematic.! DIFFUSION. Diffusion, in the sense of an IC processing step, refers to the controlled forced migration of impurities into the substrate or adjacent material. The resultant impurity profile, which plays a major role in the performance of the integrated circuit, is affected by temperature and time as well as the temperature-time relationship during processing. Subsequent diffusions generally cause some additional migration of earlier diffusions. Actually, the diffusion process continues indefinitely, but at normal operating temperatures of the integrated circuit it takes tens of years or longer for the additional movement to become significant. The method by which the impurities are introduced varies. A solid deposition layer or a gaseous layer above the surface can be used as the source of impurities. Impurities can also be accelerated to selectively bombard the substrate so that they actually become lodged inside the substrate very near the surface. This technique, termed ion implantation, offers very accurate control of impurity concentrations but causes significant crystal damage near the surface. The purpose of a diffusion following deposition is to cause a migration of carriers into the substrate from either solid or gaseous surface layers. A diffusion step following ion implantation is used to mend or anneal bombardment-induced fractures in the single crystalline structure at the surface of the substrate as well as to cause additional impurity migration. As in the etching process, the direction of impurity diffusion is difficult to control with accuracy. Impurities typically diffuse both vertically and laterally from the surface at comparable rates in a manner similar to that observed for the isotropic etch of Fig. 2.1-2a. CONDUCTORS AND RESISTORS. Aluminum or other metals are often used as conductors for interconnection of components on an integrated circuit. These metals are typically deposited, patterned, and etched to leave interconnects where desired. The thickness of the popular aluminum films is typically about 6000- 8000 A but may be as much as 20,000 A for linear (analog) single-level metal processes. Metal films are particularly useful for interconnects that must carry large currents, but traces must be wide enough to avoid the metal migration, or electromigration problem. Electromigration is the movement of atoms with current flow and can be likened to wind erosion of dirt. If significant metal migration occurs, the conductors become open, resulting in failure of an integrated circuit. Metal migration is insignificant provided the peak current density in the conductor is below a certain threshold. For aluminum, this threshold is around 1 mA/u?. This threshold is material dependent and ranges from 0.05 mA/y? to 2 mA/2 for other similar materials. Nonmetallic films are widely used for conductors and interconnects when current flow is small. These materials are typically worse conductors than metals40 Visi DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS and thus cause a significant voltage drop when currents are large. These materials find limited applications as resistors. Polysilicon is one of the most popular nonmetallic conductors. Polysilicon differs from single crystalline silicon, which is often used as a substrate material, only in that polysilicon is composed of a large number of nonaligned, randomly oriented, small silicon crystals. Although polysilicon is chemically identical to single crystal silicon, its electrical characteristics are much different. Polysilicon is a good conductor when heavily doped and a good resistor when lightly doped. Polysilicon is often used for gates of field effect transistors (MOSFETs) and as an electrode for capacitors. Polysilicon can be deposited over SiO. SiOz can also be readily grown on polysilicon and is often used to serve as a dielectric and isolate two polysilicon layers in processes where double polysilicon (double poly) layers are available. Polysilicon’s characteristics are dependent on the size of the small crystals, often termed the grain size. It can be deposited on a variety of materials and the growth rate can be fairly fast. Polysilicon films are typically about 2000 A thick and are often termed poly. Silicides and/or refractory metals are often used on top of or in place of polysilicon for fabricating conductors. These materials are often much better conductors than polysilicon. OXIDATION. Oxidation is the process whereby oxygen molecules from a gas above the substrate or surface material cause the growth of an oxide on the surface. Since the substrate or surface material is typically silicon, the oxidation process produces silicon dioxide. The speed at which the SiO, layer grows is a function of the doping concentration and the temperature of the substrate during oxidation. The SiO. layer serves as a very good insulator between the substrate or surface material and whatever is placed upon it. When the SiQ> layer is grown on the substrate, a small amount of the Si in the substrate is consumed to provide for the Si molecules in the oxide. The growth of x microns of SiO consumes approximately 0.47x microns of single crystal silicon. As an alternative to oxidation, the SiO layer can be applied by CVD. This technique is used extensively when the SiO> layer must cover something other than Si since no silicon molecules are available for oxidation. CVD can also be done at lower temperatures, which is advantageous if additional diffusion of previously deposited materials must be minimized. SiO, layers formed by oxidation are generally more uniform than those formed by a CVD process. Other types of oxides are also used as insulating layers in fabricating ICs. Doped deposited oxides such as phosphosilicate glass (PSG) are often used as insulators on top of polysilicon. Some of these are doped to improve reflow characteristics during annealing. This doping helps reduce sharp boundaries (improve step coverage) introduced during etching of polysilicon. Nitride (Si3N,) is also used as a dielectric between two levels of polysilicon in some processes. The dielectric constant of Si;Ny is about four times that of SiO. This offers potential for much higher capacitance densities for fixed dielectric thicknesses or much thinner dielectrics for a fixed capacitance density. A thin layer of SiO> is generally applied to the Si prior to the SisNg to minimize the mechanical stress associated with a direct Si interface to SisN4. This stressTecunotocy 41 is caused by a difference in the lattice characteristics of single-crystal silicon and the SisNy layer. Although somewhat different chemically, polyimides are also used as insulating layers, most notably between two metal layers. Polyimides tend to smooth abrupt underlying irregularities, thus reducing the effects of sharp boundaries of underlying metal layers. EPITAXY. Epitaxial growth is generally a CVD. It warrants singling out, however, because of the extensive use of this process step in bipolar integrated circuitry and because epitaxial layers are ideally single crystalline extensions of the substrate. Epitaxial layers are grown slowly enough that the molecules added to the surface can align with the underlying crystalline structure of the substrate to form a crystalline epitaxial layer. A small amount of n- or p-type impurities is generally intentionally introduced into the epitaxial layer during the epitaxial growth to obtain a doped epitaxial layer. Several excellent textbooks provide considerably more detail about semiconductor processing; the interested reader may consult References 3-6. 2.1.2. Packaging and Testing After processing, the integrated circuits are tested and packaged. The first step in the testing process generally involves a process verification to make certain that the process parameters are within the tolerances acceptable for the product. To facilitate this verification, test plugs containing special test structures specially designed for this purpose are included on the wafer at several locations in place of the regular circuits themselves. Alternatively, to avoid sacrificing the potential production die sites that are devoted to test plugs, there is a growing trend to integrate the test patterns into the scribe lines, which are existing grid lines void of circuitry where cuts will be made to separate the dies. A wafer prober is used to make mechanical contact with the test plugs so that electrical measurements can be made. Assuming the process parameters are within tolerance, the individual dies are automatically probed and electrically tested. Defective dies are marked with ink and later discarded. After probing, the wafer is scribed (typically with a wafer saw) both horizontally and vertically between adjacent dies, and the dies are separated. Following separation the individual dies are die attached, or die bonded, to a carrier or to the IC package itself. Wire bonds are subsequently made from the pins of the package to the appropriate locations on the die. The bonding wires are typically of either gold or aluminum. The diameter of this wire is in the range of 1 mil. After the wire bonds are complete, the packages are formed or closed and a final electrical test (and burn in for some parts) is completed. Packaging technology saw minimal advancements through the late 1970s and early 1980s. It is well recognized that existing packaging techniques are a major bottleneck in the evolution of IC technology. Considerable effort on a worldwide basis is focused on the packaging problem. Practical alternatives to the conventional packaging approach, described above, will likely evolve in the next few years.42 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS 2.2. SEMICONDUCTOR PROCESSES There are currently three basic processes used for the fabrication of monolithic integrated circuits containing active devices. These are the NMOS, CMOS, and bipolar processes. The first two are both termed MOS (Metal Oxide Semiconduc- tor) processes even though, as will be discussed later, the standard acronym is no longer completely descriptive. A fourth approach essentially combines bipolar and MOS technologies into a single but more involved process. The mixed bipolar-MOS process is called Bi-MOS. A fifth method for constructing ICs is termed the hybrid process. These processes are depicted in Fig. 1.2-1 Generic processes similar to those used in industry will be discussed in this section. The generic NMOS and CMOS processes discussed are very similar to those available through MOSIS' and the same terminology and conventions that have been established by MOSIS will be followed when practical. Several excellent references provide additional information about the NMOS and CMOS processes available through MOSIS and about MOS processing in general.**74" Additional information about these generic processes, such as design rules and process parameters, are discussed in Section 2.3. Details about a typical Bi- MOS process are not presented, but the basic approach should be apparent after studying the basic MOS and bipolar processes. The NMOS (n-channel MOS) and CMOS (Complementary Metal Oxide Semiconductor) processes are quite similar in that both have the field effect transistor (FET or MOSFET) as the basic active device. In the NMOS process n-channel MOSFETs are available as the active devices whereas in the CMOS process both n-channel and p-channel devices are available. When compared to the NMOS process, the CMOS process offers advantages in design simplicity at the expense of more processing steps. It is often the case that CMOS also offers improvements in power dissipation and performance and in some cases even size over NMOS. These tradeoffs must be considered when selecting the most economical process for a given application. Another MOS process, PMOS, is available but will not be singled out because it is essentially a dual of the NMOS. process. In the PMOS process the basic active device is the p-channel MOSFET. Although the PMOS process was commonly used for some of the earlier MOS circuits, the NMOS process offers some advantages due to characteristics of *The MOSIS (MOS Implementation System) program is sponsored by the U.S. Department of Defense Advanced Research Projects Agency (DARPA). Academic participation in this program has been supported by NSF since 1981, Authorized participants undertake designs in one of several MOS processes supported by the program and submit these designs to MOSIS for fabrication. Designs from a large number of different institutions are combined on a multiproject chip format to significantly reduce the fabrication costs below what would be experienced if designs were independently fabricated, MOSIS assumes responsibility for both mask generation and processing. Eight to ten weeks after the published closing date for a specific processing lot, the designer is scheduled to receive packaged parts and occasionally some unpackaged dies, Technical information about these parts is also included. Additional information about the MOSIS program can be obtained from USC Information Sciences Institute, 4676 Admiralty Way, Marina Del Rey, CA 90292-6695, (213) 822-1511.TecHNoLoGy 43 semiconductor materials available (specifically, electron mobility is higher than hole mobility) and is more popular today. The bipolar process is so named because the basic active device is the Bipolar Junction Transistor (BJT). Higher speeds are currently available with the bipolar process than for the NMOS and CMOS processes although significant improvements in the speed of the latter processes have been and continue to be made. Bipolar integrated circuits are noted for their considerable internal power dissipation compared to that of the NMOS and CMOS processes. For logic circuits the NMOS and CMOS circuits have a significantly higher component density than their bipolar counterparts. The hybrid process combines thin and/or thick film passive components that are on one or more separate substrates with active devices from a separate substrate onto a common carrier. This makes hybrid ICs quite expensive. For applications that require precise and temperature-stable passive components, the hybrid process often offers a practical solution. MATERIAL CHARACTERIZATION. Some terminology that is common to most semiconductor processes is best introduced at this point. Throughout this text the notation n* will denote a heavily doped n-type semiconductor region, and n~ will denote a lightly doped region. The designation n* or n~ will be assumed relative to the context in which this designation is made. No superscript will be included if the region is doped somewhere between n* and n° or if it is not necessary to make the distinction in the given context. The same convention will be followed for p, p*, and p~ designations. The resistivity of a homogeneous material is a volumetric measure of resistive characteristics of the material. The resistivity is typically specified in terms of ohms-cm (-cm). If a right rectangular solid of material of length Z and cross sectional area A (see Fig. 2.2-1a) has a measured resistance of R between the two ends, then the resistivity of the material is given by AR pao (2.2-1) where it is assumed that the contacts on the two ends cover the entire surface and are perfectly conducting. The sheet resistance is a measure of the characteristics of a large, uniform sheet or film of material that is arbitrarily thin. The sheet resistance is specified in terms of ohms per square of surface area. If a rectangular sheet of material of length L and width W (see Fig. 2.2-1b) has a measured resistance R between the two opposite ends, then the sheet resistance of the material is given by WwW. Ro = R— 2.2-2) ‘oO 7 (2.2-2) where it is assumed that the contacts on the two edges cover the entire edge and are perfectly conducting. It should be emphasized that both the resistivity and sheet resistance are characteristics of materials independent of particular values for A, L, W, and R in the previous equations.44 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Cross-section : | area, A i ea —b- ew - resistivity = p bp S aa (a) >——— + sheet resistance a a Rol aa (b) w Ro [+ 1 1 1 1 t t Ro | | 5] 1 | 56 841A (d) FIGURE 2.2-1 Resistive characteristics of bulk and sheet materials: (a) Resistivity, (b) Sheet resistance, (c)&(d) Graphical calculations from sheet resistance.Tecunotocy 45 Example 2.2-1. Determine the length of a 100 kQ rectangular resistor that is 25 4. wide and is to be constructed from a thin sheet of material with a sheet resistance of Rg = 1000/0. Solution. From Eq. 2.2-2, pues » (oxo Ro 100.2 Note the excessive length of the 100 kQ resistor! | oe The sheet resistance of a thin layer of thickness z constructed from a material that has a resistivity p is given by Ro=® (2.2-3) The resistance of thin rectangular regions of length L and width W on an integrated circuit can be readily obtained from the sheet resistance by counting the number of square blocks of length W that can be placed in the rectangular region. If N blocks can be placed adjacently in the region, then the resistance in terms of the sheet resistance, Ro, is given by R=NRo (2.2-4) An example illustrating this technique is depicted in Fig. 2.2-1c. Occasionally it is necessary to determine the resistance of nonrectangular regions such as that shown in Fig. 2.2-Id or the serpentined pattern of Problem 2.11. The problem of determining resistance of irregular regions is difficult, but for rectangular regions containing the right angles shown, the rule of thumb of adding 0.55 squares for each corer is often used. Example 2.2-2. If Rq = 450/0, determine the value of the U-shaped resistor of Fig. 2.2-1d. Solution. The U-shaped resistor is broken into squares of length W in the same figure. Counting squares and assigning 0.55 squares to each comer, we obtain a resistor of value 8.1 Rg = 364.5 0. It is often necessary to specify the temperature characteristics of resistors and capacitors. The Temperature Coefficient of Resistance (TCR) and Temperature Coefficient of Capacitance (TCC) are typically used for this purpose. These temperature coefficients, which are generally expressed in terms of ppm/°C, are defined by TC = fF \ a \ 10%ppmec (2.2-5) where x is the temperature-dependent #) of either the resistor or the capacitor. If the temperature coefficient is independent of temperature, then the value of the component at a temperature T> can be obtained from its value at temperature T, by the expression (Tp) = x(Ty eB (2.2-6)46 Visi DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS which is often closely approximated by x(Tx) =~ x(T)U1 + (1, — Ty(TC/109)] 22-7) If the TC is a function of temperature, then the previous expressions are good only in local neighborhoods of T;. The value of TC, which can be either positive or negative, is determined by the material properties and is often quite small. The absolute values of TC are often less than 1000 ppm/°C. Unfortunately, since integrated circuits are often expected to operate over a relatively wide temperature range (0-70°C commercial or —55 to 125°C military) the effects of the TC can be significant. Example 2.2-3. Determine the percentage error introduced in calculating x(T2) from x(T;) by using the simpler linear equation (2.2-7) compared to (2.2-6) if T, =30°C, T; =60°C, and the temperature coefficient is constant and given by TC = 1000 ppm/°c. Solution. Using the exact expression we obtain x(60) = x(30)e°° = x(30)(1.0304545) Using the approximate expression we obtain (60) = x(30)[1 + (30)(.001)] = x(30)(1.030000) Thus, the error is about 0.044%. Some resistors and capacitors, in addition to being temperature dependent, are also somewhat voltage dependent. This voltage dependence introduces non- linearities in circuits using these devices along with the corresponding harmonic distortion (THD) in many applications. The voltage dependence of resistors and capacitors is characterized by the voltage coefficient, defined by = [4 4~\106 - ve = (hav joo ppm/V (2.2-8) where x is the voltage-dependent value of a resistor or capacitor. The voltage coefficient is analogous to the temperature coefficient, as can be seen by com- paring Eqs. 2.2-5 and 2.2-8. 2.2.1 MOS Processes ‘A brief qualitative discussion of the principle of operation of the MOS transistor at de and low frequency is now presented to provide insight into the MOS process itself. A detailed quantitative presentation about modeling these devices appears in Chapter 3. OPERATION OF THE MOSFET. Consider the n-channel enhancement MOSFET shown in Fig. 2.2-2. In the cross-sectional views it can be.seen that the gate (Metalgate} drain to source | gate drain substrate ‘substrate (a) top view (0) Ves =0, Vos 0 (cutot Yes Vos t source ‘gate drain depletion region inversion region (induced channel) (6) 0< Vag < Vy. Yog = 0 (cutof) 2) Vas> Vp, Vos =0 (ohmic) T Vos source f gate drain pa {0 metal or insulator nregion n+ region pregion p+ region depletion ‘conductor region FIGURE 2.2.2 Operation of n-channel MOSFET (horizontal and vertical scale factors are different). or conductor) is over the insulator (Oxide), which is in turn over the substrate (Semiconductor). The source of the acronym MOSFET should be apparent. If the substrate is tied to the source as shown in Fig. 2.2-2b, then with a zero gate— source voltage the n-type drain and source regions are isolated from each other by the p-type substrate, preventing any current flow from drain to source. A depletion region also forms between the n* drain and source regions and the lightly doped substrate, as depicted in Fig. 2.2-2b-f. The corresponding pn junction is reverse48 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS biased under normal operation and has minimal effects on current flow at de and low frequencies. If a positive gate voltage is applied, electrons will start to deplete the substrate near the surface under the gate. This tends to deplete the p-type substrate in this region and form what is called a depletion region under the gate. A simplified pictorial presentation of this situation is shown in Fig. 2.2-2c. If the gate voltage is increased sufficiently, a number of electrons will be attracted to the substrate surface under the gate sufficient to make this region n-type. This n-type region, which is created electrically (by the electric field established by the gate bias) in the p-type substrate, is called an inversion layer. The gate-source voltage necessary to create the inversion layer is called the threshold voltage, Vy. The inversion layer, shown in Fig. 2.2-2d, is often termed the channel of the MOSFET. Once the inversion layer is created, current will flow from the drain to source or source to drain if a small voltage is applied between these regions. The insulator under the gate prevents any gate current from flowing, thus forcing the current entering the drain to be equal to that leaving the source. Increasing the gate-source voltage beyond the threshold voltage brings additional electrons under the gate, causing an increase in the thickness of the inversion layer and increased current flow from the drain to source (or source to drain) under a fixed drain-to-source bias. If a large drain-source (or source-drain) voltage is applied, this voltage itself will tend to deplete the inversion layer due to the potential drop across the region caused by the current flow. A cross section of the device is shown under a small drain-to-source bias in Fig. 2.2-2e and under a large drain- to-source bias in Fig. 2.2-2f. For a fixed gate-source voltage, there is a value of Vps that effectively pinches off the channel near the drain. This does not cause a decrease in drain current (Ip), for if it did, the inversion layer would immediately reappear since the channel current itself causes the pinching of the inversion layer. If the value of Vps is increased further, the drain current will remain nearly constant. When the gate-source voltage is greater than the threshold voltage, the MOS transistor is said to be operating in the ohmic region prior to the pinching of the channel and in the saturation region when the channel is pinched off. If the gate-source voltage is less than the threshold voltage, almost no drain or source current will flow even when a bias is applied to the drain and source contacts. In this case the device is said to be cutoff. The relationship between Ip, Vps, and Vos for a typical MOSFET, termed the output characteristics, is shown in Fig. 2.2-3, along with the ohmic and saturation regions of operation. The cutoff region is the Zp = 0 line in this figure. The gate current remains at /g = 0 in all three regions of operation. The value of the threshold voltage is determined by the concentration of the p-type impurities in the substrate. If some n-type impurities are added to the region under the gate near the surface of the substrate, the threshold voltage will decrease. If sufficient impurities are added, the region itself will become n-type and the threshold voltage will become negative. An n-channel device withTecHNoLocy 49 saturation region Vos = 4V Vas =3.5V Ves = 3V Vas = 2.5V Ves = 2V FIGURE 2.2-3 Typical output characteristics for an n-channel MOSFET. Vos a positive threshold voltage is termed an enhancement MOSFET and those with a negative threshold voltage are termed depletion MOSFETs. MOS devices formed in a p-substrate (or tub) and thus having n-type drain and source diffusions and an n-type channel are termed n-channel transistors. Those formed in an n-type substrate (or tub) with p-type drain and source diffusions and a p-type channel are termed p-channel transistors. In contrast to the convention introduced above for n-channel transistors, p-channel transistors with a negative threshold voltage are termed enhancement devices and those with a positive threshold voltage are termed depletion devices. Commonly used symbols for enhancement and depletion n- and p-channel devices are shown in Fig. 2.2-4. Since the polarity of the substrate is often known. for either the NMOS or PMOS processes, the simplified notation shown in Fig. 2.2-4, which does not maintain this information in the device symbol, has been widely adopted for both NMOS and PMOS devices. 2.2.14 NMOS Process Although both NMOS and PMOS processes are currently available, the NMOS process has been used more extensively in recent years. The NMOS process is preferred because the characteristics of the n-channel MOSFET are preferable to those of the p-channel MOSFET. This is attributable to a higher mobility for electrons than for holes. The discussion that follows will be based upon the NMOS process. Modifications of this presentation to describe the PMOS process are straightforward and are thus left to the reader. A discussion of a generic double-polysilicon, self-aligned silicon gate NMOS enhancement/depletion process follows. This can be considered as a typical standard process although processes that offer more as well as less flexibility are also standard. This process is similar to a widely used MOSIS NMOS process augmented by a second polysilicon layer. The same basic approach useddrain D gatee—| substrate = G 4 Sub source s n-channel enhancement p-channel enhancement D o o-| Sub o-— ‘Sub s s n-channel depletion channel depletion D s G aa G —t s D alternate n-channel alternate p-channel notation notation D D G of G 4 [ s s simplified enhancement simpitied depletion o- G 4 simplified n-channel simplified p-channel D t!o 'e Yoo oa electric variable convention (n- or p-channel, enhancement or depletion) 50 FIGURE 2.2-4 Symbols for MOS transistors.tecunoLocy 51 here is used for other NMOS processes. The MOS transistors in this process are similar to those depicted in Fig. 2.2-2, with the exception that polysilicon (a good conductor) is used instead of metal for the gate. Field effect transistors with polysilicon gates are also called MOS transistors or MOSFETs even though the acronym MOS is no longer completely descriptive. The devices that are available in this process are 1. n-channel enhancement MOSFETs. 2, n-channel depletion MOSFETs. 3. Capacitors. 4, Resistors. The method of physically constructing each of these components in this process and interconnecting them to form the simple circuit shown in Fig. 2.2- 5 will now be addressed. Both top views and cross-sectional views are presented in Fig. 2A1 of Appendix 2A, Cross sections are along sections AA’ and BB’ of Fig. 2Ala. A summary of the major process steps appears in Table 2A. of Appendix 2A. Additional information about this process relating to layout sizing rules, physical feature sizes, and electrical characterization parameters of the generic NMOS process can be found in Tables 2A.2-2A.5 of Appendix 2A. (Table 2A.3 appears in Plate 5 in the color plate insert.) The circuit designer must present the top view of each mask level for fabrication but must have a firm understanding of the cross-sectional view for effective design. For the NMOS process, the starting point is a polished p-type silicon disc. The thickness of the disc is typically around 500 y. A layer of SiO> in the neighborhood of 1000 A thick is first added to the entire wafer using the oxidation process. On top of this a layer of SisN, (about 1500 A thick) is applied by the Yoo *———— M2 vie V, Mt * ae ec FIGURE 2.2.5 Veno A simple NMOS circuit.52 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS CVD process. Following the application of a layer of photoresist, Mask #1 is used to pattern the surface. Mask #1, which is often called the moat, or n* diffusion mask, defines in photoresist the drain, source, and channel regions of all transistors as well as any other regions where n* implants are desired. After exposure, development removes the photoresist layer in areas that are not to be moat ( i.e., the complement of the moat, or the antimoat), A top (Mask #1 pattern) and cross-sectional view at this stage of what will be the two transistors appear in Fig. 2A.la. The SizN, is then etched from the areas not protected by the photoresist. A high-energy implant of p-type impurities (typically boron) is then applied to the entire wafer. The remaining photoresist protects the moat regions from this implant. This heavy implant is used to raise the threshold voltage in the antimoat region (often called the field) and to provide electrical isolation between adjacent devices. After this field implant and a drive in diffusion, the remaining photoresist is stripped. A thick layer of SiO» (about 10,000 A) is then thermally grown by the oxidation process over the wafer. This layer is formed in the field, but no oxidation can take place in the region protected by the SisN, because Si3Ny does not oxidize. The thick field oxide layer is termed a local oxidation layer and is often called LOCOS. The oxidation consumes some of the substrate silicon. The second cross section in Fig. 2A.la shows the state of the wafer following growth of the field oxide. This corresponds to Step 10 in the process scenario of Table 2A.1. Following removal of the SisNg, the thin layer of SiOz under the SisN, is stripped and another SiO, layer is grown. With the moat now protected only by the very thin SiO» layer, a light n- type implant over the entire wafer can be applied (optional) to set the threshold voltage of the enhancement devices. This implant is light enough so that all p- type regions remain p-type. If used, the implant is applied to the entire wafer to avoid the need for an additional mask. A heavier selective implant is required in regions that are to serve as the channels of depletion transistors. To achieve this, a second layer of photoresist is applied to the entire wafer, and the second mask, Mask #2 (termed the implant mask), is used to pattern the photoresist so that only the channel regions of depletion transistors are unprotected. Another n-type implant is used to make the exposed regions n-type with the remaining photoresist serving as an implant mask. After stripping the photoresist, the wafer is as shown in Fig. 2A.1d. This corresponds to the status of the wafer at Step 19 in Table 2A.1. Direct contacts between the lower polysilicon layer and moat are termed buried contacts. In the process scenario of Table 2A.1 this is listed as an optional step and is not used in the layout shown in Fig. 2A.1 although it could be used, if available, to reduce the area required for contacting the gate of M2 to its source. To make a buried contact, the thin gate oxide must be patterned and etched to remove the insulating SiO» layer and create paths (vias) through which the following polysilicon layer can contact the moat. Mask #A is used to pattem the buried contact vias. Although the buried layer contact can reduce area, the additional processing costs needed to provide this feature are often not justified; hence the buried contact feature is often not available in NMOS processes.tecunoLocy 53 After stripping of any thin oxides that may be present at this stage in the moat region, a uniform thin layer of SiOz, often termed gate oxide (200 to 1000 A thick), is grown on the surface of the wafer. Stripping and regrowing provide better control of the critical gate oxide thickness. A layer of polysilicon (termed POLY 1), which is about 2000 A thick, is then deposited on the surface of the entire wafer. This is covered with photoresist, patterned with Mask #3, and etched to remove unwanted POLY I. The POLY I layer is used as gates for both enhancement and depletion transistors, as a plate for capacitors, as a conductor, and for resistors. The formation of a capacitor, a resistor, and enhancement and depletion transistors can be seen in Fig. 2A.lc. This corresponds to Step 27 in the process scenario of Table 2A.1. Note that the POLY I layer is over gate oxide in cross section AA’ and above field oxide in cross section BB’. The remaining uncovered thin layers of SiO are stripped and another thin layer (500-1000 A) of SiO, is again grown over the entire surface. This serves as the dielectric for POLY I-POLY II capacitors, as an insulator for POLY I-POLY II crossovers, and as the gate oxide for transistors that use the POLY II layer as the gate. The thickness of this oxide layer is often ideally the same as that of the first gate oxide layer. By stripping the unexposed oxide and regrowing, a buildup in the depth of the oxide layers is prevented and more uniformity is attained. A second layer of polysilicon (termed POLY II) is then deposited, followed by photoresist and patterning with Mask #B. In the circuit shown in Fig. 2.2-5, the POLY II layer is used only for the upper plate of the capacitor, as shown in Fig. 2A.1d (Step B.9 of Table 2A.1). Note that it is slightly smaller than the underlying POLY I layer. This difference is standard practice when trying to accurately match capacitors to make one plate a little smaller than the other so that the smaller plate will effectively define the capacitor area independent of slight misalignments of the two plates. Additional practical considerations that further improve matching will be discussed later. ‘After stripping the thin SiO, layers, an n* diffusion is applied to the entire wafer. The field oxide and polysilicon layers serve as masks to the diffusion and prevent impurities from reaching the substrate in the protected areas. The nt diffusion creates the n-type drain and source regions of all transistors and makes any other unprotected moat areas n-type. The portion of the light depletion diffusion that is not protected by the polysilicon gates also becomes more heavily doped. Note that although no mask is used at this step, the n* diffusion mask, which was used as the first masking step, has essentially determined the n* diffusion regions fabricated at this step. The n* diffusion also penetrates into any exposed polysilicon layers, increasing the conductivity in these regions. The n* diffusion depth is about 5000 A. It will be seen in the section discussing process parameters that the sheet resistance for POLY I and POLY Il layers is about the same but that the sheet resistance of POLY I under POLY I is higher. This is due to the absence of the additional n* diffusion in the lower layer. Since the polysilicon gates serve as masks for the n* drain and source diffusions, the process is said to be self-aligned. In a self-aligned process, small misalignments of the gate (POLY I or POLY If) masks will not affect the gate geometry or dimensions, nor will they make the transistors nonfunctional.54 Visi DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS Next, another insulating layer is deposited over the wafer surface. Doped deposited oxide, such as PSG, is often used for this purpose. This rather thick layer, ~ 6000 A, serves as an insulator between the uppermost polysilicon layer and the subsequent metal layer. The field oxide depth is further increased with this deposited oxide layer. The entire wafer is again covered with photoresist, and Mask #4 (actually the fifth or sixth mask if POLY II and/or buried contact options are available) is used to pattern contact openings for the purpose of obtaining electrical contact from the top with the desired components. After the photoresist is developed, an etch that attacks the insulating layer but does not affect polysilicon or silicon makes the required openings. This etch is stopped in the vertical direction only by polysilicon or the single-crystal silicon of the substrate. The wafer takes the form shown in Fig. 2A.le (Step 34 of Table 2A.1). Metal (typically aluminum) is then deposited over the entire wafer, followed by another layer of photoresist. This metal layer is typically about 7000 A thick. This photoresist is patterned by Mask #5, followed by an etch to remove unwanted metal. The metalization is used to interconnect components and provide external access to the integrated circuit. A metalization that interconnects the four basic components to form the circuit shown in Fig. 2.2-5 is shown in Fig. 2A1f (Step 40 of Table 2A.1). Large, square metal areas, called bonding pads, are needed to allow for contact with the IC package. Small bonding wires will later be connected from these pads to the pins on the IC package. These pads are also patterned with the metalization mask but are not shown in Fig. 2A.f because of the large amount of area required for bonding pads relative to that needed for the components in Fig. 2.2-5. A bonding pad is shown in Fig. 2A1g. Four of these would be needed to interface the circuit of Fig. 2.2-5 with the IC package. The Vp contact comes from the bottom side of the substrate. The bonding pad size has remained relatively constant for a long period of time even though considerable reductions in feature size of geometries on the die itself have been experienced. This is because the methods of physically mounting the die in packages and interconnecting the bonding pads to the pins in the package have not changed much. With bonding wires typically about 1 mil in diameter, it is difficult to reduce bonding pad size significantly. The entire surface is finally covered with a passivation layer (often called glass or p-glass) to provide long-term stability of the IC by minimizing atmo- spheric contamination. A layer about 10,000 A thick is often used for passivation. Since this layer is also an electrical insulator, it is necessary to again pattern it and make openings above the metal pads to allow for attaching the bonding wires. The final mask, Mask #6, is used for this purpose and is shown in Fig. 2A.1g. For the simple circuit of Fig. 2.2-5, the area required for the bonding pads dominates that needed for the circuit itself. For simple circuits this is generally the case but as the complexity of the circuit increases, the percentage of the total area required for bonding pads becomes quite small. Giving the information for each mask separately, as was done in Fig. 2A.1, makes it difficult to perceive the entire circuit and determine layer to layerTecunoLocy 55 alignment. Sophisticated software packages termed layout editors are widely used, in which layers are color-coded and displayed simultaneously on high-resolution monitors. A single layout that simultaneously shows all mask information is shown in color in Plate 2. A color convention has been established for distin- guishing separate layers. The color convention adopted in Plate 2 corresponds to that used in the MOSIS process and is discussed in more detail later in this chapter. ‘An interesting observation can be made from the layout of the MOS transistors of Fig. 2A.1. The MOS devices are totally geometrically symmetric with respect to drain and source and so must also be electrically symmetric. The designation of drain and source is thus arbitrary. In many applications a convention has evolved for convenience and consistency in device modeling in regard to drain and source designation. This convention will be discussed in Chapter 3. When appropriate, we will follow the established convention throughout this text. In the process described, séveral alternative methods for constructing resistors and capacitors are available. For example, a region of moat with two contacts can be used as a resistor, and a capacitor can be made between POLY I and metal. Processing step modifications such as omission of one polysilicon layer, omission of the depletion mask, substitution of metal gates for the polysilicon gates, and addition of another mask and implant to create enhancement transistors with two different threshold voltages are possible and common. Process procedure modifications such as using diffusions instead of implants; changing types of impurities; varying the thickness of oxide, polysilicon, or metal layers; including or excluding oxide stripping and regrowing steps; and changing types of photoresist are widespread and play major roles in yield, fabrication costs, and performance. The IC design engineer must be familiar with the process steps that will be used in fabrication when embarking on a new design. For the process just described, it is the responsibility of the circuit designer to provide all information necessary to construct the seven masks shown in Fig. 2A. The size, shape, and spacing of the components are judiciously determined. The size and shape affect the performance of the circuit and are at the control of the circuit designer for optimizing performance, within constraints of minimum allowable size as determined by the capabilities of the process and maximum size as determined by economics. The spacing is also constrained by the capabilities of the process itself. The spacing and sizing specifications are obtainable from the design rules of the process, which are discussed later in this chapter. A process engineer will typically be responsible for providing design rules for a particular process. 2.2.16 CMOS Process A discussion of a typical generic single-polysilicon silicon gate, p-well, n- substrate CMOS process follows. As in the NMOS case, variants in this process — such as a second metal layer, a second polysilicon layer, additional implants, oppositely doped substrate, or metal gates —are also well established. The devices available in the CMOS process under consideration are56 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS 1, n-channel MOSFETs. 2. p-channel MOSFETs. 3. Capacitors. 4, Resistors. 5. Diodes. 6. npn bipolar transistors. 7. pnp bipolar transistors. The diodes and bipolar transistors are often considered parasitic components and are generally not extensively used as components in the circuit design itself. The process is tailored to maintain optimal characteristics in the n- and p-channel MOSFETs at the expense of poor characteristics for the bipolar transistors. ‘A method of physically constructing each of the first four components in the list will be considered. The approach followed here is similar to that followed for the NMOS process except that all mask details are included on the single layout of Fig. 2B.1 of Appendix 2B. A color version of this figure appears in Plate 3. Fewer details about oxide growth, photoresist application and patterning, and so on are provided since these steps are very similar to the corresponding steps for the NMOS process. Cross-sectional views along AA’ and BB’ in Fig. 2B. 1a after each major step are shown in Fig. 2B.1. Interconnections follow the approach used in Section 2.2-la for the NMOS process and are not discussed here. A summary of the major process steps appears in Table 2B.1. Additional information about this process relating to layout sizing rules, physical feature sizes, and electrical characterization parameters of the generic CMOS process can be found in Tables 2B.2-2B.5 of Appendix 2B. The process described here is very similar to the 3 4 CMOS/bulk process available through MOSIS.” The starting point of this CMOS process is a polished n-type silicon disc. A layer of SiO, is first grown on the entire disc, followed by the application of a layer of photoresist. This photoresist is patterned with Mask #1 to provide openings for a p-tub (alternatively, p-well), which will serve as the substrate for the n-channel MOS devices. Either a deposition or implant is used to introduce the p-type impurities that form the tub. This diffusion is quite deep (about 30,000 ). The remaining photoresist and SiOz are then stripped, a thin layer of SiO, regrown, and the entire surface covered with a layer of SizNg. Mask #2, termed the moat mask or the active mask by MOSIS, is used to pattern the SisNg layer. The SisNg layer is then etched away except above the regions that are to be the n* and p* diffusions or channel regions for the n-channel and p-channel MOSFETs. These diffusions will be added by subsequent processing steps to form drain and source regions for MOSFETs as well as to form guard rings. These protected regions are again termed moat. After the SijN, layer is opened, the remaining photoresist is stripped. Figure 2B.1b depicts the wafer after Step 15 of the process scenario of Table 2B.1. An optional field threshold adjust step may be introduced at this point. This field threshold adjust would be used to raise the threshold voltage in the n-typetecHNoLocy 57 substrate in regions that will not contain devices. This will provide increased isolation between the p-channel transistors. Although an additional mask is required for this field adjust (Mask #A1 of Table 2B.1), the mask would be the complement of the union of the p-well mask and the active mask, Masks #1 and #2. As such, this mask information would be generated automatically and need not be separately provided by the designer. A thick layer of field oxide (typically 10,000 A) is grown in the regions not protected by the remaining Si3N, that was patterned with Mask #2. The SisN,, along with the remaining SiO» that was under this layer, are then stripped. The wafer at this stage is as depicted in Fig. 2B.1c. This corresponds to Step 18 in the process scenario of Table 2B.1. Note that along cross section AA’ several isolated areas are not protected by the field oxide. These areas will be used for fabricating transistors and guard rings. No breaks in the field oxide appear in the BB’ cross section. This corresponds to the region where the resistor and capacitor will appear; these devices are fabricated on top of the field oxide. Next, a thin, uniform layer of SiOz (200 to 1000 A), called in this case gate oxide, is regrown. A layer of polysilicon (typically 2000 A) is then deposited, covered with photoresist, and patterned with Mask #3. This polysilicon layer, termed POLY or POLY I, is used for the gates of all transistors, as a plate on capacitors, for resistors, and for interconnects. Following etching and stripping, the wafer takes the form shown in Fig. 2B.1d. This corresponds to Step 25 in the process scenario of Table 2B.1. An optional second polysilicon layer, termed POLY II, could be included here, as provided in the process scenario. The second polysilicon layer is not depicted in Fig. 2B.1. This second polysilicon layer would be separated from the first by a thin (500 to 1000 A) insulating layer of SiO». The main purpose of the second polysilicon layer would be for the formation of capacitors with POLY I and POLY II as electrodes, although this layer would also find some use in interconnects and crossovers if available. The capacitance density and electrical characteristics of the poly—poly capacitors are more attractive than those obtainable with other capacitors available in this process. An additional mask, termed the POLY Il or electrode mask, is needed to pattern this polysilicon layer. The etch of both the POLY I and POLY II layers produces an abrupt, sharp edge, making reliable coverage of this edge with thin material difficult. Since the oxide between POLY I and POLY II is thin, crossing of a POLY I boundary with POLY II may result in either a break in the POLY II or a shorting of POLY I and POLY II. To circumvent these problems, the crossing of a POLY I boundary with POLY II is often not permitted. At this stage the drain and source diffusions for both the n-channel and p-channel transistors are added. Although two different types of diffusions and hence two separate masks are required, the designer need specify only one of the two masks. In this process, only those areas not protected by field oxide are capable of accepting any diffusion impurities. This is termed the moat, or active, region. It is further provided in this process that any moat area that is not exposed to n-type impurities will be exposed to p-type impurities. Consequently, the designer selects those moat regions that are to become p-type with Mask #4,58 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS which is termed the p* select mask. The n* select mask (Mask #5), which is used to pattern those regions of moat that are to become n-type, is automatically generated from the complement of the p* select mask intersected with the moat (active) mask. p* select is used in the substrate to form p-channel transistors and interconnects and is used in the p-well to provide ohmic contact to the p-well as well as for guard rings. Correspondingly, n* select is used in the p-well to form n-channel transistors and interconnects, and in the substrate to make top ohmic contacts as well as additional guard rings. Further comments about guard rings and their role in latch- up protection appear in Section 2.4. As was the case in the NMOS process, the polysilicon layer or layers are patterned prior to the p* and n* diffusions. The polysilicon that lies in the moat serves as a diffusion mask for these diffusions and provides self-alignment of the gate with the drain and source regions. The n* and p* diffusions are much shallower than the p-well diffusion and are typically in the 5000 A and 7000 A ranges, respectively. Following the p* and n* diffusions, which occur prior to Step 36 in the process scenario, the cross-sectional profile is as shown in Fig. 2B.1e. The n-channel and transistors, along with the ohmic contacts and guard rings, are clearly this stage. A thick insulating layer, which is a deposited oxide (often PSG), is then placed over the entire wafer. This insulating layer is about 6000 A thick and serves as an insulator between the uppermost polysilicon layer and the subsequent metal layer. This causes a further thickening of the field oxide and is depicted above the dashed interface of the field oxide layer shown in Fig. 2B.1f. Mask #6 is used to pattern contact openings. Areas unprotected by photoresist after patterning are etched away. This etch will consume insulating layers but is stopped by either polysilicon or the silicon substrate. This provides for metal contact of either a polysilicon layer or a p* or n* diffusion depending on which is the uppermost layer present. After the contacts are opened, metal is applied uniformly to the wafer and patterned with Mask #7. This is termed the metal mask (or, if subsequent metal layers are to be added, the metal 1 mask). This corresponds to Step 48 in the process scenario and the cross section of Fig. 2B.1f. An optional second metal can be added at this stage. This requires two additional mask steps, one for making contact with underlying metal 1 and the other for patterning the second metal layer. The mask used to pattern the contact openings, or vias, between the two metal layers is termed the via mask. Polyimide is often used as the insulating layer between the two metals because it offers advantages in step coverage over other commonly used insulating layers. Following application of a passivation layer, often termed p-glass, the passivation is opened above the bonding pads to provide for electrical contact from the top with Mask #8. This is often termed the glass mask. The pad layout is similar to that discussed for the NMOS process and depicted in Fig. 2A.1g. This completes the CMOS processing steps for the generic CMOS process scenario of Table 2B.1. The resistor, capacitor, n-channel MOSFET, and p- channel MOSFET should be apparent from Figs. 2B.1a and 2B.1f.TecHNoLocy 59 2.2.1¢ Practical Process Considerations The equipment needed for the CMOS process is basically the same as is needed for the NMOS process previously described. With this equipment the minimum feature size for the CMOS process is comparable to that for the NMOS process. It should be noted that eight masks and considerably more processing steps than are required for the basic six-mask NMOS process are needed for this CMOS process. In addition, it will be seen later that considerably more area is required for the same number of devices in a CMOS process than in an NMOS process with the same feature size. The increase in size is due largely to the required size of the large p-tubs and the n- and p-type guard rings. These increases in area are, however, often offset by less complicated designs and/or the superior performance that is attainable with the CMOS process. Several physical and processing-dependent material characteristics cause the physical MOSFET to differ from the ideal. The processing-dependent material characteristics will be considered first. WIDTH AND LENGTH REDUCTION. A typical cross section of the n-channel MOSFET along EE’ and FF’ of Fig. 2B.1a is compared with the ideal in Fig. 2.2-6. These cross sections are intentionally not to scale so that they will better illustrate the actual characteristics. Ideal F-F’ cross section i i gate | 1 oxide, | polysilicon glass sa ‘bird's ‘& a» beak’ TR Weta fied |. i gate [pw 7 PX) PT oxide oe oxide ot p-well | drain-source lateral | 1 diffusion diffusion (b) @ Typical E-E’ cross section ‘Typical F-F’ cross section FIGURE 2.2-6 Width and length reduction in MOSFETS.60 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS It will be seen later that the width and length of the MOSFET are key parameters at the control of the designer that play a major role in device performance. The width, W, is the width of the moat, or active, region as depicted in Fig. 2.2- 6a, which corresponds to the EE’ cross section of the MOSFET, and the length L is the distance between the drain and source diffusions, as indicated in the FF’ cross section of Fig. 2.2-6c. It should be emphasized that the device dimensions are determined by the size of the intersection of the poly mask and the active mask and not by the dimensions of the poly pattern that forms the gate. In the typical cross section of Fig. 2.2-6b, it can be seen that during the field oxide growth, encroachment into the active region effectively reduced the width of the transistor. This oxide encroachment is termed bird’s beaking due to the distinctive shape of the encroachment. This is particularly troublesome because the width of the transistor is no longer precisely defined and because the exact amount of width reduction is not easily controllable. A second factor that affects the effective width is the accuracy with which the protective Si3N, layer used to pattern the field oxide can be controlled. The effective width of this layer is affected by both the patterning of the photoresist and the problems associated with etching that were discussed in Section 2.1. In addition, since a thin SiOz layer (200-800 A) is applied prior to the SisNg to minimize mechanical stress at the SizNy interface, the encroachment of the SiOz growth also limits accuracy. Similar problems in controlling the length of the transistor exist, as indicated in Figs. 2.2-6c and d. The major source of length reduction is associated with the lateral diffusion of the drain and source diffusions, which are difficult to precisely control. Assuming the lateral and vertical diffusion rates are equal and that the diffusion depth is 5000 A, the total length reduction due to lateral diffusion, since it diffuses in from both ends, would be around 1 yw. This is very significant and problematic in short channel transistors. Other factors that affect the effective length are the accuracy in patterning the photoresist that defines the polysilicon gate length and the accuracy in controlling the polysilicon gate etch itself. In summary, both length and width reduction are inherent with existing processing technologies. Although they can be partially compensated for by considering these reductions during design or automatically adjusting (termed size-adjust) the geometrical database to over- or undersize the appropriate mask geometries, these effects are difficult to precisely control, and the exact width and length of the device are difficult to define. These effects are particularly troublesome for small geometries with device dimensions in the 1 » or smaller range. Partial compensation with the mask size-adjust is often provided, thus allowing the designer to assume that the nominal value of the actual dimensions on silicon agree with those specified on the design. LATERAL WELL DIFFUSION. Lateral diffusion associated with the creation of the p-well also deserves mention. The depth of the p-well is about 3 4. and, the lateral diffusion associated with the well formation is comparable. Although not a major factor limiting device performance, this lateral diffusion consumes considerable surface area and forces the designer to leave a large distance between isolated p-wells and between any p-well and p* diffusion in the substrate, thusTecHNoLocy 61 increasing chip cost by increasing die area. One way to partially minimize the impact of the large amount of area associated with well boundaries is to group large numbers of n-channel transistors into a single p-well when the wells for these transistors are to be tied to the same potential. Tradeoffs between these area savings and the corresponding increase in interconnect area must be made. LATCH-UP. The physics of layered doped silicon is also problematic. It is well known that a four-layer sandwich of doped material, npnp or pnpn, forms a Silicon Controlled Rectifier (SCR). Once an SCR is “fired” (switched to on conducting state), it continues to conduct until the gate signal is removed and current flow is interrupted. Several parasitic bipolar transistors and an SCR are identified on the cross section of Fig. 2.2-7 which is based on Fig. 2B.1f. Several diodes can also be identified. Although this CMOS process has not been optimized for obtaining good performance of these bipolar devices, there are limited practical applications of some of the diodes and bipolar transistors. The SCR, however, is very undesirable and if it is caused to fire, excessive current will usually flow, causing destructive failure of the integrated circuit. The firing of the SCR is termed Jatch-up in CMOS circuits. The CMOS designer must make certain that latch-up cannot occur in any design. Latch-up problems are strongly layout dependent. A theoretical treatment of the latch-up problem is beyond the scope of this text, but a thorough understanding of this problem is not needed for successfully designing CMOS circuits provided the designer is familiar with layout techniques that circumvent the problem. Guard rings are widely used to prevent latch-up. Exact requirements for guard ring ep Beale rn a = = | eo 4 8 n-substrate npn transistor pnp pnp SCR transistor npn transistor FIGURE 2.2-7 Parasitic transistors in a p-well CMOS process.62 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS placement will be determined once a particular CMOS process is defined. In some processes, separate and additional n* and/or p* diffusions are included specifically for guard ring formation. This requires additional masks and additional processing steps. In the CMOS process discussed in this section, no additional masking or processing steps are required since the normal drain and source diffusions are also used to fabricate guard rings. One way to obtain latch-up protection in the generic CMOS process of this section is to completely encircle every p-well with a p* guard ring. Such a guard ring is shown in Fig. 2B.1a around the periphery of the p-well. Metal contact is made as often as possible to this guard ring to further reduce resistance. The guard ring will then typically be connected via metallization to the lowest dc potential in the circuit—Vsg or ground, for example. Although not shown in Fig. 2B.1a, encircling the p-well with an n* guard ring provides additional protection and is also desirable. A partial n* guard ring separating the p-well from the p- channel substrate transistor can be seen in the same figure. As before, numerous metal contacts are made to this guard and it is subsequently tied to the highest potential in the circuit. Breaks in a guard ring must be avoided since these breaks could provide a path for breakdown. Consider first the p* guard ring in the p-well. Breaks can occur one of two ways. The most obvious is to exclude a segment from either the moat mask or the p* select mask. The other way is to cross the guard ring anywhere with polysilicon in the process described in Table 2B.1. Such a crossing will cause a break because the polysilicon is patterned prior to the p* diffusion and serves as a mask to this diffusion. The break would thus occur under any polysilicon crossing of the intended guard ring. The exclusion of polysilicon crossing of the guard ring is undesirable from a circuit designer's viewpoint because it complicates interconnection between devices in the p-well and those outside the p-well; all interconnection crossings must be made of metal to avoid breaking the guard ring. Polysilicon crossing of guard rings in other process scenarios where a separate p* guard ring diffusion is available may be permissible. Correspondingly, breaks in the n* guard ring will occur if a segment is omitted from the active mask, if it is crossed with p* select, or if it is crossed with polysilicon. ‘Although complete enclosure of the p-well with the n* guard ring is desirable, some designers using the generic CMOS process described in this section use only the p+ guard ring or have the p* guard ring and include the n* guard material only between the p-channel transistors and the p-well, as depicted in Fig. 2B. 1a. INPUT PROTECTION. Static breakdown is also of concern, and protection of inputs must be provided to prevent destructive breakdown when handling the devices. The major sources of concern are inputs that have a direct connection to a region separated from the rest of the circuit only by thin oxide, such as gate oxide or poly-poly oxide, with no direct connection to any diffused region. Such inputs would include the gates of any transistors or any connection to a floating polysilicon capacitor electrode. The breakdown is due to a destructive breakdownTECHNOLOGY 63 of this thin oxide due to electric fields that exceed the oxide breakdown voltage. As stated in Chapter 1, silicon dioxide will break down when electric fields are in the 5 MV/cm to 10 MV/cm range. With 1000 A gate oxides, this would occur for voltage inputs in the 50 V to 100 V range. Although these are beyond the maximum allowable input voltages specified for a typical 3 4 CMOS process, these voltages are much less than the static voltages experienced when handling these chips. The problem is even worse for thinner gate oxides. Such breakdown is destructive and must be prevented. Input protection circuitry is used for this purpose. This input protection must not interfere with the normal operation of the circuit. A single simple protection circuit is typically developed and is used repeatedly by connecting it to each pad that requires protection. One common protection scheme involves connecting the input pads through a small polysilicon resistor to a reverse-biased diode that nondestructively breaks down at voltages below the critical gate oxide breakdown voltage. The node that is to be protected then becomes an internal node coincident with the node corresponding to the interconnection between the protection resistor and the diode. The resistor is used to safely limit peak current flow in the protection diode. In the CMOS process described in this section, this diode would be constructed by putting an n* diffusion in a p-well with a p* select guard ring around the periphery of the well. This guard ring would be connected to the lowest potential in the circuit, typically ground or Vs, and the n* diffusion would be connected to the pad that is to be protected through the polysilicon resistor. This protection circuit provides protection through the reverse breakdown voltage of the diode if the input is positive and through normal forward-biased diode conduction if the input is negative. For the NMOS process, single diode protection can be attained by connecting the critical node through a polysilicon resistor to an n* diffusion. No guard ring is available or required in an NMOS circuit. ‘An alternative that provides all protection through normal forward-biased diode conduction is obtained if a second diode of opposite polarity shunts the diode just described. This diode is constructed from a p* diffusion in the substrate, with the n-substrate connected to the highest potential in the circuit and the p* diffusion connected to the intersection node of the first diode and the polysilicon resistor. It is recommended that this p* diffusion be encircled by an n* guard ring, which also would be connected to the substrate. Under normal operation the diodes in the input circuitry do not conduct, so the input protection is ideally transparent to the user. Actuaily, the diodes do contribute to a small amount of leakage current. They also contribute to a small parasitic capacitance connected to an ac ground, which may be of limited concer in some applications. Although the input protection schemes discussed could be used on any input or output pad, such circuitry is generally not required on pads that are already directly connected to a diffusion region, even if they are also connected to layers separated by thin oxide from other nodes in the circuit, because the diffused region itself forms part of the diode and thus provides inherent self-protection. Nevertheless, care should always be exercised when handling any MOS devices, even if good circuit-level protection has been included, to reduce the chance of destroying the integrated circuit by static breakdown.64 ‘VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS 2.2.2 Bipolar Process The basic active devices in the bipolar process are the npn and pnp transistors. These names are descriptive since the devices are constructed with three layers of n- or p- type semiconductor material, with the middle layer different frorn the other two. These layers can be fabricated either laterally or vertically. A simplified pictorial description of these transistors, including the established symbols for the devices, appears in Fig. 2.2-8. Several excellent references discuss the basic operation of the BJT.3:2~!” The modeling of the BJT is discussed in Chapter 3. As will be seen later, the characteristics of the collector and emitter regions as well as their geometries are intentionally different and as such the designation of the collector and emitter contacts is not arbitrary. The convention that has been established for designating the collector and emitter contacts will be discussed in Chapter 3. npn pnp FIGURE 2.2-8 Pictorial Description Symbol Collector ntype [-— Collector p-type +—» Base Base type |. Emitter Emitter c ptype —c n-type t—B B p-type -—*E E electrical variable convention (npn or pnp) Bipolar transistors.TECHNOLOGY 65 The components available in the bipolar process are 1. npn bipolar transistors. 2. pnp bipolar transistors. 3, Resistors. 4, Capacitors. 5, Diodes. 6. Zener diodes. 7. Junction Field Effect Transistors (JFETs)—not available in all bipolar processes. A familiarity with the process is crucial to utilizing this wide variety of components in the design of an integrated circuit. Unlike discrete component circuit design with these same devices, whose characteristics can be specified over a wide range and which can be connected in any manner, the basic characteristics of the devices available for bipolar integrated circuits are determined by the process and the range of practical values and parameters is severely limited. In addition, the methods of interconnection are strictly limited, the basic devices have characteristics that are quite temperature dependent, and the passive component values are typically somewhat dependent on the signal applied. In spite of these restrictions (to be discussed later), very clever analog and digital bipolar integrated circuits have evolved. The bipolar process is used for the popular TTL, ECL, and I'L digital logic families as well as a host of linear integrated circuits, including the 741 operational amplifier, the 723 voltage regulator, and the 565 phase locked loop. Although minor variances in the processing steps are common, the major differences are in device sizes and impurity concentrations and profiles. The discussion of a typical seven-mask bipolar process follows. The major process steps are outlined in Table 2C.1 of Appendix 2C. The construction of npn transistors, pnp transistors, resistors, and capacitors will be considered. The location of these components can be seen in the top view containing mask information shown in Fig. 2C.1a of Appendix 2C. ‘The starting point in this bipolar process is a clean, polished p-type silicon wafer. A layer of SiQ> is first grown over the wafer. Following application of a layer of photoresist, Mask #1 is used to pattern the n* buried layer. The n* buried layer serves the purpose of decreasing collector resistance and minimizing the parasitic current flow from collector to substrate in npn transistors. It also helps decrease the base resistance in lateral pnp transistors. Either a deposition or implant, followed by a drive in diffusion, can be used to introduce the n- type impurities into the substrate through the openings provided by Mask #1. A layer of oxide, which grows during the diffusion, is then stripped. After the n* diffusion the wafer takes the form shown in Fig. 2C.1b. ‘An n-type epitaxial (crystalline) layer is then grown over the entire wafer. ‘The thickness of this layer typically varies between 2 @ and 15 q, with the thinner layers used for digital circuits and the thicker layers for analog circuits. ‘This layer will be used for the collector region in npn transistors. The epitaxial66 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS layer is shown in Fig. 2C. 1c. Note that some of the impurities in the buried layer have migrated (or out-diffused) into the epitaxial layer during its growth. A thick layer of SiO» (typically 5000 A) is then grown over the entire surface. Mask #2 is used to pattern the SiO> layer for the p* isolation diffusion. SiO is etched from the areas not photographically protected by Mask #2 to allow for this drive in diffusion following a p* deposition. The p* isolation diffusion is used to electrically separate adjacent transistors. It is wide and deep since it must completely penetrate the epitaxial layer to provide the required isolation. The wafer at this stage is as shown in Fig. 2C.1d. Although the isolation diffusion is shown with vertical edges in the figure, lateral diffusion, typically comparable to the vertical diffusion, causes significant out-diffusion laterally under the oxide layer, thus making the top of the channel stop considerably wider than the bottom. Following this diffusion, another thick layer of SiO, is grown over the entire wafer. An optional shallow, high-resistance p-diffusion could be added at this step. This is not depicted in Fig. 2C.1 but is listed as an option in Table 2C.1. This step would provide a mechanism for making practical diffused resistors in the 1 kQ to 20 kO range. A typical sheet resistance of this region would be 1 k/0 to 2 kO/O . Mask #A in Table 2C.1 is used to pattern these regions. Mask #3 is used to pattern the SiO, layer and define the base regions for the npn transistors as well as the collector and emitter regions for lateral pnp devices. A p-type deposition and a subsequent drive in diffusion create these regions in the unprotected areas. This diffusion is much shallower than was the isolation diffusion and must not penetrate the epitaxial layer. The isolation mask openings provided by Mask #2 are typically reopened with Mask #3 to provide a few additional p-type impurities. The wafer at this stage is shown in Fig. 2C.le. Following growth of another layer of SiO, Mask #4 is used to pattern the emitter regions for the npn transistors. An n* deposition followed by a drive in diffusion creates the emitter regions. Openings are also made in the oxide above the collector to add small n* wells in the lightly doped collector region to provide for better electrical contact from the surface. The integrated circuit at this stage is as depicted in Fig. 2C.1f. The emitter diffusions must be shallow so as not to penetrate the relatively shallow p-type base regions already created. The amount and profile of the impurities in the n* emitter regions and the thickness of the p-type base region, which is now sandwiched between the n* emitter and the n- collector, strongly influence the gain of the transistor. Mask #5 is used to pattern contact openings to allow for top contact of the circuit with the metallization. The entire circuit is then covered with a thin layer of metal. Mask #6 is used to pattern the metal, followed by the addition of a passivation layer. The completed cross-sectional view of the four components under consideration is shown in Fig. 2C.1g. Mask #7 patterns pad openings to allow for electrical contact to the bonding pads. Two modifications of this process deserve mention. One involves adding a deep collector diffusion. This requires an additional masking step and is used to diffuse impurities under the area where the collector contacts are to be made. This step would occur either before or after the isolation diffusion and is used toTECHNOLOGY 67 extend n* impurities all the way from the surface to the buried layer. Since this is such a deep diffusion, an area penalty in the collector is experienced. The deep diffusion is used to reduce collector resistance in high-current applications. The second modification involves adding an additional p-diffusion in the p-channel stops. This also requires an additional mask step and is used to avoid surface inversion in high-voltage parts. With the exception of open collector circuits, this step is not common in basic logic parts. The npn and pnp transistors in this process are depicted in Fig. 2.2-9. The npn transistor is called a vertical npn device since the emitter, base, and collector regions are stacked vertically. It can now be seen that the n* buried layer decreases the collector resistance that must be modeled in series with the collector, The pnp transistor is called a lateral device since it is stacked laterally (horizontally). The base width cannot practically be made as narrow and the base area is not as accurately controllable as for the npn device. In addition, the emitter and collector regions must have the same impurity profile. The characteristics of the lateral transistors are generally considered poorer than those of the vertical devices. Other pnp transistors, not shown in Fig. 2C.1, can be constructed by using the p-type base diffusion as the emitter, the n-type epitaxial layer as the base, and the p-type substrate as the collector. These devices are called substrate transistors. The performance of these devices is also mediocre, and applications are restricted since all collectors of substrate transistors are common. The capacitor that was constructed in Fig. 2C.1 may at the outset appear to be merely a diode. It would serve the purpose of a diode, even though the area is considerably more than may be required in most applications. When reverse biased, however, the depletion layer forms the dielectric, and the p and n regions on either side form the capacitor plates. Capacitors made like this, with total collector base collector emitter emitter vertical lateral npn pnp transistor transistor FIGURE 2.2-9 Vertical and lateral transistors in a bipolar process.68 VLSI DESIGN TECHNIQUES FOR ANALOG AND DIGITAL CIRCUITS capacitances from the sub-picofarad to the 100 picofarad range, have proven practical. The capacitors are not without limitations, however. The requirement that the junction must always be reverse biased severely limits the interconnection flexibility of this device. The width of the depletion layer is voltage dependent, making the capacitance nonlinear. Temperature also affects the capacitance value. Finally, the base-emitter junction typically breaks down with a reverse bias of about 7 V, limiting the maximum voltage that can be applied to the capacitor. The base-collector junction can also be used as a capacitor. Its characteristics are very similar to the base-emitter capacitor with the exception that it offers an increased reverse breakdown at the expense of a lower capacitance density. Junction capacitors will be discussed in more detail in Chapter 3. An alternative to the junction capacitor would be a metal-oxide-semiconductor capacitor formed between the metal and the n* emitter diffusion. Although the characteristics of this capacitor would be better than those of the junction capacitors, an extra mask step is generally required to provide a means of selectively stripping the thick oxide above the emitter region so that a thin oxide can be regrown. The thin oxide is needed to get the capacitance density up to a practical level. The resistor of Fig. 2C.1 is actually just a serpentined strip of the lightly doped p-type base diffusion. The underlying n-type epitaxial layer is generally contacted and taken to the highest potential in the circuit to prevent current flow into this region. Several other techniques for fabricating resistors in this process are available. They will be discussed in Chapter 3. Although minimum feature sizes are comparable for the bipolar and MOS processes, standard bipolar processes require more area per device than do the NMOS processes. A major reason for this increased area is the deep and wide p* channel stops that are required for device isolation in standard bipolar processes. An alternative bipolar process using trench isolation”? is available which offers a significant improvement in component density over the standard bipolar process. 2.2.3 Hybrid Technology The hybrid approach to integrated circuit design involves attaching two or more integrated circuit dies (typically of different types), along with some discrete components in some cases, in a single package to form what is called a hybrid integrated circuit. It is often, and desirably, transparent to the consumer whether the circuit is monolithic or hybrid; in some cases, however, the hybrid packages are considerably larger. The hybrid integrated circuit is typically more costly than the monolithic structures. The extra cost and size of hybrid integrated circuits is offset, in some demanding applications, by improved performance capabilities. Hybrid circuits containing discrete components occupy considerably less area than the conventional PC board/discrete component approach. They have played a major role in demanding analog signal processing applications such as high-resolution A/D and D/A converters and precision active filters. Tolerances, temperature dependence, and area-induced component value limits for resistors and capacitors in standard MOS and bipolar processes have limited the development of monolithic integrated circuits for precision continuous-time signal processing. Thick film and thin film passive components have reasonable toler-TECHNOLOGY 69 ances, are easily trimmable, have acceptable temperature coefficients that can be tailored for tracking, and offer reasonable tradeoffs between area required and component values. These thick film and thin film networks are commonly used for the passive components in hybrid integrated circuits. A discussion of thick film and thin film processing technologies follows. THICK FILM CIRCUITS. The thick film technology is relatively old, requires considerable area compared to monolithic circuits, can be used for relatively high- power applications, and can be applied at relatively high frequencies (up to 1 GHz) although it is typically limited to a few MHz. The increased area required by the thick film circuits is offset by the reduced cost in equipment and processing materials required for the thick film process, the latter being a small fraction of that required for either bipolar or MOS processes. The components available in a thick film process are resistors and capacitors along with conducting interconnects. Layers of different material are successively screened onto an insulating substrate. These materials are used for resistors and conductors as well as for the dielectrics of capacitors. The number of resistive layers varies but practical limitations generally restrict this to at most three. Typical thickness of these layers (called pastes or inks) is about 20 j1, but they may vary considerably by design. The actual thickness of these layers is not accurately controllable (+ 30%) due to limitations in the screening process itself. The thick film process offers the most advantages for resistor fabrication. Although capacitors are often included, the electrical characteristics of thick film capacitors are not outstanding and the capacitance density is quite low. Discrete chip capacitors, which have much better characteristics than their thick film counterparts, are often bonded to thick film resistive networks in hybrid circuit applications. The minimum conductor width in a typical thick film process is about 250 #, and minimum resistor widths are about 1250 jz. It can be seen that these are orders of magnitude larger than the corresponding minimum feature sizes for the MOS and bipolar processes (1-5 1). Screening involves forcing the paste through small holes in a tightly stretched piece of fabric called a screen, typically constructed of stainless steel. The grid is quite regular. The spacing of the holes can be specified, but practical physical limitations relating to both the mechanical characteristics of the steel and the physical characteristics of the inks prevent the use of extremely fine meshes. Screens with a grid spacing ranging from 100 to 300 filaments/inch are typical. This spacing restricts thick film resolution to somewhere around 500 yz. Where paste is not desired, holes in the screen are plugged by a mask. A squeegee is used to force the ink through the unrestricted areas. Following screening, each layer is fired to harden it. Inks are available with sheet resistances that satisfy the equation 10/0 < Ro < 10 MQ/O (2.2-9) for fired layers 20 ys thick. This large latitude in ink characteristics allows for a wide range of resistor values. Since only one type of ink can be used for each

Vlsi Design Techniques For Analog and Digital Circuits PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Vlsi Design Techniques For Analog and Digital Circuits PDF

Uploaded by

Copyright:

Available Formats

You might also like