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DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered Flip-Flops
DM74LS373/DM74LS374
3-STATE Octal D-Type Transparent Latches and
Edge-Triggered Flip-Flops
General Description A buffered output control input can be used to place the eight
outputs in either a normal logic state (high or low logic levels)
These 8-bit registers feature totem-pole 3-STATE outputs or a high-impedance state. In the high-impedance state the
designed specifically for driving highly-capacitive or rela- outputs neither load nor drive the bus lines significantly.
tively low-impedance loads. The high-impedance state and
The output control does not affect the internal operation of
increased high-logic level drive provide these registers with
the latches or flip-flops. That is, the old data can be retained
the capability of being connected directly to and driving the
or new data can be entered even while the outputs are off.
bus lines in a bus-organized system without need for inter-
face or pull-up components. They are particularly attractive
for implementing buffer registers, I/O ports, bidirectional bus Features
drivers, and working registers. n Choice of 8 latches or 8 D-type flip-flops in a single
The eight latches of the DM54/74LS373 are transparent package
D-type latches meaning that while the enable (G) is high the n 3-STATE bus-driving outputs
Q outputs will follow the data (D) inputs. When the enable is n Full parallel-access for loading
taken low the output will be latched at the level of the data n Buffered control inputs
that was set up. n P-N-P inputs reduce D-C loading on data lines
The eight flip-flops of the DM54/74LS374 are edge-triggered
D-type flip flops. On the positive transition of the clock, the Q
outputs will be set to the logic states that were set up at the
D inputs.
Connection Diagrams
Dual-In-Line Packages
’LS373
DS006431-1
’LS374
DS006431-2
Function Tables
DM54/74LS373
Output Enable D Output
Control G
L H H H
L H L L
L L X Q0
H X X Z
H = High Level (Steady State), L = Low Level (Steady State), X = Don’t Care
↑ = Transition from low-to-high level, Z = High Impedance State
Q0 = The level of the output before steady-state input conditions were estab-
lished.
DM54/74LS374
Output Clock D Output
Control
L ↑ H H
L ↑ L L
L L X Q0
H X X Z
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Logic Diagrams
DM54/74LS334 DM54/74LS374
Transparent Latches Positive-Edge-Triggered Flip-Flops
DS006431-3 DS006431-4
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Absolute Maximum Ratings (Note 1) Operating Free Air Temperature Range
DM54LS −55˚C to +125˚C
Supply Voltage 7V
DM74LS 0˚C to +70˚C
Input Voltage 7V
Storage Temperature Range −65˚C to +150˚C
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’LS373 Electrical Characteristics (Continued)
over recommended operating free air temperature range (unless otherwise noted)
Symbol Parameter Conditions Min Typ Max Units
(Note 4)
ICC Supply Current VCC = Max, OC = 4.5V, 24 40 mA
Dn, Enable = GND
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Recommended Operating Conditions (Continued)
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’LS374 Switching Characteristics
at VCC = 5V and TA = 25˚C
RL = 667Ω
Symbol Parameter CL = 45 pF CL = 150 pF Units
Min Max Min Max
fMAX Maximum Clock Frequency 35 20 MHz
tPLH Propagation Delay Time 28 32 ns
Low to High Level Output
tPHL Propagation Delay Time 28 38 ns
High to Low Level Output
tPZH Output Enable Time 28 44 ns
to High Level Output
tPZL Output Enable Time 28 44 ns
to Low Level Output
tPHZ Output Disable Time 20 ns
from High Level Output (Note 11)
tPLZ Output Disable Time 25 ns
from Low Level Output (Note 11)
Note 9: All typicals are at VCC = 5V, TA = 25˚C.
Note 10: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 11: CL = 5 pF.
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Physical Dimensions inches (millimeters) unless otherwise noted
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
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DM74LS373/DM74LS374 3-STATE Octal D-Type Transparent Latches and Edge-Triggered
Flip-Flops
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.