Chapter 1 Exercise Solutions

1.1

There are 14 nodes in the circuit. Thus, there are 14×2 = 28 single stuck-at faults.

For multiple stuck-at fault, it has (2 + 1)14 − 1 = 4782968 multiple stuck-at faults.
For collapsed single stuck-at fault:

Number of collapsed faults = 2×(number of POs + number of fanout stems)

+ total number of gate (including inverter) inputs

− total number of inverters
Here number of POs = 1, number of fanout stems = 3, total number of gate inputs = 10, number of

inverter = 2. Therefore, the number of collapsed faults = 2×(1 + 3) + 10 − 2 = 16.

1.2
A feedback bridging fault will transforms a combinational circuit into a sequential one, as the
following figure shows:

1.3
To detect all single stuck-at faults of the n-input NAND, we need n+1test vectors. In fact, in order
to detect the s-a-1 fault at the inputs, the following patterns are needed:
n

VLSI Test Principles and Architectures Ch. 1 – Introduction – P. 1/2

 n
(01111……1), (10111……1), (11011……1), (11101……1), (11110……1), ……, (11111……0)

In addition, (1111……1) is required to detect the inputs s-a-0 faults and the output s-a-1 fault.

1.4
Four patterns are enough to exhaustively test each gate in the parity checker independent of n.
They are as follows.

(00┅0), (11┅1),(011┅1), and (100┅0).

1.5
k
1000
λ = ∑ λi , λi = 9
. Thus, λ = 10 × 500 = 5 × 10
−6 −4

i =1 10
1
= 2 × 10 = 2000 hours.
3
MTBF =
λ

1.6

t = T × (1 − System _ availability )
= 1× 365 × 24 × 60 × 60 × (1 − 99.999%) = 315.36sec

1.7
(1− 0.9)
Defect level = 1 − 0.5 = 1 − 0.933 = 6.7%

VLSI Test Principles and Architectures Ch. 1 – Introduction – P. 2/2