Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-1

LECTURE 180 – POWER SUPPLY REJECTION RATIO

(READING: GHLM – 434-439, AH – 286-293)
Objective
The objective of this presentation is:
1.) Illustrate the calculation of PSRR
2.) Examine the PSRR of the two-stage, Miller compensated op amp
Outline
• Definition of PSRR
• Calculation of PSRR for the two-stage op amp
• Conceptual reason for PSRR
• Summary

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-2

What is PSRR?
Vdd

V2 - VDD
Av(Vdd=0)
PSRR = Add(Vin=0) Vout
Vin V1 +
Vss VSS

How do you calculate PSRR? Fig.180-01

You could calculate Av and Add and divide, however

Vdd
V2

V2 - VDD Av(V1-V2)
Vout V1 Vout
V1 +
Vss VSS ±AddVdd

Fig. 180-02
Vout = AddVdd + Av(V1-V2) = AddVdd - AvVout → Vout(1+Av) = AddVdd
Vout Add Add 1
∴V = ≈
dd 1+Av Av PSRR+
= (Good for frequencies up to GB)

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-3

Positive PSRR of the Two-Stage Op Amp

Vdd

gm6(V1-Vdd)
1 I3 rds4 rds6
M6 VDD gm3 Cc
Cc rds1 rds2 I3
M3 M4 Vout
gm1V5 gm2V5 + +
Vdd

M1 M2 CI CII V1 CI CII rds7

Vdd - I3 gm1Vout rds5 Vout
gm3
M5 + V5 - - -
M7
VBias V5 ≈ 0
VSS gm6(V1-Vdd)
rds4 rds6
gm1Vout Cc
Vdd gds1Vdd
+ +
rds2 V1 CI CII Vout rds7
- -
Fig. 180-03 - -
The nodal equations are:
(gds1 + gds4)Vdd = (gds2 + gds4 + sCc + sCI)V1 − (gm1 + sCc)Vout
(gm6 + gds6)Vdd = (gm6 − sCc)V1 + (gds6 + gds7 + sCc + sCII)Vout
Using the generic notation the nodal equations are:
GIVdd = (GI + sCc + sCI)V1 − (gmI + sCc)Vout
(gmII + gds6)Vdd = (gmII − sCc)V1 + (GII + sCc + sCII)Vout
whereGI = gds1 + gds4 = gds2 + gds4, GII = gds6 + gds7, gmI = gm1 = gm2 and gmII = gm6
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-4

Positive PSRR of the Two-Stage Op Amp - Continued

Using Cramers rule to solve for the transfer function,Vout/Vdd, and inverting the transfer
function gives the following result.
Vdd s2[CcCI+CICII + CIICc]+ s[GI(Cc+CII) + GII(Cc+CI) + Cc(gmII − gmI)] + GIGII+gmIgmII
Vout = s[Cc(gmII+GI+gds6) + CI(gmII + gds6)] + GIgds6

We may solve for the approximate roots of numerator as

 sCc  s(CcCI+CICII+CcCII) 
Vdd gmIgmII gmI + 1  gmII Cc + 1
PSRR+ = Vout ≅  GIgds6   


  


sgmII C c 
 
 G g + 1
 I ds6 

where gmII > gmI and that all transconductances are larger than the channel
conductances.
 sCc  sCII   s   s
 


Vdd gmIgmII gmI + 1  g + 1 

 GIIAvo GB
+ 1  |p2|
+ 1
  mII    
+
∴ PSRR = V =Gg   sgmIICc  =  gds6  sGIIAvo 

out  I ds6 
 GIgds6 + 1   g
 ds6GB
+ 1


ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-5

Positive PSRR of the Two-Stage Op Amp - Continued

GIIAv0
gds6

|PSRR+(jω)| dB

0 ω
gds6GB GB |p2| Fig. 180-04
GIIAv0
At approximately the dominant pole, the PSRR falls off with a -20dB/decade slope and
degrades the higher frequency PSRR + of the two-stage op amp.
Using the values of Example 6.3-1 we get:
PSRR+(0) = 68.8dB, z1 = -5MHz, z2 = -15MHz and p1 = -906Hz

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-6

Concept of the PSRR+ for the Two-Stage Op Amp

Vdd

Vout
M6 VDD Vdd 1
Cc Vout RoutCc
M3 M4 Cc Vout 0dB ω

M1 M2 CI CII Vdd Rout

Other sources
of PSRR+
M5 besides Cc
M7
VBias
VSS
Fig. 180-05

1.) The M7 current sink causes VSG6 to act like a battery.

2.) Therefore, Vdd couples from the source to gate of M6.
3.) The path to the output is through any capacitance from gate to drain of M6.
Conclusion:
The Miller capacitor Cc couples the positive power supply ripple directly to the output.
Must reduce or eliminate Cc.
ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002
Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-7

Negative PSRR of the Two-Stage Op Amp withVBias Grounded

M6 VDD
Cc Vout
M3 M4

Cc
M1 M2 CI CII
+
RI CI CII RII Vout
M5 gmIVout gmIIV1 gm7Vss
M7 V -
VBias ss

VBias grounded VSS

Fig. 180-06

Nodal equations for VBias grounded:

0 = (GI + sCc+sCI)V1 - (gmI+sCc)Vo
gm7Vss = (gMII-sCc)V1 + (GII+sCc+sCII)Vo
Solving for Vout/Vss and inverting gives
Vss s2[CcCI+CICII+CIICc]+s[GI(Cc+CII)+GII(Cc+CI)+Cc(gmII −gmI)]+GIGII+gmIgmII
Vout = [s(Cc+CI)+GI]gm7

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-8

Negative PSRR of the Two-Stage Op Amp withVBias Grounded - Continued

Again using techniques described previously, we may solve for the approximate roots as
 sCc  s(CcCI+CICII+CcCII) 
Vss gmIgmII gmI + 1  gmII Cc + 1
PSRR- = Vout ≅  GIgm7   


   

s(C c+C I ) 
 
 
 GI + 1
This equation can be rewritten approximately as
 sCc   sCII   s   s 
 g + 1  g + 1 
 G A GB + 1 
 |p | +1

Vss gmIgmII  mI
    mII  
 II v0 
   2
PSRR- = Vout ≅  GIgm7   
 =


   sC c   g m7
  s g mI 



 G + 1
   
  +1 
 I   GB G I 
Comments:
PSRR- zeros = PSRR + zeros
DC gain ≈ Second-stage gain,
PSRR- pole ≈ (Second-stage gain) x (PSRR+ pole)
Assuming the values of Ex. 6.3-1 gives a gain of 23.7 dB and a pole -147 kHz. The dc
value of PSRR- is very poor for this case, however, this case can be avoided by correctly
implementing VBias which we consider next.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-9

Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS

M6 VDD
Cc Vout
M3 M4

M1 M2 CI CII Cgd7 rds7

Cc
Vss rds5
M5 + +
M7 V CI RI V1 gmIIV1 CII rds6 Vout
VBias ss
gmIVout
- -
VBias connected to VSS VSS
Fig. 180-07

If the value of VBias is independent of Vss, then the model shown results. The nodal
equations for this model are
0 = (GI + sCc + sCI)V1 - (gmI + sCc)Vout
and
(gds7 + sCgd7)Vss = (gmII - sCc)V1 + (GII + sCc + sCII + sCgd7)Vout
Again, solving for Vout/Vss and inverting gives
Vss s2[CcCI+CICII+CIICc+CICgd7+CcCgd7]+s[GI(Cc+CII+Cgd7)+GII(Cc+CI)+Cc(gmII−gmI)]+GIGII+gmIgmII
Vout = (sCgd7+gds7)(s(CI+Cc)+GI)

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-10

Negative PSRR of the Two-Stage Op Amp withVBias Connected to VSS - Continued

Assuming that gmII > gmI and solving for the approximate roots of both the numerator
and denominator gives
 sCc  s(CcCI+CICII+CcCII) 
Vss gmIgmII gmI + 1  gmII Cc + 1
PSRR- = Vout ≅  GIgds7   


   sCgd7   s(CI+C c) 



 g +1  G + 1 
 ds7   I 

This equation can be rewritten as

  s   s
 
 
 
+ 1
Vss GIIAv0 GB  |p2|  +1
PSRR- = V ≈  g  
out  ds7   sCgd7   sCc
 
  gds7 +1  GI + 1
  

Comments:
• DC gain has been increased by the ratio of GII to gds7
• Two poles instead of one, however the pole at -gds7/Cgd7 is large and can be ignored.
Using the values of Ex. 6.3-1 and assume that Cds7 = 10fF, gives,
PSRR-(0) = 76.7dB and Poles at -71.2kHz and -149MHz

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-11

Frequency Response of the Negative PSRR of the Two-Stage Op Amp with VBias

;;
Connected to VSS
GIIAv0

;;
gds7
Invalid

|PSRR-(jω)| dB
;;
region
of
analysis

;;
0
GI
Cc ;;
GB |p2|
ω
Fig. 180-08

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-12

Approximate Model for Negative PSRR with VBias Connected to Ground

M6 VDD iss
Cc Vout M5 or M7
M3 M4

VBias
M1 M2 CI CII Vss

M5 VSS
M7 V
VBias ss

VBias grounded VSS

Fig. 180-09

Vout
Path through the input stage is not important Vss
as long as the CMRR is high.
Path through the output stage: 20 to
vout ≈ issZout = gm7ZoutVss 40dB

Vout 

1 

∴ V = gm7Zout = gm7Rout sR C +1
ss  out out 
0dB 1 ω
RoutCout Fig.180-10

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-13

Approximate Model for Negative PSRR with VBias Connected to VSS

M6 VDD
Cc Vout
M3 M4
rds7
vout
M1 M2 CI CII
Vss Zout

M5 rds7
What is Zout? VBias M7 Vss Path through Cgd7
is negligible
Vt VBias connected to VSS VSS
Zout = I ⇒ Fig. 180-11
t
gmIVt 

 Cc CII+Cgd7 It
It = gmIIV1 = g GI+sCI+sCc
mII

+ rds6||rds7 +
GI+s(CI+Cc) CI RI V1 gmIIV1 Vout Vt
Thus, Zout = gmIgMII gmIVout
- -
Fig.180-12
∴
rds7
Vss 1+ Zout s(Cc+CI) + GI+gmIgmIIrds7 -GI
Vout = 1 = s(Cc+CI) + GI ⇒ Pole at C +C
c I

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-14

The two-stage op amp will never have good PSRR because of the Miller compensation.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002

Lecture 180 – Power Supply Rejection Ratio (2/16/02) Page 180-15

SUMMARY
• PSRR is a measure of the influence of power supply ripple on the op amp output
voltage
• PSRR can be calculated by putting the op amp in the unity-gain configuration with the
input shorted.
• The Miller compensation capacitor allows the power supply ripple at the output to be
large
• The two-stage op amp will never have good PSRR unless some modifications are made.

ECE 6412 - Analog Integrated Circuit Design - II © P.E. Allen - 2002