//Verilog code for D-Latch

module d_latch(D,E,Q);
input D,E;
output Q;
reg Q;

always @(D) begin

if(E) // This is equivalent to E==1
Q = D;
end
endmodule

//Testbench of D-latch
module d_latchtb();
reg D; reg E;
wire Q;
d_latch dind(D,E,Q);

//Clock generstion
initial begin
E=0;
forever
#5 E= ~E;
end

//Create Stimulus
initial begin
D=0;
repeat(10) begin
#1 D= ~D;
#2 D= ~D;
#3 D= ~D;
end
#5 $finish;
end

//monitor
always @(Q) begin
if(Q!=D)
fail();
else
pass(); //Inverilog function is task
end
task fail;
begin
$display($time, ".module dlatch fail. Q: %b, D: %b",Q,D);
end
endtask
task pass;
begin
$display($time, ".module dlatch pass. Q: %b, D: %b",Q,D);
end
endtask
endmodule