Lectures 6-10: Basic Computor Organization snd Design 4 Overview one BASIC COMPUTER ~ ORGANIZATION AND DESIGN + Instruction Codes + Computer Registers + Computer instructions + Timing and Controt + Instruction Cycle + Memory Reference Instructions + Input-Output and Interrupt += Complete Computer Description + Design of Basic Computer + Design of Accumulator LogicLectures 6-10: Basic computor Section 6-1 Oraanrmation and Destan 2 instruction codon ee a INSTRUCTION CODES + Program: A set of instructions that specify the operations, operands, and the sequence by which processing has to occur. + Instruction Cede: A group of bits that tell the computer to perform @ Speciiic operation (a sequence of micro-operation) >macro-operation - usually divided into operation code, operand address, addressing mode, etc. - basic addressing modes. immediate, Direct, Indirect SsenrySection 6-1 Lectures 6-10: Basic computor Organtzation and Design a INDIRECT ADDRESS Instruction Format ithe? [araso—asr Pra — aa ctive Address(EFA, EA) ‘The address, that can be directly used without modification to access an operand for a. computation-type Instruction, or as the target address for a branch-type instructionLectures 6-10: Section 6-2: na Desian 4 Registers COMPUTER REGISTERS Registers in the Basic Computer oz Memory z 7 ° List or BC Registers Hold memory eperanc Holae addres for memory Accumuator | Rrocennor regintar Program Gounter ‘Temporary RealsterLectures 6-10: Section 6-2: RegistersLectures 6-10: Baste computor Section 6-8: Organtzation and Design 6 ingtructions COMPUTER(BC) INSTRUCTIONS Basic Computer Instruction code format Memory-Reference Instructions(OP-code = 000 ~ 110)| (igsessst+ eames 1 egister-Reference Instruction=(OP-code = 111, 1 = 0} Input-Output Instructions (OP-code =111, 1 = 1) Coot aedLectures 6-10: Basic computor Section 6-8: Organtzation and Design 7 instructions BASIC COMPUTER INSTRUCTIONS Description AND memory word AE Load AC trom memory Store contont of AC into memory ranch unconditionally Clear AC. Increment AC ‘Skip next inate. positive Skip next instr. negative Skip next instr IFAC Ie zero Skip next Instr. If Ete zero Halt computer Input character to AG. ‘Output character trom AC Skip on input tag Interrupt on Interrupt ottLectures 6-10: Section 6-8: a instructions INSTRUCTION SET COMPLETENESS A computer should have a set of instructions ‘So that the user can construct machine language programs to evaluate any function that is known to be computabl Instruction Types Functional instructions Arithmetic, logic, and shift instructions - ADD, CMA, INC, CIR, CIL, AND, CLA Transfer Instructions - Data transfers between the main memory and the processor registers -LDA, STA Control Instructions - Pregram sequencing and control - BUN, BSA, ISZ Inpuvoutput Instructions = Input and output - INP, OUTLectures 6-10: Section 6-4 Basic computor Organtzation and Design 9 Timing ana contro! TIMING AND CONTROL, Control unit of basic computer J rorernent ar [—— aay Control unit implementation Hardwired implementation Microprogrammed ImplementationLectures 6-10: Basic computor Section 6-4 Oraanrmation and Destan 40 Timing ana controt TIMING SIGNALS - Generated by 4-bit sequence counter and 4x16 decoder = The SC can be incremented or cleared. -Example: To, 11. T2, 73. T4, TO, T1,. Assume: At time T4, SC Is cleared to 0 It decoder ‘output Ds is active. Dgt%: Se<-0Lectures 6-10: Basic computor Section 6-6: Oraanrmation and Destan a4 Inetruction Gyore INSTRUCTION CYCLE BC Instruction cycle [Fetch Decode [Indirect] Execut + Fetch and Decode To: AR «PG (S0S152-010, TO-1) (eosts2—194, 11-4 D7’ Decode IRM 214), AR €-IR(OAT}, | AIRS)Lectures 6-10: section 64 Basic computor jection 42 Inetruction Gyore Organtzation and Design DETERMINE THE TYPE ~ OF INSTRUCTION Decode Opsode im RET. Bie en MeO AD eet) AR <— MIAR] Nething Execute a register-reterence instr. Execute an input-output instr.Lectures 6-10: Basic Computer 13 Section 6-6: Organization and Design Instruction Cycle ee REGISTER REFERENCE INSTRUCTIONS ~ Register Reference Instructions are identified when -D=1,1=0 - Register Ref. Instr. Is specified in by ~ by, of IR Transferred to AR during T - Execution starts with timing signal T; Register Reference Instruction 04,2, 14 sc<0 CLA AC <0 CLE E<0 CMA AC <-AC CME E interrupt. The /O interface, Instead of the CPU, monitors the VO device. When the interface rounds that the 1/0 device Is ready for data transfer, it generates an interrupt request to the CPU Upon detecting an interrupt, the CPU stops momentarily the task It Is doing, branches to the service routine to process the data transter, and then returns to the task It was pertorming. = LEN (Interrupt-enable flip-flop) - ean be set and cleared by instructions - when cleared, the computer cannot be InterruptedLectures 6-10: Oraantzauon and Destan 2a Section 6-7: WO and Interrupt FLOWCHART FOR INTERRUPT CYCLE - The int and Save return address operation. - At the beginning of the next Instruction cycle, the Instruction that ts read from memory Is in address 1. - At memory adaress 1, the programmer must store ‘@ branch Instruction that sends the control to an Interrupt service routine - The Instruction that returns the control to the original Program Is “indirect BUN 0”Lectures 6-10: section 6 Basic computor ection 6-7 a 2a YO and Imerrupt Organtzation and Design REGISTER TRANSFER OPERATIONS ~ IN INTERRUPT CYCLE Register Transfer Statements for Interrupt Cycle INIEN (FGI + FGO)T:'T'T,” => T.'Ty'T2' (EN)(FGI+ FGO): R <1 = The fetch and decode phases of the Instruction cycle must be modified: Replace Ty, T;,T, with R'T,, R'T,, R'T, - The interrupt cycle : RT: AR <-0, TR<-PC RT: MAR] DR Add wath DR Aco7) = INPR Transfer from INPR Aes Ae Gomplement AG = shr AC, ACUS) < — AG = ahlAG, Acta) E Ac=0 AG= AG.Lectures 6-10: Section 6-10: Design of AG Logic CONTROL OF AC REGISTER Gate structures fer controlling the LD, INR, and CLR of AG Fegm ages 32 3gLectures 6-10: Baste Computor Section 6-10: Organtation and Deoran 35 besign of AC Logic ADDER AND LOGIC CIRCUIT One stage of Adder and Logic circuit (Output of oF in F | lL acorn “>I nce