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TMS320C2X User Guide PDF
TMS320C2X User Guide PDF
User's Guide
1604907-9761 revision C
January 1993
Running Title—Attribute Reference
Chapter 1
Introduction
The TMS32010, the first digital signal processor in the TMS320 family, was
introduced in 1982. Since that time, the TMS320 family has established itself
as the industry standard for digital signal processing. The powerful instruction
set, inherent flexibility, high-speed number-crunching capabilities, and innova-
tive architecture make these high-performance, cost-effective processors
ideal for many telecommunications, computer, commercial, industrial, and mil-
itary applications.
Note:
Throughout this document, TMS320C2x refers to the TMS320C25,
TMS320C25-33, TMS320C25-50, TMS320E25, TMS320C26, and
TMS320C28 unless stated otherwise. Where applicable, ROM includes the
on-chip EPROM of the TMS320E25.
1-1
General Description
1-2 Introduction
General Description
ÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
P
E
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
R TMS320C4x
F
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C40
O TMS320C3x TMS320C40-40
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
R
M TMS320C30
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
A TMS320C30-27
TMS320C30-40
N
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C31 TMS320C5x
C TMS320C31-27
E
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C31-40
TMS320C50
TMS320C31PQA
TMS320C51
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C53
TMS320C2x
M
I
ÇÇÇÇÇÇ
ÇÇÇÇÇÇ
TMS320C25
ÇÇÇÇÇÇ ÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
P TMS320E25
S TMS320C25-33
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C25-50
/ TMS320C26
M TMS320C1x
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C28
F
TMS320C10
L
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320C10-14/-25
O TMS320C14
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
P TMS320E14/P14
S TMS320C15/LC15
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320E15/P15
TMS320C15-25
ÇÇÇÇÇÇ
ÇÇÇÇÇÇÇÇÇÇÇ
TMS320E15-25
TMS320C16
TMS320C17/LC17
TMS320E17/P17
GENERATION
ÇÇ
ÇÇ
Fixed-Point Generations Floating-Point Generations
Plans for expansion of the TMS320 family include more spinoffs of the existing
generations as well as more powerful future generations of digital signal pro-
cessors.
The TMS320 family combines the high performance and specialized features
necessary in digital signal processing (DSP) applications with an extensive
program of development support, including hardware and software develop-
ment tools, product documentation, textbooks, newsletters, DSP design work-
shops, and a variety of application reports. See Appendix K for a discussion
of the wide range of development tools available.
1-3
General Description
1-4 Introduction
General Description
1-5
Key Features
- 32-bit ALU/accumulator
1-6 Introduction
Key Features
- Device packaging:
68-pin PGA (TMS320C25)
68-lead PLCC (TMS320C25, TMS320C26, and TMS320C28)
68-lead CER-QUAD (TMS320E25)
80-pin QFP (TMS320C28)
1-7
Typical Applications
1-8 Introduction
Typical Applications
1-9
1-10 Introduction
Running Title—Attribute Reference
Chapter 2
Conversion sockets that accept PLCC and CER-QUAD packages and have
a PGA footprint are commercially available. For more information, refer to Ap-
pendix D.
When using the XDS emulator, refer to subsection 6.1.3 for user target design
considerations.
The TMS320C26 is similar to the TMS320C25 except for its internal memory
configuration. This is discussed in Section 3.4 and in Appendix B.
Topics in this chapter include
Topic Page
2-1
TMS320C2x Pinouts
CLKR
CLKX
V CC
V CC
D10
D12
D13
D14
D15
D11
D8
D9
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
VSS 10 60 IACK
D7 11 59 MSC
D6 12 58 CLKOUT1
D5 13 57 CLKOUT2
D4 14 56 XF
D3 15 55 HOLDA
D2 16 54 DX
D1 17 53 FSX
D0 18 52 X2 CLKIN
SYNC 19 51 X1
INT0 20 50 BR
INT1 21 49 STRB
INT2 22 48 R/W
VCC 23 47 PS
DR 24 46 IS
FSR 25 45 DS
A0 26 44 VSS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
V CC
A11
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A12
A13
A14
A15
V SS
CLKOUT1
CLKOUT2
X2/CLKIN
HOLDA
STRB
MSC
VSS
FSX
R/W
DX
BR
DS
PS
XF
X1
IS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
IACK 1 64 WAKEUP
PDI 2 63 VSS
VCC 3 62 A15
VCC 4 61 A14
CLKX 5 60 A13
VSS 6 59 A12
ADVANCE INFORMATION
CLKR 7 58 VSS
RS 8 57 A11
READY 9 56 A10
HOLD 10 55 A9
BIO 11 54 A8
MP/MC 12 53 VCC
D15 13 52 VCC
VSS 14 51 A7
D14 15 50 A6
D13 16 49 VSS
VCC 17 48 A5
D12 18 47 A4
D11 19 46 A3
D10 20 45 A2
D0 21 44 A1
D6 22 43 PDACK
VSS 23 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 4042 VSS
VSS 24 41 A0
INT0
INT1
INT2
SYNC
FSR
D7
D6
D5
D4
D3
D2
VSS
D1
D0
VCC
DR
2-3
TMS320C2x Signal Descriptions
Multiprocessing Signals
BR G11/50 O Bus request signal. Asserted when the TMS320C2x requires ac-
cess to an external global data memory space. READY is as-
serted to the device when the bus is available and the global data
memory is available for the bus transaction.
HOLD A7/67 I Hold input. When this signal is asserted, the TMS320C2x places
the data, address, and control lines in the high-impedance state.
HOLDA E10/55 O Hold acknowledge signal. Indicates that the TMS320C2x has
gone into the hold mode and that an external processor may ac-
cess the local external memory of the TMS320C2x.
SYNC F2/19 I Synchronization input. Allows clock synchronization of two or
more TMS320C2xs. SYNC is an active-low signal and must be
asserted on the rising edge of CLKIN.
2-5
TMS320C2x Signal Descriptions
Supply/Oscillator Signals
CLKOUT1 C11/58 O Master clock output signal (CLKIN frequency/4). CLKOUT1 rises
at the beginning of quarter-phase 3 (Q3) and falls at the beginning
of quarter-phase 1 (Q1).
CLKOUT2 D10/57 O A second clock output signal. CLKOUT2 rises at the beginning of
quarter-phase 2 (Q2) and falls at the beginning of quarter-phase
4 (Q4).
VCC A10/61 I Four 5-V supply pins, tied together externally.
B10/62
H2/23
L6/35
VSS B1/10 I Three ground pins, tied together externally.
K11/44
L2/27
X1 G10/51 O Output pin from the internal oscillator for the crystal. If a crystal is
not used, this pin should be left unconnected.
X2/CLKIN F11/52 I Input pin to the internal oscillator from the crystal. If crystal is not
used, a clock may be input to the device on this pin
† Pin numbers apply to CER-QUAD as well as to PLCC.
‡ Input/Output/High-impedance state.
2-7
2-8 Pinouts and Signal Descriptions
Read This First
iii
How to Use This Manual
v
Style and Symbol Conventions / Information About Cautions
- Braces ( { and } ) indicate a list. The symbol | (read as or) separates items
within the list. Here’s an example of a list:
Unless the list is enclosed in square brackets, you must choose one item
from the list.
The information in a caution is provided for your protection. Please read each
caution carefully.
vii
Related Documentation From Texas Instruments
Speech:
Gray, A.H. and Markel, J.D., Linear Prediction of Speech. New York, NY:
Springer-Verlag, 1976.
Jayant, N.S. and Noll, Peter, Digital Coding of Waveforms. Englewood Cliffs,
NJ: Prentice-Hall, Inc., 1984.
Papamichalis, Panos, Practical Approaches to Speech Coding. Englewood
Cliffs, NJ: Prentice-Hall, Inc., 1987.
Rabiner, Lawrence R. and Schafer, R.W., Digital Processing of Speech
Signals. Englewood Cliffs, NJ: Prentice-Hall, Inc., 1978.
Image Processing:
Andrews, H.C. and Hunt, B.R., Digital Image Restoration. Englewood Cliffs,
NJ: Prentice-Hall, Inc., 1977.
Gonzales, Rafael C. and Wintz, Paul, Digital Image Processing. Reading, MA:
Addison-Wesley Publishing Company, Inc., 1977.
Pratt, William K., Digital Image Processing. New York, NY: John Wiley and
Sons, 1978.
Digital Control Theory:
Jacquot, R., Modern Digital Control Systems. New York, NY: Marcel Dekker,
Inc., 1981.
Katz, P., Digital Control Using Microprocessors. Englewood Cliffs, NJ:
Prentice-Hall, Inc., 1981.
Kuo, B.C., Digital Control Systems. New York, NY: Holt, Reinholt and Winston,
Inc., 1980.
Moroney, P., Issues in the Implementation of Digital Feedback Compensators.
Cambridge, MA: The MIT Press, 1983.
Phillips, C. and Nagle, H., Digital Control System Analysis and Design.
Englewood Cliffs, NJ: Prentice-Hall, Inc., 1984.
Trademarks
MS, and MS-DOS are trademarks of Microsoft Corp.
VAX, VMS, and Ultrix are trademarks of Digital Equipment Corp.
PC-DOS is a trademark of International Business Machines Corp.
Sun 3 is a trademark of Sun Microsystems, Inc.
UNIX is a registered trademark of UNIX Systems Laboratories.
XDS is a trademark of Texas Instruments Incorporated.
ix
x Read This First
Contents
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2
1.2 Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
1.3 Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
2 Pinouts and Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 TMS320C2x Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
2.2 TMS320C2x Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
3 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
3.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6
3.3 Internal Hardware Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3.4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.1 Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.2 Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12
3.4.3 TMS320C2x Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-15
3.4.4 TMS320C26 Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16
3.4.5 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.6 Auxiliary Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3.4.7 Memory Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
3.4.8 Memory-to-Memory Moves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27
3.5 Central Arithmetic Logic Unit (CALU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28
3.5.1 Scaling Shifter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.5.2 ALU and Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30
3.5.3 Multiplier, T and P Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32
3.6 System Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.6.1 Program Counter and Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35
3.6.2 Pipeline Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-37
3.6.3 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47
3.6.4 Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-49
3.6.5 Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-52
3.6.6 Repeat Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.6.7 Powerdown Modes (TMS320C25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-53
3.7 External Memory and I/O Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.7.1 Memory Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-54
3.7.2 Internal Clock Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
3.7.3 General-Purpose I/O Pins (BIO and XF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-56
xi
Contents
xiii
Contents
Figures
xv
Figures
xvii
Tables
Tables
1–1 TMS320C2x Processors Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
1–2 Typical Applications of the TMS320 Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
2–1 TMS320C2x Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
3–1 TMS320C2x Internal Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9
3–2 TMS320C25/26 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17
3–3 Memory-Mapped Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-22
3–4 PM Shift Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-33
3–5 Instruction Pipeline Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40
3–6 Status Register Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-50
3–7 Interrupt Locations and Priorities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-59
3–8 Serial Port Bits, Pins, and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-63
3–9 Global Data Memory Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-77
4–1 Indirect Addressing Arithmetic Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6
4–2 Bit Fields for Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
4–3 Instruction Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12
4–4 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14
5–1 Program Space and Time Requirements for µ-/A-Law Companding . . . . . . . . . . . . . . . . . 5-69
5–2 256-Tap Adaptive Filtering Memory Space and Time Requirements . . . . . . . . . . . . . . . . . 5-74
5–3 Bit-Reversal Algorithm for an 8-Point Radix-2 DIT FFT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-77
5–4 FFT Memory Space and Time Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-81
6–1 Timing Parameters of TBP38L165-35 Direct Interface to TMS320C25 . . . . . . . . . . . . . . . 6-15
6–2 Timing Parameters of TBP38L165-35 to TMS320C25 (Address Decoding) . . . . . . . . . . 6-19
6–3 Wait States Required for Memory/Peripheral Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-20
6–4 Timing Parameters of WS57C64F-12 Interface to TMS320C25 . . . . . . . . . . . . . . . . . . . . . 6-24
6–5 Timing Parameters of TMS27C64-20 Interface to TMS320C25 . . . . . . . . . . . . . . . . . . . . . 6-26
6–6 Timing Parameters of CY7C169-25 Interface to TMS320C25 . . . . . . . . . . . . . . . . . . . . . . 6-27
E–1 TMS320C2x Instructions by Cycle Class . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
E–2 Cycle Timings for Cycle Classes When Not in Repeat Mode . . . . . . . . . . . . . . . . . . . . . . . . E-3
E–3 Cycle Timings for Cycle Classes When in Repeat Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-5
F–1 Pin Nomenclature (TMS320E25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-5
F–2 TMS320E25 Programming Mode Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . F-6
F–3 TMS320E25 EPROM Protect and Protect Verify Mode Levels . . . . . . . . . . . . . . . . . . . . . . F-12
G–1 Data Converter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-4
G–2 Switched-Capacitor Filter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-4
G–3 Telecom Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-8
G–4 Switched-Capacitor Filter ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . G-8
xix
Examples
Examples
5–1 Processor Initialization (TMS320C25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3
5–2 Processor Initialization (TMS320C26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4
5–3 BIO–XF Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-7
5–4 RS232 Transfer Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12
5–5 TMS320C26BFNL Bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-17
5–6 Subroutines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-22
5–7 Software Stack Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-24
5–8 Clock Divider Using Timer (TMS320C25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-26
5–9 Instruction Repeating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-27
5–10 Computed GOTO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-28
5–11 Context Save (TMS320C25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-30
5–12 Context Restore (TMS320C25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-31
5–13 Interrupt Service Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-32
5–14 Moving External Data to Internal Data Memory With BLKD . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5–15 Moving Program Memory to Data Memory With BLKP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-33
5–16 Moving Program Memory to Data Memory With TBLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5–17 Moving Internal Data Memory to Program Memory With TBLW . . . . . . . . . . . . . . . . . . . . . 5-34
5–18 Moving Data From I/O Space Into Data Memory With IN . . . . . . . . . . . . . . . . . . . . . . . . . . 5-34
5–19 Moving Data From Data Memory to I/O Space With OUT . . . . . . . . . . . . . . . . . . . . . . . . . . 5-35
5–20 Configuring and Using On-Chip RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-37
5–21 Program Execution From On-Chip Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-39
5–22 Program Execution From On-Chip Memory (TMS320C26) . . . . . . . . . . . . . . . . . . . . . . . . . 5-41
5–23 Using BIT and BBZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5–24 Using BITT and BBNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-45
5–25 Bit-Reversed Carry Addition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
5–26 FFT Bit Reversals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-48
5–27 Using the AR0 Test Bit to Calculate the Square Root of a Long Integer . . . . . . . . . . . . . . 5-50
5–28 Using MACD for Moving Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-52
5–29 Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-53
5–30 Multiply-Accumulate Using the MAC Instruction (TMS320C25) . . . . . . . . . . . . . . . . . . . . . 5-54
5–31 Multiply-Accumulate Using the LTA-MPY Instruction Pair . . . . . . . . . . . . . . . . . . . . . . . . . . 5-54
5–32 Using SQRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-57
5–33 Divide 33 by 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-58
5–34 Using SUBC for Integer Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
5–35 Using SUBC for Fractional Division . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-59
5–36 Using NORM for Floating-Point Multiply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-61
xx Table of Contents
Examples
xxi
xxii Table of Contents
a
Chapter 3
Architecture
The TMS320C26 is similar to the TMS320C25 except for its internal memory
configuration. This is discussed in Section 3.4 and in Appendix B.
3-1
Architectural Overview
The large on-chip 4K-word masked ROM on the TMS320C25 can reduce the
cost of systems, thus providing for a true single-chip DSP solution (see
Figure 3–1). Programs of up to 4K words can be masked into the internal pro-
gram ROM. The remainder of the 64K-word program memory space is located
externally. Large programs can execute at full speed from this memory space.
Programs may also be downloaded from slow external memory to on-chip
RAM for full-speed operation.
The 4K-word on-chip EPROM on the TMS320E25 allows realtime code devel-
opment and modification for immediate evaluation of system performance.
Instructions can be executed from the EPROM at full speed. The EPROM is
equipped with a security mechanism allowing you to protect proprietary in-
formation. A programming adapter socket is available from Texas Instruments
that provides 68- to 28-pin conversion for programming with standard PROM
programmers. Refer to Appendix F for details.
3-2 Architecture
Architectural Overview
Multiplier
Serial
Interface
32-Bit ALU/ACC
Shifters
Address (16)
Timer
3-3
Architectural Overview
The TMS320C2x scaling shifter has a 16-bit input connected to the data bus
and a 32-bit output connected to the ALU. The scaling shifter produces a left-
shift of 0 to 16 bits on the input data, as programmed in the instruction. The
LSBs of the output are filled with zeros, and the MSBs may be either filled with
zeros or sign-extended, depending upon the state of the sign-extension mode
bit of status register ST1. Additional shift capabilities enable the processor to
perform numerical scaling, bit extraction, extended arithmetic, and overflow
prevention.
Up to eight levels of hardware stack are provided for saving the contents of the
program counter during interrupts and subroutine calls. Instructions are avail-
able for saving the device’s complete context. PUSH and POP instructions
permit a level of nesting restricted only by the amount of available RAM. The
interrupts used in these devices are maskable.
3-4 Architecture
Architectural Overview
3-5
Functional Block Diagram
The TMS320C2x architecture is built around two major buses: the program
bus and the data bus. The program bus carries the instruction code and im-
mediate operands from program memory. The data bus interconnects various
elements, such as the central arithmetic logic unit (CALU) and the auxiliary
register file, to the data RAM. Together, the program and data buses can carry
data from on-chip data RAM and internal or external program memory to the
multiplier in a single cycle for multiply/accumulate operations.
The TMS320C2x has a high degree of parallelism; for example, while the data
is being operated upon by the CALU, arithmetic operations may also be imple-
mented in the auxiliary register arithmetic unit (ARAU). Such parallelism re-
sults in a powerful set of arithmetic, logic, and bit-manipulation operations that
may all be performed in a single machine cycle.
LEGEND:
ACCH = Accumulator high IFR = Interrupt flag register PC = Program Counter
ACCL = Accumulator low IMR = Interrupt mask register PFC = Prefetch counter
ALU = Arithmetic logic unit IR = Instruction register RPTC = Repeat instruction counter
ARAU = Auxiliary register arithmetic unit MCS = Microcall stack GREG = Global memory allocation register
ARB = Auxiliary register pointer buffer QIR = Queue instruction register RSR = Serial port receive shift register
ARP = Auxiliary register pointer PR = Product register XSR = Serial port transmit shift register
DP = Data memory page pointer PRD = Period register for timer AR0-AR = Auxiliary registers
DRR = Serial port data receive register TIM = Timer ST0.ST = Status registers
DXR = Serial port data transmit register TR =Temporary register C = Carry bit
3-6 Architecture
Functional Block Diagram
CLKOUT1
CLKOUT2
X2/CLKIN
IS
DS
PS 16 16 16
X1
16
PFC(16) QIR(16)
R/W
STRB IR(16)
16
READY STO(16)
MUX
BR
Controller
16 ST1(16)
XF
HOLD 16 16 RPTC(8)
HOLDA IFR(6)
MCS(16) PC(16)
MSC
DR
BIO CLKR
RS FSR
IACK 12 16 16 DX
CLKX
Address Stack FSX
MP/MC 16 16 8
3 (8 x 16) RSR(16)
INT(2-0) Program
ROM/ XSR(16)
16 16 EPROM 16
DRR(16)
(4096 × 16)
MUX
A15-A0
16 DXR(16)
Instruction 16 TIM(16)
RBIT 16 PRD(16)
16
6 IMR(6)
16 16 8 GREG(8)
MUX
D15-D0 16 16
16
Program Bus
Data Bus
16
16 16 16 16 16
16 16
3 9
AR0(16) TR(16)
7 LSB
3 AR1(16) From IR MUX
ARP(3) AR2(16) DP(9) 16
Multiplier
AR3(16)
9 Shifter(0-16)
AR4(16)
3 AR5(16) PR(32)
AR6(16)
32 32
AR7(16) 16
ARB(3)
Shifter(–6, 0, 1, 4)
16
16 32
3 MUX
ARAU(16)
MUX
16 16
32
MUX MUX
32
16 16 ALU(32)
DATA/PROG 32
Block B2
(32 × 16) RAM (256 × 16)
Block B0 C ACCH(16) ACCL(16)
Data RAM
Block B1 32
16
(256 × 16)
MUX Shifter(0-7)†
16 16 16 16
Data Bus
3-7
Functional Block Diagram
CLKOUT1
CLKOUT2
X2/CLKIN
IS
DS
PS 16 16 16
X1
16
PFC(16) QIR(16)
R/W
STRB IR(16)
READY 16
STO(16)
BR MUX
Controller
16 ST1(16)
XF
HOLD 16 16 RPTC(8)
HOLDA IFR(6)
MSC MCS(16) PC(16)
DR
BIO CLKR
RS FSR
IACK 8 16 16 DX
CLKX
Address Stack FSX
16 16 8
(8 × 16)
MP/MC
3 RSR(16)
INT(2-0) Bootload
16 Program XSR(16)
16 ROM 16
DRR(16)
MUX
D15-D0 16 16
16
Program Bus
Data Bus
16
16 16 16 16 16
16 16
3 9
AR0(16) TR (16)
7 LSB
3 AR1(16) From IR MUX
ARP(3) AR2(16) DP(9) 16
Multiplier
AR3(16)
9 Shifter(0-16)
AR4(16)
3 AR5(16) PR(32)
AR6(16)
32 32
AR7(16) 16
ARB(3) 16
Shifter(–6, 0, 1, 4)
ARAU(16)
32
3 MUX
16
MUX
32
MUX MUX MUX MUX
16 16 16 16 ALU(32)
32 32
DATA DATA/PROG DATA/PROG DATA/PROG
RAM (32 × 16) RAM (512 × 16) RAM (512 × 16) RAM (512 × 16)
C ACCH(16) ACCL(16)
Block B2 Block B3 Block B1 Block B0
32
Data Bus
3-8 Architecture
Internal Hardware Summary
3-9
Internal Hardware Summary
Microcall Stack MCS (15–0) A single-word stack that temporarily stores the contents of the PFC
while the PFC is being used to address data memory with the block
move (BLKD/BLKP), multiply-accumulate (MAC/MACD), and table
read/write (TBLR/TBLW)and table read/write (TBLR/TBLW) instruction
Multiplier MULT A 16 × 16-bit parallel multiplier.
Period Register PRD (15–0) A 16-bit memory-mapped register used to reload the timer.
Prefetch Counter PFC (15–0) A 16-bit counter used to prefetch program instructions. The PFC con-
tains the address of the instruction currently being prefetched. It is up-
dated when a new prefetch is initiated. The PFC is also used to address
program memory when using the block move (BLKP), multiply-accu-
mulate (MAC/MACD), and table read/write (TBLR/TBLW) instructions
and to address data memory when using the block move (BLKD)
instruction.
Product Register PR(31–0) A 32-bit product register used to hold the multiplier product. The PR can
also be accessed as the most or least significant words by using the
SPH/SPL (store P register high/low) instructions.
Program Bus P(15–0) A 16-bit bus used to route instructions (and data for the MAC and MACD
instructions).
Program Counter PC (15–0) A 16-bit program counter used to address program memory. The PC
always contains the address of the next instruction to be executed. The
PC contents are updated following each instruction decode operation.
Program Memory Address PAB(15–0) A 16-bit bus that carries the program memory address.
Bus
Queue Instruction Register QIR(15–0) A 16-bit register used to store prefetched instructions.
Random Access Memory RAM (B0) A RAM block with 256 × 16 locations configured as either data or pro-
(data or program) gram memory. (512 × 16 for TMS320C26)
Random Access Memory RAM (B1) A data RAM block, organized as 256 × 16 locations. (512 × 16 can be
(data only) configured as program or data for TMS320C26)
Random Access Memory RAM (B2) A data RAM block, organized as 32 × 16 locations.
(data only)
Random Access Memory RAM (B3) A RAM block with 512 × 16 locations configured as either data or pro-
(data or program) (TMS320C26 only) gram memory (TMS320C26 only).
Read Only Memory ROM A ROM block, 4096 × 16 (256 × 16 for TMS320C26; 8192 × 16 for
TMS320C28).
Repeat Counter RPTC (7–0) An 8-bit counter to control the repeated execution of a single instruction.
Serial Port Data DRR(15–0) A 16-bit memory-mapped serial port data receive register. Only the
Receive Register eight LSBs are used in the byte mode.
Serial Port Data Transmit DXR(15–0) A 16-bit memory-mapped serial port data transmit register. Only the
Register eight LSBs are used in the byte mode.
3-10 Architecture
Internal Hardware Summary
3-11
Memory Organization
In the TMS320C26, of the 1568 words, 32 words (block B2) are always data
memory, and all other words are programmable as either data or program
memory, as shown in Figure 3–5. A data memory size of 1568 words allows
the TMS320C26 to handle a data array of 1536 words, while still leaving 32
locations for intermediate storage. When using B0, B1, or B3 as program
memory, instructions can be downloaded from external program memory into
on-chip RAM, and then executed.
The TMS320C2x can address a total of 64K words of data memory. The on-
chip data memory and internally reserved locations are mapped into the lower
1K words of the data memory space. Data memory is directly expandable up
to 64K words while still maintaining full-speed operation. A READY line is pro-
vided for interface to slower, less expensive memories, such as DRAMs.
3-12 Architecture
Memory Organization
16 16 16
MUX MUX
16 16
Block B2
(32 × 16)
Data RAM Data/Prog
Block B1 RAM (256 × 16)
(256 × 16) Block B0
16
16 MUX
16
16 To Program Bus
3-13
Memory Organization
MUX
16 16 16 16
16
16 16 16 16 To Program Bus
Data Bus
In another mapping technique, the XF (external flag) pin is used to toggle the
MP/MC pin by dynamically enabling or disabling the on-chip ROM. Note that
care must be taken and the instruction pipeline operation (see subsection
3.6.2) must be understood when using this method.
3-14 Architecture
Memory Organization
The on-chip memory blocks (B0, B1, and B2) consist of a total of 544 words
of RAM. Program/data RAM block B0 (256 words) resides in pages 4 and 5
of the data memory map when configured as data RAM and at addresses
0FF00h to 0FFFFh when configured as program RAM. Block B1 (always data
RAM) resides in pages 6 and 7, while block B2 resides in the upper 32 words
of page 0. Note that the remainder of page 0 is composed of the memory-
mapped registers and internally reserved locations, and pages 1–3 of the data
memory map consist of internally reserved locations. The internally reserved
locations may not be used for storage, and their contents are undefined when
read. See subsection 3.4.4 for further information on the memory-mapped reg-
isters.
The on-chip RAM is mapped into either the 64K-word data memory or program
memory space, depending on the memory configuration (see Figure 3–5).
The CNFD/CNFP instructions are used to configure block B0 as either data
or program memory, respectively. The BLKP (block move from program
memory to data memory) instruction may be used to download program in-
formation to block B0 when it is configured as data RAM. Then a CNFP (config-
ure block as program memory) instruction may be used to convert it to program
RAM (see the code example in subsection 5.4.2). Regardless of the configura-
tion, you may still execute from external program memory. Note that when
accessing internal program memory, external control lines remain inactive.
Reset configures all internal RAM as data. Note that, due to internal pipelining,
when the CNFD or CNFP instruction is used to remap RAM block B0, there is
a delay before the new configuration becomes effective. This delay is one fetch
cycle if execution is from internal program RAM. On the TMS320C2x, there is
a delay of two fetch cycles if execution is from ROM or external program
memory. This is particularly important if program execution is from the loca-
tions around 0FF00h. Accordingly, a CNFP instruction must be placed at loca-
tion 0FEFDh in external memory if execution is to continue from the first loca-
tion in block B0. If a CNFP is placed at location 0FEFDh, and the instruction
at location 0FEFFh is a two-word instruction, the second word of the instruction
will be fetched from the first location in block B0. If execution is from above
location 0FF00h and block B0 is reconfigured, care must be taken to assure
that execution resumes at the appropriate point in a new configuration.
3-15
Memory Organization
The on-chip program ROM can be mapped into the lower 4K words of program
memory. This ROM is enabled when MP/MC is set to a logic low. To disable
the on-chip ROM and use these lower addresses externally, MP/MC must be
set to a logic high. If all internal RAM blocks are configured as data memory,
a program address in the range FF00 to FFFFh accesses external program
memory.
The external data memory, selected with DS (Data Select), always starts at
address 800h (2048 decimal), regardless of the configuration mode of the in-
ternal memory.
Because internal memory blocks B0, B1, and B3 (new) are of different size,
the internal data memory blocks of the TMS320C26 reside in pages 0 and 4
to 15, while those of the TMS320C25 reside in, pages 0 and 4 to 7. Table 3–2
shows both processors and their internal memory locations. Program memory
is also affected by the different block sizes, and the results are given in
Table 3–2.
3-16 Architecture
Memory Organization
As shown in Table 3–2 along with Figure 3–6 and Figure 3–7, there is no
difference between the TMS320C25/26 data spaces except for the location of
memory blocks; therefore, no data memory modification is necessary.
However for an internal program (such as relocatable code), the start and stop
addresses of each RAM block must be considered.
3-17
Memory Organization
B1
05FFh
0600h
07FFh
0800h
External
FFFF
External/ROM External/ROM
External
FBFF
FA00
B0
External
FBFF
FC00
B1 New Block
FDFF
FE00
FEFF
FF00 B3 New Block
B0
FFFF FFFF
3-18 Architecture
Memory Organization
If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode
on TMS320C25)
If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode
on TMS320C25)
3-19
Memory Organization
If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode)
If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode
3-20 Architecture
Memory Organization
If MP/MC = 1 If MP/MC = 0
(Microprocessor Mode) (Microcomputer Mode)
3-21
Memory Organization
The auxiliary registers may be used for indirect addressing of data memory or
for temporary data storage. Indirect auxiliary register addressing (see
Figure 4–2) allows placement of the data memory address of an instruction
operand into one of the auxiliary registers. These registers are pointed to by
a three-bit auxiliary register pointer (ARP) that is loaded with a value from 0
through 7, designating AR0 through AR7, respectively. The auxiliary registers
and the ARP may be loaded either from data memory or by an immediate oper-
and defined in the instruction. The contents of these registers may also be
stored in data memory. (Chapter 4 describes the programming of the indirect
addressing mode.)
3-22 Architecture
Memory Organization
AR4 1 0 3 B h 0FFFFh
AR5 2 6 B 1 h
AR6 0 0 0 8 h
AR7 8 4 3 D h
3-23
Memory Organization
MUX 3
16 In B Out In A
Auxiliary Register Arithmetic 3
Unit (ARAU) (16)
3 LSB
Auxiliary Register File Bus (AFB) 16 3 or IR
3 MSB 3 MSB
Data Bus (16)
16
As shown in Figure 3–11, auxiliary register 0 (AR0) or the eight LSBs of the
instruction registers can be connected to one of the inputs of the ARAU. The
other input is fed by the current AR (being pointed to by ARP). AR(ARP) refers
to the contents of the current AR pointed to by ARP. The ARAU performs the
following functions:
3-24 Architecture
Memory Organization
Although the ARAU is useful for address manipulation in parallel with other op-
erations, it may also serve as an additional general-purpose arithmetic unit,
since the auxiliary register file can directly communicate with data memory.
The ARAU implements 16-bit unsigned arithmetic, whereas the CALU imple-
ments 32-bit 2s-complement arithmetic. Instructions provide branches depen-
dent on the comparison of the auxiliary register pointed to by ARP with AR0.
The BANZ instruction permits the auxiliary registers to be used also as loop
counters.
The three-bit auxiliary register pointer buffer (ARB), shown in Figure 3–8, pro-
vides storage for the ARP on subroutine calls and interrupts.
The 16-bit data address bus (DAB) addresses data memory in one of the fol-
lowing two ways:
1) By the direct address bus (DRB) using the direct addressing mode (for
example, ADD 10h), or
2) By the auxiliary register file bus (AFB) using the indirect addressing mode
(for example, ADD *).
Operands are also addressed by the contents of the program counter in the
immediate addressing mode.
Figure 3–12 illustrates operand addressing in the direct, indirect, and immedi-
ate addressing modes.
3-25
Memory Organization
Instruction
Direct Addressing Opcode dma
DP
9
7 16
Operand
Instruction
Indirect Addressing Opcode ARP
3 16
AR (ARP) Operand
Instruction
Immediate Operand Opcode Operand
PC Instruction
or
PC+1 Operand
In the direct addressing mode, the 9-bit data memory page pointer (DP) points
to one of 512 pages, each page consisting of 128 words. The data memory
address (dma), specified by the seven LSBs of the instruction, points to the
desired word within the page. The address on the direct address bus (DRB)
is formed by concatenating the 9-bit DP with the 7-bit dma.
In the indirect addressing mode, the currently selected 16-bit auxiliary register
AR(ARP) addresses the data memory through the auxiliary register file bus
(AFB). While the selected auxiliary register provides the data memory address
and the data is being manipulated by the CALU, the contents of the auxiliary
register may be manipulated through the ARAU. See Figure 3–12 for an ex-
ample of indirect auxiliary register addressing. The direct and indirect addres-
sing modes are described in detail in Section 4.1.
3-26 Architecture
Memory Organization
The BLKD instruction moves a block within data memory, and the BLKP
instruction moves a block from program memory to data memory. When used
with the repeat instructions (RPT/RPTK), the BLKD/BLKP instructions effi-
ciently perform block moves from on- or off-chip memory.
3-27
Central Arithmetic Logic Unit (CALU)
2) Data is passed through the scaling shifter and the ALU where the arithme-
tic is performed, and
One input to the ALU is always provided from the accumulator, and the other
input may be transferred from the product register (PR) of the multiplier or from
the scaling shifter that is loaded from data memory.
3-28 Architecture
Central Arithmetic Logic Unit (CALU)
Program Bus
16 16
Data Bus
16
16 MUX
16
TR(16)
16 16
SX or 0 Shifter 0 Multiplier
(0-16)
PR(32)
SX Shifter(–6, 0, 1, 4) 0
MUX
32 32
MUX
32 32
SX A B
32 or 0 ALU(32)
16
C ACCH(16) ACCL(16) 0
32
SFL(0-7)
Data Bus 16 16
3-29
Central Arithmetic Logic Unit (CALU)
The TMS320C2x also contains several other shifters, which allow it to perform
numerical scaling, bit extraction, extended-precision arithmetic, and overflow
prevention. These shifters are connected to the output of the multiplier and the
accumulator.
The 32-bit accumulator (see Figure 3–13) is split into two 16-bit segments for
storage in data memory: ACCH (accumulator high) and ACCL (accumulator
low). Shifters at the output of the accumulator provide a left-shift of 0 to 7
places on the TMS320C2x. This shift is performed while the data is being
transferred to the data bus for storage. The contents of the accumulator re-
main unchanged. When the ACCH data is shifted left, the LSBs are transferred
from the ACCL, and the MSBs are lost. When ACCL is shifted left, the LSBs
are zero-filled, and the MSBs are lost.
3-30 Architecture
Central Arithmetic Logic Unit (CALU)
the exponent specified by the four low-order bits of the T register (TR). ADDT
and SUBT (add to/subtract from accumulator with shift specified by the T regis-
ter) instructions have also been provided to allow additional arithmetic opera-
tions.
The accumulator on the TMS320C25 also has an associated carry bit that is
set or reset, depending on various operations within the device. The carry bit
allows more efficient computation of extended-precision products and addi-
tions or subtractions. It is also useful in overflow management. The carry bit
is affected by most arithmetic instructions as well as the shift and rotate instruc-
tions. It is not affected by loading the accumulator, logical operations, or other
such nonarithmetic or control instructions. It is also not affected by the multiply
(MPY, MPYK, and MPYU) instructions, but is affected by the accumulation pro-
cess in the MAC and MACD instructions. Examples of carry bit operation are
shown in Figure 3–14.
X F F F F F F F F ACC X 0 0 0 0 0 0 0 0 ACC
+ 1 – 1
1 0 0 0 0 0 0 0 0 0 F F F F F F F F
X 7 F F F F F F F ACC X 8 0 0 0 0 0 0 0 ACC
+ 1 (OVM=0) – 1 (OVM=0)
0 8 0 0 0 0 0 0 0 1 7 F F F F F F F
1 0 0 0 0 0 0 0 0 ACC 0 F F F F F F F F ACC
+ 0 (ADD – 0 (SUBB
Instruction) Instruction)
0 0 0 0 0 0 0 0 1 1 F F F F F F F E
3-31
Central Arithmetic Logic Unit (CALU)
The value added to or subtracted from the accumulator, shown in the exam-
ples of Figure 3–14, may come from either the input scaling shifter or the shift-
er at the output of the P register. The carry bit is set if the result of an addition
or accumulation process generates a carry; it is reset to zero if the result of a
subtraction generates a borrow. Otherwise, it is reset after an addition or set
after a subtraction.
The ADDC (add to accumulator with carry) and SUBB (subtract from accumu-
lator with borrow) instructions provided on the TMS320C25 use the previous
value of carry in their addition/subtraction operation (see these instructions in
Chapter 4 for more detailed information).
The one exception to operation of the carry bit, as shown in Figure 3–14, is in
the use of the ADDH (add to high accumulator) and SUBH (subtract from high
accumulator) instructions. The ADDH instruction can set the carry bit only if
a carry is generated, and the SUBH instruction can reset the carry bit only if
a borrow is generated; otherwise, neither instruction can affect it.
Two branch instructions, BC and BNC, can execute branching on the status
of the carry bit. The SC, RC, and LST1 instructions can also be used to load
the carry bit. The carry bit is set to one on a hardware reset.
The SFL and SFR (in-place one-bit shift to the left/right) instructions on the
TMS320C2x and the ROL and ROR (rotate to the left/right) instructions on the
TMS320C25 implement shifting or rotating of the contents of the accumulator
through the carry bit. The SXM bit affects the definition of the SFR (shift accu-
mulator right) instruction. When SXM = 1, SFR performs an arithmetic right
shift, maintaining the sign of the accumulator data. When SXM = 0, SFR per-
forms a logical shift, shifting out the LSB and shifting in a zero for the MSB. The
SFL (shift accumulator left) instruction is not affected by the SXM bit and be-
haves the same in both cases, shifting out the MSB and shifting in a zero. Re-
peat (RPT or RPTK) instructions may be used with the shift and rotate instruc-
tions for multiple shift counts.
- A 16-bit temporary register (TR) that holds one of the operands for the
multiplier,
3-32 Architecture
Central Arithmetic Logic Unit (CALU)
The output of the product register can be left-shifted 1 or 4 bits. This is useful
for implementing fractional arithmetic or justifying fractional products. The out-
put of the PR can also be right-shifted 6 bits to enable the execution of up to
128 consecutive multiply/accumulates without the possibility of overflow.
Two multiply/accumulate instructions (MAC and MACD) fully utilize the com-
putational bandwidth of the multiplier, allowing both operands to be processed
simultaneously. The data for these operations may reside anywhere in internal
or external memory or can be transferred to the multiplier each cycle via the
program and data buses. This provides for single-cycle multiply/accumulates
when used with repeat (RPT/RPTK) instructions. Note that the DMOV portion
of the MACD instruction will not function with external data memory address-
es. On the TMS320C2x, the MAC and MACD instructions can be used with
both operands in either internal or external memory or one each in on-chip
RAM. The SQRA (square/add) and SQRS (square/subtract) instructions pass
the same value to both inputs of the multiplier for squaring a data memory val-
ue.
After the multiplication of two 16-bit numbers, the 32-bit product is loaded into
the PR on the TMS320C2x. The product from the PR may be transferred to
the ALU.
Four product shift modes (PM) are available at the PR output and are useful
when performing multiply/accumulate operations and fractional arithmetic, or
when justifying fractional products. The PM field of status register ST1 speci-
fies the PM shift mode, as shown in Table 3–4.
3-33
Central Arithmetic Logic Unit (CALU)
Left shifts specified by the PM value are useful for implementing fractional
arithmetic or justifying fractional products. For example, the product of either
two normalized, 16-bit, 2s-complement numbers or two Q15 numbers con-
tains two sign bits, one of which is redundant. Q15 format, one of the various
types of Q format, is a number representation commonly used when perform-
ing operations on noninteger numbers (see subsection 5.6.7 for an explana-
tion and examples of Q15 representation). The single-bit left shift eliminates
this extra sign bit from the product when it is transferred to the accumulator.
This results in the accumulator contents being formatted in the same manner
as the multiplicands. Similarly, the product of either a normalized, 16-bit, 2s-
complement or Q15 number and a 13-bit, 2s-complement constant contains
five sign bits, four of which are redundant. This is the case, for example, when
using the MPYK instruction. Here the four-bit shift properly aligns the result as
it is transferred to the accumulator.
The four least significant bits of the T register (TR) also define a variable shift
through the scaling shifter for the LACT/ADDT/SUBT (load/add-to/subtract-
from accumulator with shift specified by the TR) instructions. These instruc-
tions are useful in floating-point arithmetic where a number needs to be de-
normalized, that is, floating-point to fixed-point conversion. The BITT (bit test)
instruction allows testing of a single bit of a word in data memory based on the
value contained in the four LSBs of the TR.
3-34 Architecture
System Control
16 16
16
MCS PFC QIR
(16) (16) MUX (16)
16
16 16
PC (16)
IR
(16)
16 16
To Program
Address Bus
Stack 16
(8 × 16)
16
16
16
Data Bus
3-35
System Control
To start a new fetch cycle, the PC is loaded either with PC+1 or with a branch
address (for instructions such as branches, calls, or interrupts). In the case of
conditional branches where the branch is not taken, the PC is incremented
once more beyond the location of the branch address.
The TMS320C2x also has a feature that allows the execution of the next single
instruction N+1 times. N is defined by loading an 8-bit counter RPTC (repeat
counter). If this repeat feature is used, the instruction is executed, and the
RPTC is decremented until the RPTC goes to zero. This feature is useful with
many instructions, such as NORM (normalize contents of accumulator),
MACD (multiply and accumulate with data move), and SUBC (conditional sub-
tract). When used with some multicycle instructions, such as MACD, the re-
peat features can result in these instructions effectively executing in a single
cycle.
The stack is 16 bits wide and eight levels deep. The PC stack is accessible
through the use of the PUSH and POP instructions. Whenever the contents
of the PC are pushed onto the top of the stack, the previous contents of each
level are pushed down, and the bottom (eighth) location of the stack is lost.
Therefore, data will be lost if more than eight successive pushes occur before
a pop. The reverse happens on pop operations. Any pop after seven sequen-
tial pops yields the value at the bottom stack level. All of the stack levels then
contain the same value. Two additional instructions, PSHD and POPD, push
a data memory value onto the stack or pop a value from the stack to data
memory. These instructions allow a stack to be built in data memory for the
nesting of subroutines/interrupts beyond four/eight levels.
3-36 Architecture
System Control
The difference in pipeline levels does not necessarily affect instruction execu-
tion speed, but merely changes the fetch/decode sequence. Most instructions
execute in the same number of cycles, regardless of whether they are
executed from internal RAM, ROM, or external program memory. The effects
of pipelining are included in the instruction cycle timings for the TMS320C25
listed in Appendix D.
In the three-level pipeline on the TMS320C25, the PFC contains the address
of the next instruction to be prefetched. Once an instruction is prefetched, the
instruction is loaded into the IR, unless the IR still contains an instruction cur-
rently executing, in which case the prefetched instruction is stored in the QIR.
The PFC is then incremented, and after the current instruction has completed
execution, the instruction in the QIR is loaded into the IR to be executed.
The PC contains the address of the next instruction to be executed and is not
used directly in instruction fetch operations, but merely serves as a reference
pointer to the current position within the program. The PC is incremented as
each instruction is executed. When interrupts or subroutine call instructions
occur, the contents of the PC are pushed onto the stack to preserve return link-
age to the previous program context.
The prefetch, decode, and execute operations of the pipeline are independent,
thus allowing instruction executions to overlap. During any given cycle, three
different instructions can be active, each at a different stage of completion.
Figure 3–16 shows the operation of the three-level pipeline for single-word,
single-cycle instructions executing from either internal program ROM or exter-
nal memory with no wait states.
3-37
System Control
CLKOUT1
N N+1 N+2
prefetch
N-1 N N+1
decode
N-2 N-1 N
execute
CLKOUT1
N N+1 N+2
prefetch
N N+1 N+2
decode
N-1 N N+1
execute
3-38 Architecture
System Control
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Clock
CLKOUT1
CLKOUT2
STRB
AUXREG INST0 ARAU LOAD INST1 ARAU LOAD INST2 ARAU LOAD
RAMWR INST1
3-39
System Control
When using an add instruction (for example, ADD *+,12,AR4), the device
fetches the instruction in cycle 1. During Q2 and Q3 of cycle 2, the instruction
is decoded. This includes the ALU command decode as well as generation of
the data operand fetch address. In this case, the address comes from an auxil-
iary register. During Q4 of cycle 2 and Q1 of cycle 3, the operand is fetched
from the RAM location. The increment of the auxiliary register is performed
during Q3 and Q4 of cycle 2, and the value is loaded into the auxiliary register
in Q1 of cycle 3. The ARP is also updated in Q1 of cycle 3. During Q2 and Q3
of cycle 3, the data is passed through the barrel shifter to execute the 12-bit
left-shift, and the data is added by the ALU to the contents in the accumulator.
In Q4 of the third cycle, the ALU result is loaded into the accumulator. The sta-
tus of the ALU operation is loaded into the status register in Q1 of the fourth
cycle. The bits being loaded into the status register at this time consist of the
current ALU status and the ARP associated with the next instruction.
In the case of a store instruction (for example, SACL *0–,3,AR2), the device
operates the first two cycles in the same manner as the ADD instruction. In Q1
and Q2 of the third cycle, the data in the accumulator is passed through a barrel
shifter, left-shifted 3 bits, and zero-filled. The lower 16 bits of the shifted value
are written to the address specified by the current auxiliary register. During Q3
and Q4 of the third cycle, the index register (AR0) is added to the contents of
the current auxiliary register and loaded back into the current auxiliary register
in Q1 of the fourth phase. In Q1 of the fourth cycle, the auxiliary register pointer
is changed to AR2. There is no execution phase of this instruction. Figure 3–19
shows the ADD and SACL instructions operating back-to-back in a program
sequence. It is assumed that both instructions reside in external, zero wait-
state memory and that the data resides in on-chip RAM.
3-40 Architecture
System Control
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Clock
CLKOUT1
CLKOUT2
STRB
Data
When the device is reading instructions out of on-chip ROM, the basic internal
operation of the pipeline is the same. The only difference is that the control
lines (that is, STRB, PS, and R/W) are inactive. If the device is fetching the
instructions from on-chip RAM, the pipeline is shortened to 2.5 cycles, since
the device can fetch the instruction in half a cycle as opposed to the full cycle
required in an external or on-chip ROM fetch. The instruction is fetched during
Q4 and Q1, then decoded in Q2 and Q3. The rest of the pipeline tracks as de-
scribed above.
3-41
System Control
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Clock
CLKOUT1
CLKOUT2
STRB
Address ADD *+,12, AR4 Wait State SACL *0,3, AR2 Wait State OR *+
Data
Multiplexed External Data Bus. The external data bus is multiplexed to sup-
port all three memory spaces of the TMS320C25. Therefore, external fetches
to multiple spaces in the same instruction add additional machine cycles to the
pipeline execution of the instruction. This is due to the fact that the external
fetch takes a full cycle, whereas the internal equivalent takes two quarter
phases and can be included in the execution stage of the three-deep pipeline.
Accessing the data memory space is controlled by setting of the data page
pointer or the value contained in the auxiliary register used in any instruction.
Also affecting the pipeline is the access of the I/O bus or the tables in program
memory (that is, IN, OUT, TBLR, and TBLW). Figure 3–21 shows how the pipe-
line processes an instruction with external program and data access.
3-42 Architecture
System Control
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Clock
CLKOUT1
CLKOUT2
STRB
PS
DS
3-43
System Control
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Clock
CLKOUT1
CLKOUT2
STRB
Data
Status BV
Execute BV SUB
3-44 Architecture
System Control
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
Clock
CLKOUT1
CLKOUT2
STRB
Data
INTRAM RET
DATARAM ADD
Status
3-45
System Control
3-46 Architecture
System Control
memory to run in a single cycle. The normal operation of the instruction takes
only two quarter phases of the execution cycle to fetch the on-chip data
memory, whereas off-chip access requires all four quarter phases. The pipe-
line is, however, optimized to handle a repeated instruction that accesses ex-
ternal data memory with only one extra cycle for the first external fetch.
External Program/Data Access. Visibility of the pipeline when using external
program and data memory requires a monitoring of the MSC, STRB, PS, and
DS lines. The MSC line indicates at the rising edge of CLKOUT2 whether or
not the cycle is the beginning of a new instruction fetch; that is, MSC active low
indicates the completion of an instruction and the acquisition of another
instruction. The PS (program select) line indicates that the data bus is currently
being used to fetch an instruction. A step in the pipeline is not indicated, since
the PS line remains while the pipeline is fetching instructions externally. To
track the fetches, the STRB line, which frames external accesses, must be
monitored.
The PS line being active low does not necessarily mean that the device is
fetching an instruction. In the cases of table read/write (TBLR/TBLW), multiply/
accumulate (MAC/MACD), and block transfer (BLKP) instructions, the device
uses the PS line active low to access tables.
To monitor external data memory fetches, watch the data select (DS) line in
conjunction with the STRB line. An active low on the DS line indicates the data
bus is currently being used to access data memory space. This line remains
low for two memory fetches in the case of an accumulator store followed by
an ALU instruction, both operating with off-chip memory. However, two STRB
pulses will identify the individual access. Likewise, the line remains low for
many cycles in the case of a repeated instruction. I/O space access operates
similarily to data space operation with the OUT and IN instructions replacing
the save and ALU instruction.
A clear understanding of this information in conjunction with the data in Appen-
dix E should be sufficient to predict the operation of the TMS320C25 pipeline.
3.6.3 Reset
Reset (RS) is a nonmaskable external interrupt that can be used at any time
to put the TMS320C2x into a known state. Reset is typically applied after pow-
erup when the machine is in a random state.
Driving the RS signal low causes the TMS320C2x to terminate execution and
forces the program counter to zero. RS affects various registers and status
bits. At powerup, the state of the processor is undefined. For correct system
operation after powerup, a reset signal must be asserted low for at least three
clock cycles to guarantee a reset of the device (see Section 5.1 for other impor-
tant reset considerations). Processor execution begins at location 0, which
normally contains a B (branch) statement to direct program execution to the
system initialization routine (also see Section 5.1 for an initialization routine
example). Section 6.1 provides system control circuitry design examples.
3-47
System Control
1) RAM configuration bits are set so that all on-chip RAM resides in data
space.
2) The program counter (PC) is set to 0, and the address bus A15–A0 is driv-
en with all zeros while RS is low.
4) All memory and I/O space control signals (PS, DS, IS, R/W, STRB, and
BR) are deasserted by setting them to high levels while RS is low.
5) All interrupts are disabled by setting the INTM (interrupt mode) bit to 1.
(Note that RS is nonmaskable.) The interrupt flag register (IFR) is reset to
all zeros.
10) The TIM register is set to the maximum value (0FFFFh) on reset. Also, the
PRD register on the TMS320C25 is initialized by reset to 0FFFFh. (See
Example 5–1). The TIM register begins decrementing only after RS is
deasserted.
11) The IACK (interrupt acknowledge) signal is generated in the same manner
as a maskable interrupt.
13) The ARB, ARP, DP, IMR, OVM, and TC bits are not initialized by reset.
Therefore, it is critical that you initialize these bits in software following re-
set.
3-48 Architecture
System Control
Execution starts from location 0 of program memory when the RS signal is tak-
en high. Note that if RS is asserted while in the hold mode, normal reset opera-
tion occurs internally, but all buses and control lines remain in the high-imped-
ance state. Upon release of HOLD and RS, execution starts from location zero.
The TMS320C2x can be held in the reset state indefinitely.
Note:
Reset does not have internal Schmidt hysteresis. To insure proper reset op-
eration, avoid slow rise and fall times.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1 ARB CNF TC SXM C 1 1 HM FSM XF FO TXM PM
The status register ST1 of the TMS320C26 uses one of the unused bits and
the CNF bit of the TMS320C25 to define the four configuration modes as de-
scribed above. The bits are named CNF0 and CNF1 and can be set by the
instruction CONF const, where const is a number between 0 and 3. This two-
bit constant is loaded into the two status register bits CNF0 and CNF1.
Some additional instructions or functions may affect the status bits, as indi-
cated in Table 3–6.
The bits can also be modified by the LST1 instruction, and both are set to 0
by RESET. If TMS320C26 designs are started by using the TMS320C25 as a
base, consider defining the mask for loading the status register ST1 with the
instruction LST1 in such a way that the TMS320C26 is also configured as de-
sired.
3-49
System Control
Figure 3–25 shows the two status registers of the TMS320C26. All bits, be-
sides the redefined CNF0 (CNF in the TMS320C25) and the new CNF1 bit, are
unchanged.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST1: ARB CNF0 TC SXM C 1 CNF1 HM FSM XF FO TXM PM
3-50 Architecture
System Control
3-51
System Control
Data Bus
16
PRD (16)
16
16
Crystal
Divide by Clock (Load) Zero
or TIM (16)
External Four Detect
Clock
16
Tint
CLKOUT1
The TIM register is set to the maximum value (0FFFFh) on reset for the
TMS320C25. The PRD register on the TMS320C25 is also initialized by reset
to 0FFFFh. (See Example 5–1). The TIM register begins decrementing only
after RS is deasserted. Following this, the TIM and PRD registers may be re-
loaded under program control. See subsection 3.6.3 for reset information.
The TIM register, data memory location 2, holds the current count of the timer.
At every CLKOUT1 cycle the TIM register is decremented by one. The PRD
register, data memory location 3, holds the starting count for the timer. A timer
interrupt (TINT) is generated every time the timer decrements to zero. The tim-
er is reloaded with the value contained in the period (PRD) register within the
next cycle after it reaches zero so that interrupts can be programmed to occur
at regular intervals of (PRD + 1) cycles of CLKOUT1. This feature is useful for
control operations and for synchronously sampling or writing to peripherals.
By programming the PRD register from 1 to 65,535 (0FFFFh), a TINT can be
generated every 2 to 65,536 cycles on the TMS320C25. A PRD register value
of zero is not allowed.
The timer and period registers can be read from or written to on any cycle. The
count can be monitored by reading the TIM register. A new counter period can
be written to the period register without disturbing the current timer count. The
timer will then start the new period after the current count is complete. If both
the PRD and TIM registers are loaded with a new period, the timer begins
decrementing the new period without generating an interrupt. Thus, the pro-
grammer has complete control of the current and next periods of the timer.
3-52 Architecture
System Control
If the timer is not used, either TINT is to be masked or all maskable interrupts
are to be disabled by a DINT instruction. The PRD register can then be used
as a general-purpose data memory location. If TINT is used, the PRD and TIM
registers are to be programmed before unmasking the TINT.
3-53
External Memory and I/O Interface
- Data, program, and I/O space select (DS, PS, and IS) signals, and
The R/W (read/write) signal controls the direction of the transfer, and STRB
(strobe) provides a timing signal to control the transfer.
The TMS320C2x I/O space consists of 16 input and 16 output ports. These
ports provide the full 16-bit parallel I/O interface via the data bus on the device.
A single input or output operation, using the IN or OUT instructions, typically
takes two cycles; however, when used with the repeat counter, the operation
becomes single-cycle.
I/O design is simplified by having I/O treated the same way as memory. I/O de-
vices are mapped into the I/O address space using the processor’s external
address and data buses in the same manner as memory-mapped devices.
When addressing internal memory, the data bus must be in the high-imped-
ance state and the control signals go to an inactive state (logic high). Refer to
Chapter 5 for the effect instructions have on I/O.
Interfacing to memory and I/O devices of varying speeds is accomplished by
using the READY line. When communicating with slower devices, the
TMS320C2x processor waits until the other device completes its function,
signals the processor via the READY line, and continues execution
(see Chapter 6).
3-54 Architecture
External Memory and I/O Interface
Appendix E provides cycle timings for instructions, both when repeated and
when not repeated. The following is a summary of program execution, orga-
nized according to memory configuration.
PI/DI or PR/DI When both program and data memory are on-chip,
the processor runs at full speed with no wait states.
Note that IN and OUT instructions have different
cycle timings when program memory is internal; IN
requires two cycles to execute, whereas OUT re-
quires only one cycle.
PE/DI If external program memory is sufficiently fast, this
memory mode can run at full speed because internal
data operations can occur coincidentally with exter-
nal program memory accesses. If external program
memory is not fast enough, wait states may be gener-
ated by using the READY input.
PI/DE, PE/DE, or PR/DE
Additional cycles are required to execute instructions
that reference an external data memory space. At
least two cycles are required to execute read from ex-
ternal data memory instructions such as ADD, LAR,
etc. Further additional cycles may be required be-
cause of wait states if external data memory is not
fast enough to be accessed within a single cycle.
Note, however, that the TMS320C2x has the capabil-
ity of executing write to external data memory instruc-
tions in a single cycle when program memory is inter-
nal (two cycles are required if program memory is
also external). Additional cycles are also required in
this case if external data memory is not sufficiently
fast.
In all memory configurations where the same bus is used to communicate with
external data, program, or I/O space, the number of cycles required to execute
a particular instruction may further vary, depending on whether the next
instruction fetch is from internal or external program memory. Instruction
execution and operation of the pipeline are discussed in subsection 3.6.2 and
in the succeeding subsections.
3-55
External Memory and I/O Interface
Phase # Q3 Q4 Q1 Q2 Q3 Q4
CLKOUT1
CLKOUT2
Q1
Q2
Q3
Q4
The BIO pin is useful for monitoring peripheral device status. It is especially
useful as an alternative to using an interrupt when it is necessary not to disturb
time-critical loops. When the BIO input pin is active (low), execution of the
BIOZ instruction causes a branch to occur.
3-56 Architecture
External Memory and I/O Interface
In Figure 3–28, BIO is sampled at the end of Q4. The timing diagram shown
is for a sequence of single-cycle, single-word instructions without branches lo-
cated in external memory. Because of variations in pipelining due to instruc-
tions prior to and following the BIOZ instruction, this timing may vary. There-
fore, it is recommended that several cycles of setup be provided if BIO is to be
recognized on a particular cycle.
CLKOUT1
CLKOUT2
STRB
BIO Valid
The XF (external flag) output pin is set to a high level by the SXF (set external
flag) instruction and reset to a low level by the RXF (reset external flag) instruc-
tion. XF is set high by RS.
The relationship between the time the SXF/RXF instruction is fetched before
the XF pin is set or reset is shown in Figure 3–29. As with BIO, the timing
shown for XF is for a sequence of single-cycle, single-word instructions lo-
cated in external memory. Actual timing may vary with different instruction se-
quences.
3-57
External Memory and I/O Interface
CLKOUT1
STRB
(SXF or RXF)
N N+1 N+2 N+3
fetch
XF
(SXF)
XF
(RXF)
3-58 Architecture
Interrupts
3.8 Interrupts
When an interrupt occurs, it is stored in the 6-bit interrupt flag register (IFR).
This register is set by the external user interrupts INT(2–0) and the internal in-
terrupts RINT, XINT, and TINT. Each interrupt is stored in the IFR until it is rec-
ognized, and then automatically cleared by the IACK (interrupt acknowledge)
signal or the RS (reset) signal. The RS signal is not stored in the IFR. No
instructions are provided for reading from or writing to the IFR.
3-59
Interrupts
The INTM (interrupt mode) bit, which is bit 9 of status register ST0, enables
or disables all maskable interrupts. INTM = 0 enables all the unmasked inter-
rupts, and INTM = 1 disables these interrupts. The INTM is set to 1 by the IACK
(interrupt acknowledge) signal, the DINT instruction, or a reset. This bit is reset
to 0 by the EINT instruction. Note that the INTM does not actually modify the
IMR or IFR.
If both the HOLD line and an interrupt go active during a multicycle instruction
or a repeat loop, the HOLD takes control of the processor at the end of the
instruction or loop. When HOLD is released, the interrupt is acknowledged.
3-60 Architecture
Interrupts
IACK
IACK
RS
DINT
From
Q D Data
+5 V Bus
Interrupt
CLR
D Q Mask Interrupt
Register Mode S
Interrupt (INTM)
Edge Q
FF Idle
R
INT EINT
(0, 1, CLK IACK
or 2)
Priority
Decode To
D Q D Q PC
SYNC Interrupt
Interrupt
FF Flag
Processor
Register
Interrupt
Active Machine
CLK CLK State
Q2 Q1
Due to the level sensitivity of the external interrupts and the synchronization
of the interrupts (first on Q2, then on Q1 of the following machine cycle), the
INT line must be set to an inactive high at least two cycles before the enabling
interrupts (EINT). If this criteria is not met, the TMS320C25 will immediately
take the interrupt trap following the EINT plus the next instruction.
If the INTM bit and mask register have been properly enabled, the interrupt sig-
nal is accepted by the processor. An IACK (interrupt acknowledge) signal is
then generated. The IACK clears the appropriate interrupt edge flip-flop and
disables the INTM latch. The logic is the same for INT1 and INT2.
3-61
Interrupts
Figure 3–32 shows an interrupt, interrupt acknowledge, and various other sig-
nals for the special case of single-cycle instructions. An interrupt generated
during the current (N) fetch cycle still allows the fetch and execution of that
instruction. The N+1 and N+2 instructions are also fetched, then discarded,
and the address N+1 is pushed onto the top of the stack. The instruction is
fetched again upon a return command from the interrupt routine.
CLKOUT2
STRB
INT2–INT0
Three dummy execute cycles occur on an interrupt, as shown in the timing dia-
gram for the TMS320C25 (Figure 3–32). The IACK signal is asserted low dur-
ing CLKOUT1 low when the device initiates a fetch from the interrupt location
I. Note that IACK is a valid signal only when CLKOUT1 is low. An external de-
vice can determine which interrupt had occurred by latching the address bus
value present on A4–A1 with the rising edge of CLKOUT2 when IACK is low.
3-62 Architecture
Serial Port
A full-duplex on-chip serial port provides direct communication with serial de-
vices such as codecs, serial A/D converters, and other serial systems. The in-
terface signals are compatible with codecs and many other serial devices with
a minimum of external hardware. The serial port may also be used for inter-
communication between processors in multiprocessing applications.
The bits, pins, and registers that control serial port operation are listed in
Table 3–8. Availability of a function on a particular device is also indicated.
The serial port uses two memory-mapped registers: the data transmit register
(DXR) that holds the data to be transmitted by the serial port, and the data re-
ceive register (DRR) that holds the received data (see Figure 3–33). Both reg-
isters operate in either the 8-bit byte mode or 16-bit word mode, and may be
accessed in the same manner as any other data memory location. Each regis-
ter has an external clock, a framing synchronization pulse, and associated
shift registers. Any instruction accessing data memory can be used to read
from or write to these registers; however, the BLKD (block move from data
memory to data memory) instruction cannot be used to read these registers.
The DXR and DRR registers are mapped into locations 0 and 1 in the data ad-
dress space. The XSR and RSR registers are not directly accessible through
software.
3-63
Serial Port
0001h DXR
If the serial port is not being used, the DXR and DRR registers can be used
as general-purpose registers. In this case, the CLKR or FSR should be con-
nected to a logic low to prevent a possible receive operation from being initi-
ated.
Three bits in status register ST1 are used to control the serial port operation:
FO, TXM, and FSM. The FO (format) bit defines whether data to be transmitted
and received is an 8-bit byte or a 16-bit word. If FO = 0, the data is formatted
in 16-bit words. If FO = 1, the data is formatted in 8-bit bytes. In the 8-bit mode,
only the eight least significant bits are used for transmit/receive operations.
The FO bit is loaded by the FORT (format serial port registers) instruction. On
reset, FO is set to 0.
The TXM (transmit mode) bit is used to determine if the frame synchronization
pulse for the transmit operation is generated externally or internally. If TXM =
1, the FSX pin becomes an output pin, and a framing pulse is produced on the
FSX pin every time the DXR register is loaded. This framing pulse is synchro-
nized with the rising edge of CLKX. If TXM = 0, the FSX pin becomes an input
pin. The TMS320C2x then waits for an external synchronization pulse before
beginning transmission. On a reset, TXM is set to zero, configuring FSX to be
an input. The TXM bit can be loaded by the LST1, STXM, or RTXM instruc-
tions.
The FSM (frame synchronization mode) status register bit is used to determine
whether frame sync pulses are required for each serial port transfer. When
FSM = 1, frame sync pulses are required; consequently, they are not required
when FSM = 0. FSM is set by the SFSM (set frame synchronization mode)
instruction and cleared by the RFSM (reset frame synchronization mode)
instruction. When FSM = 1 and frame sync pulses are required, an FSX pulse
will cause the XSR to be loaded with data from the DXR, and transmission will
begin. If an FSX is presented prior to the last bit of the current transmission,
the XSR will be reloaded from the DXR, thus aborting the current transmission
and immediately beginning a new one.
The frame sync mode is useful in communicating to PCM highways. For ATT
T1 and CCITT G711/712 lines, the processor can communicate directly in
these formats by counting the transmitted/received bytes in software and per-
forming SFSM/RFSM instructions as needed to set/reset the FSM bit.
3-64 Architecture
Serial Port
Data Bus
16 16
Load
Control
(Load)
DRR (16) Logic DXR (16)
Load (Load)
16 Control 16
Logic
RSR (16) XSR (16)
(Carry) (Carry)
(Carry) (Carry)
Byte/Word Counter (Clear) (Clear) Byte/Word Counter
FSR FSX
DR RINT CLKR CLKX XINT DX
Data is clocked onto the DX pin from the XSR of the TMS320C25 by a CLKX
signal. Data is clocked into the RSR of the TMS320C25 from the DR pin by a
CLKR signal. CLKX and CLKR are required to be present only during actual
serial port transfers, and may be stopped (at a valid logic level) when no data
is being transferred. Data bits can be transferred in either 8-bit bytes or 16-bit
words. Data is clocked out to DX on the rising edges of CLKX, while data is
clocked in from DR on the falling edges of CLKR. The MSB of the data is trans-
ferred first.
The XSR and RSR are connected to the DXR and DRR, respectively. For
transmit operations, the contents of DXR are transferred to XSR when a new
transmission begins. For a receive operation, the contents of RSR are trans-
ferred to DRR when all of the bits have been received. Thus, the serial port is
double-buffered because data may be transferred to or from the DXR or DRR
while another transmit or receive operation is being performed.
Serial port transfers on the TMS320C25 are generally initiated by a frame sync
pulse. The exception to this is when the continuous mode of operation is used
with FSM = 0, as described in a subsequent paragraph. Frame sync pulses are
input on FSX for transmit operations and on FSR for receive operations.
3-65
Serial Port
The transmit timing diagram is shown in Figure 3–35. The transmit operation
begins when data is written into the data transmit register (DXR). The
TMS320C2x begins transmitting data when the frame synchronization pulse
(FSX) goes low while CLKX is high or going high. The data, starting with the
MSB, is then shifted out via the DX pin with the rising edge of CLKX. When all
bits have been transmitted, an internal transmit interrupt (XINT) is generated
on the rising edge of CLKX. When the serial port is not transmitting, DX is
placed in the high-impedance state.
CLKX
FSX
(TXM=1)
DX MSB LSB
8 or 16 Bits
XINT
DX and FSX are unaffected by assertion of the HOLD input. Upon assertion
of HOLD, any serial port transmission in progress on the DX pin is completed
before DX is placed in the high-impedance state. FSX remains configured as
either an input or output, remaining low if it is an output.
The receive operation is similar to the transmit operation. The receive timing
diagram is shown in Figure 3–36. Reception is initiated by a frame synchro-
nization pulse on the FSR pin. After FSR goes low, data on the DR pin is
clocked into the RSR register on the TMS320C25 on every negative-going
edge of CLKR. The first data bit is considered the MSB, and RSR is filled ac-
cordingly. After all the bits have been received (as specified by FO), an internal
receive interrupt (RINT) is generated on the rising edge of CLKR, and the con-
tents of RSR are transferred to DRR.
3-66 Architecture
Serial Port
CLKR
FSR
DR MSB LSB
8 or 16 Bits
RINT
Serial port transfers on the TMS320C25 are generally initiated by a frame sync
pulse, except when the continuous mode of operation is used with FSM = 0.
Frame sync pulses are input on FSX for transmit operations and on FSR for
receive operations. If FSM = 1, frame sync pulses are required; if FSM = 0, they
are not required. FSM is set by the SFSM (set frame synchronization mode)
instruction and cleared by the RFSM (reset frame synchronization mode)
instruction.
3-67
Serial Port
CLKX
FSX
(TXM=1)
DX
A1 A2 A3 A4 A5 A6 A7 A8 B1
(F0=1)
MSB LSB
XINT
DXR DXR
Loaded Reloaded
XSR
Loaded XSR
(During CLKX Low) Reloaded
CLKR
FSR
DR
A1 A2 A3 A4 A5 A6 A7 A8 B1
(F0=1)
MSB LSB
RINT
DRR
Loaded
From RSR
3-68 Architecture
Serial Port
When TXM = 1 (FSX is an output) and the serial port register DXR is loaded,
a framing pulse is generated on the next rising edge of CLKX. The XSR is
loaded with the current contents of DXR while FSX is high and CLKX is low.
Transmission begins when FSX goes low while CLKX is high or is going high.
Figure 3–37 shows the timing for the byte mode (FO = 1). XINT is generated
on the rising edge of CLKX after all 8 or 16 bits have been transmitted and DX
is placed in the high-impedance state. If DXR is reloaded before the next rising
edge of CLKX after XINT, FSX will again be generated as shown, and XSR will
be reloaded.
The receive operation is similar to the transmit operation. The contents of RSR
are loaded into DRR while CLKR is low, just after reception of the last bit sent
by the transmitting device (see Figure 3–38). RINT is generated on the next
rising edge of CLKR, and DRR may be read at any time before the reception
of the final bit of the next transmission. When operating in the byte mode, the
eight MSBs of the DRR are the contents of the eight LSBs of the DRR prior to
reception of the current byte, as shown in Figure 3–39 for the TMS320C25.
3-69
Serial Port
CLKX
FSX
(TXM=1)
DX
A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2
(F0=1)
MSB LSB
XINT
CLKR
FSR
DR
A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2
(F0=1)
MSB LSB
RINT
Read Read
DRR DRR
DRR DRR
Loaded Loaded
From RSR From RSR
3-70 Architecture
Serial Port
Figure 3–42 and Figure 3–43 show operation of the serial port for both states
of TXM to illustrate differences in operation for each case. FSM is initially set
to one, and frame sync pulses are required to initiate serial transfers. Before
the completion of the transmission (that is, before the next serial port interrupt),
the FSM must be reset to zero by means of an RFSM (reset FSM) instruction.
RFSM can occur either before or after the write to DXR or read from DRR.
From this point on, the FSX and FSR inputs are ignored, with transmission oc-
curring every CLKX cycle and reception occurring every CLKR cycle as long
as those clocks are present.
If FSX is configured as an output, it will remain low until FSM is set back to one
and DXR is reloaded. If DXR is not reloaded with new data every XINT (every
8 or 16 CLKX cycles, depending on FO), the last value loaded will be trans-
mitted on DX continuously. Note that this is different from the case with
FSM = 1 where DX is placed into a high-impedance state if DXR is not reloaded
before transmission of the last bit of the current word in XSR. For example, if
byte C is not loaded into DXR as indicated in Figure 3–42, bits of byte B
(B1–B8) will be retransmitted instead of bits of byte C as shown.
For receive operations, DRR is loaded from RSR (and an RINT is generated)
every 8 or 16 CLKR cycles (depending on FO), regardless of whether or not
DRR has been read. An overrun of DRR is also possible with FSM = 1 if DRR
is not read before the next RINT. The only way to stop continuous transmission
or reception once started, when FSM = 0, is either to stop CLKX or CLKR or
to perform an SFSM (set FSM) instruction.
3-71
Serial Port
CLKX
FSX
(TXM=1)
FSX
(TXM=0)
DX
(F0=1) A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2
MSB LSB
XINT
DXR RFSM
Loaded
With B
XSR DXR XSR
Loaded Loaded Loaded
From DXR With C
CLKR
FSR
DR
(F0=1) A7 A8 B1 B2 B3 B4 B5 B6 B7 B8 C1 C2
MSB LSB
RINT
Read RFSM
DRR
DRR Read DRR
Loaded DRR Loaded
From RSR From RSR
3-72 Architecture
Serial Port
As shown in Figure 3–44 and Figure 3–45, RFSM may occur before a write to
DXR, regardless of the state of TXM. If TXM = 1, FSX is generated in a normal
manner on the next rising edge of CLKX, but only once. If TXM = 0, the
TMS320C25 waits to transmit until FSX is pulsed, but from then on, the FSX
input is ignored. Note that just as in the case of continuous-mode operation
without sync pulses described in subsection 3.9.5, the first data written to DXR
(byte A) is output twice unless DXR is reloaded before the second transmis-
sion is started. It is important to consider this dummy cycle when using continu-
ous-mode serial operation.
The receive timings are the same as those for the transmit operations with
TXM = 0. The TMS320C25 waits to receive data until FSR is pulsed, but there-
after the FSR input is ignored. No dummy cycle is associated with the receive
operation; this is because DRR has a post-buffering nature as opposed to the
prebuffering nature of DXR.
3-73
Serial Port
CLKX
FSX
(TXM=1)
FSX
(TXM=0)
DX
(F0=1) A1 A2 A3 A4 A5 A6 A7 A8 A1 A2
MSB LSB
XINT
RFSM XSR
XSR
Loaded
Reloaded
DXR
Loaded
With A
CLKR
FSR
DR A1 A2 A3 A4 A5 A6 A7 A8 B1 B2
(F0=1)
MSB LSB
RINT
RFSM DRR
Loaded
From RSR
3-74 Architecture
Multiprocessing and Direct Memory Access (DMA)
3.10.1 Synchronization
In a multiprocessor environment, the SYNC input can be used to greatly ease
interface between processors. This input is used to cause each TMS320C2x
in the system to synchronize its internal clock, thereby allowing the processors
to run in lock-step operation.
The timing diagram for the SYNC input is shown in Figure 3–46 for the
TMS320C2x.
3-75
Multiprocessing and Direct Memory Access (DMA)
CLKIN
SYNC
CLKOUT1
CLKOUT2
1) The processor machine cycle is reset to Q1, provided that the timing re-
quirements for SYNC are met. If SYNC is asserted at the beginning of Q1,
Q3, or Q4, the current instruction is improperly executed. If SYNC is as-
serted at the beginning of Q2, the current instruction is executed properly.
Global memory is memory shared by more than one processor; therefore, ac-
cess to it must be arbitrated. When using global memory, the processor’s ad-
dress space is divided into local and global sections. The local section is used
by the processor to perform its individual function, and the global section is
used to communicate with other processors.
3-76 Architecture
Multiprocessing and Direct Memory Access (DMA)
The contents of GREG determine the size of the global memory space. The
legal values of GREG and corresponding global memory spaces are shown
in Table 3–9. Note that values other than those listed in the table lead to frag-
mented memory maps.
CLKOUT1
STRB
A15–A0 Valid
BR, DS
R/W Valid
READY
3-77
Multiprocessing and Direct Memory Access (DMA)
The timing for the HOLD and HOLDA signals is shown in Figure 3–48. HOLD
has the same setup time as READY and is sampled at the beginning of quar-
ter-phase 3. If the setup time is met, it takes three machine cycles before the
buses and control signals go to the high-impedance state. Note that unlike the
external interrupts (INT2 – INT0), HOLD is not a latched input. The external
device must keep HOLD low until it receives a HOLDA from the TMS320C2x.
After HOLD is deasserted, program execution resumes from the same point
at which it was halted. HOLDA is removed synchronously with HOLD, as
shown in Figure 3–48. If the setup time is met, two machine cycles are required
before the buses and control signals become valid.
HOLD is not treated as an interrupt. If the TMS320C2x was executing the IDLE
instruction before entering the hold state, it resumes executing IDLE once it
leaves the hold state.
The hold function on the TMS320C25 has two distinct operating modes:
3-78 Architecture
Multiprocessing and Direct Memory Access (DMA)
The operating mode is selected by the HM (hold mode) status register bit on
the TMS320C25. The HOLD signal is pulled low, as shown in the first part of
Figure 3–48. When HM = 1, the TMS320C25 halts program execution and en-
ters the hold state directly. When HM = 0, the processor enters the hold state
directly, as shown in Figure 3–48, if program execution is from external
memory or if external data memory is being accessed. If program execution
is from internal memory, however, and if no external data memory accesses
are required, the processor enters the hold state externally, but program
execution continues internally. This allows more efficient system operation be-
cause a program may continue executing while an external DMA operation is
being performed.
3-79
Multiprocessing and Direct Memory Access (DMA)
CLKOUT1
STRB
HOLD
PS, DS,
Valid Valid
or IS
R/W
D15–D0 IN IN
fetch N N+1 - -
N-2 N-1 N -
execute
HOLDA
3-80 Architecture
Multiprocessing and Direct Memory Access (DMA)
CLKOUT1
STRB
HOLD
PS, DS,
Valid Valid Valid
or IS
R/W
D15-D0 IN IN IN
- - - N+2 N+3 N+4
fetch
- - - N+1 Dummy N+2
execute
HOLDA
3-81
General Description of the TMS320C26
In many applications, the large internal memory of the TMS320C26 allows you
to build single-chip solutions with all data and programs internal and the option
to reload programs or algorithms. A memory size of 1568 words allows the
TMS320C26 to handle a data array of, for example, 1024 words with an on-
chip program RAM of 512 words and additional 32 words of data RAM. When
using internal blocks as program memory, instructions can be downloaded
from external program memory into on-chip RAM and then executed. The
TMS320C26 allows the DMOV function in all internal data memory blocks. An-
FIR filter programmed with the MAC or MACD instructions can use the internal
program RAM for storing the coefficients.
3-82 Architecture
General Description of the TMS320C28
3-83
3-84 Architecture
Running Title—Attribute Reference
Chapter 4
The TMS320C26 is similar to the TMS320C25 except for its internal memory
configuration. This is discussed in Section 3.4 and in Appendix B.
Topic Page
4-1
Memory Addressing Modes
Both direct and indirect addressing can be used to access data memory. Direct
addressing concatenates seven bits of the instruction word with the nine bits
of the data memory page pointer to form the 16-bit data memory address. Indi-
rect addressing accesses data memory through the auxiliary registers. In im-
mediate addressing, the data is based on a portion of the instruction word(s).
The following sections describe each addressing mode and give the opcode
formats and some examples for each mode.
Note:
The data page pointer is not initialized by reset and is therefore undefined
after powerup. The TMS320C2x development tools, however, utilize default
values for many parameters, including the data page pointer. Because of
this, programs that do not explicitly initialize the data page pointer may
execute improperly, depending on whether they are executed on a
TMS320C2x device or by using a development tool. Thus, it is critical that
all programs initialize the data page pointer in software.
DP (9)
7 7 LSBs From
Instruction
Register (IR)
16
Direct addressing can be used with all instructions except CALL, the branch
instructions, immediate operand instructions, and instructions with no oper-
ands. The direct addressing format is as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode 0 dma
Bits 15 through 8 contain the opcode. Bit 7 = 0 defines the addressing mode
as direct, and bits 6 through 0 contain the data memory address (dma).
0 0 0 0 0 1 0 1 0 0 0 0 1 0 0 1
The opcode of the ADD 9,5 instruction is 05h and appears in bits 15 through
8. The notation nnh indicates nn is a hexadecimal number. The shift count of
5h appears in bits 11 through 8 of the opcode. The data memory address 09h
appears in bits 6 through 0.
4-3
Memory Addressing Modes
The auxiliary registers (AR) provide flexible and powerful indirect addressing.
Eight auxiliary registers (AR0–AR7) are provided on the TMS320C2x. To se-
lect a specific auxiliary register, the auxiliary register pointer (ARP) is loaded
with a value from 0 through 7 designating AR0 through AR7 (see Figure 4–2).
3 3
Auxiliary
Registers
3
ARB (3) ARP (3) AR0 (16)
(ARP = 2) 3 AR1 (16)
AR2 (16)
AR3 (16)
AR4 (16)
AR5 (16)
AR6 (16) 16
AR7 (16)
16
16
ARAU (16) 16-Bit Data Address
The contents of the auxiliary registers may be operated upon by the auxiliary
register arithmetic unit (ARAU), which implements 16-bit unsigned arithmetic.
The ARAU performs auxiliary register arithmetic operations in the same cycle
as the execution of the instruction. (Note that the increment or decrement of
the indicated AR is always executed after the use of that AR in the instruction.)
In indirect addressing, any location in the 64K data memory space can be ac-
cessed via the 16-bit addresses contained in the auxiliary registers. These can
be loaded by the instructions LAR (load auxiliary register), LARK (load auxilia-
ry register immediate), and LRLK (load auxiliary register long immediate). The
auxiliary registers on the TMS320C2x can be modified by ADRK (add to auxil-
iary register short immediate) or SBRK (subtract from auxiliary register short
immediate). The TMS320C2x auxiliary registers can also be modified by the
MAR (modify auxiliary register) instruction or, equivalently, by the indirect ad-
dressing field of any instruction supporting indirect addressing. AR(ARP) de-
notes the auxiliary register selected by ARP.
In either case, the contents of the auxiliary register pointed to by the ARP regis-
ter are used as the address of the data memory operand. Then, the ARAU per-
forms the specified mathematical operation on the indicated auxiliary register.
Additionally, the ARP may be loaded with a new value. All indexing operations
are performed on the current auxiliary register in the same cycle as the original
instruction.
4-5
Memory Addressing Modes
sponding to one-half of the array size, and AR(ARP) be set to the base address
of the data (the first data point). See subsection 5.7.4 for an FFT example using
bit-reversed addressing modes.
Indirect addressing can be used with all instructions except immediate oper-
and instructions and instructions with no operands. The indirect addressing
format is as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bits 15 through 8 contain the opcode, and bit 7 = 1 defines the addressing
mode as indirect. Bits 6 through 0 contain the indirect addressing control bits.
Bits 5 and 4 control the arithmetic operation to be performed with AR(ARP) and
AR0. When set, bit 5 indicates that an increment is to be performed. If bit 4 is
set, a decrement is to be performed. Table 4–1 shows the correspondence of
bit pattern and arithmetic operation.
0 0 0 No operation on AR(ARP)
0 0 1 AR(ARP) – 1 → AR(ARP)
0 1 0 AR(ARP) + 1 → AR(ARP)
0 1 1 Reserved
1 0 0 AR(ARP) – AR0 → AR(ARP) [reverse carry propagation]
1 0 1 AR(ARP) – AR0 → AR(ARP)
1 1 0 AR(ARP) + AR0 → AR(ARP)
1 1 1 AR(ARP) + AR0 → AR(ARP) [reverse carry propagation]
Bit 3 and bits 2 through 0 control the auxiliary register pointer (ARP). Bit 3
(NAR) determines if a new value is loaded into the ARP. If bit 3 = 1, the contents
of bits 2 through 0 (Y = next ARP) are loaded into the ARP. If bit 3 = 0, the con-
tents of the ARP remain unchanged.
Table 4–2 shows the bit fields, notation, and operation used for indirect ad-
dressing. For some instructions, the notation in Table 4–2 includes a shift
code: for example, *0+,8,3 where 8 is the shift code and Y = 3.
The CMPR (compare auxiliary register with AR0), and BBZ/BBNZ (branch if
TC bit equal/not equal to zero) instructions facilitate conditional branches
based on comparisons between the contents of AR0 and the contents of
AR(ARP).
The auxiliary registers may also be used for temporary storage via the load and
store auxiliary register instructions, LAR and SAR, respectively.
4-7
Memory Addressing Modes
0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0
1 1 0 0 1 0 1 1 8-Bit Constant
For long immediate instructions, the constant is a 16-bit value in the word fol-
lowing the opcode. The 16-bit value can be optionally used as an absolute
constant or as a 2s-complement value.
ADLK Add to accumulator long immediate with shift (absolute or
2s complement)
ANDK AND immediate with accumulator with shift
LALK Load accumulator long immediate with shift (absolute or 2s
complement)
LRLK Load auxiliary register long immediate
ORK OR immediate with accumulator with shift
SBLK Subtract from accumulator long immediate with shift (ab-
solute or 2s complement)
XORK Exclusive-OR immediate with accumulator with shift.
4-9
Memory Addressing Modes
The ADLK instruction uses the word following the instruction opcode as the
immediate operand. The instruction format for ADLK is as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 Shift 0 0 0 0 0 0 1 0
16-Bit Constant
4-11
Instruction Set
- Control and I/O (RHM, SHM, RTC, STC, RFSM, and SFSM)
- Accumulator and register (SPH, SPL, ADDK, SUBK, ADRK, SBRK, ROL,
and ROR).
4-13
Instruction Set
4-15
Instruction Set
4-17
Individual Instruction Descriptions
Execution (PC) + 1 → PC
(ACC) + [(dma) × 2 shift ] → ACC
If SXM = 1:
Then (dma) is sign-extended.
If SXM = 0:
Then (dma) is not sign-extended.
4-19
EXAMPLE Example Instructions
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Opcode examples are shown of both direct and indirect addressing or of the
use of an immediate operand.
Description Instruction execution and its effect on the rest of the processor or memory con-
tents are described. Any constraints on the operands imposed by the proces-
sor or the assembler are discussed. The description parallels and supple-
ments the information given by the execution block.
Words 1
The digit specifies the number of memory words required to store the instruc-
tion and its extension words.
Cycles
The table shows the number of cycles required for a given TMS320C2x
instruction to execute in a given memory configuration when executed as a
single instruction or in the repeat mode. The column headings in the tables in-
dicate the program source location (PI, PE, or PR) and data destination or
source (DI or DE), defined as follows:
The number of cycles required for each instruction is given in terms of the pro-
gram/data memory and I/O access times as defined in the following listing:
p = 0; If Tmem ≤ Tac
d Data memory wait states. Represents the number of cycles the device
must wait for external data memory to respond to an access. This
number is calculated in the same way as the p number.
i I/O memory wait states. Represents the number of cycles the device
must wait for external I/O memory to respond to an access. This num-
ber is calculated in the same way as the p number.
Other abbreviations used in the tables and their meanings are as follows:
INT Interrupt.
4-21
EXAMPLE Example Instructions
C C
The sample code presented in the above format shows the effect of the code
on memory and/or registers. The use of the carry bit (C) provided on the
TMS320C25 is shown in the small box.
Operands None
Execution (PC) + 1 → PC
|(ACC)| → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 1
Description If the contents of the accumulator are greater than or equal to zero, the accu-
mulator is unchanged by the execution of ABS. If the contents of the accumula-
tor are less than zero, the accumulator is replaced by its 2s-complement value.
Note that 80000000h is a special case. When the overflow mode is not set, the
ABS of 80000000h is 80000000h. In the overflow mode, the ABS of
80000000h is 7FFFFFFFh. In either case, the OV status bit is set. The carry
bit (C) on the TMS320C2x is always reset to zero by the execution of this
instruction.
Words 1
Cycles
4-23
ABS Absolute Value of Accumulator
Example ABS
C C
ACC X 0FFFFFFFFh ACC 0 1h
C C
Execution (PC) + 1 → PC
(ACC) + [(dma) x 2 shift ] → ACC
If SXM = 1:
Then (dma) is sign-extended.
If SXM = 0:
Then (dma) is not sign-extended.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location are left- shifted and add-
ed to the accumulator. During shifting, low-order bits are zero-filled. High-order
bits are sign-extended if SXM = 1 and zero-filled if SXM = 0. The result is
stored in the accumulator.
Words 1
Cycles
4-25
ADD Add to Accumulator With Shift
C C
Execution (PC) + 1 → PC
(ACC) + (dma) + (C) → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location and the value of the carry
bit are added to the accumulator. The carry bit is then affected in the normal
manner.
Words 1
Cycles
C C
4-27
ADDC Add to Accumulator With Carry
C C
Execution (PC) + 1 → PC
(ACC) + [(dma) × 216] → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location are added to the upper
half of the accumulator (bits 31 through 16). Low-order bits are unaffected by
ADDH. The carry bit (C) on the TMS320C2x is set if the result of the addition
generates a carry; otherwise, C is unaffected. The carry bit can only be set, not
reset, by the ADDH instruction.
Words 1
Cycles
4-29
ADDH Add to High Accumulator
C C
Execution (PC) + 1 → PC
(ACC) + 8-bit positive constant → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 0 0 8-Bit constant
Description The 8-bit immediate value is added, right-justified, to the accumulator with the
result replacing the accumulator contents. The immediate value is treated as
an 8-bit positive number, regardless of the value of SXM.
Words 1
Cycles
Example ADDK 5h
C C
4-31
ADDS Add to Accumulator With Sign-Extension Suppressed
Execution (PC) + 1 → PC
(ACC) + (dma) → ACC
(dma) is a 16-bit unsigned number.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the specified data memory location are added with sign-exten-
sion suppressed. The data is treated as a 16-bit unsigned number, regardless
of SXM. The accumulator behaves as a signed number. Note that ADDS pro-
duces the same results as an ADD instruction with SXM = 0 and a shift count
of 0.
Words 1
Cycles
C C
4-33
ADDT Add to Accumulator With Shift Specified by T Register
Execution (PC) + 1 → PC
If SXM = 1:
Then (dma) is sign-extended.
If SXM = 0:
Then (dma) is not sign-extended.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The data memory value is left- shifted and added to the accumulator, with the
result replacing the accumulator contents. The left- shift is defined by the four
LSBs of the T register, resulting in shift options from 0 to 15 bits. Sign extension
on the data memory value is controlled by SXM.
Words 1
Cycles
T 0FF94h T 0FF94h
C C
4-35
ADLK Add to Accumulator Long Immediate With Shift
Execution (PC) + 2 → PC
(ACC) + [ constant x 2 shift ] → ACC
If SXM = 1:
Then –32768 ≤ constant ≤ 32767.
If SXM = 0:
Then 0 ≤ constant ≤ 65535.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 shift 0 0 0 0 0 00 1 0
16-Bit Constant
Description The 16-bit immediate value, left- shifted as specified, is added to the accumu-
lator. The result replaces the accumulator contents. SXM determines whether
the constant is treated as a signed 2s-complement number or as an unsigned
number. The shift count is optional and defaults to zero.
Words 2
Cycles
C C
Execution (PC) + 1 → PC
AR(ARP) + 8-bit positive constant → AR(ARP)
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The 8-bit immediate value is added, right-justified, to the currently selected
auxiliary register with the result replacing the auxiliary register contents. The
addition takes place in the ARAU, with the immediate value treated as an 8-bit
positive integer.
Words 1
Cycles
4-37
AND AND With Accumulator
Execution (PC) + 1 → PC
(ACC(15–0)) AND (dma) → ACC(15–0)
0 → ACC(31–16)
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The lower half of the accumulator is ANDed with the contents of the addressed
data memory location. The upper half of the accumulator is ANDed with all ze-
roes. Therefore, the upper half of the accumulator is always zeroed by the AND
instruction.
Words 1
Cycles
C C
4-39
ANDK AND Immediate With Accumulator With Shift
Execution (PC) + 2 → PC
(ACC(30–0)) AND [( constant × 2 shift )] → ACC(30–0)
0 → ACC(31) and all other bit positions unoccupied by shifted constant.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direct: 1 1 0 1 shift 0 0 0 0 0 10 0 0
Description The 16-bit immediate constant is left-shifted as specified and ANDed with the
accumulator. The result is left in the accumulator. Low-order bits below and
high-order bits above the shifted value are treated as zeros, clearing the corre-
sponding bits in the accumulator. Note that the accumulator’s most-significant
bit is always zeroed regardless of the shift-code value.
Words 2
Cycles
C C
Operands None
Execution (PC) + 1 → PC
(ACC) + ( shifted P register) → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 1
Description The contents of the P register are shifted as defined by the PM status bits and
added to the contents of the accumulator. The result is left in the accumulator.
APAC is not affected by the SXM bit of the status register; the P register is al-
ways sign-extended.
The APAC instruction is a subset of the LTA, LTD, MAC, MACD, MPYA, and
SQRA instructions.
Words 1
Cycles
C C
4-41
B Branch Unconditionally
Execution pma → PC
Modify AR(ARP) and ARP as specified.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified, and control
passes to the designated program memory address (pma). Note that no AR
or ARP modification occurs if nothing is specified in those fields. The pma can
be either a symbolic or a numeric address.
Words 2
Cycles
Operands None
Execution (ACC(15–0)) → PC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Encoding
1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1
Description The branch uses the lower half of the accumulator (bits 15 – 0) for the branch
address.
Words 1
Cycles
Example BACC
C C
4-43
BANZ Branch on Auxiliary Register Not Zero
Execution If AR (ARP) ≠ 0:
Then pma → PC;
Else (PC) + 2 → PC.
Modify AR (ARP) as specified.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description Control is passed to the designated program memory address (pma) if the cur-
rent auxiliary register is not equal to zero. Otherwise, control passes to the next
instruction. The current auxiliary register and ARP are also modified as speci-
fied.
Description The current auxiliary register is either incremented or decremented from zero
when the branch is not taken. Note that the AR modification defaults to *-
(decrement current AR by one) when nothing is specified, making it compat-
ible with the TMS320C1x. The pma can be either a symbolic or a numeric ad-
dress.
Words 2
Cycles
PC 46h PC 35h
or
AR 0h AR 0FFFFh
PC 46h PC 48h
PC 117h PC 64h
or
AR 0h AR 1h
PC 117h PC 119h
Note:
BANZ is designed for loop control using the auxiliary registers as loop count-
ers. Using *0 + or *0 – allows modification of the loop counter by a variable
step size. Care must be exercised when doing this, however, because the
auxiliary registers behave as modulo 65 536 counters, and zero may be
passed without being detected if ARO > 1.
4-45
BBNZ Branch on TC Bit Not Equal to Zero
Affected by TC bit
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address if TC = 1. Otherwise, con-
trol passes to the next instruction. Note that no AR or ARP modification occurs
if nothing is specified in those fields. The pma can be either a symbolic or nu-
meric address. Note that the TC bit may be affected by the BIT, BITT, CMPR,
LST1, NORM, RTC, and STC instructions.
Words 2
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address if TC = 0. Otherwise, con-
trol passes to the next instruction. No AR or ARP modification occurrs if noth-
ing is speciified in those fields. The pma can be either a symbolic or a numeric
address. Note that the TC bit is affected by the BIT, BITT, CMPR, LST1,
NORM, RTC, and STC instructions.
Words 2
Cycles
4-47
BC Branch on Carry
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address if the carry bit C is high.
Otherwise, control passes to the next instruction. Note that no AR or ARP mod-
ification occurs if nothing is specified in those fields. The pma can be either a
symbolic or a numeric address.
Note that the carry bit C is affected by all add, subtract, and accumulate
instructions as well as the ABS, LST1, NEG, RC, SC, rotate, and shift instruc-
tions. The carry bit is not affected by execution of BC, BNC, or nonarithmetic
instructions.
Words 2
Cycles
Example BC PRG512 ;If the carry bit C = 1, 512 is loaded into the
;program counter. Otherwise, the PC is
;incremented by 2.
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the contents of
the accumulator are greater than or equal to zero. Otherwise, control passes
to the next instruction. Note that no AR or ARP modification occurs if nothing
is specified in those fields. The pma can be either a symbolic or a numeric ad-
dress.
Words 2
Cycles
Example BGEZ PRG217 ;217 is loaded into the program counter if the
;accumulator is greater than or equal to zero.
4-49
BGZ Branch if Accumulator Greater Than Zero
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the contents of
the accumulator are greater than zero. Otherwise, control passes to the next
instruction. Note that no AR or ARP modification occurs if nothing is specified
in those fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles
Example BGZ PRG342 ;342 is loaded into the program counter if the
;accumulator is greater than or equal to zero.
Execution If BIO = 0:
Then pma → PC;
Else (PC) + 2 → PC.
Modify AR (ARP) and ARP as specified.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the BIO pin is low.
Otherwise, control passes to the next instruction. Note that no AR or ARP mod-
ification occurs if nothing is specified in those fields. The pma can be either a
symbolic or a numeric address.
BIOZ in conjunction with the BIO pin can be used to test if a peripheral is ready
to send or receive data. Polling the BIO pin by using BIOZ may be preferable
to an interrupt when executing time-critical loops.
Words 2
Cycles
Example BIOZ PRG64 ;If the BIO pin is active (low), then a branch
;to location 64 occurs.
4-51
BIT Test Bit
Execution (PC) + → PC
(dma bit at bit address (15-bit code) ) → TC.
Affects TC.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The BIT instruction copies the specified bit of the data memory value to the TC
bit of status register ST1. Note that the BITT, CMPR, LST1, and NORM instruc-
tions also affect the TC bit in status register ST1. A bit code value is specified
that corresponds to a certain bit address in the instruction, as given by the fol-
lowing table:
Bit Code
Bit Address 11 10 9 8
(LSB) 0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
(MSB) 15 0 0 0 0
Words 1
Cycles
4-53
BITT Test Bit Specified by T Register
Execution (PC) + 1 → PC
(dma bit at bit address (15–T register(3–0) )) → TC
Affects TC.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The BITT instruction copies the specified bit of the data memory value to the
TC bit of status register ST1. Note that the BIT, CMPR, LST1, and NORM
instructions also affect the TC bit in status register ST1. The bit address is spe-
cified by a bit code value contained in the LSBs of the T register, as given in
the following table:
Bit Code
Bit Address 3 2 1 0
(LSB) 0 1 1 1 1
1 1 1 1 0
2 1 1 0 1
3 1 1 0 0
4 1 0 1 1
5 1 0 1 0
6 1 0 0 1
7 1 0 0 0
8 0 1 1 1
9 0 1 1 0
10 0 1 0 1
11 0 1 0 0
12 0 0 1 1
13 0 0 1 0
14 0 0 0 1
(MSB) 15 0 0 0 0
Words 1
Cycles
TR 1h TR 1h
TC 0h TC 1h
4-55
BLEZ Branch if Accumulator Less Than or Equal to Zero
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the contents of
the accumulator are less than or equal to zero. Otherwise, control passes to
the next instruction. Note that no AR or ARP modification occurs if nothing is
specified in those fields. The pma can be either a symbolic or a numeric ad-
dress.
Words 2
Cycles
Example BLEZ PRG63 ;63 is loaded into the program counter if the
;accumulator is less than or equal to zero.
If (repeat counter) ≠ 0:
Then (dma1, addressed by PFC) → dma2,
Modify AR(ARP) and ARP as specified,
(PFC) + 1 → PFC,
(repeat counter) – 1 → repeat counter.
4-57
BLKD Block Move From Data Memory to Data Memory
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description Consecutive memory words are moved from a source data memory block to
a destination data memory block. The starting address (lowest) of the source
block is defined by the second word of the instruction. The starting address
of the destination block is defined by either the dma contained in the opcode
(for direct addressing) or the current AR (for indirect addressing). In the indi-
rect addressing mode, both the current AR and ARP may be modified in the
usual manner. In the direct addressing mode, dma2 is used as the destination
address for the block move but is not modified upon repeated executions of
the instruction. Thus, the contents of memory at the dma2 address will be the
same as the contents of memory at the last dma1 address in a repeat se-
quence.
RPT or RPTK must be used with the BLKD instruction, in the indirect addres-
sing mode, if more than one word is to be moved. The number of words to be
moved is one greater than the number contained in the repeat counter RPTC
at the beginning of the instruction. At the end of this instruction, the RPTC con-
tains zero and, if using indirect addressing, AR(ARP) will be modified to con-
tain the address after the end of the destination block. Note that the source
and destination blocks do not have to be entirely on-chip or off-chip. However,
BLKD cannot be used to transfer data from a memory-mapped register to any
other location in data memory.
The PC points to the instruction following BLKD after execution. Interrupts are
inhibited during a BLKD operation used with RPT or RPTK.
Words 2
Cycles
Example RPTK 2
BLKD 0F400h,*+ ;If current auxiliary register contains 1030.
dma1
Before Instruction After Instruction
Data Data
Memory 7F98h Memory 7F98h
62464 62464
Data Data
Memory 0FFE6h Memory 0FFE6h
62465 62465
Data Data
Memory 9522h Memory 9522h
62466 62466
dma2
Before Instruction After Instruction
Data Data
Memory 7F98h Memory 7F98h
1030 1030
Data Data
Memory 9315h Memory 0FFE6h
1031 1031
Data Data
Memory 2531h Memory 9522h
1032 1032
4-59
BLKP Block Move From Program Memory to Data Memory
Description Consecutive memory words are moved from a source program memory block
to a destination data memory block. The starting address (lowest) of the
source block is defined by the second word of the instruction. The starting ad-
dress of the destination block is defined by either the dma contained in the op-
code (for direct addressing) or the current AR (for indirect addressing). In the
indirect addressing mode, both the ARP and the current AR may be modified
in the usual manner. In the direct addressing mode, dma is used as the des-
tination address for the block move but is not modified by repeated executions
of the instruction. Thus, the contents of memory at the dma address will be
the same as the contents of memory at the last pma address in a repeat se-
quence.
RPT or RPTK must be used with the BLKP instruction if more than one word
is to be moved. The number of words to be moved is one greater than the num-
ber contained in the repeat counter RPTC at the beginning of the instruction.
At the end of this instruction, the RPTC contains zero and, if using indirect ad-
dressing, AR(ARP) will be modified to contain the address after the end of the
destination block. Note that source and destination blocks do not have to be
entirely on-chip or off-chip.
The PC points to the instruction following BLKP after execution. Interrupts are
inhibited during a BLKP operation.
If the MP/MC pin on the TMS320C25 is low at the time of execution of this
instruction and the program memory address used is less than 4096, an on-
chip ROM location will be read.
Words 2
Cycles
4-61
BLKP Block Move From Program Memory to Data Memory
Example RPTK 2
BLKP 65120,*+ ;If current auxiliary register contains 2048.
pma
Before Instruction After Instruction
Data Data
Memory 0A089h Memory 0A089h
65120 65120
Data Data
Memory 2DCEh Memory 2DCEh
65121 65121
Data Data
Memory 3A9Fh Memory 3A9Fh
65122 65122
dma
Before Instruction After Instruction
Data Data
Memory 1234h Memory 0A089h
2048 2048
Data Data
Memory 2005h Memory 2DCEh
2049 2049
Data Data
Memory 0E98Ch Memory 3A9Fh
2050 2050
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 1 1 1 See Section 4.1
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the contents of
the accumulator are less than zero. Otherwise, control passes to the next
instruction. Note that no AR or ARP modification occurs when nothing is speci-
fied in those fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles
4-63
BNC Branch on No Carry
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address if the carry bit C is low.
Otherwise, control passes to the next instruction. Note that no AR or ARP
modification occurs when nothing is specified in those fields. The pma can be
either a symbolic or a numeric address.
Note that the carry bit C is affected by all add, subtract, and accumulate
instructions as well as the ABS, LST1, NEG, RC, SC, rotate, and shift instruc-
tions. The carry bit is not affected by execution of the BC, BNC, or nonarith-
metic instructions.
Words 2
Cycles
Example BNC PRG325 ;If the carry bit C = 0, 325 is loaded into
;program counter. Otherwise, the PC is the
;incremented by 2.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 1 1 See Section 4.1
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the OV (overflow
flag) is clear. Otherwise, the OV is cleared, and control passes to the next
instruction. Note that no AR or ARP modification occurs if nothing is specified
in those fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles
Example BNV PRG315 ;315 is loaded into the program counter if the
;overflow flag is clear. OV is cleared.
4-65
BNZ Branch if Accumulator Not Equal to Zero
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 0 1 1 See Section 4.1
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the contents of
the accumulator are not equal to zero. Otherwise, control passes to the next
instruction. Note that no AR or ARP modification occurs if nothing is specified
in those fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles
Example BNZ PRG320 ;320 is loaded into the program counter if the
;accumulator does not equal zero.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 0 0 0 1 See Section 4.1
Description The current auxiliary register and ARP are modified as specified, and the over-
flow flag is cleared. Control passes to the designated program memory ad-
dress (pma) if the OV (overflow flag) is set. Otherwise, control passes to the
next instruction. Note that no AR or ARP modification occurs if nothing is spe-
cified in those fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles
4-67
BZ Branch if Accumulator Equals Zero
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 0 1 1 0 1 See Section 4.1
Description The current auxiliary register and ARP are modified as specified. Control then
passes to the designated program memory address (pma) if the contents of
the accumulator are equal to zero. Otherwise, control passes to the next
instruction. Note that no AR or ARP modification occurs if nothing is specified
in those fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles Cycles
Operands None
Execution (PC) + 1 → TOS
(ACC(15–0)) → PC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0
Description The current program counter is incremented and pushed onto the top of the
stack. Then, the contents of the lower half of the accumulator are loaded into
the PC. The carry bit on the TMS320C25 is unaffected by this instruction.
Words 1
Cycles
4-69
CALA Call Subroutine Indirect
Example CALA
PC 25h PC 83h
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The current auxiliary register and ARP are modified as specified, and the PC
(program counter) is incremented by two and pushed onto the top of the stack.
The specified program memory address (pma) is then loaded into the PC.
Note that no AR or ARP modification occurs if nothing is specified in those
fields. The pma can be either a symbolic or a numeric address.
Words 2
Cycles
4-71
CALL Call Subroutine
pma
Before Instruction After Instruction
PC 33h PC 6Dh
Operands None
Execution (PC) + 1 → PC
(ACC) → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 1
Description The contents of the accumulator are replaced with its logical inversion (1s
complement).
Words 1
Cycles
Example CMPL
C C
4-73
CMPR Compare Auxiliary Register With Auxiliary Register AR0
Operands 0 ≤ CM ≤ 3
Execution (PC) + 1 → PC
Compare AR(ARP) to AR0, placing result in TC bit of status register ST1.
Affects TC.
Not affected by SXM; does not affect SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 1 0 1 0 0 CM
Description The CMPR instruction performs the following comparisons dependent on the
value of CM:
If CM = 00, test if AR(ARP) = AR0
If CM = 01, test if AR(ARP) < AR0
If CM = 10, test if AR(ARP) > AR0
If CM = 11, test if AR(ARP) ≠ AR0
If the result of a test is true, a one is loaded into the TC status bit. Otherwise,
TC is loaded with a zero. The auxiliary registers are treated as unsigned inte-
gers in the comparison.
Words 1
Cycles
TC 1h TC 0h
Operands None
Execution (PC) + 1 → PC
0 → RAM configuration control (CNF) status bit
Affects CNF.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 0
Description On-chip RAM block 0 is configured as data memory. The block is mapped to
locations 512 through 767 in data memory. This instruction is the complement
of the CNFP instruction and sets the CNF bit in status register ST1 to a zero.
CNF is also loaded by the CNFP and LST1 instructions.
Words 1
Cycles
4-75
CNFP Configure Block as Program Memory
Operands None
Execution (PC) + 1 → PC
1 → RAM configuration control (CNF) status bit
Affects CNF.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 1
Description On-chip RAM block 0 is configured as program memory. The block is mapped
to locations 65280 through 65535 in program memory space. This instruction
is the complement of the CNFD instruction and sets the CNF bit in status regis-
ter ST1 to a one. CNF is also loaded by the CNFD and LST1 instruction.
Configuring this block as program memory allows the use of the program
counter as an address generator to access data from on-chip RAM. Used in
conjunction with the repeat instructions, this allows two data memory locations
to be addressed simultaneously, one from the auxiliary registers and one from
the program counter. Instructions that take advantage of this feature are the
MAC, MACD, BLKD, and BLKP instructions.
Words 1
Cycles
Operands o ≤ constant ≤ 3
Execution (PC) + 1 → PC
Constant → program/data memory configuration mode status bits
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 1 1 CNF1 CNF0
Description The two low-order CNF bits of the instruction word are copied into the CNF0
and CNF1 field of status register ST1. The CNF0 and CNF1 status bits config-
ure the on-chip RAM blocks into program or data memory. The bit combina-
tions and their meanings are shown below in the CONF mode decoding table.
Words 1
Cycles
4-77
DINT Disable Interrupt
Operands None
Execution (PC) + 1 → PC
1 → interrupt mode (INTM) status bit
Affects INTM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 1
Description The interrupt mode (INTM) status bit is set to logic 1. Maskable interrupts are
disabled immediately after the DINT instruction executes. Note that the LST
instruction does not affect INTM.
The unmaskable interrupt, RS, is not disabled by this instruction, and the inter-
rupt mask register (IMR) is unaffected. Interrupts are also disabled by a reset.
Words 1
Cycles
Affected by CNF.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the specified data memory address are copied into the con-
tents of the next higher address. DMOV works only within the on-chip data
RAM blocks B0, B1, and B2. It works within block B0 if it is configured as data
memory and the data move function is continuous across the boundaries of
blocks B0 and B1; that is, it works for locations 512 to 1023. The data move
function cannot be used on external data memory. If used on external data
memory or memory-mapped registers, DMOV will read the specified memory
location but will perform no other operations.
When data is copied from the addressed location to the next higher location,
the contents of the addressed location remain unaltered.
The data move function is useful in implementing the z–1 delay encountered
in digital signal processing. The DMOV function is included in the LTD and
MACD instructions (see the LTD and MACD instructions or more information).
Words 1
Cycles
4-79
DMOV Data Move in Data Memory
Data Data
Memory 2h Memory 43h
521 521
Operands None
Execution (PC) + 1 → PC
0 → interrupt-mode (INTM) status bit
Affects INTM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0
Description The interrupt-mode flag (INTM) in the status register is cleared to logic 0.
Maskable interrupts are enabled after the instruction following EINT executes.
This allows an interrupt service routine to re-enable interrupts and execute a
RET instruction before any other pending interrupts are processed. Note that
the LST instruction does not affect INTM. (See the DINT instruction for further
information.)
Words 1
Cycles
4-81
FORT Format Serial Port Registers
Operands Constant = 0 or 1
Execution (PC) + 1 → PC
Constant → format (FO) status bit
Affects FO.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 1 1 1 FO
Description The format (FO) status bit is loaded by the instruction with the LSB specified
in the instruction. The FO bit is used to control the formatting of the transmit
and receive shift registers of the serial port. If FO = 0, the registers are config-
ured to receive/transmit 16-bit words. If FO = 1, the registers are configured
to receive/transmit 8-bit bytes. FO is set to zero on a reset.
Words 1
Cycles
Operands None
Execution TMS320C25:
(PC) + 1 → PC
0 → interrupt mode (INTM) status bit
Affects INTM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 1
Description The IDLE instruction forces the program being executed to wait until an inter-
rupt or reset occurs. The PC is incremented only once, and the device remains
in an idle state until interrupted. On the TMS320C25, INTM is automatically set
to zero. Execution of the IDLE instruction causes the TMS320C25 to enter the
powerdown mode (see subsection 3.6.7). The on-chip timer continues to oper-
ate normally after execution of an IDLE instruction.
Words 1
Cycles
4-83
IN Input Data From Port
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The IN instruction reads a 16-bit value from one of the external I/O ports into
the specified data memory location. The IS line goes low to indicate an I/O ac-
cess, and the STRB, R/W, and READY timings are the same as for an external
data memory read.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the specified data memory address are left-shifted and loaded
into the accumulator. During shifting, low-order bits are zero-filled. High-order
bits are sign-extended if SXM = 1 and zeroed if SXM = 0.
Words 1
Cycles
C C
4-85
LACK Load Accumulator Immediate Short
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 0 8-Bit Constant
Description The 8-bit constant is loaded into the accumulator right-justified. The upper 24
bits of the accumulator are zeroed (that is, sign extension is suppressed).
Words 1
Cycles
C C
If SXM = 1:
Then (dma) is sign-extended.
If SXM = 0:
Then (dma) is not sign-extended.
Affected by SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The LACT instruction loads the accumulator with a data memory value that has
been left-shifted. The left-shift is specified by the four LSBs of the T register,
resulting in shift options from 0 to 15 bits. Using the T register’s contents as
a shift code provides a variable shift mechanism.
Words 1
Cycles
4-87
LACT Load Accumulator With Shift Specified by T Register
T 3014h T 3014h
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 shift 0 0 0 0 0 00 0 1
16-Bit Constant
Description The left-shifted 16-bit immediate value is loaded into the accumulator. The
shifted 16-bit constant is sign-extended if SXM = 1; otherwise, the high-order
bits of the accumulator (past the shift) are set to zero. Note that the MSB of the
accumulator can be set only if SXM = 1 and a negative number is loaded. The
shift count is optional and defaults to zero.
Words 2
Cycles
C C
C C
4-89
LAR Load Auxiliary Register
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the specified data memory address are loaded into the desig-
nated auxiliary register (AR).
The LAR and SAR (store auxiliary register) instructions can be used to load
and store the auxiliary registers during subroutine calls and interrupts. If an
auxiliary register is not being used for indirect addressing, LAR and SAR en-
able the register to be used as an additional storage register, especially for
swapping values between data memory locations without affecting the con-
tents of the accumulator.
Words 1
Cycles
Note:
LAR, in the indirect addressing mode, ignores any AR modifications if the AR
specified by the instruction is the same as that pointed to by the ARP. There-
fore, in Example 2, AR4 is not decremented after the LAR instruction.
4-91
LARK Load Auxiliary Register Immediate Short
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 0 AR 8-Bit Constant
Description The 8-bit positive constant is loaded into the designated auxiliary register (AR)
right-justified and zero-filled (that is, sign-extension suppressed).
LARK is useful for loading an initial loop counter value into an auxiliary register
for use with the BANZ instruction.
Words 1
Cycles
Operands 0 ≤ constant ≤ 7
Execution (PC) + 1 → PC
(ARP) → ARB
Constant → ARP
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 1 1 0 0 0 1 ARP
Description The auxiliary register pointer is loaded with the contents of the three LSBs of
the instruction (a 3-bit constant identifying the desired auxiliary register). The
old ARP is copied to the ARB field of status register ST1. ARP can also be mo-
dified by the LST, LST1, and MAR instructions, as well as any instruction that
is used in the indirect addressing mode.
The LARP instruction is a subset of MAR; that is, the opcode is the same as
MAR in the indirect addressing mode. The following instruction has the same
effect as LARP:
MAR *,constant
Words 1
Cycles
4-93
LDP Load Data Memory Page Pointer
Affects DP.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The nine LSBs of the contents of the addressed data memory location are
loaded into the DP (data memory page pointer) register. The DP and 7-bit data
memory address are concatenated to form 16-bit data memory addresses.
The DP may also be loaded by the LST and LDPK instructions.
Words 1
Cycles
DP 1FFh DP 0DCh
Affects DP.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 0 DP
Description The DP (data memory page pointer) register is loaded with a 9-bit constant.
The DP and 7-bit data memory address are concatenated to form 16-bit direct
data memory addresses. DP ≥ 8 specifies external data memory. DP = 4
through 7 specifies on-chip RAM blocks B0 or B1. Block B2 is located in the
upper 32 words of page 0. DP may also be loaded by the LST and LDP instruc-
tions.
Words 1
Cycles
4-95
LPH Load High P Register
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The P register high-order bits are loaded with the contents of data memory.
The low-order P register bits are unaffected.
The LPH instruction is particularly useful for restoring the high-order bits of the
P register after subroutine calls or interrupts.
Words 1
Cycles
P 30079844h P F79C9844h
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 0 AR 0 0 0 0 0 0 0 0
16-Bit Constant
Description The 16-bit immediate value is loaded into the auxiliary register specified by the
AR field. The specified constant must be an unsigned integer, and its value is
not affected by SXM.
Words 2
Cycles
4-97
LST Load Status Register ST0
Description Status register ST0 is loaded with the addressed data memory value. Note that
the INTM (interrupt mode) bit is unaffected by LST. ARB is also unaffected
even though a new ARP is loaded. If a next ARP value is specified via the indi-
rect addressing mode, the specified value is ignored. Instead, ARP is loaded
with the value contained within the addressed data memory word.
The LST instruction is used to load status register ST0 after interrupts and sub-
routine calls. The ST0 contains the status bits: OV (overflow flag) bit, OVM
(overflow mode) bit, INTM (interrupt mode) bit, ARP (auxiliary register pointer),
and DP (data memory page pointer). These bits were stored (by the SST
instruction) in the data memory word as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Words 1
Cycles
Example 1 LARP 0
LST *,1 ;The data memory word addressed by the contents
;of auxiliary register AR0 is loaded into
;status register ST0, except for the INTM bit.
;Note that even though a next ARP value is
;specified, that value is ignored, and even
;though a new ARP is loaded, the old ARP is not
;loaded into ARB.
Data Data
Memory 0CE06h Memory 0CE06h
1023 1023
Data Data
Memory 0EE04h Memory 0EE04h
1023 1023
4-99
LST1 Load Status Register ST1
Affects ARP, ARB, CNF, TC, SXM, XF, FO, TXM, and PM.
Affects C, HM, and FSM (TMS320C25)
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description Status register ST1 is loaded with the data memory value. The bits of the data
memory value, which are loaded into ARB, are also loaded into ARP to facili-
tate context switching. Note that if a next ARP value is specified via the indirect
addressing mode, the specified value is ignored.
LST1 is used to load status bits after interrupts and subroutine calls. ST1 con-
tains these status bits: ARB (auxiliary register pointer buffer), CNF (RAM con-
figuration control), TC (test/control), SXM (sign-extension mode), XF (external
flag), FO (serial port format), TXM (transmit mode), and the PM (product regis-
ter shift mode). ST1 on the TMS320C25 also contains status bits: C (carry),
HM (hold mode), and FSM (frame synchronization mode). The bits loaded into
status register ST1 from the data memory word are as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
† On the TMS320C26, bits 12 and 7 hold CONF0 and CNF1, respectively (see the CONF
instruction for decoding).
Words 1
Cycles
Example 1 LARP 3
LST1 *– ;The data memory word addressed by the contents
;of auxiliary register AR3 replaces the status
;bits of status register ST1, and AR3 is
;decremented.
Data Data
Memory 4F90h Memory 4F90h
1022 1022
4-101
LST1 Load Status Register ST1
Data Data
Memory 6190h Memory 6190h
1022 1022
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The T register is loaded with the contents of the specified data memory ad-
dress (dma). The LT instruction may be used to load the T register in prepara-
tion for multiplication. See the LTA, LTD, LTP, LTS, MPY, MPYK, MPYA, MPYS,
and MPYU instructions.
Words 1
Cycles
T 3h T 62h
4-103
LTA Load T Register and Accumulate Previous Product
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The T register is loaded with the contents of the specified data memory ad-
dress (dma). The contents of the product register, shifted as defined by the PM
status bits, are added to the accumulator, with the result left in the accumulator.
Words 1
Cycles
T 3h T 62h
P 0Fh P 0Fh
4-105
LTD Load T Register, Accumulate Previous Product, and Move Data
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The T register is loaded with the contents of the specified data memory ad-
dress (dma). The contents of the P register, shifted as defined by the PM status
bits, are added to the accumulator, and the result is placed in the accumulator.
The contents of the specified data memory address are also copied to the next
higher data memory address.
This instruction is valid for blocks B1 and B2 and is also valid for block B0 if
block B0 is configured as data memory. The data move function is continuous
across the boundary of blocks B0 and B1 but cannot be used with external data
memory or memory-mapped registers. This function is described under the
instruction DMOV. Note that if used with external data memory, the function
of LTD is identical to that of LTA.
Words 1
T 3h T 62h
P 0Fh P 0Fh
4-107
LTP Load T Register and Store P Register in Accumulator
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The T register is loaded with the contents of the addressed data memory loca-
tion, and the product register is stored in the accumulator. The shift at the out-
put of the product register is controlled by the PM status bits.
Words 1
Cycles
T 3h T 62h
P 0Fh P 0Fh
ACC X 5h ACC X Fh
C C
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The T register is loaded with the contents of the addressed data memory loca-
tion. The contents of the product register, shifted as defined by the contents
of the PM status bits, are subtracted from the accumulator. The result is left
in the accumulator.
Words 1
Cycles
4-109
LTS Load T Register and Subtract Previous Product
T 3h T 62h
P 0Fh P 0Fh
(PC) + 2 → PC
(PFC) → MCS
(pma) → PFC
If (repeat counter) ≠ 0:
Then (ACC) + (shifted P register) → ACC,
(dma) → T register,
(dma) × (pma, addressed by PFC) → P register,
Modify AR(ARP) and ARP as specified,
(PFC) + 1 → PFC,
(repeat counter) – 1 → repeat counter.
Else (ACC) + (shifted P register) → ACC
(dma) → T register
(dma) × (pma, addressed by PFC) → P register
Modify AR(ARP) and ARP as specified.
(MCS) → PFC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The MAC instruction multiplies a data memory value (specified by dma) by a
program memory value (specified by pma). It also adds the previous product,
shifted as defined by the PM status bits, to the accumulator.
The data and program memory locations on the TMS320C25 may be any non-
reserved, on-chip or off-chip memory locations. If the program memory is
block B0 of on-chip RAM, then the CNF bit must be set to one. Note that the
upper eight bits of the program memory address should be set to 0FFh in order
to address B0 program RAM, and the upper six bits of dma should be set to
0 to address a location below 1024. When used in the direct addressing mode,
the dma cannot be modified during repetition of the instruction.
4-111
MAC Multiply and Accumulate
When the MAC instruction is repeated, the program memory address con-
tained in the PC/PFC is incremented by one during its operation. This enables
accessing a series of operands in memory. MAC is useful for long sum-of-
products operations, since MAC becomes a single-cycle instruction once the
RPT pipeline is started.
Words 2
Cycles
The following example shows register and memory contents before and after
the third step repeat loop:
Data Data
Memory 23h Memory 23h
770 770
Program Program
Memory 0FAAAh Memory 0FAAAh
65282 65282
P 458972h P 0FFFF453Eh
4-113
MACD Multiply and Accumulate With Data Move
(PC) + 2 → PC
(PFC) → MCS
(pma) → PFC
If (repeat counter) ≠ 0:
Then (ACC) + (shifted P register) → ACC,
(dma) → T register,
(dma) × (pma, addressed by PFC) → P register,
(dma) → dma + 1,
Modify AR(ARP) and ARP as specified,
(PFC) + 1 → PFC,
(repeat counter) – 1 → repeat counter.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The MACD instruction multiplies a data memory value (specified by dma) by
a program memory value (specified by pma). It also adds the previous product,
shifted as defined by the PM status bits, to the accumulator.
The data and program memory locations on the TMS320C25 may be any non-
reserved, on-chip or off-chip memory locations. If the program memory is
block B0 of on-chip RAM, then the CNF bit must be set to one. Note that the
upper eight bits of the program memory address should be set to 0FFh in order
to address B0 program RAM, and the upper six bits of dma should be set to
0 to address a location below 1024. When used in the direct addressing mode,
the dma cannot be modified during repetition of the instruction. If MACD ad-
dresses one of the memory-mapped registers or external memory as a data
memory location, the effect of the instruction will be that of a MAC instruction
(see the DMOV instruction description).
MACD functions in the same manner as MAC, with the addition of data move
for block B0, B1, or B2. Otherwise, the effects are the same as for MAC. This
feature makes MACD useful for applications such as convolution and trans-
versal filtering.
When the MACD instruction is repeated, the program memory address con-
tained in the PC/PFC is incremented by one during its operation. This enables
accessing a series of operands in memory. When used with RPT or RPTK,
MACD becomes a single-cycle instruction, once the RPT pipeline is started.
Note:
The data move function for MACD can occur only within the data blocks
B0 – B2 of the on-chip RAM. B3 can also be used for the TMS320C26.
Words 2
Cycles
4-115
MACD Multiply and Accumulate With Data Move
The following example shows register and memory contents before and after
the third step repeat loop:
Data Data
Memory 23h Memory 23h
1021 1021
Data Data
Memory 7FCh Memory 23h
1022 1022
Program Program
Memory 0FAAAh Memory 0FAAAh
65282 65282
P 458972h P 0FFFF453Eh
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The MAR instruction acts as a no-operation instruction in the direct addressing
mode. In the indirect addressing mode, the auxiliary registers and the ARP are
modified; however, no use is made of the memory being referenced. MAR is
used only to modify the auxiliary registers or the ARP. If a next ARP is specified,
the old ARP is copied to the ARB field of status register ST1. Note that any op-
eration that MAR performs can also be performed with any instruction that sup-
ports indirect addressing. ARP may also be loaded by an LST instruction.
In the direct addressing mode, MAR is a NOP. Also, the instruction LARP is
a subset of MAR (that is, MAR *,4 performs the same function as LARP 4).
Words 1
Cycles
4-117
MAR Modify Auxiliary Register
ARP 1 ARP 5
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the T register are multiplied by the contents of the addressed
data memory location. The result is placed in the P register.
Words 1
Cycles
Data Data
Memory 7h Memory 7h
1037 1037
T 6h T 6h
P 36h P 2Ah
4-119
MPYA Multiply and Accumulate Previous Product
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the T register are multiplied by the contents of the addressed
data memory location. The result is placed in the P register. The previous prod-
uct, shifted as defined by the PM status bits, is also added to the accumulator.
Words 1
Cycles
T 6h T 6h
P 36h P 2Ah
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 0 1 13-Bit Constant
Description The contents of the T register are multiplied by the signed, 13-bit constant. The
result is loaded into the P register. The immediate field is right-justified and
sign-extended before multiplication, regardless of SXM.
Words 1
Cycles
Example MPYK –9
P 2Ah P 0FFFFFFC1h
4-121
MPYS Multiply and Subtract Previous Product
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the T register are multiplied by the contents of the addressed
data memory location. The result is placed in the P register. The previous prod-
uct, shifted as defined by the PM status bits, is also subtracted from the accu-
mulator.
Words 1
Cycles
T 6h T 6h
P 36h P 2Ah
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The unsigned contents of the T register are multiplied by the unsigned con-
tents of the addressed data memory location. The result is placed in the P reg-
ister. Note that the multiplier acts as a 17 ×17-bit signed multiplier for this
instruction, with the MSB of both operands forced to zero.
The shifter at the output of the P register will always invoke sign-extension on
the P register when PM = 3 (right-shift by 6 mode). Therefore, this shift mode
should not be used if unsigned products are desired.
Words 1
Cycles
4-123
MPYU Multiply Unsigned
T 0FFFFh T 0FFFFh
P 1h P 0FFFE0001h
Operands None
Execution (PC) + 1 → PC
(ACC) × –1 → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 1
Description The contents of the accumulator are replaced with its arithmetic complement
(2s complement). The OV bit is set when taking the NEG of 80000000h. If
OVM = 1, the accumulator contents are replaced with 7FFFFFFFh. If
OVM = 0, the result is 80000000h. The carry bit C on the TMS320C2x is reset
to zero by this instruction for all nonzero values of the accumulator and is set
to one if the accumulator equals zero.
Words 1
Cycles
Example NEG
4-125
NOP No Operation
Operands None
Execution (PC) + 1 → PC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0
Description No operation is performed. The NOP instruction affects only the PC. NOP
functions in the same manner as the MAR instruction in the direct addressing
mode; NOP has the same opcode as MAR in the direct addressing mode with
dma = 0.
Words 1
Cycles
Example NOP
Operands None
Execution TMS320C25:
(PC) + 1 → PC
If (ACC) = 0:
Then 1 → TC;
Else, if (ACC(31)) XOR (ACC(30)) = 0:
Then 0 → TC,
(ACC) × 2 → ACC,
Modify AR(ARP) as specified;
Else 1 → TC.
Affects TC.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 1 Modify AR 0 0 1 0
Description The NORM instruction is provided for normalizing a signed number that is con-
tained in the accumulator. Normalizing a fixed-point number separates it into
a mantissa and an exponent. To do this, the magnitude of a sign-extended
number must be found. ACC bit 31 is exclusive-ORed with ACC bit 30 to deter-
mine if bit 30 is part of the magnitude or part of the sign extension. If they are
the same, they are both sign bits, and the accumulator is left-shifted to elimi-
nate the extra sign bit.
Words 1
Cycles
4-127
NORM Normalize Contents of Accumulator
The first method is used to normalize a 32-bit number and yields a 5-bit expo-
nent magnitude. The second method is used to normalize a 16-bit number and
yields a 4-bit exponent magnitude. If the number requires only a small amount
of normalization, the first method may be preferable to the second. This results
because Example 1 runs only until normalization is complete. Example 2 al-
ways executes all 15 cycles of the repeat loop. Specifically, Example 1 is more
efficient if the number requires five or less shifts. If the number requires six or
more shifts, Example 2 is more efficient.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The low-order bits of the accumulator are ORed with the contents of the ad-
dressed data memory location. The high-order bits of the accumulator are
ORed with all zeros. Therefore, the upper half of the accumulator is unaffected
by this instruction.
Words 1
Cycles
4-129
ORK OR Immediate With Accumulator With Shift
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 Shift 0 0 0 0 0 1 0 1
16-Bit Constant
Description The left-shifted 16-bit immediate constant is ORed with the accumulator. The
result is left in the accumulator. Low-order bits below and high-order bits above
the shifted value are treated as zeroes. The corresponding bits of the accumu-
lator are unaffected. Note that the most significant bit of the accumulator is not
affected, regardless of the shift code value.
Words 2
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The OUT instruction writes a 16-bit value from a data memory location to the
specified I/O port. The IS line goes low to indicate an I/O access, and the
STRB, R/W, and READY timings are the same as for an external data memory
write. OUT is a single-cycle instruction when in the PI/DI memory configuration
(see Appendix D).
Words 1
Cycles
4-131
PAC Load Accumulator With P Register
Operands None
Execution (PC) + 1 → PC
(shifted P register) → ACC
Affected by PM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 0 1 0 0
Description The contents of the P register are loaded into the accumulator, shifted as spe-
cified by the PM status bits.
Words 1
Cycles
Description The contents of the top of the stack (TOS) are copied to the low accumulator,
and the stack is popped after the contents are copied. The upper half of the
accumulator is set to all zeros.
The hardware stack is a last-in, first-out stack with eight (TMS320C2x) loca-
tions. Any time a pop occurs, every stack value is copied to the next higher
stack location, and the top value is removed from the stack. After a pop, the
bottom two stack words will have the same value. Because each stack value
is copied, if more than seven pops (due to POP, POPD, or RET instructions)
occur before any pushes occur, all levels of the stack contain the same value.
No provision exists to check stack underflow.
Words 1
Cycles
Example POP
Before Instruction After Instruction
4-133
POPD Pop Top of Stack to Data Memory
Execution (PC) + 1 → PC
(TOS) → dma
POP stack one level.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The value from the top of the stack is transferred into the data memory location
specified by the instruction. The values are also popped in the lower seven
locations (TMS320C2x) of the stack. The hardware stack is described in the
previous instruction POP. The lowest stack location remains unaffected. No
provision exists to check stack underflow.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The value from the data memory location specified by the instruction is trans-
ferred to the top of the stack. The values are also pushed down in the lower
seven locations (TMS320C2x) of the stack, as described in the instruction
PUSH. The lowest stack location is lost.
Words 1
Cycles
4-135
PUSH Push Low Accumulator Onto Stack
Operands None
Execution (PC) + 1 → PC
Push all stack locations down one level.
(ACC(15–0)) → TOS
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 1 1 0 0
Description The contents of the lower half of the accumulator are copied onto the top of
the hardware stack. The stack is pushed down before the accumulator value
is copied.
Words 1
Cycles
Example PUSH:
ACC X 7h ACC X 7h
C C
Stack 2h Stack 7h
5h 2h
3h 5h
0h 3h
12h 0h
86h 12h
54h 86h
3Fh 54h
Syntax [ label ] RC
Operands None
Execution (PC) + 1 → PC
0 → carry bit C in status register ST1
Affects C.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 0
Description The carry bit C in status register ST1 is reset to logic zero. The carry bit may
also be loaded directly by the LST1 and SC instructions.
Words 1
Cycles
4-137
RET Return From Subroutine
Description The contents of the top stack register are copied into the program counter. The
stack is then popped one level. RET is used with CALA and CALL for subrou-
tines.
Words 1
Cycles
Example RET
Before Instruction After Instruction
PC 96h PC 37h
Operands None
Execution (PC) + 1 → PC
0 → FSM status bit in status register ST1
Affects FSM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 0
Description The RFSM status bit resets the FSM status bit to logic zero. In this mode, exter-
nal FSR pulses are not required to initiate the receive operation for each word
received, but rather only one FSR pulse is required to initiate a continuous
mode of operation. The same holds true for FSX when TXM = 0. After the first
FSR/FSX pulse, these inputs are then in a don’t care state. If TXM = 1, FSX
is pulsed the first time DXR is loaded but remains low thereafter. See Section
3.9 for further details on the operation of the serial port. FSM may also be
loaded by the LST1 and SFSM instructions.
Words 1
Cycles
4-139
RHM Reset Hold Mode
Operands None
Execution (PC) + 1 → PC
0 → HM status bit in status register ST1
Affects HM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 0
Description The RHM instruction clears internal execution when acknowledging an active
HOLD (HM = 1). When HM = 0, the processor may continue execution out of
internal memory but puts its external interface in a high-impedance state.
Words 1
Cycles
Operands None
Execution (PC) + 1 → PC
(ACC(31)) → C
(ACC(30 – 0)) → ACC(31 –1)
(C, before ROL) → ACC(0)
Affects C.
Not affected by SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 0
Description The ROL instruction rotates the accumulator left one bit. The MSB is shifted
into the carry bit, and the value of the carry bit from before the execution of the
instruction is shifted into the LSB.
Words 1
Cycles
Example ROL
4-141
ROR Rotate Accumulator Right
Operands None
Execution (PC) + 1 → PC
(ACC(0)) → C
(ACC(31–1)) → ACC(30–0)
(C, before ROR) → ACC(31)
Affects C.
Not affected by SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 1 0 1
Description The ROR instruction rotates the accumulator right one bit. The LSB is shifted
into the carry bit, and the value of the carry bit from before the execution of the
instruction is shifted into the MSB.
Words 1
Cycles
Example ROR
Operands None
Execution (PC) + 1 → PC
0 → OVM status bit in status register ST0
Affects OVM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0
Description The OVM status bit is reset to logic zero, which disables the overflow mode.
If an overflow occurs with OVM reset, the OV (overflow flag) is set, and the
overflowed result is placed in the accumulator.
Words 1
Cycles
4-143
RPT Repeat Instructions as Specified by Data Memory Value
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The eight LSBs of the addressed data memory value are loaded into the repeat
counter (RPTC). This causes the following instruction to be executed one time
more than the number loaded into the RPTC (provided that it is a repeatable
instruction). Interrupts are masked out until the next instruction has been
executed the specified number of times. (Interrupts cannot be allowed during
the RPT/next instruction sequence, because the RPTC cannot be saved dur-
ing a context switch.) The RPTC counter is cleared on a RS.
RPT and RPTK are especially useful for repeating instructions, such as BLKP,
BLKD, IN, MAC, MACD, NORM, OUT, TBLR, TBLW, and others.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 1 8–Bit Constant
Description The 8-bit immediate value is loaded into the RPTC (repeat counter). This
causes the following instruction to be executed one time more than the number
loaded into the RPTC (provided that it is a repeatable instruction). Interrupts
are masked out until the next instruction has been executed the specified num-
ber of times. (Interrupts cannot be allowed during the RPT/next instruction se-
quence, because the RPTC cannot be saved during a context switch.) The
RPTC is cleared on a RS.
RPT and RPTK are especially useful for repeating instructions, such as BLKP,
BLKD, IN, MAC, MACD, NORM, OUT, TBLR, TBLW, and others.
Words 1
Cycles
4-145
RSXM Reset Sign-Extension Mode
Operands None
Execution (PC) + 1 → PC
0 → SXM sign-extension mode status bit
Affects SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 0
Description The RSXM instruction resets the SXM status bit to logic zero, which sup-
presses sign-extension on shifted data memory values for the following arith-
metic instructions: ADD, ADDT, ADLK, LAC, LACT, LALK, SBLK, SUB, and
SUBT.
The RSXM instruction affects the definition of the SFR instruction. SXM may
also be loaded by the LST1 and SSXM instructions.
Words 1
Cycles
Operands None
Execution (PC) + 1 → PC
0 → TC test/control flag in status register ST1
Affects TC.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 0
Description The TC (test/control) flag in status register ST1 is reset to logic zero. TC can
also be loaded by the LST1 and STC instructions.
Words 1
Cycles
4-147
RTXM Reset Serial Port Transmit Mode
Operands None
Execution (PC) + 1 → PC
0 → TXM transmit mode status bit
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0
Description The RTXM instruction resets the TXM status bit, which configures the serial
port transmit section in a mode where it is controlled by an FSX (external fram-
ing pulse). The transmit operation is started when an external FSX pulse is ap-
plied. TXM may also be loaded by the LST1 and STXM instructions.
Words 1
Cycles
Operands None
Execution (PC) + 1 → PC
0 → XF external flag pin and status bit
Affects XF.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 0
Description The XF pin and XF status bit in status register ST1 are reset to logic zero. XF
may also be loaded by the LST1 and SXF instructions.
Words 1
Cycles
Example RXF ;XF pin and status bit are reset to logic zero.
4-149
SACH Store High Accumulator With Shift
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The SACH instruction copies the entire accumulator into a shifter, where it
shifts the entire 32-bit number anywhere from 0 to 7 bits on the TMS320C2x.
It then copies the upper 16 bits of the shifted value into data memory. The accu-
mulator itself remains unaffected.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The low-order bits of the accumulator are shifted left 0 to 7 bits on the
TMS320C2x, as specified by the shift code, and stored in data memory. The
low-order bits are filled with zeros, and the high-order bits are lost. The accu-
mulator itself is unaffected.
Words 1
Cycles
4-151
SAR Store Auxiliary Register
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the designated auxiliary register (AR) are stored in the ad-
dressed data memory location.
When you are modifying the contents of the current auxiliary register in the in-
direct addressing mode, SAR ARn (when n = ARP) stores the value of the aux-
iliary register contents before it is incremented, decremented, or indexed by
AR0.
Words 1
Cycles
Data Data
Memory 18h Memory 37h
798 798
Data Data
Memory 0h Memory 401h
1025 1025
4-153
SBLK Subtract From Accumulator Long Immediate With Shift
If SXM = 1:
Then –32768 ≤ constant ≤ 32767.
If SXM = 0:
Then 0 ≤ constant ≤ 65535.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 Shift 0 0 0 0 0 0 1 1
16-Bit Constant
Description The immediate field of the instruction is subtracted from the accumulator. The
result replaces the accumulator contents. SXM determines whether the
constant is treated as a signed 2s-complement number or as an unsigned
number. The shift count is optional and defaults to zero.
Words 2
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 1 1 1 1 1 1 8-Bit Constant
Description The 8-bit immediate value is subtracted, right-justified, from the currently se-
lected auxiliary register with the result replacing the auxiliary register contents.
The subtraction takes place in the ARAU, with the immediate value treated as
an 8-bit positive integer.
Words 1
Cycles
4-155
SC Set Carry Bit
Syntax [ label ] SC
Operands None
Execution (PC) + 1 → PC
1 → carry bit C in status register ST1
Affects C.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 0 0 1
Description The carry bit C in status register ST1 is set to logic one. The carry bit may also
be loaded directly by the LST1 and RC instructions.
Words 1
Cycles
Operands None
Execution (PC) + 1 → PC
(ACC(31) ) → C
(ACC(30–0) ) → ACC(31–1)
0 → ACC(0)
Affects C.
Not affected by SXM bit.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0
Description The SFL instruction shifts the entire accumulator left one bit. The least signifi-
cant bit is filled with a zero. On the TMS320C2x, the most significant bit is
shifted into the carry bit (C). Note that SFL, unlike SFR, is unaffected by SXM.
Words 1
Cycles
Example SFL
4-157
SFR Shift Accumulator Right
Description The SFR instruction shifts the accumulator right one bit.
If SXM = 1, the instruction produces an arithmetic right shift. The sign bit (MSB)
is unchanged and is also copied into bit 30. Bit 0 is shifted into the carry bit (C).
If SXM = 0, the instruction produces a logical right shift. All of the accumulator
bits are shifted by one bit to the right. The least significant bit is shifted into the
carry bit, and the most significant bit is filled with a zero.
Words 1
Cycles
Syntax SFSM
Operands None
Execution (PC) + 1 → PC
1 → FSM status bit in status register ST1
Affects FSM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 1 1 1
Description The SFSM instruction sets the FSM status bit to logic one. In this mode, an
external FSR pulse is required for a receive operation, and an external FSX
pulse is required if TXM = 0. If TXM = 1, FSX pulses are generated in the nor-
mal manner every time the transmit shift register XSR is loaded. See Section
3.7 for details on the operation of the serial port. FSM may also be loaded by
the LST1 and RFSM instructions.
Words 1
Cycles
4-159
SHM Set Hold Mode
Operands None
Execution (PC) + 1 → PC
1 → HM status bit in status register ST1
Affects HM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 1 0 0 1
Description The SHM instruction halts internal execution when acknowledging an active
HOLD (HM = 1). When HM = 0, the processor may continue execution out of
internal memory but puts its external interface in a high-impedance state. This
bit is set to 1 by a reset.
Words 1
Cycles
Operands None
Execution (PC) + 1 → PC
1 → overflow mode (OVM) status bit
Affects OVM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1
Description The OVM status bit is set to logic one, which enables the overflow (saturation)
mode. If an overflow occurs with OVM set, the overflow flag OV is set, and the
accumulator is set to the largest representable 32-bit positive (7FFFFFFFh)
or negative (80000000h) number according to the direction of overflow.
Words 1
Cycles
Example SOVM ;The overflow mode bit OVM is set, enabling the
;overflow mode on any subsequent arithmetic
;operations.
4-161
SPAC Subtract P Register From Accumulator
Operands None
Execution PC) + 1 → PC
(ACC) – (shifted P register) → ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 0 1 1 0
Description The contents of the P register, shifted as defined by the PM status bits, are sub-
tracted from the contents of the accumulator. The result is stored in the accu-
mulator. Note that SPAC is unaffected by SXM; the P register is always sign-
extended.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The high-order bits of the P register, shifted as specified by the PM bits, are
stored in data memory. Neither the P register nor the accumulator are affected
by this instruction. High-order bits are sign-extended when the right-shift by 6
mode is selected. Low-order bits are taken from the low P register when left-
shifts are selected.
Words 1
Cycles
Data Data
Memory 4567h Memory 0E079h
515 515
4-163
SPL Store Low P Register
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The low-order bits of the P register, shifted as specified by the PM bits, are
stored in data memory. Neither the P register nor the accumulator are affected
by this instruction. High-order bits are taken from the high P register when the
right-shift by 6 mode is selected. Low-order bits are zero-filled when left-shifts
are selected.
Words 1
Cycles
Data Data
Memory 4567h Memory 9844h
515 515
Operands 0 ≤ constant ≤ 3
Execution (PC) + 1 → PC
Constant → product register shift mode (PM) status bits
Affects PM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 1 0 PM
Description The two low-order bits of the instruction word are copied into the PM field of
status register ST1. The PM status bits control the P register output shifter.
This shifter has the ability to shift the P register output either one or four bits
to the left or six bits to the right, or to perform no shift. The bit combinations and
their meanings are shown below.
PM ACTION
00 No shift of multiplier output
01 Output left-shifted 1 place and zero-filled
10 Output left-shifted 4 places and zero-filled
11 Output right-shifted 6 places, sign-extended; LSB bits lost.
The left-shifts allow the product to be justified for fractional arithmetic. The
right-shift by six bits has been incorporated to implement up to 128 multiply–
accumulate processes without the possibility of overflow occurring. PM may
also be loaded by an LST1 instruction.
Words 1
Cycles
4-165
SQRA Square and Accumulate Previous Product
Description The contents of the P register, shifted as defined by the PM status bits, are add-
ed to the accumulator. The addressed data memory value is then loaded into
the T register, squared, and stored in the P register.
Words 1
Cycles
T 3h T 0Fh
P 12Ch P 0E1h
Description The contents of the P register, shifted as defined by the PM status bits, are sub-
tracted from the accumulator. The addressed data memory value is then
loaded into the T register, squared, and stored into the P register.
Words 1
Cycles
T 1124h T 8h
P 190h P 40h
4-167
SST Store Status Register ST0
In the direct addressing mode, status register ST0 is always stored in page 0,
regardless of the value of the DP register. The processor automatically forces
the page to be 0, and the specific location within that page is defined in the
instruction. Note that the DP register is not physically modified. This allows
storage of the DP register in the data memory on interrupts, etc., in the direct
addressing mode without having to change the DP. In the indirect addressing
mode, the data memory address is obtained from the auxiliary register se-
lected. (See the LST instruction for more information.)
The SST instruction can be used to store status register ST0 after interrupts
and subroutine calls. The ST0 contains the status bits: OV (overflow flag),
OVM (overflow mode), INTM (interrupt mode), ARP (auxiliary register pointer),
and DP (data memory page pointer). The status bits are stored in the data
memory word as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARP OV OVM 1 INTM DP
Note that SST * may be used to store status register ST0 anywhere in data
memory, while SST in the direct addressing mode is forced to page 0.
Words 1
Cycles
Data Data
Memory 0Ah Memory 0A408h
96 96
4-169
SST1 Store Status Register ST1
Description Status register ST1 is stored in data memory. In the direct addressing mode,
status register ST1 is always stored in page 0, regardless of the value of the
DP register. The processor automatically forces the page to be 0, and the spe-
cific location within that page is defined in the instruction. Note that the DP reg-
ister is not physically modified. This allows the storage of the DP in the data
memory on interrupts, etc., in the direct addressing mode without having to
change the DP. In the indirect addressing mode, the data memory address is
obtained from the auxiliary register selected. (See the LST1 instruction for
more information.)
SST1 is used to store status bits after interrupts and subroutine calls. ST1 con-
tains the status bits: ARB (auxiliary register pointer buffer), CNF (RAM configu-
ration control), TC (test/control), SXM (sign-extension mode), XF (external
flag), FO (serial port format), TXM (transmit mode), and the PM (product regis-
ter shift mode). ST1 on the TMS320C2x also contains the status bits: C (carry)
bit, HM (hold mode), and FSM (frame synchronization mode). The bits loaded
into status register ST1 from the data memory word are as follows:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ARB CNF † TC SXM C 1 1† HM FSM XF FO TXM PM
† On the TMS320C26, bits 12 and 7 hold CNF0 and CNF1, respectively (see the CONF
instruction for decoding).
Note that SST1 * may be used to store status register ST1 anywhere in data
memory, while SST1 in the direct addressing mode is forced to page 0.
Words 1
Cycles
Data Data
Memory 0Bh Memory 0A7E0h
97 97
4-171
SSXM Set Sign-Extension Mode
Operands None
Execution (PC) + 1 → PC
1 → SXM status bit in status register ST1
Affects SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1
Description The SSXM instruction sets the SXM status bit to logic 1, which enables sign-
extension on shifted data memory values for the following arithmetic instruc-
tions: ADD, ADDT, ADLK, LAC, LACT, LALK, SBLK, SUB, and SUBT.
In addition, SSXM affects the definition of the SFR instruction. You can load
SXM with the LST1 and RSXM instructions, as well.
Words 1
Cycles
Operands None
Execution (PC) + 1 → PC
1 → TC test/control flag in status register ST1
Affects TC.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 1 0 0 1 1
Description The TC (test/control) flag in status register ST1 is set to logic one. TC may also
be loaded by the LST1 and RTC instructions.
Words 1
Cycles
4-173
STXM Set Serial Port Transmit Mode
Operands None
Execution (PC) + 1 → PC
1 → TXM status bit in status register ST1
Affects TXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1
Description The STXM instruction sets the TXM status bit to logic 1, which configures the
serial port transmit section to a mode where the FSX pin behaves as an output.
A pulse is produced on the FSX pin each time the DXR register is loaded inter-
nally. The transmission is initiated by the negative edge of this pulse. TXM may
also be loaded by the LST1 and RTXM instructions. If the FSM status bit is a
logic zero and serial port operation has already started, the FSX pin will be driv-
en low if TXM = 1.
Words 1
Cycles
Description The contents of the addressed data memory location are left-shifted and sub-
tracted from the accumulator. During shifting, low-order bits are zero-filled.
High-order bits are sign-extended if SXM is high and zero-filled if SXM is low.
The result is stored in the accumulator.
Words 1
Cycles
4-175
SUBB Subtract from Accumulator with Borrow
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location and the value of the carry
bit are subtracted from the accumulator. The carry bit is then affected in the
normal manner (see subsection 3.5.2).
Words 1
Cycles
If ALU output ≥ 0:
Then (ALU output) × 2 + 1 → ACC;
Else (ACC) × 2 → ACC.
Affects OV.
Affects C.
Not affected by OVM (no saturation); is affected by SXM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The SUBC instruction performs conditional subtraction, which may be used for
division. The 16-bit numerator is placed in the low accumulator, and the high
accumulator is zeroed. The denominator is in data memory. SUBC is executed
16 times for 16-bit division. After completion of the last SUBC, the quotient of
the division is in the lower-order 16-bit field of the accumulator, and the remain-
der is in the high-order 16 bits of the accumulator. SUBC provides the normally
expected results for division when both the denominator and numerator are
positive. The denominator is affected by the SXM bit. If SXM=1, then the de-
nominator must have a 0 value in the MSB. If SXM=0, then any 16-bit denomi-
nator value will produce the expected results. The numerator, which is in the
accumulator, must initially be positive (that is, bit 31 must be 0) and must re-
main positive following the accumulator shift, which occurs during the SUBC
operation.
If the 16-bit numerator contains less than 16 significant bits, the numerator
may be placed in the accumulator left-shifted by the number of leading nonsig-
nificant zeroes. The number of executions of SUBC is reduced from 16 by that
number. One leading zero is always significant.
Note that SUBC affects OV but is not affected by OVM, and therefore the accu-
mulator does not saturate upon positive or negative overflows when this
instruction is executed.
Words 1
4-177
SUBC Conditional Subtract
Cycles
Example RPTK 15
SUBC DAT2 ;(DP = 4)
or
RPTK 15
SUBC * ;If current auxiliary register contains 514.
Before Instruction After Instruction
Data Data
Memory 7h Memory 7h
514 514
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location are subtracted from the
upper 16 bits of the accumulator. The 16 low-order bits of the accumulator are
unaffected. The result is stored in the accumulator. The carry bit C on the
TMS320C2x is reset if the result of the subtraction generates a borrow; other-
wise, C is unaffected.
Words 1
Cycles
4-179
SUBK Subtract from Accumulator Short Immediate
Description The 8-bit immediate value is subtracted, right-justified, from the accumulator
with the result replacing the accumulator contents. The immediate value is
treated as an 8-bit positive number, regardless of the value of SXM.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location are subtracted from the
accumulator with sign-extension suppressed. The data is treated as a 16-bit
unsigned number, regardless of SXM. The accumulator behaves as a signed
number. SUBS produces the same result as a SUB instruction with SXM = 0
and a shift count of 0.
Words 1
Cycles
4-181
SUBT Subtract from Accumulator with Shift Specified by T Register
Description The data memory value is left-shifted and subtracted from the accumulator.
The left-shift is defined by the four LSBs of the T register, resulting in shift op-
tions from 0 to 15 bits. The result replaces the accumulator contents. Sign-ex-
tension on the data memory value is controlled by the SXM status bit.
Words 1
Cycles
T 0FF98h T 0FF98h
Operands None
Execution (PC) + 1 → PC
1 → external flag (XF) pin and status bit
Affects XF.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 0 1 1 0 1
Description The XF pin and the XF status bit in status register ST1 are set to logic 1. XF
may also be loaded by the LST1 and RXF instructions.
Words 1
Cycles
Example SXF ;The XF pin and status bit are set to logic 1.
4-183
TBLR Table Read
Description The TBLR instruction transfers a word from a location in program memory to
a data memory location specified by the instruction. The program memory ad-
dress is defined by the low-order 16 bits of the accumulator. For this operation,
a read from program memory is performed, followed by a write to data memory.
In the repeat mode, TBLR effectively becomes a single-cycle instruction, and
the program counter that contains the ACCL is incremented once each cycle.
If the MP/MC pin on the TMS320C25 is low at the time of execution of this
instruction and the program memory address used is less than 4096, an on-
chip ROM location will be read.
Words 1
Cycles
Program Program
Memory 306h Memory 306h
23 23
Data Data
Memory 75h Memory 306h
518 518
4-185
TBLW Table Write
Description The TBLW instruction transfers a word in data memory to program memory.
The data memory address is specified by the instruction, and the program
memory address is specified by the lower 16 bits of the accumulator. A read
from data memory is followed by a write to program memory to complete the
instruction. In the repeat mode, TBLW effectively becomes a single-cycle
instruction, and the program counter that contains the ACCL is incremented
once each cycle.
If the MP/MC pin on the TMS320C25 is low at the time of execution of this
instruction and the program memory address used is less than 4096, an on-
chip ROM location will be addressed but not written to.
Words 1
Cycles
not applicable
Table in external memory:
1+n+np 1+2n+nd+np 2+n+np+p 2+2n+nd+np 2+n+np 2+2n+nd+np
+p
Data Data
Memory 4339h Memory 4339h
4101 4101
Program Program
Memory 306h Memory 4339h
257 257
4-187
TRAP Software Interrupt
Operands None
Execution (PC) + 1 → stack
30 → PC
Not affected by INTM; does not affect INTM.
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 1 1 0 0 0 0 1 1 1 1 0
Description The TRAP instruction is a software interrupt that transfers program control
to program memory location 30 and pushes the program counter plus one onto
the hardware stack. The instruction at location 30 may contain a branch
instruction to transfer control to the TRAP routine. Putting PC + 1 onto the stack
enables an RET instruction to pop the return PC (points to instruction after the
TRAP) from the stack.
Words 1
Cycles
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The low half of the accumulator is exclusive-ORed with the contents of the ad-
dressed data memory location. The upper half of the accumulator is not af-
fected by this instruction.
Words 1
Cycles
C C
4-189
XORK XOR Immediate with Accumulator with Shift
1 1 0 1 Shift 0 0 0 0 0 1 1 0
16-Bit Constant
Description The left-shifted 16-bit immediate constant is exclusive-ORed with the accumu-
lator, leaving the result in the accumulator. Low-order bits below and high-or-
der bits above the shifted value are treated as zeros, thus not affecting the cor-
responding bits of the accumulator. Note that the MSB, most significant bit, of
the accumulator is not affected, regardless of the shift code value.
Words 2
Cycles
C C
Operands None
Execution (PC) + 1 ≤ PC
0 ≤ ACC
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0
Description The contents of the accumulator are replaced with zero. The ZAC instruction
has been implemented as a special case of LACK. (ZAC assembles as LACK
0.)
Words 1
Cycles
Example ZAC
C C
4-191
ZALH Zero Low Accumulator and Load High Accumulator
Description ZALH loads a data memory value into the high-order half of the accumulator.
The low-order bits of the accumulator are zeroed.
Words 1
Cycles
C C
Description The ZALR instruction loads a data memory value into the high-order half of the
accumulator and rounds the value by adding 1/2 LSB; that is, the 15 low bits
(bits 0 –14) of the accumulator are set to zero, and bit 15 of the accumulator
is set to one.
Words 1
Cycles
C C
4-193
ZALS Zero Accumulator, Load Low Accumulator with Sign-Extension Suppressed
Encoding 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Description The contents of the addressed data memory location are loaded into the 16
low-order bits of the accumulator. The upper half of the accumulator is zeroed.
The data is treated as a 16-bit unsigned number rather than a 2s-complement
number. Therefore, there is no sign-extension with this instruction, regardless
of the state of SXM. (ZALS behaves the same as a LAC instruction with no
shift, and SXM = 0.)
Words 1
Cycles
C C
Software Applications
This chapter provides explanations of how to use the various TMS320C2x pro-
cessor and instruction set features along with assembly language coding ex-
amples. More information about specific applications can be found in the book,
Digital Signal Processing Applications with the TMS320 Family (literature
number SPRA012A).
The assembly source code examples in this chapter contain directives and
commands specific to the Texas Instruments Assembly Language Tools. Pub-
lication TMS320 Fixed-Point DSP Assembly Language Tools (literature num-
ber SPRU018B) is highly recommended as a reference.
The TMS320C26 is similar to the TMS320C25 except for its internal memory
configuration. This is discussed in Section 3.4 and in Appendix B.
5-1
Processor Initialization
*
.text
INIT ROVM ; DISABLE OVERFLOW MODE.
LDPK 0 ; POINT DP REGISTER TO DATA PAGE 0.
LARP 7 ; POINT TO AUXILIARY REGISTER 7.
LACK 3Fh ; LOAD ACCUMULATOR WITH 3Fh.
SACL 4 ; ENABLE ALL INTERRUPTS VIA IMR.
*
* INTERNAL DATA MEMORY INITIALIZATION.
*
5-3
Processor Initialization
*
EINT ; ENABLE ALL INTERRUPTS.
5-5
Processor Initialization
- The download begins at data block B0 (0200h) in internal space and con-
tinues until the length specified by the download mode is reached. The
appropriate memory blocks are then configured as program, and execu-
tion transfers to the first address in program block B0 (0FA00h).
- If the RS signal is not a clean TTL signal, the various processor sections
may not be properly synchronized with each other. This is because the
RS pin does not have an internal Schmidt trigger built into it. It is there-
fore recomended that you use a Schmidt-triggered gate with an RC time
constant and external switch to avoid this.
If the BIO signal is low at reset, a parallel I/O mode download will be initiated.
Otherwise, bootloader control passes to modes 2 and 3. The BIOZ (BIO pin)
test is made 36+2d cycles after reset, but it is recommended that the BIO pin
be initialized at power-up or reset. The value of d is the number of wait states
used at global memory address 08000h. In this case, a read of memory loca-
tion 08000h is used as a delay and is part of the global EPROM download op-
tion. However, the status of that test is not used until after the BIO pin has been
polled.
Each transfer of program data from the host is accomplished through a BIO
and XF handshake with the host. A data transfer is initiated by the host, driving
the BIO pin low. When the BIO pin goes low, the C26 inputs the data from port
address zero and stores it in the currently available memory location. The C26
then drives the XF pin high to indicate to the host that the data has been re-
ceived. The C26 then waits for the BIO pin to go high before setting the XF pin
low. The low status of the XF line can then be polled by the host to indicate that
the C26 is ready for another piece of data.
BIO
XF
Host
Requests ’C26 Ready Data Data Repeat
Transmit to Receive Input Was
Received
Note: The falling edge of BIO acts like a latch, causing the C26 to input the data.
5-7
Processor Initialization
Note: In all transfers, the XF pin can be ignored as long as the host allows
sufficient time for the C26 to get ready for the next transfer.
This is the first word sent to the C26. The bit fields for this word are given below.
This word defines the interrupt and final memory configuration to be installed
after bootstrapping. During the bootload process, blocks B0, B1, and B3 are
configured as data and always loaded first. This word is loaded into the C26
by a single transfer with the upper bits being masked off. The configuration is
as follows.
Bits D0–D5 are loaded into the interrupt mask register (IMR).
Bits D6 & D7 define the memory configuration after download:
D7 D6 Program Memory Data Memory
0 0 B0 B1, B2, B3
0 1 B0, B1 B2, B3
1 0 B0, B1, B3 B2
Figure 5–4. Building LENGTH From STATUS and PROGRAM LENGTH Words
X X X X X LA L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
5-9
Processor Initialization
The next LENGTH program words are then loaded into the internal RAM fol-
lowed by external data RAM at 0800h. In the 8-bit mode, two words are trans-
ferred for each complete program word. That is, 4K transfers will result in up
to 2K program words received. Also note that the maximum length can extend
past the last address of block B3, into external data memory, by 512 words.
In the 8-bit mode, the byte sequence is low to high.
The CHECKSUM word verifies the correct result of the transfer. The checksum
is defined as the lower 16 bits of the sum of all program words transferred. The
checksum does not include any control words or the final checksum sent by
the host. After completing the program transfer, the host transmits a precalcu-
lated checksum, and the C26 returns the status on the XF line and port PA0.
The checksum status definitions are shown below. In the 8-bit mode, the byte
sequence is low to high.
Note: If a checksum error occurs, this will cause the normal BIO–XF hand-
shake to fail. A host timeout (loop count) can be used to verify a failed
handshake and is a good method to detect a failed checksum as well.
After loading the CHECKSUM, the value previously transmitted in the configu-
ration word reconfigures the internal memory and interrupts. The C26 then
waits for a falling edge on the BIO pin before program control is passed to the
first address of B0. If a checksum error has occurred, this allows the host to
check the status and possibly reboot the system. When BIO goes low, program
control is always passed to the first address of program block B0, regardless
of the checksum status.
Note: Because the XF pin is used as a handshake signal during transfers with
the host, suitable software control must verify the correct sumcheck
status.
5.1.1.2 Mode 2: Serial Download From an RS232 Port (8 Data Bits, 2 Stop Bits, 1 Start Bit)
If the BIO signal is found to be high 39+2d cycles after reset, a test is made
to determine if external global memory (EPROM, mode 3) is present. If this
fails, a serial download is performed. It is recommended that you initialize the
BIO pin at reset to avoid inadvertently selecting the wrong mode. The value
of d is the number of wait states for global memory address 08000h and be-
comes part of the delay before polling the BIO pin.
The presence of an unmodified B instruction in the global data space (but not
in normal data space) determines whether there is an external EPROM in glob-
al memory. For more information, refer to subsection 5.1.1.3.
The serial link is RS232 standard, using TTL levels at the BIO and XF pins. In
this case, the BIO pin receives the data from the host via an RS232 line receiv-
er, and the XF pin sends status back to the host via a line driver. The receive
levels and data format are shown below.
1/4 75189
2
TX BIO
1/4 75188
3
RX XF
7
GND Vss
5-11
Processor Initialization
On reset, XF is driven high, indicating that a transfer has been initiated. If the
download is not successful and the checksum fails, XF is driven low, indicating
a failure. The host should wait until this time to poll the checksum verification
status. The levels are given below.
RS232 line levels are not TTL-compatible. RS232 line drivers and
receivers, such as the Texas Instruments 75188 and 75189, must be
used to interface to the RS232 level.
The first word transmitted by the host detects the baud rate by sampling the
low period of the start bit. In this case, the stop bits have been previously hold-
ing the BIO line high, and the start bit drives the line low. The next bit is data
and must be driven high. Since the data is received MSB first, the synchroniza-
tion word sent to the serial port may be 1xxxxxxx. The low period of the start
bit is sampled by using a software timing loop. The C26 then times out the re-
maining data bits (dummy bits) and waits for the next start bit (BIO going low).
Note that the serial link is not interrupt driven and therefore uses all of the avail-
able processor overhead for timing the incoming data stream.
The second word sent to the C26 is the 8-bit STATUS word. The bit fields are
given below.
Bits D0, D1, and D2 are the MSBs of the program length.
Bit D3 selects the reset/download mode:
0 = reset only (no download)
1 = start download of the program
Bit D4 selects the transmission/memory format:
0 = 8-bit format
1 = 16-bit format (not allowed in serial mode)
Bits D4–D7 should be set low. (Do not use them).
5-13
Processor Initialization
The third word defines the interrupt and final memory configuration to be
installed after bootstrapping. During the bootload process, blocks B0, B1 and
B3 are configured as data and are always loaded first. This word is loaded into
the C26 with a single transfer with the upper bits being masked off. The config-
uration is as follows.
Bits D0–D5 are loaded into the interrupt mask register (IMR)
Bits D6 & D7 define the memory configuration after download
D7 D6 Program Memory Data Memory
0 0 B0 B1, B2, B3
0 1 B0, B1 B2, B3
1 0 B0, B1, B3 B2
Figure 5–7. Building LENGTH From STATUS and PROGRAM LENGTH Words
Don’t Care STATUS PROGRAM LENGTH
Word Bits Word Bits
D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
X X X X X LA L9 L8 L7 L6 L5 L4 L3 L2 L1 L0
The next LENGTH program words are then loaded into the internal RAM fol-
lowed by external data RAM at 0800h. In the RS232 mode, two words are
transferred for each complete program word. That is, 4K word transfers will re-
sult in up to 2K program words received. Also note that the maximum length
can extend past the last address of block B3, into external data memory, by
512 words. In the RS232 mode, the byte sequence is low to high.
The CHECKSUM word is used to verify correct result of the transfer. The
checksum is defined as the lower 16 bits of the sum of all program words trans-
ferred. The checksum does not include any control words or the final check-
sum sent by the host. After completing the program transfer, the host transmits
a precalculated checksum, and the C26 returns the status on the XF line and
port PA0. The checksum status definitions are shown below. In the RS232
mode, the byte sequence is low to high.
XF=0 or PA0= 00h, indicates a checksum error.
XF=1 or PA0=0FFh, indicates a correct checksum.
SYNCHRONIZATION (1 RS232 transfer)
After loading the CHECKSUM, the value previously transmitted in the configu-
ration word reconfigures the internal memory and interrupts. The C26 then
waits for a falling edge on the BIO pin before program control is passed to the
first address of B0. If a checksum error has occurred, this allows the host to
check the status and possibly reboot the system. When BIO goes low, program
control is always passed to the first address of program block B0, regardless
of the checksum status.
Note: XF is driven high by reset and remains high to indicate that a transfer
is in progress. A high level on XF also indicates that a checksum is cor-
rect. If needed, a host timeout can be used to determine if the XF status
indicates a transfer is in progress or a correct checksum has been re-
ceived.
5-15
Processor Initialization
The signature test subtracts the value of a B instruction (0FF80h) from the re-
sulting combined 16 bits of the first two words in location 08000h. If a zero is
returned in the accumulator, it indicates that a branch was found. The
TMS320C26 performs this test in global memory by setting GREG=080h. If a
B instruction is present, it indicates that a valid EPROM may have been found.
The ’C26 performs the same test in normal data space by setting GREG=0h.
If a B instruction is present again, mode 3 is aborted and mode 2 (RS232 serial
port) operation is entered.
The downloading then continues until all of B0, B1, and B3 are filled with data
(1536 words). If additional data recovery is needed, your downloaded program
can take over. The memory to be loaded is recovered from the lower 8 data
bits (D0–D7) in a HI,LO,HI,LO order. The upper byte is masked out. The byte
ordering for the first few words, including the test branch, is shown in
Figure 5–8.
5-17
Processor Initialization
5-19
Processor Initialization
***********************************************************
* EPROM BOOTLOAD *
***********************************************************
Full_Load: lrlk AR1, LEPROM ;
Test_Load1: lark AR2, 080h ; Entry = Global DS
sar AR2, GREG ; Load length = AR1
Test_Load2: lrlk AR7, EPROM–1 ; Entry = Norm DS
lrlk AR3, ADRESS ; load destination
moreEPROM: adrk 2 ; point to LOW word
lac MASKFF ; only load lower 8 bits
and *– ; get upper 8 bits
add *+,8,AR3 ; store value
sacl * ; reloading clears MSB’s
lac *+,AR1 ; Mask upper bits
banz moreEPROM,*–,AR7 ; Finished load?
sach GREG ; Set normal DS
sblk 0FF80h ; Accu = B(ranch)?
ret ;
5-21
Program Control
5.2.1 Subroutines
The TMS320C2x has a 16-bit program counter (PC) and a eight-level hard-
ware stack for PC storage. The CALL and CALA subroutine calls store the cur-
rent contents of the program counter on the top of the stack. The RET (return
from subroutine) instruction then pops the top of the stack to the program
counter.
Example 5–6 illustrates the use of a subroutine to determine the square root
of a 16-bit number. Processing proceeds in the main routine to the point where
the square root of a number should be taken. At this point a CALL is made to
the subroutine, transferring control to that section of the program memory for
execution and then returning to the calling routine via the RET instruction when
execution has completed.
Example 5–6.Subroutines
* AUTOCORRELATION
*
* THIS ROUTINE PERFORMS A CORRELATION OF TWO VECTORS AND THEN CALLS A SQUARE ROOT
* SUBROUTINE THAT WILL DETERMINE THE RMS AMPLITUDE OF THE WAVEFORM.
*
AUTOC
.
.
.
LAC ENERGY
CALL SQRT
SACL ENERGY
.
.
.
*
* SQUARE ROOT
*
* THIS SUBROUTINE DETERMINES THE SQUARE ROOT OF A NUMBER X THAT IS LOCATED IN THE
* LOW HALF OF THE ACCUMULATOR WHEN THE ROUTINE IS CALLED. THE FRACTIONAL SQUARE
* ROOT OF XS TAKEN, WHERE 0 < X < 1 AND WHERE 1 IS REPRESENTED BY 7FFFh. THE
* RESULT IS RETURNED TO THE CALLING ROUTINE IN THE ACCUMULATOR.
*
ST0 .set 60h ; SAVED STATUS REGISTER ST0 ADDRESS
ST1 .set 61h ; SAVED STATUS REGISTER ST1 ADDRESS
NUMBER .set 62h ; NUMBER X WHOSE SQUARE ROOT IS TAKEN
TEMPR .set 63h ; INTERMEDIATE ROOTS
*
.text
SQRT SST ST0 ; SAVE STATUS REGISTER ST0.
SST1 ST1 ; SAVE STATUS REGISTER ST1.
LDPK 0 ; LOAD DATA PAGE POINTER = 0.
SSXM ; SET SIGN-EXTENSION MODE.
SPM 1 ; LEFT-SHIFT PR OUTPUT TO ACCUMULATOR.
SACL NUMBER ; SAVE X.
LARP AR1 ; INITIALIZE VARIABLES FOR SQUARE ROOT.
LARK AR1,11 ; 12 ITERATIONS
LALK 800h ; ASSUME X IS LESS THAN 200h.
SACL GUESS ; SET INITIAL GUESS TO 800h.
SACL TEMPR ; SET FIRST INTERMEDIATE ROOT TO 800h.
SACH ROOT ; SET SQUARE ROOT VALUE TO 0.
LAC NUMBER ; LOAD X INTO THE ACCUMULATOR.
SBLK 200h ; TEST IF X IS LESS THAN 200h.
BLZ SQRTLP ; IF YES, TAKE THE ROOT;
LAC GUESS,3 ; IF NO, THEN REINITIALIZE.
SACL GUESS ; SET INITIAL GUESS TO 4000h.
SACL TEMPR ; SET FIRST INTERMEDIATE ROOT TO 4000h.
LARK AR1,14 ; 15 ITERATIONS
*
* SQUARE ROOT LOOP
*
SQRTLP SQRA TEMPR ; SQUARE TEMPORARY (INTERMEDIATE) ROOT.
ZALH NUMBER ; CHECK IF RESULT IS LESS THAN X.
SPAC
BLZ NEXTLP ; IF IT’S NOT, SKIP ROOT UPDATE.
ZALH TEMPR ; IF IT IS, SET ROOT EQUAL TEMPR.
SACH ROOT
NEXTLP LAC GUESS,15 ; SCALE DOWN GUESS BY 2 TO CONVERGE.
SACH GUESS
ADDH ROOT ; ADD CURRENT ROOT ESTIMATE.
SACH TEMPR ; UPDATE TEMPORARY ROOT VALUE.
BANZ SQRTLP ; REPEAT SPECIFIED NO. OF ITERATIONS.
LAC ROOT ; LOAD THE ROOT OF X.
LST1 ST1 ; RESTORE STATUS REGISTER ST1.
LST ST0 ; RESTORE STATUS REGISTER ST0.
RET
The hardware stack is allocated for use in interrupts, subroutine calls, pipe-
lined instructions, and debugging. The TMS320C2x disables all interrupts
when it takes an interrupt trap. If interrupts are enabled more than one instruc-
tion before the return of the interrupt service routine, the routine can also be
interrupted, thus using another level of the hardware stack. This condition
should be considered when managing the use of the stack. When nesting sub-
routine calls, each call uses a level of the stack. The number of levels used by
the interrupt must be remembered as well as the depth of the nesting of sub-
routines. One level of the stack is reserved for debugging, to be used for break-
point/single-step operations. If debugging is not used, this extra level is avail-
able for internal use.
5-23
Program Control
Use the PUSH and POP instructions to access the hardware stack via the ac-
cumulator. Two additional instructions, PSHD and POPD, are included in the
instruction set so that the stack may be directly stored to and recovered from
data memory.
A software stack can be implemented by using the POPD instruction at the be-
ginning of each subroutine in order to save the PC in data memory. Then be-
fore returning from a subroutine, a PSHD is used to put the proper value back
onto the top of the stack.
When the stack has seven values stored on it and two or more values are to
be put on the stack before any other values are popped off, a subroutine that
expands the stack is needed, such as shown in Example 5–7. In this example,
the main program stores the stack starting location in memory in AR2 and indi-
cates to the subroutine whether to push data from memory onto the stack or
pop data from the stack to memory. If a zero is loaded into the accumulator
before calling the subroutine, the subroutine pushes data from memory to the
stack. If a one is loaded into the accumulator, the subroutine pops data from
the stack to memory.
Because the CALL instruction uses the stack to save the program counter, the
subroutine pops this value into the accumulator and utilizes the BACC (branch
to address specified by accumulator) instruction to return to the main program.
This prevents the program counter from being stored into a memory location.
The subroutine in Example 5–7 uses the BANZ (branch on auxiliary register
not zero) instruction to control all of its loops.
The TMS320C2x 16-bit on-chip timer and its associated interrupt perform vari-
ous functions at regular time intervals. On the TMS320C25, the timer is a down
counter that is continuously clocked by CLKOUT1 and counts (PRD + 1)
cycles of CLKOUT1. By programming the period (PRD) register from 1 to
65,535 (0FFFFh), a timer interrupt (TINT) can be generated every 2 to 65,536
cycles. (A period register value of zero is not allowed.)
Two memory-mapped registers operate the timer. The timer (TIM) register,
data memory location 2, holds the current count of the timer. At every
CLKOUT1 cycle, the TIM register is decremented by one. The PRD register,
data memory location 3, holds the starting count for the timer. When the TIM
register decrements to zero, a timer interrupt (TINT) is generated. In the follow-
ing cycle, the contents of the PRD register are loaded into the TIM register. In
this way, a TINT is generated every (PRD + 1) cycles of CLKOUT1 on the
TMS320C25.
You can read from or write to the timer and period registers on any cycle. You
can monitor the count by reading the TIM register and write a new counter peri-
od to the PRD register without disturbing the current timer count. The timer will
then start the new period after the current count is complete. If both the PRD
and TIM registers are loaded with a new period, the timer begins decrementing
the new period without generating an interrupt. Thus, you have complete con-
trol of the current and next periods of the timer.
For the TMS320C25, the TIM register is set to the maximum value on reset
(0FFFFh), and the PRD register is also initialized by reset to 0FFFFh. The TIM
register begins decrementing only after RS is deasserted. If the timer is not
used, TINT should be masked. The PRD register can then be used as a gener-
al-purpose data memory location. If you use TINT, you should program the
PRD and TIM registers before unmasking the TINT.
Example 5–8 shows the assembly code that implements the timer to divide
down the CLKOUT1 signal. To generate a 9600-Hz clock signal, load the PRD
register with 520. In the timer interrupt service routine, the XF line is toggled.
The XF output is used also as an input for BIO in this example. The output of
XF will provide a 50-percent duty cycle clock signal as long as the main routine
or other interrupt routines do not disable interrupts. Interrupts may be disabled
by direct or implied use of DINT or by executing instructions in the repeat
mode. The value for the PRD register is calculated as follows:
TMS320C25:
5-25
Program Control
5-27
Program Control
You can program a simple computed GOTO in the TMS320C2x by using the
CALA instruction. This instruction uses the contents of the accumulator as the
direct address of the call. Thus, the call address can be computed in the ALU,
as shown in Example 5–10.
5-29
Interrupt Service Routine
5-31
Interrupt Service Routine
Example 5–14. Moving External Data to Internal Data Memory With BLKD
* THIS ROUTINE USES THE BLKD INSTRUCTION TO MOVE A BLOCK OF EXTERNAL DATA MEMORY
* (DATA PAGES 8 AND 9) TO INTERNAL BLOCK B1 (DATA PAGES 6 AND 7).
*
MOVED LARP AR2
LRLK AR2,300h ; DESTINATION IS BLOCK B1 IN RAM.
RPTK 255 ; REPEAT NEXT INSTRUCTION 256 TIMES.
BLKD 400h,*+ ; MOVE EXTERNAL BLOCK TO BLOCK B1.
RET ; RETURN TO MAIN PROGRAM.
For systems that have external program memory but no external data memory,
BLKP can be used to move program memory blocks into data memory.
Example 5–15 demonstrates how to use the BLKP instruction.
5-33
Memory Management
The TBLR instruction is another method for transferring data from program
memory into data memory. When the TBLR instruction is used, a calculated,
rather than predetermined, location of a block of data in program memory may
be specified for transfer. A routine using this approach is shown in
Example 5–16.
Example 5–17. Moving Internal Data Memory to Program Memory With TBLW
* THIS ROUTINE USES THE TBLW INSTRUCTION TO MOVE DATA VALUES FROM INTERNAL DATA
* MEMORY TO EXTERNAL PROGRAM MEMORY. THE CALLING ROUTINE MUST SPECIFY THE
* DESTINATION PROGRAM MEMORY ADDRESS IN THE ACCUMULATOR. ASSUME THAT THE
* ACCUMULATOR CONTAINS THE ADDRESS IN PROGRAM MEMORY INTO WHICH THE DATA IS
* TRANSFERRED.
*
*
*
*
*
*
TABLEW LARP AR4
LRLK AR4,380 ; SOURCE ADDRESS = PAGE 7.
RPTK 127 ; TRANSFER 128 VALUES.
TBLW *+ ; MOVE DATA TO EXTERNAL PROGRAM RAM.
RET ; RETURN TO CALLING PROGRAM.
The IN and OUT instructions are used to transfer data between the data
memory and the I/O space, as shown in Example 5–18 and Example 5–19.
Example 5–18. Moving Data From I/O Space Into Data Memory With IN
* THIS ROUTINE USES THE IN INSTRUCTION TO MOVE DATA VALUES FROM THE I/O SPACE
* INTO DATA MEMORY. DATA ACCESSED FROM I/O PORT 15 IS TRANSFERRED TO SUCCESSIVE
* MEMORY LOCATIONS ON DATA PAGE 5.
*
INPUT LARP AR2
LRLK AR2,2C0h ; DESTINATION ADDRESS = PAGE 5.
RPTK 63 ; TRANSFER 64 VALUES.
IN *+,PA15 ; MOVE DATA INTO DATA RAM.
RET ; RETURN TO CALLING PROGRAM.
Example 5–19. Moving Data From Data Memory to I/O Space With OUT
* THIS ROUTINE USES THE OUT INSTRUCTION TO MOVE DATA VALUES FROM THE DATA MEMORY
* TO THE I/O SPACE. DATA IS TRANSFERRED TO I/O PORT 8 FROM SUCCESSIVE MEMORY
* LOCATIONS ON DATA PAGE 4.
*
OUTPUT LARP AR4
LRLK AR4,200h ; SOURCE ADDRESS = PAGE 4.
RPTK 63 ; TRANSFER 64 VALUES.
OUT *+,PA8 ; MOVE DATA FROM DATA RAM.
RET ; RETURN TO CALLING PROGRAM.
TMS320C26
The reconfigurable memory space of the TMS320C26 is different in both the
number of configurable blocks and the size of the blocks. For the TMS320C2x,
only 256 words in Block B0 are reconfigurable using the CNFD and CNFP
instructions. The TMS320C26 has three reconfigurable blocks —B0, B1 and
B3—each 512 words in length.
Four possible configurations for the three blocks of the TMS320C26 are set
with the immediate instruction CONF. The configuration instructions CNFD
and CNFP are not defined for the TMS320C26, and CONF is not defined for
the TMS320C2x.
Because the start and stop addresses of internal memory are not the same,
applications using the reconfigurable memory of the TMS320C2x will need to
be redefined. The memory maps and block descriptions are given in subsec-
tion 3.4.3 and in Appendix B.
5-35
Memory Management
Data 96–127
Block B2
(0060h–007Fh)
Data 512–767
Block B0
(0200h–02FFh)
Data 768–1023
Block B1
(0300h–03FFh)
Data 96–127
Block B2
(0060h–007Fh)
Prog 65280–65535
Block B0
(0FF00h–0FFFFh)
Data 768–1023
Block B1
(0300h–03FFh)
5-37
Memory Management
5-39
Memory Management
5-41
Memory Management
5-43
Fundamental Logical and Arithmetic Operations
The product register shift mode option forces all products to be shifted before
they are accumulated. The products can be left-shifted one bit to delete the
extra sign bit when two 16-bit signed numbers are multiplied. The products can
be left-shifted four bits to delete the extra sign bits in multiplying a 16-bit data
value by a 13-bit constant. The product shifter can also be used to shift all prod-
ucts six bits to the right to allow up to 128 product accumulations without the
threat of an arithmetic overflow, thereby avoiding the overhead of overflow
management. The shifter can be disabled to cause no shift in the product when
working with integer or 32-bit precision operations. This also maintains com-
patibility with TMS320C1x code. These operations are controlled by the value
contained in the PM bits of status register ST1. The SPM instruction sets the
PM bits. This feature affects all the instructions that use the product of the mul-
tiplier, that is, APAC, LTA, LTD, LTP, LTS, MAC, MACD, MPYA, MPYS, PAC,
SPAC, SPH, SPL, SQRA, and SQRS.
Because the BIT instruction requires the bit code to be specified with the
instruction, it cannot be placed in a loop to test several different bits of a data
word or bits determined by prior processing for efficient use. The TMS320C2x
also has a BITT instruction in which the bit code is specified in the T register.
Because the T register can easily be modified, BITT may be used to test all
bits of a data word if placed within a loop or to test a bit location determined
by past processing.
5-45
Advanced Arithmetic Operations
5.6.2 Scaling
Scaling the data coming into the accumulator or already in the accumulator is
useful in signal processing algorithms. This is frequently necessary in adapta-
tion or other algorithms that must compute and apply correction factors or
normalize intermediate results. Scaling and normalizing are implemented on
the TMS320C2x via right and left shifts in the accumulator and shifts of data
on the incoming path to the accumulator.
Right and left shifts of the accumulator can be performed using the SFL and
SFR instructions. SFL performs a logical left shift. SFR performs logical or
arithmetic right shifts depending on the state of the SXM bit in the status regis-
ter. A one in the SXM bit, corresponding to sign-extension enabled, causes an
arithmetic shift to be performed.
First, to double the value of a number, you need only to add it to itself. Simply
stated, the ARAU can have the current ARP=0 such that a *0+ modification will
add AR0 to itself. The code would look this way:
lrlk AR0,Value ; load a value into AR0
larp AR0 ; point the current ARP to AR0
mar *0+ ; add AR0 to itself (logical left shift!)
5-47
Advanced Arithmetic Operations
Second, for bit-reversed carry addition in the ARAU, the logic of the ARAU pro-
pogates the carries from any half adder to the right, instead of left as in a nor-
mal addition. In otherwords, bit-reversed carry addition works as if you were
looking at the inputs and outputs with a mirror; it reverses the order. Note that
this also causes the LSBs to swap places with the MSBs. Two examples are
given. Example 5–25 shows AR0 bit reverse added to itself (ARP=0).
Example 5–26 shows what is normally used in FFT bit reversals and other
DSP algorithms (ARP != 0), with a “mirror” line drawn for reference.
C C C C C 1
0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1 <–– AR0
+ 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 1 <–– AR0
0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 0 <–– New AR0
C> C> C> C> C> C> C> (last carry
is lost)
Mirror
Line
Bit-reversed carry addition is effective as a logical shifter that does not use the
accumulator in any way. Here are some other applications:
- In another application, AR0 can be loaded with a single bit. This bit is then
shifted during each pass through the main loop and used as a test bit. This
test is a successive approximation approach to calculating the square root
of a 32-bit integer. Example 5–27 shows what the code will look like.
Compare this to the same algorithm in subsection 5.2.1.
5-49
Advanced Arithmetic Operations
Example 5–27. Using the AR0 Test Bit to Calculate the Square Root of a Long Integer
***********************************************************
* LNG_SQRT.ASM Calculates the 16 bit sqrt of a long int *
* *
* long lng_sqrt(long); /* C prototype */ *
* *
* s |–––––––––––| This routine uses a succesive *
* t | AR0 | approximation technique that *
* a |–––––––––––| holds both the test bit and *
* c | AR2 | the guess in ARx registers *
* k |–––––––––––| *
* entry> | guess | mem config |pi/di| *
* |–––––––––––| –––––––––––––|–––––| *
* | input hi | cycles (pos) | 243 | *
* |–––––––––––| (0/neg) | 7 | *
* | input lo | *
* |–––––––––––| *
***********************************************************
.global _lng_sqrt
_lng_sqrt:
blez ret_0 ;
adrk 2 ; >AR0
sar AR0,*– ;store AR0 >AR2
sar AR2,*– ;store AR2 >AR3
lrlk AR0,08000h ;initial test bit
lrlk AR2,08000h ;initial guess 0
;––––––––––––––––––––––––––––––––––––––––––––––––;
; This section performs successive aproximation ;
;––––––––––––––––––––––––––––––––––––––––––––––––;
more: sar AR2,* ;store guess
lt * ;square guess (unsigned)
mpyu *– ;
pac ;
subh *– ;ACCU = guess – input
subs *+ ;
mar *+,AR0 ;
bgz too_hi,*BR0+,AR2 ;AR0>>1; guess^2 > input?
too_low mar *0+,AR0 ;add test bit if guess too low
banz more,*,AR1 ;more test bits?
b done ;
too_hi: mar *0–,AR0 ;sub test bit if guess too
high
banz more,*,AR1 ;more test bits
larp AR2 ;Always +1 LSB error
mar *–,AR1 ;subtract LSB
done: sar AR2,* ;store final guess (result)
zals *+ ;load result in ACCU
lar AR2,*+ ;restore AR0 & AR2
lar AR0,* ;
sbrk 2 ;restore AR1
ret ;
ret_0: zac ;if input <=0
ret ;then return 0
.end
The data move function allows a word to be copied from the currently ad-
dressed data memory location in on-chip RAM to the next higher location while
the data from the addressed location is being operated upon (that is, by the
CALU). The data move and the CALU operation are performed in the same
cycle. In addition, an ARAU operation may also be performed in the same
cycle when using the indirect addressing mode. The data move function is use-
ful in implementing algorithms, such as convolutions and digital filtering, where
data is being passed through a time window. It models the z – 1 delay operation
encountered in those applications. The data move function is continuous
across the boundary of the on-chip data memory blocks B0, B1, and B2. How-
ever, the data move function cannot be used if off-chip memory is referenced.
Y(n) + ȍ+
k
2
0
H(k)X(n * k)
where the H values stay the same, and the X values are shifted each time the
microprocessor performs one of the following series of multiplications (similar
to operations performed in FIR filters):
5-51
Advanced Arithmetic Operations
Program Data
Block B0 Block B1
PC H2 0FF00h 300h X2
H1 0FF01h 301h X1
H0 0FF02h 302h X0 AR1
(Coefficients) (Samples)
If the MACD instruction is replaced with the following two instructions, then the
MAC instruction can be utilized with the same results.
MAC *
DMOV *–
In cases where many more than three MACD instructions are required, the
RPT or RPTK instructions may be used with MACD, yielding the same com-
putational results but using less assembly code.
5.6.5 Multiplication
The TMS320C2x hardware multiplier normally performs 2s-complement
16-bit by 16-bit multiplies and produces a 32-bit result in one processor cycle.
A single TMS320C2x instruction, MPYU, can be used to multiply two 16-bit un-
signed numbers. To multiply two operands, one operand must be loaded into
the T register (TR). The second operand is moved by the multiply instruction
to the multiplier, which then produces the product in the P register (PR). Before
another multiply can be performed, the contents of the PR must be moved to
the accumulator. A single-multiply program is shown in Example 5–29. Pipe-
lining multiplies and PR moves makes it possible to perfom most multiply op-
erations in a single cycle.
The pipelining of the MAC and MACD instructions incurs a certain amount of
overhead in execution. In those cases where speed is more critical than pro-
gram memory, it may be beneficial to use LTA or LTD and MPY instructions
rather than MAC or MACD. Example 5–30 and Example 5–31 show an imple-
mentation of multiply-accumulates using the MAC instruction. Example 5–31
shows an implementation of multiply-accumulates using the LTA-MPY instruc-
tion pair. Figure 5–11 and Figure 5–12 provide graphically the information
necessary to determine the efficiency of use for each of the techniques.
5-53
Advanced Arithmetic Operations
ZAC ; 1 1
LT D1 ; 1 1
MPY C1 ; 1 1
LTA D2 ; 1 1
MPY C2 ; 1 1
.
. ; 2N 2N
. ;
LTA DN ; 1 1
MPY CN ; 1 1
APAC ; 1 2+2N 1 2+2N
24
22
20 X
18
Execution in Clock Cycles
16
14
12
10
6
= MAC Implementation
4 = LTA-MPY Implementation
X = Break-Even Point
2
1 2 3 4 5 6 7 8 9 10 11
5-55
Advanced Arithmetic Operations
24
22
20
Program Memory in Words
18
16
14
12
10 X
6
= MAC Implementation
4 = LTA-MPY Implementation
X = Break-Even Point
2
1 2 3 4 5 6 7 8 9 10 11
5.6.6 Division
Division is implemented on the TMS320C2x by repeated subtractions using
SUBC, a special conditional subtract instruction. Given a 16-bit positive nu-
merator and denominator, the repetition of the SUBC command 16 times pro-
duces a 16-bit quotient in the low accumulator and a 16-bit remainder in the
high accumulator.
SUBC implements binary division in the same manner as is commonly done
in long division. The numerator is shifted until subtracting the denominator no
longer produces a negative result. For each subtraction that does not produce
a negative answer, a one is put in the LSB of the quotient and then shifted. The
shifting of the remainder and quotient after each subtraction produces the sep-
aration of the quotient and remainder in the low and high halves of the accumu-
lator.
There are similarities between long division and the SUBC method of division.
Both methods are used to divide 33 by 5 in Example 5–33.
The condition of the denominator, less than the shifted numerator, is deter-
mined by the sign of the result; both the numerator and denominator must be
positive when you use the SUBC command. Thus, you must determine the
sign of the quotient and compute the quotient with the absolute value of the
numerator and denominator.
5-57
Advanced Arithmetic Operations
Integer and fractional division can be implemented with the SUBC instruction
as shown in Example 5–34 and Example 5–35, respectively. When you imple-
ment a divide algorithm, it is important to know if the quotient can be repre-
sented as a fraction and the degree of accuracy to which the quotient is to be
computed. For integer division, the absolute value of the numerator must be
greater than the absolute value of the denominator. For fractional division, the
absolute value of the numerator must be less than the absolute value of the
denominator.
000000000000110 Quotient
0000000000000101 )000000000100001
–101
110
–101
11 Remainder
SUBC Method:
RPTK 14
SUBC DENOM ; 15-CYCLE DIVIDE LOOP.
SACL QUOT
LAC TEMSGN
BGEZ DONE ; DONE IF SIGN IS POSITIVE.
ZAC
SUB QUOT
SACL QUOT ; NEGATE QUOTIENT IF NEGATIVE.
DONE LAC QUOT
RET ; RETURN TO MAIN PROGRAM.
5-59
Advanced Arithmetic Operations
5-61
Advanced Arithmetic Operations
The algorithm in Example 5–38 executes in 22 machine cycles. The key to this
performance is the parallel addressing of both multiplicands simultaneously.
The operation is made possible by the use of the data bus to fetch one multipli-
cand and the program bus to fetch the other. The auxiliary register indexes
down the column of one matrix while the PC generates incremental addres-
sing of each row of the other matrix. Each cycle of the repeat loop performs
the following operations:
The TMS320C25 has two features that help to make extended-precision cal-
culations more efficient. One of the features is the carry status bit. This bit is
affected by all arithmetic operations of the accumulator (ABS, ADD, ADDC,
ADDH, ADDK, ADDS, ADDT, ADLK, APAC, LTA, LTD, LTS, MAC, MACD,
MPYA, MPYS, NEG, SBLK, SPAC, SQRA, SQRS, SUB, SUBB, SUBC, SUBH,
SUBK, SUBS, and SUBT). The carry bit is also affected by the rotate and shift
accumulator instructions (ROL, ROR, SFL, and SFR) or may be explicitly mo-
dified by the load status register ST1 (LST1), reset carry (RC), and set carry
(SC) instructions. For proper operation, the overflow mode bit should be reset
(OVM = 0) so that the accumulator results will not be loaded with the saturation
value. Note that this means that some additional code may be required if over-
flow of the most significant portion of the result is expected.
The carry bit is set whenever the addition of a value from the input scaling shift-
er or the P register to the accumulator contents generates a carry out of bit 31.
Otherwise, the carry bit is reset because the carry out of bit 31 is a zero. One
exception to this case is the ADDH instruction, which can only set, not reset,
the carry bit. This allows the accumulation to generate the proper single carry
when the addition to either the lower or upper half of the accumulator actually
causes the carry. The following examples help to demonstrate the significance
of the carry bit on the TMS320C25 for additions:
X F F F F F F F F ACC X F F F F F F F F ACC
+ 1 +
F F F F F F F F
1 0 0 0 0 0 0 0 0 1 F F F F F F F E
X 7 F F F F F F F ACC X 7 F F F F F F F ACC
+ 1 +
F F F F F F F F
0 8 0 0 0 0 0 0 0 1 7 F F F F F F E
X 8 0 0 0 0 0 0 0 ACC X 8 0 0 0 0 0 0 0 ACC
+ 1 +
F F F F F F F F
0 8 0 0 0 0 0 0 1 1 7 F F F F F F F
1 0 0 0 0 0 0 0 0 ACC 1 F F F F F F F F ACC
+ 0 (ADDC) + 0 (ADDC)
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0
1 8 0 0 0 F F F F ACC 1 8 0 0 0 F F F F ACC
+ (ADDH) + (ADH)
0 0 0 0 0 0 0 0 7 F F F 0 0 0 0
1 8 0 0 0 F F F F 1 F F F F F F F F
5-63
Advanced Arithmetic Operations
As in addition, the carry bit on the TMS320C25 is reset whenever the input
scaling shifter or the P-register value subtracted from the accumulator con-
tents generates a borrow into bit 31. Otherwise, the carry bit is set because no
borrow into bit 31 is required. One exception to this case is the SUBH instruc-
tion, which can only reset the carry bit. This allows the generation of the proper
single carry when the subtraction from either the lower or upper half of the ac-
cumulator actually causes the borrow. The following examples help to demon-
strate the significance of the carry bit for subtractions:
X 0 0 0 0 0 0 0 0 ACC X 0 0 0 0 0 0 0 0 ACC
– 1 –
F F F F F F F F
0 F F F F F F F F 0 0 0 0 0 0 0 0 1
X 7 F F F F F F F ACC X 7 F F F F F F F ACC
– 1 –
F F F F F F F F
1 7 F F F F F F E 0 8 0 0 0 0 0 0 0
X 8 0 0 0 0 0 0 0 ACC X 8 0 0 0 0 0 0 0 ACC
– 1 –
F F F F F F F F
1 7 F F F F F F F 0
8 0 0 0 0 0 0 1
0 0 0 0 0 0 0 0 0 ACC 0 F F F F F F F F ACC
– 0 (SUBB) – 0 (SUBB)
0 F F F F F F F F 1 F F F F F F F E
0 8 0 0 0 F F F F ACC 0 8 0 0 0 F F F F ACC
– (SUBH) – (SUBH)
0 0 0 1 0 0 0 0 F F F F 0 0 0 0
0 7 F F F F F F F 0 8 0 0 1 F F F F
The coding in Example 5–40 shows the advantage of using the carry (C) sta-
tus bit on the TMS320C25.
5-65
Advanced Arithmetic Operations
*
* TAKE THE ABSOLUTE VALUE OF BOTH X AND Y.
*
ABSX ZALH X1 ; ACC = X1 00
ADDS X0 ; ACC = X1 X0
ABS
SACH X1 ; SAVE X1 .
SACL X0 ; SAVE X0 .
ABSY ZALH Y1 ; ACC = Y1 00
ADDS Y0 ; ACC = Y1 Y0
ABS
SACH Y1 ; SAVE Y1 .
SACL Y0 ; SAVE Y0 .
*
* MULTIPLY |X| AND |Y| TO PRODUCE | W |.
*
MULT LT X0 ; T = X0
MPYU Y0 ; T = X0, P = X0*Y0
SPL W0 ; SAVE W0 .
SPH W1 ; SAVE PARTIAL W1 .
MPYU Y1 ; T = X0, P = X0*Y1
LTP X1 ; T = X1, P = X0*Y0, ACC = X0*Y1
MPYU Y0 ; T = X1, P = X1*Y0, ACC = X0*Y1
ADDS W1 ; T = X1, P = X1*Y0,
5-67
Application-Oriented Operations
5.7.1 Companding
In the area of telecommunications, one of the primary concerns is the I/O band-
width in the communications channel. One way to minimize this bandwidth is
by companding (COMpress/exPAND). Companding is defined by two interna-
tional standards, A-law and µ-law, both based on the compression of the
equivalent of 13 bits of dynamic range into an 8-bit code. The standard
employed in the United States and Japan is µ-law; the European standard is
A-law. Detailed descriptions and code examples of both types are presented
in an application report on companding routines included in the book, Digital
Signal Processing Applications with the TMS320 Family (literature number
SPRA012A).
Table 5–1. Program Space and Time Requirements for µ-/A-Law Companding
Function Memory Words Program Cycles Time (µs) Required†
Program Data Initialization Loop ‡ TMS320C25
µ-Law:
Compression 74 8 19 45 4.5
Expansion 276 2 14 5 0.5
A-Law:
Compression 100 8 19 50 5
Expansion 276 2 14 5 0.5
† Assuming initialization
‡ Worst case
In expanding from the 8-bit data to the 13-bit linear representation, table look-
up is very effective because the table length is only 256 words. This is especial-
ly true for a microcomputer design because the TMS320C25 has 4K words of
mask-programmable ROM, and the TMS320E25 has 4K words of EPROM.
The table lookup technique requires three instructions (four words of program
memory), one data memory location, 256 words of table memory, and seven
instruction cycles (program in on-chip ROM) to execute.
LAC SAMPLE ;LOAD 8-BIT DATA.
ADLK MUTABL ;ADD THE CONVERSION TABLE BASE ADDRESS.
TBLR SAMPLE ;READ THE CORRESPONDING LINEAR VALUE.
When the output data has been determined in a system transmitting compan-
ded data, a compression of the data must be performed. The compression re-
duces the data back to the 8-bit format. Unless memory for a table of length
16384 is acceptable, the table lookup approach must be abandoned for con-
version routines. Details of these implementations may be found in the ap-
plication report on companding.
5-69
Application-Oriented Operations
Digital filters are a common requirement for digital signal processing systems.
The filters fall into two basic categories: finite impulse response (FIR) and Infi-
nite impulse response (IIR) filters. For either category of filter, the coefficients
of the filter (weighting factors) may be fixed or adapted during the course of
the signal processing. Presented in Digital Signal Processing Applications
with the TMS320 Family (literature number SPRA012A), an application report
discusses the theory and implementation of digital filters.
The 100-ns instruction cycle time of the TMS320C25 reduces the execution
time of all filters —especially the IIR filters —because fewer multiply/accumu-
late routines are required. Correspondingly, the amount of data memory for
samples and coefficients is not usually the limiting factor. Because of sensitiv-
ity to quantization of the coefficients themselves, IIR filters are usually imple-
mented in cascaded second-order sections. This translates to instruction code
consisting of LTD-MPY instruction pairs rather than MACDs. Example 5–42
illustrates an implementation of a second-order IIR filter.
FIR filters also benefit from the faster instruction cycle time. An FIR filter re-
quires many more multiply/accumulates than does the IIR filter with equivalent
sharpness at the cutoff frequencies and distortion and attenuation in the pass-
bands and stopbands. The TMS320C2x can help solve this problem by mak-
ing longer filters feasible to implement. This is accomplished by allowing the
coefficients to be fetched from program memory at the same time as a sample
is being fetched from data memory. The simple implementation of this process
uses the MACD instruction with the RPT/RPTK instruction.
RPTK 255
MACD COEFFP,*–
With FIR/IIR filtering, the filter coefficients may be fixed or adapted. If the coef-
ficients are adapted or updated with time, then another factor impacts the com-
putational capacity. This factor is the requirement to adapt each of the coeffi-
cients, usually with each sample. The MPYA or MPYS and ZALR instructions
on the TMS320C25 aid with this adaptation to reduce the execution time.
ȍ+*
where e(i) = x(i) – y(i)
+ * k)
N 1
and y(i) b kx(i
K 0
5-71
Application-Oriented Operations
When the MPYA and ZALR instructions on the TMS320C25 are used, the
adaptation reduces to three instructions corresponding to three clock cycles,
as shown in the following instruction sequence. Note that the processing order
has been slightly changed to incorporate the use of the MPYA instruction. This
is due to the fact that the accumulation performed by the MPYA is the accu-
mulation of the previous product.
LRLK AR2,COEFFD ; LOAD ADDRESS OF COEFFICIENTS.
LRLK AR3,LASTAP ; LOAD ADDRESS OF DATA SAMPLES.
LARP AR2
LT ERRF ; errf = 2*B*e(i)
.
.
.
ZALR *,AR3 ; ACC = bk(i)*2**16 + 2**15
MPYA *–,AR2 ; ACC = bk(i)*2**16 + errf*x(i – k) + 2**15
; PREG = errf*x(i – k + 1)
SACH *+ ; SAVE bk(i + 1).
.
.
.
Example 5–43 shows a routine to filter a signal and update the coefficients.
Example 5–44 provides the conclusion to the adaptive FIR filter routine for the
TMS320C25.
Adaptive filter length is restricted both by execution time and memory. Due to
the adaptation, there is more processing to be completed per sample , and the
adaptation itself dictates that the coefficients be stored in the reconfigurable
block of on-chip RAM. Thus, the practical limit of an adaptive filter with no ex-
ternal data memory is 256 taps.
5-73
Application-Oriented Operations
Table 5–2 provides data memory, program memory, and CPU cycles for a
256-tap adaptive FIR filter implementation using the TMS320C25. Note that
n = 256 in the table.
Table 5–2. 256-Tap Adaptive Filtering Memory Space and Time Requirements
Device Words In Memory CPU Cycles
Data Program
TMS320C25 5 + 2n 30 + 3n 33 + 4n
The TMS320C25 reduces the execution time of all FFTs by virtue of its 100-ns
instruction cycle time. In addition to the shorter cycle time, an addressing fea-
ture has been added to the TMS320C25, which provides execution speed and
program memory enhancements for radix-2 FFTs. As demonstrated in
Figure 5–13 and Figure 5–14, the inputs or outputs of an FFT are not in se-
quential order —that is, they are scrambled. The scrambling of the data ad-
dressing is a direct result of the radix-2 FFT derivation. Observation of the fig-
ures and the relationship of the input and output addressing in each case re-
veal that the address indexing is a bit-reversed order, as shown in Table 5–3.
As a result, either the data input sequence or the data output sequence must
be scrambled in association with the execution of the FFT.
5-75
Application-Oriented Operations
Figure 5–13. An In-Place DIT FFT With In-Order Outputs and Bit-Reversed Inputs
Stage 1 Stage 2 Stage 3
x(0) x(0)
W0
x(4) x(1)
W0
x(2) x(2)
W0 W2
x(6) x(3)
W0
x(1) x(4)
W0 W1
x(5) x(5)
W0 W2
x(3) x(6)
W0 W2 W3
x(7) x(7)
0 1 2 3
LEGEND FOR TWIDDLE FACTOR: W0 = W W W W
8 W1 = 8 W2 = 8 W3 = 8
Figure 5–14. An In-Place DIT FFT With In-Order Inputs but Bit-Reversed Outputs
Stage 1 Stage 2 Stage 3
x(0) x(0)
W0
x(1) x(4)
W0
x(2) x(2)
W0 W2
x(3) x(6)
W0
x(4) x(1)
W0 W1
x(5) x(5)
W0 W2
x(6) x(3)
W0 W2 W3
x(7) x(7)
0 1 2 3
LEGEND FOR TWIDDLE FACTOR: W0 = W W W W
8 W1 = 8 W2 = 8 W3 = 8
5-77
Application-Oriented Operations
The following list shows the contents of auxiliary register AR1 when AR0 is ini-
tialized with a value of 8 (8-point FFT) and when data is being transferred by
the code that follows.
MSB LSB
RPTK 7
IN *BR0+,PA0
5-79
Application-Oriented Operations
Table 5–4 shows execution speed, program memory, and data memory for an
8-point DIT FFT implementation using the TMS320C25.
5-81
Application-Oriented Operations
Analog control systems are usually based on fixed components and are not
programmable. They are also limited to using single-purpose characteristics
of the error signal, such as P (proportional), I (integral), and D (derivative), or
a combination. These limitations, along with other disadvantages of analog
systems, such as component aging and temperature drift, are reasons why
digital control systems increasingly replace analog systems in most control ap-
plications.
The most commonly used algorithm in both analog and digital control systems
is the PID (Proportional, Integral, and Derivative) algorithm. The classical PID
ŕ
algorithm is given by
u(t) + K e(t) ) K
p i edt ) K dedt
d
The PID algorithm must be converted into a digital form for implementation on
a microprocessor. Using a rectangular approximation for the integral, the PID
algorithm can be approximated as
The PID loop takes 13 cycles to execute (1.3 µs at a 40-MHz clock rate). The
TMS320 can also be used to implement more sophisticated algorithms, such
as state modeling, adaptive control, state estimation, Kalman filtering, and op-
timal control. Other functions that can be implemented are noise filtering, sta-
bility analysis, and additional control loops.
5-83
5-84 Software Applications
Chapter 6
Hardware Applications
The TMS320C2x has the power and flexibility to satisfy a wide range of system
requirements. The 128K-word address space for program and data memory
can be used to interface external memories or to implement single-chip solu-
tions. Peripheral devices can be interfaced to the TMS320C2x to perform ana-
log signal acquisition at different levels of signal quality.
The TMS320C26 is similar to the TMS320C25 except for its internal memory
configuration. This is discussed in Section 3.4 and in Appendix B.
6-1
System Control Circuitry
Note:
Reset does not have internal Schmidt hysterisis. Avoid slow rise and fall
times to insure proper reset operation.
TMS320C25
RS
+5 V
A8
R1 = 1 MΩ
C1 = 0.47 µF
DGND
For proper system initialization, the reset signal must be applied for at least
three CLKOUT cycles, that is, 300 ns for a TMS320C25 operating at 40 MHz.
Upon powerup, it can take from several to hundreds of milliseconds before the
system oscillator reaches a stable operating state. Therefore, the powerup re-
set circuit should generate a low pulse on the reset line until the oscillator is
stable (that is, 100 to 200 ms).
The voltage on the reset pin RS is controlled by the R1C1 network (see
Figure 6–1). After a reset, this voltage rises exponentially according to the time
constant R1C1, as shown in Figure 6–2. The Schmidt-Trigger inverter in this
case could be a 74HC14. If a TTL device were used, the low-level input current
(IIL) would initially cause the voltage on C1 to rise faster than expected.
6-3
System Control Circuitry
Voltage
V = VCC (1 – e – t / τ )
VCC
V1
t 0 = 0 t1 Time
The duration of the low pulse on the reset pin is approximately t1, which is the
time it takes for the capacitor C1 to be charged to 1.5 V. This is approximately
the voltage at which the reset input switches from a logic level 0 to a logic level
1. The capacitor voltage is given by
V +V CC
ƪ* ƫ
1 e *t
t (1)
ƪ ƫ
where τ = R1C1 is the reset circuit time constant. Solving (1) for τ gives
t + * R C ln 1 * VV
1 1
CC
(2)
R1 = 1 MΩ VCC = 5 V
C1 = 0.47 µF V = V1 = 1.5 V
gives t = t1 = 167 ms. In this case, the reset circuit of Figure 6–1 can generate
a low pulse of long enough duration (167 ms) to ensure the stabilization of the
oscillator upon powerup in most systems.
The master clock frequency of 40.96 MHz is chosen because it can be conve-
niently converted to the timing signals of interface circuits used by the commu-
nications industry. A combo-codec example is given in subsection 6.5.1.
74AS04 10 KΩ
4.7 kΩ
F11
CLKIN
74AS04
47 pF 0.1 µF
10 kΩ C=
20 pF
L = 1.8 µH
= Digital Ground
The 74AS04 inverter in Figure 6–3 provides the 180-degree phase shift that
a parallel oscillator requires. The 4.7-kΩ resistor provides the negative feed-
back that keeps the oscillator in a stable state; that is, the poles of the system
are constrained in a narrow region about the jω axis of the s-plane (analog do-
main). The 10-kΩ potentiometer is used to bias the 74AS04 in the linear re-
gion.
+ jƪwL *
L
z(w) C
1
wC
ƫ (3)
wp + Ǹ 1 (4)
LC
6-5
System Control Circuitry
At frequencies significantly lower than ωp , the 1/(ωC) term in (3) becomes the
dominating term, while ωL can be neglected. This gives
z(w) + jwL for w ttw p (5)
In (5), the LC circuit appears inductive at frequencies lower than ωp. On the
other hand, at frequencies much higher than ωp, the ωL term is the dominant
term in (3), and 1/(ωC) can be neglected. This gives
Based on the discussion above, the design of the LC circuit proceeds as fol-
lows: choose the pole frequency ωp approximately halfway between the crys-
tal fundamental and the third harmonic. The circuit now appears inductive at
the fundamental frequency and capacitive at the third harmonic.
| z (ω) |
Inductive Capacitive
Region Region
ω
wp + Ǹ 1 (rad/s)
LC
The emulator architecture works closely with the user’s system design to allow
the user’s memory to have maximum access times. Areas of close interaction
between the emulator and target system are:
- Bus control
- Miscellaneous considerations
Bus Control
When the emulator is halted from the keyboard or any of the breakpoint func-
tions, the current state of the device being emulated is extracted by the control
processor. This processor communicates with the emulated device over the
emulated device’s data bus. Additional communication is generated by com-
mands entered from the keyboard.
Before communication between the control processor and the device being
emulated begins, the control processor generates an interlock sequence on
the emulated device’s HOLD input in order to define data bus ownership. Once
the target HOLD is deactivated, this interlock prevents the target system from
receiving an active HOLDA until the emulator has completed accessing the
processor resources. The emulator will not attempt to use the data bus until
the interlock is successful, thus guaranteeing that it will not try to use the data
bus when HOLDA is asserted to the target system.
When communication between the control processor and the device being
emulated is complete, the hold interlock is released, and the target system can
again receive hold acknowledge when HOLD is asserted. At this point, the
emulator is waiting for another command from the keyboard. Communication
between the device being emulated and the control process occurs when DS,
PS, IS, and HOLDA are all high.
6-7
System Control Circuitry
The target system should drive the data bus only when the following conditions
are met:
- HOLDA is active, or
The XDS hardware uses the data bus only while the above signals are inactive.
When these rules are not followed, the XDS gives a PROCESSOR SYNC
LOST 1160 error. This error may also be caused by signal-to-signal shorts in
the target system, misalignment of the target connector, poor grounding of the
target connector, or wiring errors on the target system.
Because the XDS adds one internal level of 7 ns in series with the READY in-
put, your system is left with only 10 ns to generate READY. This can be accom-
plished by generating READY with a 10-ns TIBPAL16R4 device. READY
should be generated from DS, PS, or IS and the decode of the address lines.
The target system must present a valid READY high on each external access,
even when using the XDS substitution memory. Suggested implementation of
READY logic on the target system should hold READY high until target
memory requiring wait states is addressed.
The XDS provides two types of memory substitution: fast static RAM at a fixed
address and slower dynamic RAM at mappable addresses. You are is respon-
sible for deselecting target memory residing in the same address of the emula-
tor’s fast static memory if this emulator memory is mapped in. (Note that the
target should not drive the data bus on a read.) This fast static emulator sub-
stitution memory consists of 8K words of fast static RAM, which can be individ-
ually mapped in as 4K words of program memory starting at address 0000 and
4K words of data memory starting at location 0000. In this case, the target sys-
tem cannot drive the data bus even though DS or PS is active. Although this
emulator static RAM can operate with zero wait states, you can model target
wait states by using the target READY signal. However, this requires the target
system to eventually respond with a valid READY high. The emulator gener-
ates wait states until it does.
The slower dynamic RAM controls bus access through the DS or PS control
signals. The target system can drive the data bus when PS or IS is asserted.
Emulator logic assures that DS, PS, and IS are returned to their inactive state
when the dynamic RAM substitution memory uses the data bus on reads.
The dynamic RAM substitution memory always uses more than one clock to
return data. An access to address space mapped to the dynamic substitution
memory is accompanied by the assertion of DS or PS, and STRB. When the
target logic generates a READY high condition, the device appears to com-
plete the memory cycle by driving DS, PS, IS, or STRB to their inactive states
at their normal switching times. The device under emulation is held not ready
for at least one extra clock cycle or until the memory substitution data is avail-
able. The memory substitution data is then driven onto the data bus on reads
while all bus control signals at the target connector are high.
Additional wait states can be added with the use of the target READY line. In
this case, the memory control lines model the target access timing. However,
the program cycle count is affected by the additional cycles internal to the emu-
lator’s access of the dynamic RAM. Since the system responds to the READY
line, the target must eventually return a valid READY high on each access.
Miscellaneous Considerations
When the XDS is powered up, the device under emulation is placed in the run
mode with all memory substitution turned off. The control processor does not
attempt to communicate with the device under emulation until you communi-
cate with the emulator. If the target system is asserting RS, HOLD, or not
READY continuously to the device under emulation, the control processor
cannot gain control of the device under emulation and reports a PROCESSOR
SYNC LOST 1160 error. This condition can be caused by a powered-up emu-
lator plugged into a powered-down target system. Although the RS, HOLD,
and READY are pulled up with resistors on the emulator, the impedance of the
powered-down target system can assert a control signal or load the data bus
so that the XDS cannot function properly.
The conductive foam on the XDS target cable must be removed along with the
foam on the logic show pod prior to XDS powerup. Failure to do so can also
cause the PROCESSOR SYNC LOST 1160 error.
TMS320C25 Designs Using HOLD and HOLDA. When the target system as-
serts HOLD active low while the emulator is processing user-invoked com-
mands requiring access of the device-under-emulation resources, the target
will not receive HOLDA until the command is complete.
When interfacing to dynamic RAM in the target system, use READY rather
than HOLD to insert refresh cycles. A user-invoked command could hold off
HOLDA long enough to lose charge in the dynamic cells. Likewise, if the ad-
dress lines to the DRAMs are not buffered, the refresh cycle in a RAS ONLY
REFRESH system could conflict with the emulator system that controls ad-
dressing during command processing.
6-9
System Control Circuitry
Stack Usage. An interrupt is used to halt the device being emulated, thereby
using one of the emulated device stack locations. When an XDS is to be used,
the applications programmer should reserve one level of the stack for code de-
velopment.
Clock Source. The XDS does not support the use of a crystal in the target sys-
tem. The emulator’s clock source can be selected from three sources:
- A clock (with TTL levels) driven up the target cable on pin F11 (PGA) or
pin 35 (PLCC),
- Serial port
The TMS320C2x can be interfaced with PROMs, EPROMs, and static RAMs.
The speed, cost, and power limitations imposed by a particular application de-
termine the selection of a specific memory device. If speed and maximum
throughput are desired, the TMS320C2x can run with no wait states. In this
case, memory accesses are performed in a single machine cycle. Alternative-
ly, slower memories can be accessed by introducing an appropriate number
of wait states or slowing down the system clock. The latter approach is more
appropriate when interfacing to memories with access times slightly longer
than those required by the TMS320C2x at full speed.
When wait states are required, the number of wait states depends on the
memory access time (see subsection 6.2.3). With no wait states, the READY
input to the TMS320C2x can be pulled high. If one or more wait states are re-
quired, the READY input must be driven low during the cycles in which the
TMS320C2x enters a wait state.
The TMS320C2x implements two separate and distinct memory spaces: pro-
gram space (64K words) and data space (64K words). Distinction between the
two spaces is made through the use of the PS (program space) and DS (data
space) pins. A third space, the I/O space, is also available for interfacing with
peripherals. This space is selected by the IS (I/O space) pin, and is discussed
in Section 6.5.
6-11
Interfacing Memories
The following brief discussion describes the TMS320C2x read and write
cycles. For the memory read and write timing diagrams, refer to the
TMS320C2x Data Sheets in Appendix A. For further information about read
and write operation, see subsection 3.7.3 . Throughout this chapter, Q is used
to indicate the duration of a quarter phase of the output clock (CLKOUT1 or
CLKOUT2). Memory interfaces discussed in this chapter assume that the
TMS320C2x is running at 40 MHz; that is, Q = 25 ns.
1) Near the beginning of the machine cycle (CLKOUT1 goes low), the ad-
dress bus and one of the memory select signals (PS, DS, or IS) becomes
valid. R/W goes high to indicate a read cycle.
2) STRB goes low no less than tsu(A) = Q –12 ns after the address bus is valid.
3) Early in the second half of the cycle, the READY input is sampled. READY
must be stable (low or high) at the TMS320C25 no later than td(SL–R) =
Q–20 ns after STRB goes low.
4) With no wait states (READY is high), data must be available no later than
ta(SL) = ta(A) – tsu(A) = 2Q – 23 ns after STRB goes low.
The sequence of events that occurs during an external write cycle is the same
as the above, with the following differences:
3) After STRB goes high, the data bus must enter a high-impedance state no
later than tdis(D) = Q+15 ns.
The TMS320C25 expects data to be valid no later than 2Q–23 ns after STRB
goes low. (This is 27 ns for a TMS320C25 operating at 40 MHz.) The access
times of the TBP38L165-35 are 35 ns maximum from address ta(A), and 20 ns
maximum from chip enable ta(S). On the TMS320C25, address becomes valid
a minimum of tsu(A) = Q–12 ns = 13 ns before STRB goes low. Therefore, the
data appears on the data bus within 27 ns after STRB goes low, as required
by the TMS320C25.
When a read cycle is followed by a write cycle, take care to avoid bus conflict.
Bus conflict also may occur when a TMS320C25 write cycle is followed by a
memory read cycle. In this case, the TMS320C25 data lines must be in a high-
impedance state before the memory starts driving the data bus.
6-13
Interfacing Memories
J10
PS
H10
STRB
H11
R/W
+5 V
20 18 19
1k Ω 8 A0
G1 G2 G3 9 D8
B8 Q0
READY 10 D9
F1 7 A1 Q1
D0 6 A2 11 D10
E2 Q2
D1 5 13 D11
E1 A3 Q3
D2 4 14 D12
D2 A4 Q4
D3 3 15 D13
D1 A5 Q5
D4 2 A6 16 D14
C2 Q6
D5 1 17 D15
C1 A7 Q7
D6 23 A8
B2
D7 22
A2 A9
D8 21 A10
B3
D9
A3
D10 TBP38L165-35
B4
D11
A4
D12
B5
D13
A5
D14
B6
D15
CLKOUT1
ta(SL)
STRB
tsu(A)
A15–A0, Valid
PS
tdis
ta(A)
D15–D0 Data In
The most critical timing parameters of the TBP38L165 -35 direct interface to
the TMS320C25 are summarized in Table 6–1.
† Because ta(E–SL) < ta(A–SL), the specification ta(A) dominates performance. All timing compari-
sons are made from strobe low.
6-15
Interfacing Memories
H10
STRB
74AS04 MEMSTRB
F1 20 18 19
D0
E2 G1 G2 G3
D1 8 9 D8
E1 A0 Q0
D2 7 10 D9
D2 A1 Q1
D3 6 11 D10
D1 A2 Q2
D4 5 13 D11
C2 A3 Q3
D5 4 14 D12
C1 A4 Q4
D6 3 15 D13
B2 A5 Q5
D7 2 16 D14
A2 A6 Q6
D8 1 17 D15
B3 A7 Q7
D9 23
A3 A8
D10 22
B4 A9
D11 21
A4 A10
D12
B5
D13 TBP38L165-35
A5
D14
B6
D15
6-17
Interfacing Memories
CLKOUT1
CLKOUT2
ta(SL)
STRB
tsu(A) t1
MEMSTRB
ta(S)
t1
PS, DS, IS, Valid
A15–A0
t2
MEMSEL
t3
READY
tdis
t4
D15–D0 Data In
The most critical timing parameters of the TBP38L165-35 interface with ad-
dress decoding to the TMS320C25 are summarized in Table 6–2.
You can automatically generate one wait state by using the microstate com-
plete (MSC) signal. The MSC output is asserted low during CLKOUT1 low to
indicate the beginning of an internal or external memory or I/O operation (see
Figure 6–9). By gating MSC with the address and PS, DS, and/or IS, you can
generate a one-wait state READY signal. Note that MSC is a valid signal only
when CLKOUT1 is low; see page A–44.
6-19
Interfacing Memories
CLKOUT1
STRB
A15–A0, Valid
PS, DS,
or IS
R/W Valid
Ready
D15–D0
(For Read Data In
Operation)
D15–D0
(For Write Data Out
Operation)
MSC
The information on the number of wait states required for a memory or periph-
eral access is summarized in Table 6–3.
Design and timing of a wait-state generator are shown in Figure 6–10 and
Figure 6–11, respectively. In the case of one wait state, time t1 in Figure 6–11
is the time from address valid to memory select of the particular device that
requires the wait state. This corresponds to the propagation delay through the
address decode logic. For a 74AS138 decoder, t1 = 10 ns (max).
Time t2 is the time from memory select going low to CLKOUT2 going low.
t2 = tp + tsu = 11 ns + 20 ns = 31 ns
Time t3 is the time from CLKOUT2 going low to READY going high.
t3 = 19 ns + 5 ns = 24 ns
READY must remain high until it is sampled again, shortly after CLKOUT1
goes high. In Figure 6–10, READY remains high well after CLKOUT1 goes
high. On the falling edge of CLKOUT2, J = 1 and K = Q = 1 are the inputs to
the J-K flip-flop; this places the flip-flop in a toggle mode. When CLKOUT2
goes low, Q goes back to logic 1. READY goes low and stays low until one of
the inputs of the 74AS30 is pulled low.
† Connections to other devices in the system that require two wait states. (Inputs not used by other devices
should be pulled up.)
‡ Connections to other devices in the system that require one wait state. (Inputs not used by other devices should
be pulled up.)
§ Connections to other devices in the system that require zero wait states. (Inputs not used by other devices
should be pulled up.)
6-21
Interfacing Memories
CLKOUT2
t2
A15–A0, Valid
PS, DS, IS
One Wait
MEMSEL
State
t3
READY t1
A15–A0, Valid
PS, DS, IS
Two Wait
MEMSEL
States
READY
A direct interface similar to that used for PROMs may be implemented when
EPROM access time meets the TMS320C2x timing specifications. A Texas
Instruments TMS27C292-35 2K × 8-bit EPROM can interface directly to the
TMS320C25 with no wait states. The TMS27C292-35 is a CMOS EPROM with
access times of 35 ns from valid address and 25 ns from chip select.
When slower, less costly EPROMs are used, a simple flip-flop circuit (see sub-
section 6.2.2 for wait-state generator design) can be used to generate one or
more wait states. Figure 6–12 shows an EPROM interface with one wait state,
where Wafer Scale WS57C64F-12 8K × 8-bit EPROMs are interfaced to the
TMS320C25. The WS57C64F-12 is the slowest member of the WS57C64F
EPROM series but still meets the specifications for one wait state. With slower
EPROMs, however, data output turnoff can be slow and must be taken into
consideration in the design. The WS57C64F-12s are mapped at address
2000h. Figure 6–13 provides the interface timing diagram.
6-23
Interfacing Memories
CLKOUT2
STRB
t2
DTSTR
PS, R/W,
A15–A0 Valid
t1
MEMSEL
READY
t3 t4
D15–D0 Valid
An EPROM interface with two wait states is shown in Figure 6–14, in which the
TMS27C64-20 is interfaced to the TMS320C25. The TMS27C64-20 is a
CMOS 8K × 8-bit EPROM with an access time of 200 ns. The timing diagram
is shown in Figure 6–15.
6-25
Interfacing Memories
CLKOUT2
STRB
t2
DTSTR
PS, R/W,
A15–A0 Valid
t1
MEMSEL
READY
t3 t4
D15–D0 Valid
For detailed information regarding EPROM interfacing, see the application re-
port, Hardware Interfacing to the TMS320C25 (literature number SPRA014A).
In cases where RAMs of different speeds are used, separate schemes for ad-
dress decoding and READY generation can be used to meet READY timing
requirements in a manner similar to that used for the PROM interface de-
scribed in subsection 6.2.1. RAMs with similar access times may then be
grouped together in one segment of memory.
The static RAM for this interface is the Cypress Semiconductor CY7C169-25
4K × 4-bit static RAM. This RAM has a 25-ns access time from address ta(A)
and a 15-ns access time from chip enable ta(CE). Note that these access times
are fast enough so that a wait-state generator is not required for this interface.
If, however, RAMs that require wait states are used in the system, the wait-
state generator described in subsection 6.2.2 can be used.
The design shown in Figure 6–16 utilizes an approach similar to the one de-
scribed in subsections 6.2.1 and 6.2.3; that is, one address decoding scheme
is used to generate READY, and a second address decoding scheme enables
the static RAM. In this design, RAMs with no wait states are mapped at the low-
er half (lower 32K words) of the TMS320C25 data space. The upper half is
used for memories with one or more wait states. Figure 6–17 shows the timing
for memory read and write cycles.
Table 6–6 summarizes the most critical timing parameters of the CY7C169-25
interface to the TMS320C25.
6-27
Interfacing Memories
CLKOUT1
DS, Valid
A15–A0
t1
READY
STRB
R/W
t2 t3
MEMSEL
t4 Read
Cycle
TMS320C25
D15–D0 t6
t7
t5
CY7C169-25
D15–D0
R/W
MEMSEL
t9 Write
t8 Cycle
TMS320C25
D15–D0
CY7C169-25
I/O4–I/O1
6-29
Interfacing Memories
Clock input and internal clock timing relationships must be considered in the
interpretation of output timing characteristics and requirements. At the clock
input to the device, only the rising edges of the clock are used to initiate transi-
tions on internal clocks and output signals. Thus, with an input clock of a stable
frequency (regardless of duty cycle variation within specifications), extremely
symmetric timing is exhibited throughout the device. A significant conse-
quence of this is that CLKOUT1, CLKOUT2, and STRB timing skew with re-
spect to each other, and high and low pulse widths are integer multiples of Q
(the input clock period or one-fourth of the output clock period) to within a few
nanoseconds. This occurs because transitions on the output signals are initi-
ated directly from the internal clocks (Q1–Q4) and driven through identical out-
put buffer circuits. Since the internal clocks are very symmetric, close tracking
of these outputs results. The large skews in these timings, as shown in the data
sheet, are a factor of temperature and process. Because there is no variation
in process and negligible variation in temperature across a single device, the
skew of the outputs relative to the inputs is consistent for all outputs. Regard-
less of the magnitude of such skews, interfaces to the TMS320C25 can be de-
signed independently of these skews in most cases.
This section discusses three interface timings: READY, memory read, and
MSC. For READY, there are two pairs of related timings; one timing can be met
without the other one being met, and the device still guaranteed to function
properly. These pairs of timings are td(SL–R) and td(C2H–R), and th(SL–R) and
th(C2H–R). These front-end and back-end READY timings are specified with re-
spect to STRB and CLKOUT2. For zero wait-state accesses, READY is refer-
enced to STRB, but for wait-state accesses, STRB remains low and another
timing reference is required. Note that the actual timings for each of these pa-
rameter pairs are identical, and the timings with respect to CLKOUT2 and
STRB are equivalent. Therefore, if READY timing meets the requirements with
respect to one of these references (but not necessarily the other), the timing
requirements of the device are satisfied regardless of the actual skews be-
tween the two signals. For the purpose of interface timing, td(C2–S) can be as-
sumed to be 0 ns with respect to other signals on the TMS320C25. The same
is also true of td(C1–S) and tw(SL); these timings can be assumed to be Q and
2Q, respectively. These relationships are accounted for in specifications and
device testing.
In memory read operations, the two key timings, ta(A) and tsu(D)R, are related
by ta(A) = tsu(A) + tw(SL) – tsu(D)R. However, when the worst case tw(SL) specifica-
tions are used in this equation to generate an expression for ta(A), the result
differs from the specification for ta(A) in the data sheet. Both the specification
for ta(A) and tsu(D)R are tested explicitly on the device and guaranteed. This
again justifies the assumption of tw(SL) to be 2Q with respect to other signals
on the device. This is confirmed by the fact that if tw(SL) = 2Q is used to calcu-
Note that when considered in the absolute sense, timings such as tw(SL) will
have some finite tolerance, although considerably less than that specified. For
example, if STRB is used to generate a WE pulse for a device that specifies
a minimum WE low pulse width, the data sheet specification for STRB low
pulse width must be used for a worst-case design.
When you design a multiwait-state generator and use the CLKOUT1 and
CLKOUT2 signals for sequencing a state machine, specifications td(C2H–R)
and th(C2H–R) must be met. Note that these signals are measured from
CLKOUT2. If you design a single wait state, you can logically combine MSC
with the address and memory strobes to generate READY. In the latter, the pa-
rameters td(M–R) and th(M–R) must be met. In either case, both sets of param-
eters are tested and guaranteed.
Note that td(MSC) is also a parameter. As such, td(MSC) is given to locate MSC
with respect to CLKOUT1 and CLKOUT2 for a multiwait-state design. In this
case, it would be inappropriate to relate the READY timing requirements from
the CLKOUT1 signal when considering a single wait state generated directly
from MSC.
6-31
Direct Memory Access (DMA)
After control of the slave’s buses is given up to the master processor, the slave
alerts the master to this fact by asserting HOLDA. This signal may be tied to
the master TMS320C2x’s BIO pin. The slave’s XF pin may be used to indicate
to the master when it has finished performing its task and needs to be repro-
grammed or requires additional data to continue processing. In a multiple
slave configuration, priority of each slave’s task may be determined by tying
the slave’s XF signals to the appropriate INT(2–0) pin on the master
TMS320C2x.
TMS320C2x TMS320C2x
(Master) (Slave)
XF HOLD
BIO HOLDA
INT0-INT2 XF
IACK BIO
A15–A0 A15–A0
Buffer
D15–D0 and D15–D0
R/W Logic
6-33
Direct Memory Access (DMA)
Master
CPU
Address
S B Local
Y Address U Program/Data
Address
S F Data Memory
T F (RAM)
E E
M R
Address Data
Disk B
Controller U
S
Address Decode/
Arbitration HOLD
Address Logic
Data Ready HOLDA
Local Address
Program/Data Data
Memory
(RAM)
Global memory can be used in various digital signal processing tasks such as
filters or modems, where the algorithm being implemented may be divided into
sections with a distinct processor dedicated to each section. In this multipro-
cessor scheme, the first and second processors may share global data
memory, as well as the second and third, the third and fourth, etc. Arbitration
logic is required to determine which section of the algorithm is executing and
which processor has access to the global memory. With multiple processors
dedicated to distinct sections of the algorithm, throughput may be increased
via pipelined execution.
By loading the global register (GREG), you can program the size of the global
memory between 256 and 32K locations in data memory. After global memory
is defined in the GREG, the TMS320C2x asserts the BR (bus request) signal
before each global memory access. The BR signal stays low on back-to-back
cycles in the TMS320C25. The processor then inserts wait states until a bus
grant is given by asserting the READY line. Figure 6–20 illustrates such a glob-
al memory interface. Because the processors can be synchronized by using
the SYNC pin, the arbitration logic can be simplified, and the address and data
bus transfers can be more efficient (see subsection 3.10.1 for information on
synchronization).
The SYNC pin on the TMS320C2x may also be used to synchronize several
processors to allow for execution of redundant fail-safe systems. SYNC per-
mits instruction broadcasting between several processors and lock-step
execution after initial synchronization.
6-35
Global Memory
BR Arbitration BR
READY Logic READY
B B
U U
A15–A0 F F A15–A0
Global
F Data F
E Memory E
D15–D0 D15–D0
R R
S S
SYNC SYNC
Sync
Program Generation Clock Program
Memory Logic Memory
When you access the external parallel I/O ports, the access to the data bus
is multiplexed over the same pins as for a program/data memory access. The
I/O space is selected by the IS signal going active low, and the address of the
port is placed on address bits A3–A0. Address bits A15–A4 are held low.
6-37
Interfacing Peripherals
74HC390 74AS869
74AS74 1 3 14 13
1CKA 1QA CLK RCO
7 1 10
2 6 1QD S0 H
D Q 2 9
4 S1 G
1CKB 11 8
F11 3 5 ENT F
+5 V CLKIN CLK Q 1CLR 23 7
ENP E
RS CLR 10 kΩ A B C D
R1= A8 1
1 MΩ +5 V 3 4 5 6
+5 V
C1= 40.96 MHz
0.47 µF 10 kΩ
4.7 kΩ
0.1 µF
74HC04
= Analog Ground 10 kΩ
47 pF C=20 pF L=1.8 µH
74AS04
= Digital Ground
Serial port transfers are initiated by framing pulses on the FSX and FSR pins
for transmit and receive operations, respectively. For transmit operations, the
FSX pin can be configured as an input or an output. This option is selected by
the transmit mode (TXM) bit of status register ST1. In this design, FSX is as-
sumed to be configured as an input; therefore, transmit operations are initiated
by a framing pulse on the FSX pin. Upon completion of receive and transmit
operations, an RINT (serial port receive interrupt) and an XINT (serial port
transmit interrupt) are generated, respectively. Interface timing of the
TMS320C25 to the TCM29C16 corresponds to the burst-mode serial port
transmit and receive operations shown in Figure 3–37 and Figure 3–38, re-
spectively. Continuous-mode operation with or without framing pulses is also
possible.
The format (FO) bit of status register ST1 is used to select the format (8-bit byte
or 16-bit word) of the data to be received or transmitted. For interfacing the
TMS320C25 to a codec, the format bit should be set to 1, formatting the data
in 8-bit bytes.
Both of these signals can be derived from the 40.96-MHz system clock with
appropriate divider circuitry. This is the primary justification for selecting 40.96
MHz as the system clock frequency. The clock divider circuit consists of a
74AS74 D-type flip-flop, a 74HC390 decade counter, and a 74AS869 8-bit up/
down counter. The hardware connections between these devices are shown
in Figure 6–21.
The 74AS869 is configured to generate the 8-kHz clock pulse (the ripple carry
output is 2.048 MHz/256 = 8 kHz). This pulse is used by the TMS320C25 and
codec as a framing pulse to initiate data transfers.
6-39
Interfacing Peripherals
The level of the analog input signal is controlled by using the TL072 opamp
connected in the inverting configuration (see Figure 6–21). Using the 500-kΩ
potentiometer, the gain of this circuit can be varied from 0 to 5. The output of
the 0.01-µF coupling capacitor drives the TCM29C16’s internal opamp. This
opamp is connected in the inverting configuration with unity gain (feedback
and input impedances having the same value of 100 kΩ).
Four serial port modes on the TLC32040 allow direct interface to TMS320C2x
processors. When the transmit and receive sections of the AIC are operating
synchronously, it can interface to two SN54299 or SN74299 serial-to-parallel
shift registers. These shift registers can then interface in parallel to the
TMS320C2x, to other TMS320 digital signal processors, or to external FIFO
circuitry. Output data pulses are emitted to inform the processor that data
transmission is complete or to allow the DSP to differentiate between two
transmitted bytes. A flexible control scheme is provided so that the functions
of the AIC can be selected and adjusted coincidentally with signal processing
via software control. Refer to the TLC32040 data sheet for detailed information
on timing and device functions.
FSR, FSX
EODR, EODX
6-41
Interfacing Peripherals
FSR
For further information regarding the AIC interface, see page 11–196 of Linear
and Interface Circuits Applications, Volume 3: Peripheral Drivers, Data Ac-
quisition Systems, Hall-Effect Devices (literature number SLYA003), pub-
lished by Texas Instruments.
The high-speed operation of the internal logic circuitry of the TLC7524 8-bit
digital-to-analog (D/A) converter allows an interface to the TMS320C2x with
a minimum of external circuitry. Figure 6–25 shows the interface circuitry,
which consists of one SN74ALS138 3-to-8-line decoder used to decode the
address of the peripheral.
TMS320C2x
74ALS138
A0 A V0 +*V D
ref 256
A1 B Where D = Digital Input
A2 C
A3 G2B
TLC7524 Vref
IS G2A
+5 V G1 Y0 CS REF
RFB
STRB WR
8
D0–D7 D0–D7 OUT1 -
OUT2 + V0
When the TMS320C2x executes an OUT instruction (see Figure 6–28), the
peripheral address is placed on the address bus and the IS line goes low, indi-
cating that the address on the bus corresponds to an I/O port and not external
data or program memory. A low level at IS enables the 74ALS138 decoder, and
the Y-output, corresponding to the address on the bus, is brought low. When
the Y-output is brought low, the TLC7524 is enabled and the data appearing
on the data bus is latched into the D/A converter by STRB. The controlling soft-
ware for the D/A interface is given on page 11-204 of Linear and Interface Cir-
cuits Applications, Volume 3: Peripheral Drivers, Data Acquisition Systems,
Hall-Effect Devices (literature number SLYA003), published by Texas Instru-
ments.
CS
WR, STRB
-
-
A 3-line to 8-line decoder (SN74ALS138)
A quad 2-input NAND gate (SN74LS00)
- A hex inverter (SN74LS04)
-
-
A quad 2-input OR gate (SN74LS32)
A quad D-type flip-flop (SN74LS175)
6-43
Interfacing Peripherals
74ALS138
A
TLC0820
B
C +5 V Mode
G2B
IS G2A Y1 CS
Y0
+5 V G1
To TMS320C2x INT
R/W
RD
WR
STRB
D Q
D Q D Q
Q
CLR Q Q D0
CLR CLR D1
D2
D3
CLKOUT1 D4
D5
D6
D7
READY
8
The 74LS138 decodes the addresses assigned to the TLC0820. One of the
addresses is used for a write operation; the other is used for a read operation.
The two different addresses are necessary to ensure that the correct number
of wait states is provided for the write and read operations. The controlling soft-
ware for the A/D interface is given on page 11–206 of Linear and Interface Cir-
cuits Applications, Volume 3: Peripheral Drivers, Data Acquisition Systems,
Hall-Effect Devices (literature number SLYA003), published by Texas Instru-
ments.
With the TMS320C2x running at 20 MHz and the TLC0820 configured as slow
memory, three wait states are necessary to provide a write pulse of sufficient
length. After conversion has begun (with the rising edge of the WR signal), the
TMS320C2x must wait at least 600 ns before the conversion result can be
read. Sufficient delay should be provided in software. To read the conversion
result, an adequate number of wait states must be provided to allow for the
data access time (320 ns minimum) of the TLC0820. As shown in the IN
instruction timing diagram of Figure 6–28, two wait states are provided when
accessing port 1.
CLKOUT1
CLKOUT2
STRB
A15–A0
Address Valid
IS, R/W
RD, WR
CS
READY
D15–D0 Data In
6-45
Interfacing Peripherals
TMS320C2x +5 V
Signals 74AS138
G1 Y7 I/O PORT 7
IS G2A Y6 I/O PORT 6
A3 G2B Y5 I/O PORT 5
Y4 I/O PORT 4
Y3 I/O PORT 3
A2 C Y2 I/O PORT 2
A1 B Y1 I/O PORT 1
A0 A Y0 I/O PORT 0
TMS320C2x TMS70C42
IS Decode Control
PA3–PA0 Logic Pins
L
A
T
C
D15–D0 H Data
L
A
T
Program C
Memory H
6-47
System Applications
TMS29C16 Line
Interface
CODEC
TMS320C25
Phone
Lines
TCM29C16
TMS320C2x Codec Analog
or Interface
TLC32040
AIC
External
Data
Memory
(Optional)
6-49
System Applications
Control Display
Interface Display
H
o TMS320C2x Address TMS34010
s DSP GSP
t TMS34070
Data
Color
B Palette
u
s
Memory
PROM TMS4256 TMS4461
or DRAM VRAM
SRAM
(Optional)
Axis
1
.
.
Memory Wait State/ .
Address To Peripherals Axis
PROM
or SRAM Decode n
(Optional)
I/O
Host Data Analog
TMS320C2x Interface Interface
CPU Memory
A/D – D/A
6-51
6-52 Hardware Applications
Appendix A
This appendix contains data sheet information on the TMS320C25 digital sig-
nal processors family, which includes the following devices:
- TMS320C25
- TMS320C25-33
- TMS320C25-50
- TMS320E25
A-1
TMS320C25 and TMS320E25 Digital Signal Processors
This appendix contains data sheet information on the TMS320C26 digital sig-
nal processor.
B-1
TMS320C26 Digital Signal Processor
This appendix contains data sheet information on the TMS320C28 digital sig-
nal processor.
C-1
TMS320C28 Digital Signal Processor
This appendix details the instruction cycle timings for the TMS320C2x proces-
sor. Instructions are first listed in a table according to cycle classification. Then
each class of instructions is listed in another table, showing the number of
cycles required for a TMS320C2x instruction to execute in a given memory
configuration singly or in repeat mode. The column headings in the tables indi-
cate the program source location (PI, PE, or PR) and data destination or
source (DI or DE), defined as follows:
PI The instruction executes from internal program memory (RAM).
PR The instruction executes from internal program memory (ROM).
PE The instruction executes from external program memory.
DI The instruction executes using internal data memory.
DE The instruction executes using external data memory.
The number of cycles required for each instruction is given in terms of the pro-
gram/data memory and I/O access times as defined in the following listing:
p Program memory wait states. Represents the number of clock cycles the
device waits for external program memory to respond to an access. Tac is
the TMS320C2x access time, in nanoseconds (maximum), required for
an external memory access with no wait states. Tmem is the memory ac-
cess time, and Tp is the clock period (4/crystal frequency).
p = 0; If Tmem ≤ Tac
p = 1; If Tac < Tmem ≤ (Tp + Tac )
p = 2; If (Tp + Tac ) < Tmem ≤ (Tp × 2 + Tac)
p = k; If [Tp × (k – 1) + Tac] < Tmem ≤ (Tp × k + Tac)
d Data memory wait states. Represents the number of cycles the device
must wait for external data memory to respond to an access. This num-
ber is calculated in the same way as the p number.
i I/O memory wait states. Represents the number of cycles the device
must wait for external I/O memory to respond to an access. This number
is calculated in the same way as the p number.
Other abbreviations used in the tables and their meanings are as follows:
br Branch from ...
int Internal program memory.
INT Interrupt.
ext External program memory.
n The number of times an instruction is executed when using the RPT or
RPTK instruction.
D-1
TMS320C2x Instruction Cycle Timings
Table D–2. Cycle Timings for Cycle Classes When Not in Repeat Mode
D-3
TMS320C2x Instruction Cycle Timings
Table D–2. Cycle Timings for Cycle Classes When Not in Repeat Mode (Concluded)
CLASS PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE
XIII Source data in on-chip RAM:
3 3+d 3+2p 3+d+2p 3 3+d
Source data in external memory:
4+d 4+2d 4+d+2p 4+2d+2p 4+d 4+2d
XIV Table in on-chip RAM:
3 3+d 4+2p 4+d+2p 4 4+d
Table in on-chip ROM:
4 4+d 4+2p 4+d+2p 4 4+d
Table in external memory:
4+p 4+d+p 4+3p 4+d+3p 4+p 4+d+p
XV (Interrupt) destination on-chip ROM
3 (minimum waits for INT)
(Interrupt) destination external memory
3+2p (minimum waits for INT)
Table D–3. Cycle Timings for Cycle Classes When in Repeat Mode
CLASS PI/DI PI/DE PE/DI PE/DE PR/DI PR/DE
I n 1+n+nd n+p 1+n+nd+p n 1+n+nd
II n 2n+nd n+p 2n+nd+p n 2n+nd
III n n+nd n+p 1+n+nd+p n n+nd
IV n n n+p n+p n n
V not repeatable
VI Table in on-chip RAM:
2+n 2+2n+nd 3+n+2p 3+2n+nd+2p 3+n 3+2n+nd
Table in on-chip ROM:
3+n 3+2n+nd 3+n+2p 3+2n+nd+2p 3+n 3+2n+nd
Table in external memory:
3+n+np 3+2n+nd+np 3+n+np+2p 3+2n+nd+np 3+n+np 3+2n+nd+np
+2p
VII not repeatable
VIII not repeatable
IX 1+n+ni 2n+nd+ni 1+n+p+ni 1+2n+nd+p 1+n+ni 2n+nd+ni
+ni
X n+ni 2n+nd+ni 1+n+p+ni 1+2n+nd+p n+ni 2n+nd+ni
+ni
XI Table in on-chip RAM:
1+n 1 + n + nd 2+n+p 2+n+nd+p 2+n 2+n+nd
Table in on-chip ROM:
2+n 2+n+nd 3+n+p 3+n+nd+p 3+n 3+n+nd
Table in external memory:
2+n+np 1+2n+nd+np 3+n+np+p 2+2n+nd+np 3+n+np 2+2n+nd+np
+p
XII Table in on-chip RAM:
1+n 2+n+nd 2+n+p 3+n+nd+p 2+n 3+n+nd
Table in on-chip ROM:
not applicable
Table in external memory:
1+n+np 1+2n+nd+np 2+n+np+p 2+2n+nd+np+p 2+n+np 2+2n+nd+np
XIII Source data in on-chip RAM:
2+n 2+n+nd 2+n+2p 2+n+nd+2p 2+n 2+n+nd
Source data in external memory:
3+n+nd 2+2n+2nd 3+n+nd+2p 2+2n+2nd 3+n+nd 2+2n+2nd
+2p
XIV Table in on-chip RAM:
2+n 2+n+nd 3+n+2p 3+n+nd+2p 3+n 3+n+nd
Table in on-chip ROM:
3+n 3+n+nd 3+n+2p 3+n+nd+2p 3+n 3+n+nd
Table in external memory:
3+n+np 2+2n+nd+np 3+n+np+2p 2+2n+nd+np 3+n+np 2+2n+nd+np
+2p
XV not repeatable
D-5
D-6 Instruction Cycle Timings
Appendix E
This appendix contains data sheet information on the SMJ320C2x digital sig-
nal processors family.
E-1
SMJ320C2x Digital Signal Processors
68-PIN GB
PIN GRID ARRAY CERAMIC PACKAGE†
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11
PRODUCTION DATA information is current as of publication date. Copyright 1992, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
• Single-Cycle Multiply/Accumulate
Instructions
description
The SMJ320C26 Digital Signal Processor is a member of the TMS320 family
of VLSI digital signal processors and peripherals. The TMS320 family sup-
ports a wide range of digital signal processing applications, such as telecom-
munications, modems, image processing, speech processing, spectrum anal-
ysis, audio processing, digital filtering, high-speed control, graphics, and other
computation intensive applications.
READY
MP/MC
HOLD
CLKR
CLKX
VCC
VCC
D10
D12
D13
D14
D15
D11
BIO
processor.
RS
D8
D9
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
The SMJ320C26 scaling shifter has VSS 10 60 IACK
a 16-bit input connected to the data D7 11 59 MSC
D6 12 58 CLKOUT1
bus and a 32-bit output connected to D5 13 57 CLKOUT2
the ALU. The scaling shifter pro- D4 14 56 XF
D3 15 55 HOLDA
duces a left shift of 0 to 16 bits on the D2 16 54 DX
input data, as programmed in the D1 17 53 FSX
D0 18 52 X2/CLKIN
instruction. The LSBs of the output SYNC 19 51 X1
are filled with zeroes, and the MSBs INT0 20 50 BR
INT1 21 49 STRB
may be either filled with zeroes or INT2 22 48 R/W
sign-extended, depending upon the VCC 23 47 PS
DR IS
status programmed into the SXM FSR
24 46
DS
25 45
(sign-extension mode) bit of status A0 26 44 VSS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
register ST1.
A10
A12
A13
A14
A15
A11
VCC
A1
A2
A3
A4
A5
A6
A7
A8
A9
VSS
E-5
Running Title—Attribute Reference
PIN NOMENCLATURE
NAME I/O/Z† DEFINITION
VCC I 5-V supply pins.
VSS I Ground pins.
X1 O Output from internal oscillator for crystal.
X2/CLKIN I Input to internal oscillator from crystal or external clock.
CLKOUT1 O Master clock output (crystal or CLKIN frequency/4).
CLKOUT2 O A second clock output signal.
D15–D0 I/O/Z 16-bit data bus D15 (MSB) through D0 (LSB). Multiplexed between program, data and I/O spaces.
A15–A0 O/Z 16-bit address bus A15 (MSB) through A0 (LSB).
PS, DS, IS O/Z Program, data and I/O space select signals.
R/W O/Z Read/write signal.
STRB O/Z Strobe signal.
RS I Reset input.
INT2, INT1, INT0 I External user interrupt inputs.
MP/MC I Microprocessor/microcomputer mode select pin.
MSC O Microstate complete signal.
IACK O Interrupt acknowledge signal.
Data ready input. Asserted by external logic when using slower devices to indicate that the current bus transaction
READY I
is complete.
BR O Bus request signal. Asserted when the SMJ320C26 requires access to an external global data memory space.
XF O External flag output (latched software – programmable signal).
Hold input. When asserted, SMJ320C26 goes into an idle mode and places the data address and control lines
HOLD I
in the high-impedance state.
HOLDA O Hold acknowledge signal.
SYNC I Synchronization input.
BIO I Branch control input. Polled by BIOZ instruction.
DR I Serial data receive input.
CLKR I Clock input for serial port receiver.
FSR I Frame synchronization pulse for receive input.
DX O/Z Serial data transmit output.
CLKX I Clock input for serial port transmitter.
FSX I/O/Z Frame synchronization pulse for transmit. May be configured as either an input or an output.
† I/O/Z denotes input/output/high-impedance state.
E-7
Running Title—Attribute Reference
PROGRAM BUS
CLKOUT1
CLKOUT2
X2/CLKIN
16
SYNC
16
DS
PS
X1
IS
QIR(16)
16 IR(16)
16 ST0(16)
R/W 16 ST1(16)
STRB RPTC(8)
PFC(16)
READY IFR(6)
CONTROLLER
BR 16 16 DR
XF 16 MUX
16 CLKR
HOLD
FSR
HOLDA MCS(16) PC(16) DX
MSC
16 CLKX
BIO 16
16 16 FSX
RS
IACK STACK RSR(16)
ADDRESS
(8 - 16) XSR(16)
MP/MC 16
PROGRAM DRR(16)
3 ROM 16
INT(2-0) DXR(16)
16 (256 x 16) 16
TIM(16)
16 16
MUX
D15–D0 16 16 16
PROGRAM BUS
DATA BUS
16
16
16 16
3 16 16 AR0(16) MUX
SHIFTER(0–16) TR(16)
AR1(16) 9
16
3
ARP(3) AR2(16)
MULTIPLIER
AR3(16) DP(9)
AR4(16)
3 7 LSB
AR5(16) FROM PR(32)
9 IR
AR6(16)
32
ARS(3) AR7(16) 16 32
16
3
SHIFTER (6.0.1.4)
ARAU(16) MUX 16
MUX
32
MUX MUX MUX MUX
16 16 16 16
ALU(32)
DATA DATA/PROG DATA/PROG DATA/PROG 32
RAM (32 x 16) RAM (512 x 16) RAM (512 x 16) RAM (512 x 16) 32
BLOCK B2 BLOCK B3 BLOCK B1 BLOCK B0
C ACCH(16) ACCL(16)
32
LEGEND:
ACCH = Accumulator high IFR = Interrupt flag register PC = Program counter
ACCL = Accumulator low IMR = Interrupt mask register PFC = Prefetch counter
ALU = Arithmetic logic unit IR = Instruction register RPTC = Repeat instruction counter
ARAU = Auxiliary register arithmetic unit MCS = Microcall stack GREG = Global memory allocation register
ARS = Auxiliary register pointer buffer QIR = Queue instruction register RSR = Serial port receive shift register
ARP = Auxiliary register pointer PR = Product register XSR = Serial port to transmit shift register
DP = Data memory page pointer PRD = Product register for timer AR0–AR7 = Auxiliary registers
DRR = Serial port data receive register TIM = Timer ST0, ST1 = Status registers E-9
DXR = Serial port data trademark register TR = Temporary register C = Carry bit
Running Title—Attribute Reference
architecture
The SMJ320C26 architecture is based on the SMJ320C25 with a different in-
ternal RAM and ROM configuration. The SMJ320C26 integrates 256 words of
on-chip ROM and 1568 words of on-chip RAM compared to 4K words of on-
chip ROM and 544 words of on-chip RAM for the SMJ320C25. The
SMJ320C26 is pin for pin compatible with the SMJ320C25.
Increased throughput on the SMJ320C26 for many DSP applications is ac-
complished by means of single cycle multiply/accumulate instructions with a
data move option, eight auxiliary registers with a dedicated arithmetic unit, and
faster I/O necessary for data intensive signal processing.
The architectural design of the SMJ320C26 emphasizes overall speed, com-
munication, and flexibility in the processor configuration. Control signals and
instructions provide floating point support, block memory transfers, communi-
cation to slower off-chip devices, and multiprocessing implementations.
Three large on-chip RAM blocks, configurable either as separate program and
data spaces or as three contiguous data blocks, provide increased flexibility
in system design. Programs of up to 256 words can be masked into the internal
program ROM. The remainder of the 64K-word program memory space is lo-
cated externally. Large programs can execute at full speed from this memory
space. Programs can also be downloaded from slow external memory to high
speed on-chip RAM. A data memory address space of 64K words is included
to facilitate implementation of DSP algorithms. The VLSI implementation of
the SMJ320C26 incorporates all of these features as well as many others, in-
cluding a hardware timer, serial port, and block data transfer capabilities.
32-bit ALU accumulator
The SMJ320C26 32-bit Arithmetic Logic Unit (ALU) and accumulator perform
a wide range of arithmetic and logic instructions, the majority of which execute
in a single clock cycle. The ALU executes a variety of branch instructions de-
pendent on the status of the ALU or a single bit in a word. These instructions
provide the following capabilities:
- Branch to an address specified by the accumulator.
- Normalize fixed point numbers contained in the accumulator.
- Test a specified bit of a word in data memory.
One input to the ALU is always provided from the accumulator, and the other
input may be provided from the Product Register (PR) of the multiplier or the
input scaling shifter which has fetched data from the RAM on the data bus. Af-
ter the ALU has performed the arithmetic or logical operations, the result is
stored in the accumulator.
The 32-bit accumulator is split into two 16-bit segments for storage in data
memory. Additional shifters at the output of the accumulator perform shifts
while the data is being transferred to the data bus for storage. The contents
of the accumulator remain unchanged.
scaling shifter
The SMJ320C26 scaling shifter has a 16-bit input connected to the data bus
and a 32-bit output connected to the ALU. The scaling shifter produces a left
shift of 0 to 16-bits on the input data, as specified in the instruction word. The
LSBs of the output are filled with zeroes, and the MSBs may be either filled with
zeroes or sign extended, depending upon the value of the SXM (sign extension
mode) bit of status register STO.
16 × 16 bit parallel multiplier
The SMJ320C26 has a 16 × 16 bit-hardware multiplier, which is capable of
computing a signed or unsigned 32-bit product in a single machine cycle. The
multiplier has the following two associated registers:
- A 16-bit Temporary Register (TR) that holds one of the operands for the
multiplier, and
Four product shift modes are available at the Product Register (PR) output that
are useful when performing multiply/accumulate operations, fractional arith-
metic, or justifying fractional products.
timer
The SMJ320C26 provides a memory mapped 16-bit timer for control opera-
tions. The on-chip timer (TIM) register is a down counter that is continuously
clocked by CLKOUT1. A timer interrupt (TINT) is generated every time the tim-
er decrements to zero, provided the timer interrupt is enabled. The timer is re-
loaded with the value contained in the period (PRD) register within the next
cycle after it reaches zero so that interrupts may be programmed to occur at
regular intervals of PRD + 1 cycles of CLKOUT1.
memory control
The SMJ320C26 provides a total of 1568 words of 16 bit on-chip RAM, divided
into four separate blocks (B0, B1, B2, and B3). Of the 1568 words, 32 words
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Running Title—Attribute Reference
(block B2) are always data memory, and all other blocks are programmable as
either data or program memory. A data memory size of 1568 words allows the
SMJ320C26 to handle a data array of 1536 words, while still leaving 32 loca-
tions for intermediate storage. When using B0, B1, or B3 as program memory,
instructions can be downloaded from external memory into on-chip RAM, and
then executed.
When using on-chip program RAM, ROM, or high speed external program
memory, the SMJ320C26 runs at full speed without wait states. However, the
READY line can be used to interface the SMJ320C26 to slower, less expen-
sive external memory. Downloading programs from slow off-chip memory to
on-chip program RAM speeds processing and cuts overall system costs.
CONFIGURATION B0 B1 B3
0 Data Data Data
1 Program Data Data
2 Program Program Data
3 Program Program Program
Regardless of the configuration, the user may still execute from external pro-
gram memory.
The SMJ320C26 provides a ROM of 256 words. The ROM is sufficient to allow
the programming of a bootstrap program and interrupt handler, or to imple-
ment self test routines.
The SMJ320C26 has six registers that are mapped into the data memory
space at the locations 0–5; a serial port data receive register, serial port data
transmit register, timer register, period register, interrupt mask register, and
global memory allocation register.
PROGRAM DATA I/
0 (0000h) 0 (0000h) 0
INTERRUPTS ON-CHIP
AND RESERVED MMRs EXTER
(EXTERNAL) 5 (0005h) 15
31 (001Fh) 6 (0006h)
32 (0020h) RESERVED PAGE 0
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
RESERVED PAGE 1-3
511 (01FFh)
512 (0200h)
ON-CHIP PAGE 4-7
EXTERNAL BLOCK B0
1023 (03FFh)
1024 (0400h)
ON-CHIP
BLOCK B1 PAGE 8-11
1535 (05FFh)
1536 (0600h)
ON-CHIP
BLOCK B3 PAGE 12-15
2047 (07FFh)
2048 (0800h)
EXTERNAL PAGE 16-511
65535 (FFFFh) 65535 (FFFFh)
2 MP/MC = 0
PROGRAM DATA I/
0 (0000h) 0 (0000h) 0
INTERRUPTS ON-CHIP
MMRs EXTER
AND RESERVED
BOOTLOAD ROM 5 (0005h) 15
6 (0006h)
255 (00FFh) RESERVED PAGE 0
95 (005Fh)
256 (0100h) 96 (0060h)
ON-CHIP
RESERVED BLOCK B2
127 (007Fh)
4095 (0FFFh) 128 (0080h)
4096 (1000h) RESERVED PAGE 1-3
511 (01FFh)
512 (0200h)
ON-CHIP PAGE 4-7
BLOCK B0
1023 (03FFh)
1024 (0400h)
ON-CHIP
EXTERNAL BLOCK B1 PAGE 8-11
1535 (05FFh)
1536 (0600h)
ON-CHIP
BLOCK B3 PAGE 12-15
2047 (07FFh)
2048 (0800h)
EXTERNAL PAGE 16-511
65535 (FFFFh)
65535 (FFFFh)
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Running Title—Attribute Reference
PROGRAM DATA I/
0 (0000h) 0 (0000h) 0
INTERRUPTS ON-CHIP
MMRs EXTER
AND RESERVED
(EXTERNAL) 5 (0005h) 15
31 (001Fh) 6 (0006h)
32 (0020h) RESERVED PAGE 0
95 (005Fh)
96 (0060h)
ON-CHIP
BLOCK B2
127 (007Fh)
EXTERNAL 128 (0080h)
RESERVED PAGE 1-3
511 (01FFh)
512 (0200h)
DOES NOT PAGE 4-7
63999 (F9FFh) EXIST
64000 (FA00h) 1023 (03FFh)
ON-CHIP 1024 (0400h)
BLOCK B0 ON-CHIP
BLOCK B1 PAGE 8-11
64511 (FBFFh)
64512 (FC00h) 1535 (05FFh)
EXTERNAL 1536 (0600h)
ON-CHIP
BLOCK B3 PAGE 12-15
65023 (FDFFh)
65024 (FE00h) 2047 (07FFh)
2048 (0800h)
EXTERNAL EXTERNAL PAGE 16-511
65535 (FFFFh)
65535 (FFFFh)
2 MP/MC = 0
PROGRAM DATA I/
0 (0000h) INTERRUPTS 0 (0000h) 0
ON-CHIP
AND RESERVED MMRs EXTER
BOOTLOAD ROM 5 (0005h) 15
255 (00FFh) 6 (0006h)
256 (0100h) RESERVED PAGE 0
RESERVED
4095 (0FFFh) 95 (005Fh)
96 (0060h)
4096 (1000h) ON-CHIP
BLOCK B2
127 (007Fh)
128 (0080h)
RESERVED PAGE 1-3
EXTERNAL 511 (01FFh)
512 (0200h)
DOES NOT PAGE 4-7
EXIST
1023 (03FFh)
63999 (F9FFh) 1024 (0400h)
ON-CHIP
64000 (FA00h) BLOCK B1 PAGE 8-11
ON-CHIP
BLOCK B0 1535 (05FFh)
64511 (FBFFh) 1536 (0600h)
64512 (FC00h) ON-CHIP
BLOCK B3 PAGE 12-15
EXTERNAL
65023 (FDFFh) 2047 (07FFh)
65024 (FE00h) 2048 (0800h)
EXTERNAL EXTERNAL PAGE 16-511
65535 (FFFFh) 65535 (FFFFh)
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Running Title—Attribute Reference
2 MP/MC = 0
127 (007Fh)
EXTERNAL 128 (0080h)
RESERVED PAGE 1-3
511 (01FFh)
512 (0200h)
DOES NOT PAGE 4-7
EXIST
63999 (F9FFh) 1023 (03FFh)
64000 (FA00h) 1024 (0400h)
ON-CHIP DOES NOT
EXIST PAGE 8-11
BLOCK B0
64511 (FBFFh) 1535 (05FFh)
64512 (FC00h) ON-CHIP 1536 (0600h)
ON-CHIP
BLOCK B1 BLOCK B3 PAGE 12-15
65023 (FDFFh) 2047 (07FFh)
65024 (FE00h) 2048 (0800h)
EXTERNAL EXTERNAL PAGE 16-511
65535 (FFFFh) 65535 (FFFFh)
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Running Title—Attribute Reference
2 MP/MC = 0
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Running Title—Attribute Reference
external interface
A serial port provides communication with serial devices, such as codecs, seri-
al A/D converters, and other serial systems. The interface signals are compat-
ible with codecs and many other serial devices with a minimum of external
hardware. The serial port may also be used for intercommunication between
processors in multiprocessing applications.
The serial port has two memory mapped registers; the data transmit register
(DXR) and the data receive register (DRR). Both registers operate in either the
byte mode or 16-bit word mode, and may be accessed in the same manner
as any other data memory location. Each register has an external clock, a
framing signal, and associated shift registers. One method of multiprocessing
may be implemented by programming one device to transmit while the others
are in the receive mode.
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Running Title—Attribute Reference
multiprocessing
- A standalone processor.
The SMJ320C26 supports DMA (direct memory access) to its external pro-
gram/data memory using the HOLD and HOLDA signals. Another processor
can take complete control of the SMJ320C26’s external memory by asserting
HOLD low. This causes the SMJ320C26 to place its address, data, and control
lines in a high impedance state, and assert HOLDA.
addressing modes
The SMJ320C26 instruction set provides three memory addressing modes; di-
rect, indirect, and immediate addressing.
Both direct and indirect addressing can be used to access data memory. In di-
rect addressing, seven bits of the instruction word are concatenated with the
nine bits of the data memory page pointer to form the 16-bit data memory ad-
dress. Indirect addressing accesses data memory through the eight auxiliary
registers. In immediate addressing, the data is embedded in the instruction
word(s).
In direct addressing, the instruction word contains the lower seven bits of the
data memory address. This field is concatenated with the nine bits of the data
memory page pointer to form the full 16-bit address. Thus, memory is paged
in the direct addressing mode with a total of 512 pages, each page containing
128 words.
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Running Title—Attribute Reference
Eight auxiliary registers (AR0–AR7) provide flexible and powerful indirect ad-
dressing. To select a specific auxiliary register, the Auxiliary Register Pointer
(ARP) is loaded with a value from 0 through 7 for AR0 through AR7 respective-
ly.
There are seven types of indirect addressing: auto increment, auto decrement,
post indexing by either adding or subtracting the contents of AR0, single indi-
rect addressing with no increment or decrement and bit reversal addressing
(used in FFTs) with increment or decrement. All operations are performed on
the current auxiliary register in the same cycle as the original instruction, fol-
lowed by an ARP update.
repeat feature
A repeat feature, used with instructions such as multiply/accumulates, block
moves, I/O transfers, and table read/writes, allows a single instruction to be
executed up to 256 times. The repeat counter (RPTC) is loaded with either a
data memory value (RPT instruction) or an immediate value (RPTK instruc-
tion). The value of this operand is one less than the number of times that the
next instruction is executed. Those instructions that are normally multicycle
are pipelined when using the repeat feature, and effectively become single-
cycle instructions.
instruction set
The SMJ320C26 microprocessor implements a comprehensive instruction set
that supports both numeric intensive signal processing operations as well as
general purpose applications, such as multiprocessing and high speed con-
trol.
For maximum throughput, the next instruction is prefetched while the current
one is being executed. Since the same data lines are used to communicate
to external data/program or I/O space, the number of cycles may vary depend-
ing upon whether the next data operand fetch is from internal or external pro-
gram memory. Highest throughput is achieved by maintaining data memory
on-chip and using either internal or fast program memory.
Table 1 lists the symbols and abbreviations used in Table 2, the instruction set
summary. Table 2 consists primarily of single-cycle, single-word instructions.
Infrequently used branch, I-O, and CALL instructions are multicycle. The in-
struction set summary is arranged according to function and alphabetized
within each functional grouping. The symbol (‡) indicates instructions that are
not included in the SMJ320C25 instruction set.
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Running Title—Attribute Reference
E-27
Running Title—Attribute Reference
B Branch unconditionally 2 1 1 1 1 1 1 1 1 1 D
BACC† Branch to address specified by accumulator 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 1
BANZ Branch on auxiliary register not zero 2 1 1 1 1 1 0 1 1 1 D
BBNZ† Branch if TC bit ≠ 0 2 1 1 1 1 1 0 0 1 1 D
BBZ† Branch if TC bit = 0 2 1 1 1 1 1 0 0 0 1 D
BC Branch on carry 2 0 1 0 1 1 1 1 0 1 D
BGEZ Branch if accumulator ≥ 0 2 1 1 1 1 0 1 0 0 1 D
BGZ Branch if accumulator > 0 2 1 1 1 1 0 0 0 1 1 D
BIOZ Branch on I/O status = 0 2 1 1 1 1 1 0 1 0 1 D
BLEZ Branch if accumulator ≤ 0 2 1 1 1 1 0 0 1 0 1 D
BLZ Branch if accumulator < 0 2 1 1 1 1 0 0 1 1 1 D
BNC Branch on no carry 2 0 1 0 1 1 1 1 1 1 D
BNV† Branch if no overflow 2 1 1 1 1 0 1 1 1 1 D
BNZ Branch if accumulator ≠ 0 2 1 1 1 1 0 1 0 1 1 D
BV Branch on overflow 2 1 1 1 1 0 0 0 0 1 D
BZ Branch if accumulator = 0 2 1 1 1 1 0 1 1 0 1 D
CALA Call subroutine indirect 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 0 0
CALL Call subroutine 2 1 1 1 1 1 1 1 0 1 D
RET Return from subroutine 1 1 1 0 0 1 1 1 0 0 0 1 0 0 1 1 0
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Running Title—Attribute Reference
development support
System development may begin with the use of the simulator, Software Devel-
opment System (SWDS), or emulator (XDS) along with an assembler/linker.
These tools give the TMS320 user various means of evaluation, from software
simulation of the second-generation TMS320s (simulator) to full-speed in-cir-
cuit emulation with hardware and software breakpoint trace and timing capa-
bilities (XDS).
Many third-party vendors offer additional development support for the second-
generation TMS320s, including assembler/linkers, simulators, high-level lan-
guages, applications software, algorithm development tools, applications
boards, software development boards, and in-circuit emulators. Refer to the
TMS320 Family Development Support Reference Guide (SPRU011A) for fur-
ther information about TMS320 development support products offered by both
Texas Instruments and its third-party suppliers.
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Running Title—Attribute Reference
absolute maximum ratings over specified temperature range (unless otherwise noted)†
Supply voltage range, VCC‡ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 7 V
Continuous power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress
rating only, and functional operation of the device at these or any other conditions beyond those indicated in the “recommended
operating conditions” section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
‡ All voltages are with respect to VSS.
This device contains circuits to protect its inputs and outputs against damage due to high static voltages or
electrostatic fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD)
of up to 2 kV according to MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid
application of any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage
or handling, the device leads should be shorted together or the device should be placed in conductive foam. In a
circuit, unused inputs should always be connected to an appropriated logic voltage level, preferably either VCC or
ground. Specific guidelines for handling devices of this type are contained in the publication Guidelines for Handling
Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies available from Texas Instruments.
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Running Title—Attribute Reference
X1 X2/CLKIN
CRYSTAL
C1 C2
E-35
Running Title—Attribute Reference
IOH/IOL
From Output
Under Test
Test
Point
CL = 80 pF
(a) Input
2.4 V
VOH (MIN)
2.2 V
0.8 V 0
VOL (MAX)
0.6 V
(b) Outputs
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Running Title—Attribute Reference
HOLD TIMING
switching characteristics over recommended operating conditions (see Note 1)
PARAMETER MIN TYP MAX UNIT
td(C1L-AL) HOLDA low after CLKOUT1 low 0† 10 ns
tdis(AL-A) HOLDA low to address three-state 0 ns
tdis(C1L-A) Address three-state after CLKOUT1 low (HOLD mode) (see Note 7) 20† ns
td(HH-AH) HOLD high to HOLDA high 25 ns
ten(A-C1L) Address driven before CLKOUT1 low (HOLD mode) (see Note 7) 8† ns
NOTES: 1. Q = 1/4tc(C)
7. A15–A0, PS, DS, IS, STRB, and R/W timings are all included in timings referenced as “address.”
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Running Title—Attribute Reference
X/2CLKIN
th(S) tw(CIL)
tsu(S)
tsu(S) tw(CIH)
SYNC
tc(C)
td(CIH-C) td(CIH-C)
tw(CL)
CLKOUT1
td(CIH-C) tw(CH)
tr(C) tf(C)
STRB
tc(C)
td(CIH-C) tw(CL)
CLKOUT2
CLKOUT1
td(C1-S)
CLKOUT2
td(C2-S) td(C2-S)
STRB
tw(SH)
tw(SL)
tsu(A) th(A)
A15–A0,
BR, PS, DS, VALID
OR IS
ta(A)
R/W
tsu(D)R
td(SL-R)
READY
th(SL-R) th(D)R
D15–D0 DATA IN
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Running Title—Attribute Reference
CLKOUT1
CLKOUT2
STRB
tsu(A) th(A)
A15–A0,
BR, PS, DS, VALID
OR IS
R/W
READY
th(D)W
tsu(D)W
ten(D) tdis(D)
CLKOUT2
STRB
A15–A0, BR
PS, DS, R/W, VALID
OR IS
th(C2H-R) th(C2H-R)
td(C2H-R) td(C2H-R)
READY
th(M-R)
td(M-R) td(M-R)
D15–D0, th(M-R)
(FOR READ DATA IN
OPERATION)
D15–D0,
(FOR WRITE
OPERATION)
MSC
td(MSC) td(MSC)
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Running Title—Attribute Reference
CLKOUT1
tw(RS)
A15–A0
FETCH
LOCATION 0
D15–D0
VALID
PS BEGIN
PROGRAM
EXECUTION
STRB
CONTROL
SIGNALS†
IACK
SERIAL PORT
CONTROLS‡
CLKOUT1
STRB
tsu(IN) th(IN)
tw(N)
INT2–INT0
tf(IN)
td(IACK)
td(IACK)
IACK
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Running Title—Attribute Reference
CLKOUT1
STRB
A15–A0
PC = N PC = N + 1 PC = N + 2 PC = N + 3
OR BRANCH ADDRESS
th(IN)
tsu(IN)
BIO VALID
CLKOUT1
STRB
td(XF)
XF VALID
CLKOUT1
CLKOUT2
STRB
HOLD
R/W
tdis(C1L-A)
D15–D0 IN IN
tdis(AL-A)
HOLDA
td(C1L-AL)
N N+1 – –
FETCH
N– 2 N – 1 N –
EXECUTE
NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact
sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
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Running Title—Attribute Reference
CLKOUT1
CLKOUT2
ten(A-C1L)
STRB
HOLD
PS, DS,
OR IS VALID
R/W
D15–D0 IN
td(HH-AH)
HOLDA
– – – N+2
FETCH
– – – N+1
EXECUTE
NOTE A: HOLD is an asynchronous input that can occur at any time during a clock cycle. If the specified timing is met, the exact
sequence shown will occur; otherwise, a delay of one CLKOUT2 cycle will occur.
tc(SCK)
tw(SCK)
tr(SCK)
CLKR
th(FS) tf(SCK)
th(DR)
tw(SCK)
FSR
tsu(FS) tsu(DR)
N = 8, 16
DR
tc(SCK)
tr(SCK)
tw(SCK)
CLKX
tw(SCK)
th(FS) tf(SCK)
td(CH-DX)
FSX
(INPUT, TXM = 0)
td(FL-DX)
tsu(FS) td(CH-DX)
tsu(FS)
DX N=1 N = 8, 16
td(CH-FS)
td(CH-FS)
FSX
(OUTPUT, TXM = 1)
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Running Title—Attribute Reference
25,40 (1.000)
24,89 (0.980)
24,38 (0.960) MECHANICAL DATA
23,88 (0.940)
C
L C
L 2,41 (0.095)
1,27 (0.050) NOM. 1,91 (0.075)
0,28 (0.011)
C
L 0,18 (0.007)
2,16 (0.085)
1,65 (0.065) Lid
0,38 (0.015)
0,13(0.005)
0,58 (0.023)
0,33 (0.013)
24,13 (0.950)
23,11 (0.910) 0,81 (0.032)
0,51 (0.020)
0,89 (0.035)
0,51 (0.020) 1,27 (0.050)
0,64 (0.025) 3,43 (0.135)
0,25 (0.010) 0,76 (0.030)
2,92 (0.115)
24, 38 (0.960)
MECHANICAL
23, 88 (0.940) DATA
21,89 (0.862) MAX
24, 38 (0.960)
TOP VIEW
23, 88 (0.940)
21,89 (0.862)
MAX
INDEX CORNER
PARAMETER MAX UNIT
Junction-to-free-air
RθJA 39.9 °C/W
thermal resistance
20, 57 (0.810) Junction-to-case
RθJC 7 °C/W
20, 07 (0.790) thermal resistance
ÉÉ
ÉÉ
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉ
ÉÉ
É
C
L
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
É
ÉÉ
ÉÉÉÉ
ÉÉ
É 0, 76 (0.030)
ÉÉ
2, 36 (0.093)
1, 96 (0.077) ÉÉ
ÉÉ ÉÉ
ÉÉ
0, 25 (0.010)
X45° CHAM ÉÉ
ÉÉ
0, 71 (0.028)
ÉÉ
ÉÉ ÉÉ
ÉÉ ÉÉ
ÉÉ
0, 56 (0.022)
C
L
ÉÉ
ÉÉ ÉÉ
ÉÉ
C
L
ÉÉ
ÉÉ
ÉÉ ÉÉ ÉÉ
1,27 (0.050)
TYP
ÉÉ
ÉÉ ÉÉ
ÉÉ ÉÉ
ÉÉ
ÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉ
É ÉÉ
1, 40 (0.055)
1, 14 (0.045)
ÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉÉÉ
ÉÉÉ
ÉÉÉÉ
ÉÉ
0,20 (0.008) R 1, 27 (0.050)
0, 77 (0.030) 3, 050 (0.120)
TYP. CL
2, 08 (0.082)
X45° CHAM
TYP., 3PLS.
ALL DIMENSIONS ARE IN MILLIMETERS AND PARENTHETICALLY IN INCHES WITH THE INCHES GOVERNING
E-51
Running Title—Attribute Reference
28,448 (1.120)
27,422
MECHANICAL DATA(1.080)
15,37 (0.605)
NOM
68-pin GB grid array ceramic package
28,448 (1.120)
TOP VIEW 15,37 (0.605) 27,422 (1.080)
NOM
3,556 (0.140)
0,508 (0.020) 1,575 (0.062)
3,048 (0.120)
0,406 (0.016) 1,473 (0.058)
L
K
J 2,54 (1.00) T.P.
H
G
F BOTTOM VIEW
E
D
1,778 (0.070) NOM
C
68 PLACES
B
1,27 (0.050) NOM
A
1 2 3 4 5 6 7 8 9 10 11
This appendix describes the TMS320E25 EPROM cell. The TMS320E25 in-
corporates a 4K × 16-bit EPROM, which is implemented from a standard
TMS27C64 EPROM cell. This expands the capabilities of the TMS320E25 in
the areas of prototyping, early field testing, and production.
Topic Page
F-1
Using the EPROM Programmer Adapter Socket
- Additionally, a jumper and test point are available for the VPP supply. The
VPP signal is a pulsed signal and fully complies with the standards for a
27C64 EPROM device. This option is never needed, and the jumpers
should be left in the internal position at all times.
To supply external VCC:
1) Find the jumper nearest the VCC pin and move the jumper so that it is over
the EXT and center pins.
Figure F–2 shows the jumper setting placement for internal and external pow-
er. The VCC and VPP pins are also shown.
Figure F–2. VCC and VPP Jumper Settings for External Power
EXT EXT
INT INT
F-3
Programming and Verification
Figure F–4 shows the wiring diagram when the TMS320E25 is programmed
with the TMS27C64 in its 28-pin output form. The illustration furnishes a table
for each pin nomenclature on the TMS27C64 with a description of that pin. Pro-
gramming the code into the device should be done in the serial mode.
68
67
66
RS 65
64
63
62
61
9
8
7
6
5
4
3
2
1
TMS27C64 10 60
11 D7 59
VCC 28
12 D6 58
PGM 27
13 D5 57
EPT 26
14 D4 56
A8 25
15 D3 55
A9 24 TMS320E25
16 D2 54
A11 23 68 PIN
17 D1 53
(FZ)
G 22
18 D0 CLKIN 52
A10 21
19 51
E 20
20 EPT 50
Q8 19
21 VPP 49
Q7 18
22 E A0 48
Q6 17 VSS
23 47
Q5 16 A1
24 46
41 PGM
35 V CC
Q4 15
38 A10
40 A12
39 A11
25 45
34 A7
29 A2
30 A3
31 A4
32 A5
33 A6
36 A8
37 A9
42 G
26 44
27
28
43
3.9 K
8
TMS27C64
A0 10
Q2 12
Q3 13
GND 14
1
2
3
4
5
6
7
8
9
Q1 11
A12
A7
A6
A5
A4
A3
A2
A1
V PP
F-5
Programming and Verification
Table G–2 shows the programming levels that are required when program-
ming, verifying, and reading the EPROM cell. Following the table are individual
descriptions of each programming level.
F.2.1 Erasure
Before programming, the memory must be erased by exposing high-intensity
ultraviolet light (wavelength = 2537 angstroms) into the chip through its trans-
parent lid. Note that normal ambient light contains the correct wavelength for
erasure. Therefore, the window should be covered with an opaque label after
programming the TMS320E25. The recommended minimum exposure dose
(UV intensity × exposure time) is 15 watt-seconds per square centimeter. If lo-
cated about 2.5 centimeters above the transparent lid, a typical filterless UV
lamp with a 12-milliwatt-per-square-centimeter output will erase the memory
in 21 minutes. After the memory is erased, all bits are in a high state.
FAST programming uses two types of programming pulses: prime and final.
The length of the prime pulse is 1 ms. After each prime pulse, the byte being
programmed is verified. If correct data is read, the final programming pulse is
applied; if correct data is not read, an additional 1-ms prime pulse is applied
up to a maximum of 25 times. The final programming pulse is 3x times the num-
ber of prime programming pulses applied. This sequence of programming and
verifying is performed at VCC = 6.0 V, and VPP = 12.5 V. When the full FAST
programming routine has been completed, all bits are verified with VCC = VPP
= 5 V.
F-7
Programming and Verification
The programming mode is achieved when VPP = 13.0 V, VCC = 6.5 V, and G
= VIH, and E = VIL. More than one TMS320E25 can be programmed by con-
necting the devices in parallel with each other. Locations may be programmed
in any order. When the SNAP! pulse programming routine has been com-
pleted, all bits are verified with VCC = VPP = 5 V.
Start
Address =
First Location
VCC = 6 ± 0.25 V
VPP = 12.5 V ± 0.25 V
X=0
Program One
1-ms Pulse
Increment X
No
Pass
Program One
Device Pulse of 3X-ms
Failed Duration
Last No Increment
Address? Address
Yes
Fail Compare
All Bytes to
Original Data
Pass
Device
Passed
F-9
Programming and Verification
Last No
Address?
Yes
Address = First Location
X=0
Program One Pulse = tw = 100 µs
No
Pass Yes
No Last
Address?
Yes
Device Failed
VCC = VPP = 5.0 V ± 10%
Final
Compare Verification
All Bytes to Fail
Original
Data
Pass
Device
Passed
HI-Z VIH/VOH
Q8–Q1 Data In Stable Data Out Valid
VIL/VOL
VPP
VPP
VCC
VCC + 1
VCC
VCC
VIH
E
VIL
PGM VIH
VIL
G VIH
VIL
F.2.6 Read
The EPROM contents can be read outside of the programming cycle if the
RBIT (ROM protect bit) has not been programmed. The read mode is accom-
plished by setting E to zero and pulsing G low. The contents of the EPROM
location, selected by the value on the address inputs, appear on D7–D0.
F-11
EPROM Protection and Verification
Table G–3. TMS320E25 EPROM Protect and Protect Verify Mode Levels
SIGNAL† TMS320E25 PIN TMS27C64 PIN EPROM PROTECT PROTECT VERIFY
E 22 20 VIH VIL
G 42 22 VIH VIL
PGM 41 27 VIH VIH
VPP 25 1 VPP VCC + 1
VCC 61,35 28 VCC + 1 VCC + 1
VSS 27,44,10 14 VSS VSS
CLKIN 52 14 VSS VSS
RS 65 14 VSS VSS
EPT 24 26 VPP VPP
Q8–Q1 11–18 9–15,13–11 Q8=PULSE Q8=RBIT
A12–A10 40–38 2,23,21 X X
A9–A7 37,36,34 24,25,3 X X
A6 33 4 X VIL
A5 32 5 X X
A4 31 6 VIH X
A3–A0 30–28,26 7–10 X X
LEGEND:
† = Signal names are in accordance with TMS27C64.
VIH = TTL high level; VIL = low-level TTL; VCC = 5 ± 0.25 V; VPP = 12.5± 0.25 V (FAST); or 13 ± 0.25 V (SNAP!);
VCC + 1 = 6 ± 0.25 V (FAST) or 6.5 ± 0.25 V (SNAP!);
X = don’t care; PULSE = low-going TTL level pulse; RBIT = ROM protect bit
Start
Program One
Pulse of 3X-ms
X=0
Duration
EPROM
Protect Protect
Setup Verify
Setup
Program One
1-ms Pulse
Device Fail Verify Pass Device
Failed RBIT Passed
X=X+1
Yes
X = 25?
No
Protect
Verify
Setup
Fail
Verify
RBIT
Pass
EPROM
Protect
Setup
F-13
EPROM Protection and Verification
Figure F–9 shows a portion of the TMS320C2x block diagram and includes the
RBIT to show how it disconnects the external and internal program spaces.
Figure F–9. How the RBIT Fits Into the TMS320E25 Block Diagrams
4K × 16
program
R-bit EPROM
cell
MUX
External
Program Bus
Program/
Data Bus
Data Bus
TREG
16 × 16
Multiplier
PREG
Programming the RBIT has some side effects that may, at first, give the ap-
pearance that the device isn’t operating properly. However, because enabling
the RBIT protects the EPROM space, this is normal operation. These side ef-
fects include:
- Instructions. Some instructions that use the external program space for
storage will not operate in the same manner when the RBIT is set.
For example, on the TMS320E25, TBLW, BLKP, and similar commands
may seem to work when used to transfer external program memory to the
internal data space connected to DBUS. However, a transfer from the in-
ternal program space to the external bus will not work. This happens be-
cause the RBIT feature is protecting this memory space.
Similarly, the MAC instruction cannot read tables stored in external pro-
gram space. In this case, the data and program must be swapped, sacrific-
ing one cycle per repeated instruction.
VIH
A4
VIL
VPP
VPP
VCC
VCC + 1
VCC
VCC
VIH
E
VIL
PGM VIH
VIL
VIH
G
VIL
VPP
EPT
VSS
VIL
A6
VIH
† 12.5 V = VPP and 6.0 V = VCC for FAST Programming; for SNAP! Programming, 13.0 V = VPP and 6.5 V = VCC.
F-15
F-16 TMS320E25 EPROM Programming
Appendix G
Texas Instruments offers many products for total system solutions, including
memory options, data acquisition, and analog input/output devices. This ap-
pendix describes a variety of devices that interface directly to the TMS320
DSPs in rapidly expanding applications.
Topic Page
G-1
Multimedia App[lications
Figure G–1 shows both the central role of the multimedia computer and the
multimedia system’s ability to integrate the various media to optimize informa-
tion flow and processing.
Video Input
Video Monitor
Image Sensor
Multimedia
Computer
Microphone Facsimile/Modem
The TLC32047 wide-band analog interface circuit (AIC) is well suited for multi-
media applications because it features wide-band audio and up to 25-kHz
sampling rates. The TLC32047 is a complete analog-to-digital and digital-to-
analog interface system for the TMS320 DSPs. The nominal bandwidths of the
filters accommodate 11.4 kHz, and this bandwidth is programmable. The
application circuit shown in Figure G–2 handles both speech encoding and
modem communication functions, which are associated with multimedia appli-
cations.
DSP
AIC DSP Encrypt/ DSP AIC DAA HYB Phone
Decrypt Line
TMS320 DSP/
TLC32047
Interface
Controller Memory
Figure G–3 shows the interfacing of the TMS320C25 DSP to the TLC32047
AIC that constitutes the building blocks of the 9600-bps V.32 bis modem
shown in Figure G–2.
DR DR VCC– –5 V
CLKR SHIFT CLK VDD +5 V
CLKX 0.1 µF
DGTL GND
D A
G-3
Multimedia Applications
G-5
Telecommunications Applications
TMS320C25 16
GND
TCM320AC36
DR J1 13 DOUT
20 kΩ
8 18
DX E11 DIN ANLGIN Codec
19 IN
MIC_GS
CLKX A9 14 DCLKX 20 kΩ
F10 2 Codec
FSX EAR_A
B9 9 3 OUT
CLKR FSR EAR_B
J2 12
FSR FSX 5
11 VDD 5V
CLK
1 kΩ PDN DCLKR
5V
1 7
7 10 7 10 1 kΩ
Reset
CLKR/CLKX
FSX/FSR
G-7
Telecommunications Applications
Analog
Phones Neighborhood Cellular
Concentrator Phone
TCM1520 Detector
TSP50C1x Speech Synthesis TCM29C13 Combo
TP3054 Combo PBX
TCM1060/30 Transient Suppres-
Low- sors TP305x
Speed TCM9050/51 HVLI/HCombo TCM29Cxx
Modem DSP/Memory/Logic
TCM1520
TCM5089 DSP
TCM3105 Modem
Phones Phones
TMS320xx DSP
TCM291x Combo TCM29Cxx Combo
Fine Tune
Echo-Cancel
D
A Telephone
TMS320C25 Line
A
Echo Canceler
Transmitter
ADC
Serial and
RS-232 TMS320C25 DAC
I/F I/O
Control Receiver
TLC320AC01
G-9
Dedicated Speech Synthesis Applications
TI has low-cost memories that are ideal to use with speech synthesis chips.
Texas Instruments can also be of assistance in developing and processing the
speech data that is used in these speech synthesis systems. Table H–6 shows
speech memory devices of different capabilities. Additionally, audio filters are
outlined in Table H–7.
Software: System:
EVM Code development tool SEB System emulator board
Speech: SEB60Cxx System emulator boards for speech
SAB Speech audition board memories
SD85000 PC-based speech analysis
system
For further information on these speech synthesis products, please call TI Linear Applications at
(214) 997–3772.
G-11
Servo Control/Disk Drive Applications
y(n)
ADC Sensor
SCSI
Data
Bus
To SCSI RAM Buffer Control Data
Host and
Interface Buffer Data Sequencer Separator
Control
Address
Decode
Control Disk Head
Select
Control
TLC32071
To To/From Disk Heads
From Spindle
SN74LS393
Motor
Table H–8 lists analog/digital interface devices used for servo control.
G-13
Servo Control/Disk Drive Applications
Figure G–10 shows the interfacing of the TMS320C14 and the TLC32071.
D0–D7 CSCNTRL
A2 CSAN
Address Decode Logic
A1 WE
A0 DEN
RESET
WE
DEN
TMS320C14 TLC32071
For further information on these servo control products, please call TI Linear
Applications at (214) 997–3772.
The AIC interfaces directly with serial-input TMS320 DSPs, which execute the
modem’s high-speed encoding and decoding algorithms. The TLC3204x fami-
ly performs level-shifting, filtering, and A/D and D/A data conversion. The
DSP’s many software-programmable features provide the flexibility required
for modem operations and make it possible to modify and upgrade systems
easily. Under DSP control, the AIC’s sampling rates permit designers to in-
clude fall-back modes without additional analog hardware in most cases.
Phase adjustments can be made in real time so that the A/D and D/A conver-
sions can be synchronized with the upcoming signal. In addition, the chip has
a built-in loopback feature to support modem self-test requirements.
G-15
Modem Applications
Figure G–11. High-Speed V.32 Bis and Multistandard Modem With the TLC320AC01 AIC
TLC320AC01 – +
+
ADC and DAC
Fine Tune
Echo-Cancel
D
A Telephone
TMS320C25/C5x Line
A
Echo Canceler
Transmitter
ADC
Serial and
RS–232 TMS320C25/C5x DAC
I/F I/O
Control Receiver
TLC320AC01
Figure G–11 shows a V.32 bis modem implementation using the TMS320C25
and a TLC320AC01. The upper TMS320C25 performs echo cancellation and
transmit data functions, while the lower TMS320C25 performs receive data
and timing recovery functions. The echo canceler simulates the telephone
channel and generates an estimated echo of the transmit data signal. The
TLC320AC01 performs the following functions:
Upper TLC320AC01 A/D Path: Converts the residual echo to a digital sig-
nal for purposes of monitoring the residu-
al echo and continuously training the echo
canceler for optimum performance. The
converted signal is sent to the upper
TMS320C25.
G-17
Advanced Digital Electronics Applications for Consumers
With the extensive use of the TMS320 DSPs in consumer electronics, much
electromechanical control and signal processing can be done in the digital do-
main. Digital systems generally require some form of analog interface, usually
in the form of high-performance ADCs and DACs. Figure G–12 shows the
general performance requirements for a variety of applications.
MSPS
300
S Instrumentation
a
m 100
p
HDTV
l
i
n
g
F 30
Broadcasting
r
ADTV
e
q DVTR
u
e
n 10
c Fax/PC
y
Bits
4 5 6 7 8 9 10
Performance/Application
TV IF TMS320
ADC DAC Buffer CRT
Amplifier DSP Video
Signal
Field System
Memory Controller
Clock
Generator
VCRs, compact disc and DAT players, and PCs are a few of the products that
have taken a major position in the marketplace in the last ten years. The audio
channels for compact disc and DAT require 16-bit A/D resolution to meet the
distortion and noise standards. See Figure G–14 for a block diagram of a typi-
cal digital audio system.
Third
384fs 128fs
Overtone Oscillator
Circuit
1024fs
1fs L L
TMS57001
Digital Audio Analog Analog
Data TMS57013/4 Dual 16/18 PWM Power
Sound Bit DAC+ Digital Filter Output
Processor Amplifier
R
R
The motion and motor control systems usually use 8- to 10-bit ADCs for the
lower frequency servo loop. Tape or disc systems use motor or motion control
for proper positioning of the record or playback heads. With the storage me-
dium compressing data into an increasingly smaller physical size, the position-
ing systems require more precision.
G-19
Advanced Digital Electronics Applications for Consumers
The converters have dual channels so that the right and left stereo signals can
be transformed into analog signals with only one chip. There are some func-
tions that allow the customers to select the conditions according to their appli-
cations, such as muting, attenuation, de-emphasis, and zero data detection.
These functions are controlled by external 16-bit serial data from a controller
like a microcomputer.
The contents of the major areas in this appendix are listed below.
Topic Page
H-1
Memories and Analog Converters
The following paragraphs give the name of each device and where the data
sheet for that device is located in order to obtain further specification informa-
tion if desired.
Data sheets for EPROM memories are located in the MOS Memory Data Book
(literature number SMYD008).
TMS27C64
TMS27C128
TMS27C256
TMS27C512
The TCM29C13/14/16/17 codecs and filters are described in the data sheet
beginning on page 2–111 of the Telecommunications Circuits Data Book (liter-
ature number SCT001). An analog interface for the DSP using a codec and
filter is provided by the TCM29C18/19 data sheet (literature number SCT021).
The data sheet for the TLC32040 analog interface circuit is provided in the In-
terface Circuits Data Book (literature number SLYD002).
In the same book are data sheets for A/D and D/A converters. The names of
the devices are as follows:
TLC0820
TLC1205/1225
TLC7524
H.2 Sockets
The sockets produced by Texas Instruments are designed for high-density
packaging needs. The production sockets and burn-in/test sockets for PGA,
PLCC, and CER-QUAD packages are compatible with the TMS320C2x
devices.
For additional information about TI sockets, contact the nearest TI sales office
or:
H-3
Crystals
H.3 Crystals
This section lists the commonly used crystal frequencies, crystal specification
requirements, and the names of suitable vendors.
Table I–1 lists the commonly used crystal frequencies and the devices with
which they can be used.
Load capacitance = 20 pF
Series resistance = 30 ohm
Power dissipation = 1 mW
X1 X2/CLKIN
Crystal
C1 C2
Vendors of crystals suitable for use with TMS320 devices are listed below.
RXD, Inc.
Norfolk, NB
(800) 228–8108
H-5
H-6 Memories, Analog Converters, Sockets, and Crystals
Appendix I
ROM Codes
The size of a printed circuit board must be considered in many DSP applica-
tions. To fully utilize the board space, Texas Instruments offers two options that
reduce the chip count and provide a single-chip solution to its customers.
These options incorporate 4K words of on-chip program from either a mask
programmable ROM or an EPROM. This allows the customer to use a code-
customized processor for a specific application while taking advantage of the
following:
- Greater memory expansion
-
-
Lower system cost
Less hardware and wiring
- Smaller PCB
If used often, the routine or entire algorithm can be programmed into the on-
chip ROM of a TMS320 DSP. TMS320 programs can also be expanded by us-
ing external memory; this reduces chip count and allows for a more flexible
program memory. Multiple functions are easily implemented by a single de-
vice, thus enhancing system capabilities.
TMS320 Development Tools are used to develop, test, refine, and finalize the
algorithms. The microprocessor/microcomputer (MP/MC) mode is available
on all ROM-coded TMS320 DSP devices when accessing either on-chip or off-
chip memory is required. The microprocessor mode is used to develop, test,
and refine a system application. In this mode of operation, the TMS320 acts
as a standard microprocessor by using external program memory. When the
algorithm has been finalized, the designer may submit the code to Texas
Instruments for masking into the on-chip program ROM. At that time, the
TMS320 becomes a microcomputer that executes customized programs out
of the on-chip ROM. Should the code need changing or upgrading, the
TMS320 may once again be used in the microprocessor mode. This shortens
the field upgrade time and avoids the possibility of inventory obsolescence.
Figure I–1 illustrates the procedural flow for TMS320 masked parts. When or-
dering, there is a one-time/nonrefundable charge for mask-tooling. A minimum
production order per year is required for any masked-ROM device. ROM
codes will be deleted from the TI system one year after the last delivery.
A digital signal processor with the EPROM option is the solution for low-volume
production orders. The EPROM option allows for form-factor emulation. Field
upgrades and changes are possible with the EPROM option.
I-1
ROM Codes
Customer Submits:
— TMS320 New Code Release Form
— Print Evaluation and Acceptance Form (PEAF)
— Purchase Order for Mask Charge Prototypes
— TMS320 Code
No Customer
Approves
Algorithm
Yes
TI Produces Prototypes
Customer
Approves
No
Prototypes (Minimum
Production Order
Required)
Yes
TMS320 Production
A TMS320 ROM code may be submitted in one of the following formats (the
preferred media is 5 1/4-in floppies):
5 1/4-in Floppy: TI-tagged or COFF format from cross-assembler
EPROM (TMS320): TMS320E14, TMS320E15, TMS320E17, TMS320E25
EPROM (others): TMS27C64
PROM: TBP28S166, TBP28S86
Modem (BBS): TI-tagged or COFF format from cross-assembler
When a code is submitted to Texas Instruments for masking, the code is refor-
matted to accommodate the TI mask generation system. System-level verifi-
cation by the customer is therefore necessary. Although the code has been re-
formatted, it is important that the changes remain transparent to the user and
do not affect the execution of the algorithm. The formatting changes involve
the removal of address relocation information (the code address begins at the
base address of the ROM in the TMS320 device and progresses without gaps
to the last address of the ROM on the TMS320 device) and the addition of data
in the reserved locations of the ROM for device ROM test. Note that because
these changes have been made, a checksum comparison is not a valid means
of verification.
With each masked device order, the customer must sign a disclaimer stating:
”The units to be shipped against this order were assembled, for expediency
purposes, on a prototype (that is, non-production qualified) manufacturing
line, the reliability of which is not fully characterized. Therefore, the antici-
pated inherent reliability of these prototype units cannot be expressly de-
fined.”
Contact the nearest TI Field Sales Office for more information on procedures,
leadtimes, and cost.
I-3
I-4 ROM Codes
Appendix J
-
shipping inspection
Product quality and reliability monitoring.
Our customer’s perception of quality must be the governing criterion for judg-
ing performance. This concept is the basis for Texas Instruments Corporate
Quality Policy, which is as follows:
“For every product or service we offer, we shall define the requirements that
solve the customer’s problems, and we shall conform to those requirements
without exception.”
Note:
Texas Instruments reserves the right to make changes in MOS semiconduc-
tor test limits, procedures, or processing without notice. Unless prior ar-
rangements for notification have been made, TI advises all customers to re-
verify current test and manufacturing conditions prior to relying on published
data.
J-1
Reliability Stress Tests
- Storage life
- Temperature cycling
- Biased humidity
- Autoclave
- Electrostatic discharge
- Package integrity
- Electromigration
- Piece parts (such as lead frame, mold compound, mount material, bond
wire, or lead finish)
- Manufacturing site.
Table K–1 lists the microprocessor and microcontroller reliability tests, the
duration of the test, and sample size. The following terms define or describe
these tests:
AOQ (Average Outgoing Quality)
Amount of defective product in a population, usu-
ally expressed in terms of parts per million (PPM).
FIT (Failure in Time) Estimated field failure rate in number of failures
per billion power-on device hours; 1000 FIT =
0.1% failure per 1000 device hours.
Operating lifetest Device dynamically exercised at a high ambient
temperature (usually 125°C) to simulate field
usage that would expose the device to a much
lower ambient temperature (such as 55°C). Using
a derived high temperature, a 55° C ambient fail-
ure rate can be calculated.
High-temperature storage
Device exposed to 150°C unbiased condition.
Bond integrity is stressed in this environment.
Biased humidity Moisture and bias used to accelerate corrosion-
type failures in plastic packages. Conditions must
include 85°C ambient temperature with an 85%
relative humidity (RH). Typical bias voltage is +5V
and ground on alternating pins.
Autoclave (pressure cooker)
Plastic-packaged devices exposed to moisture at
121° C using a pressure of one atmosphere above
normal pressure. The pressure forces moisture
permeation of the package and accelerates corro-
sion mechanisms (if present) on the device. Exter-
nal package contaminants can also be activated
and caused to generate inter-pin current leakage
paths.
Temperature cycle Device exposed to severe temperature extremes
in an alternating fashion (–65°C for 15 minutes
and 150°C for 15 minutes per cycle) for at least
1000 cycles. Package strength, bond quality, and
consistency of assembly process are stressed in
this environment.
Thermal shock Test similar to the temperature cycle test, but in-
volving a liquid-to-liquid transfer, per MIL-
STD-883C, Method 1011.
PIND Particle Impact Noise Detection test. A nonde-
structive test to detect loose particles inside a de-
vice cavity.
J-3
Reliability Stress Tests
Mechanical Sequence:
Fine and gross leak Per MIL-STD-883C, Method 1014.5
Mechanical shock Per MIL-STD-883C, Method 2002.3,
1500g, 0.5 ms, Condition B
PIND (optional) Per MIL-STD-883C, Method 2020.4
Vibration, variable frequency Per MIL-STD-883C, Method 2007.1,
20g, Condition A
Constant acceleration Per MIL-STD-883C, Method 2001.2,
20 kg, Condition D, Y1 Plane min
Fine and gross leak Per MIL-STD-883C, Method 1014.5
Electrical test To data sheet limits
Thermal Sequence:
Fine and gross leak Per MIL-STD-883C, Method 1014.5
Solder heat (optional) Per MIL-STD-750C, Method 1014.5
Temperature cycle Per MIL-STD-883C, Method 1010.5,
(10 cycles minimum) –65 to +150°C, Condition C
Thermal shock Per MIL-STD-883C, Method 1011.4,
(10 cycles minimum) –55 to +125°C, Condition B
Moisture resistance Per MIL-STD-883C, Method 1004.4
Fine and gross leak Per MIL-STD-883C, Method 1014.5
Electrical test To data sheet limits
Thermal/Mechanical Sequence:
Fine and gross leak Per MIL-STD-883C, Method 1014.5
Temperature cycle Per MIL-STD-883C, Method 1010.5,
(10 cycles minimum) -65 to +150°C, Condition C
Constant acceleration Per MIL-STD-883C, Method 2001.2,
30 kg, Y1 Plane
Fine and gross leak Per MIL-STD-883C, Method 1014.5
Electrical test To data sheet limits
Electrostatic discharge Per MIL-STD-883C, Method 3015
Solderability Per MIL-STD-883C, Method 2003.3
Solder heat Per MIL-STD-750C, Method 2031,
10 sec
Salt atmosphere Per MIL-STD-883C, Method 1009.4,
Condition A, 24 hrs min
Lead pull Per MIL-STD-883C, Method 2004.4,
Condition A
Lead integrity Per MIL-STD-883C, Method 2004.4,
Condition B1
Table K–2 provides a list of the TMS320C2x devices, the approximate number
of transistors, and the equivalent gates. The numbers have been determined
from design verification runs.
J-5
J-6 Quality and Reliability
Appendix K
Development Support
For information on pricing and availability, contact the nearest TI Field Sales
Office or authorized distributor.
K-1
Device and Development Support Tool Nomenclature
TMX and TMP devices and TMDX development support tools are shipped
against the following disclaimer:
TMS devices and TMDS development support tools have been fully character-
ized, and the quality and reliability of the device has been fully demonstrated.
Texas Instruments standard warranty applies.
Note:
Predictions show that prototype devices (TMX or TMP) will have a greater
failure rate than the standard production devices. Texas Instruments recom-
mends that these devices not be used in any production system because
their expected end-use failure rate is still undefined. Only qualified produc-
tion devices are to be used.
TI device nomenclature also includes a suffix with the device family name. This
suffix indicates the package type (for example, N, FN, or GB) and temperature
range (for example, L). Figure K–1 provides a legend for reading the complete
device name for any TMS320 family member.
PACKAGE TYPE
DEVICE FAMILY N = plastic DIP
320 = TMS320 Family J = ceramic CER-DIP
JD = ceramic DIP
side-brazed
GB = ceramic PGA
TECHNOLOGY FZ = ceramic CER-QUAD
C = CMOS FN = plastic leaded CC
E = CMOS EPROM FD = ceramic leadless CC
QFP = quad flat pack
DEVICE
C1x DSP:
10
14
15
16
17
C2x DSP:
25
26
28
C3x DSP:
30
31
C4x DSP:
40
C5x DSP:
50
51
53
K-3
Device and Development Support Tool Nomenclature
Figure K–2 provides a legend for reading the part number for any TMS320
hardware or software development tool.
MODEL‡ GENERATION‡
11 = XDS/11 1 = C1x
22 = XDS/22 2 = C2x
88 = upgrade kits 3 = C3x
4 = C4x
5 = C5x
OPERATING SYSTEM† FORMAT†
02 = C1x VAX/VMS 1 = TI-tagged
08 = C1x IBM MS/PC-DOS 5 = COFF
22 = C2x VAX/VMS
28 = C2x IBM MS/PC-DOS
32 = C3x VAX/VMS
38 = C3x IBM MS/PC-DOS
42 = C4x VAX/VMS
48 = C4x IBM MS/PC-DOS
52 = C5x VAX/VMS
58 = C5x IBM MS/PC-DOS
† Software only.
‡ Hardware only.
Index
Index-1
Index
ARAU, 3-9
B
ARB, 3-9
B, 4-42
architectural overview, 3-2
BACC, 4-43
arithmetic logic unit (ALU), 3-3
diagram, 3-3 BANZ, 4-44
direct memory access, 3-5 BBNZ, 4-46, 5-45
memory interface, 3-4 BBZ, 4-47, 5-45
multiplier, 3-3 BC, 4-48
multiprocessing, 3-4 BGEZ, 4-49
on-chip memory, 3-2
BGZ, 4-50
serial port, 3-4
BIO, 2-5, 4-56
architecture, 3-1 BIOZ, 4-51
arithmetic logic unit (ALU), 3-3, 3-9, 3-30 BIT, 4-52, 5-44, 5-45
arithmetic operations, 5-46–5-67 bit manipulation, 5-44
division, 5-57–5-59 bit-reversed (BR) addressing, 5-77
using SUBC, 5-57–5-59 BITT, 4-54, 5-45
extended-precision arithmetic, 5-62–5-67 BLEZ, 4-56
addition, 5-64 BLKD, 3-27, 4-57, 5-33
multiplication, 5-66 BLKP, 4-60, 5-33
subtraction, 5-65
block B0, 5-38
floating-point, 5-60–5-62
denormalization, 5-61 block diagram
’C26, 3-8
using LACT, 5-61
’C2x, 3-7
using NORM, 5-61
indexed addressing, 5-62 block moves, 3-27, 5-33
moving data, 5-51 BLZ, 4-63
using MACD, 5-52 BNC, 4-64
multiplication, 5-53–5-57 BNV, 4-65
measuring efficiency, 5-55 BNZ, 4-66
using LTA–MPY, 5-54
bootloader, 5-6–5-21
using MAC, 5-54 configuration words
using SQRA, 5-57 BAUD DETECT, 5-13
overflow management, 5-46 CHECKSUM, 5-10, 5-14
scaling, 5-47 INTERRUPT, 5-9, 5-14
shifting data, 5-47–5-50 PROGRAM LENGTH, 5-9, 5-14
bit-reversed carry addition, 5-48 PROGRAM WORD, 5-10, 5-14
FFT bit reversals, 5-48 STATUS, 5-9, 5-13
other applications, 5-49 SYNCHRONIZATION, 5-10, 5-15
ARP, 3-9 external memory (EPROM) download, 5-15–5-21
byte ordering, 5-16
assembly language instructions, 4-1 parallel download, 5-6–5-10
auxiliary register, arithmetic unit, 3-9 16-bit transfer sequence, 5-8
8-bit transfer sequence, 5-8
auxiliary registers, 3-9, 3-22–3-25 BIO–XF handshake example, 5-7
bus, 3-9 BIO–XF transfer protocol, 5-7
pointer, 3-9 configuration words, 5-9, 5-13–5-15
pointer buffer, 3-9 program length, 5-9
Index-2
Index
Index-3
Index
Index-4
Index
Index-5
Index
Index-6
Index
Index-7
Index
Index-8
Index
PFC, 3-10
PIC, ix
Q
PID control, 5-82 QIR, 3-10
quality and reliability, J-1–J-5
pin assignments, 2-2
queue instruction register, 3-10
pinouts, 2-1
pipeline hardware, 3-45
pipeline operation, 3-37–3-47
R
ADD followed by SACL, 3-41 R/W, 2-5
branch to on-chip RAM, 3-44 RAM(B0), 3-10
’C25, 3-39
RAM(B1), 3-10
decode, 3-37
execute, 3-37 random access memory
fetch, 3-37 data only, 3-10
instruction sequence, 3-40 data or program, 3-10
prefetch, 3-37 RBIT, F-12
RET from on-chip RAM, 3-45 RC, 4-137
three-level, 3-38 read only memory, 3-10
two-level, 3-38 READY, 2-4
wait states, 3-41 registers
with external data bus conflict, 3-43 auxiliary, 3-22
PLCC/CLCC adapter socket, F-2 DRR, 3-64
POP, 4-133 DXR, 3-64
indirect addressing, 3-23
POPD, 4-134 memory-mapped, 3-22
powerdown modes (’C25), 3-53 serial port, 3-63
powerup reset, 6-2–6-4 reliability stress tests, J-2
microcontroller tests, J-5
PR, 3-10
microprocessor tests, J-5
PRD, 3-10 test environments, J-2
prefetch counter, 3-10 types of tests, J-3
processors overview, 1-4 repeat counter, 3-10
repeat counter (RPTC), 3-53
Product Information Center, ix
reset, 2-6, 3-46, 3-47
product register, 3-10
reset circuit, 6-2–6-4
program bus, 3-10 diagram, 6-3
program control, 5-22 RET, 4-138
program counter (PC), 3-10, 3-35, 3-43 RFSM, 4-139
program execution, 5-38 RHM, 4-140
robotics, 6-51
program memory, 3-17
address bus, 3-10 ROL, 4-141
ROM, 3-10
program verify, F-8
ROM code flowchart, I-2
PS, 2-4
ROM code media, I-3
PSHD, 4-135 ROM codes, I-1–I-3
pulse programming, F-8 ROM protect bit, F-12
PUSH, 4-136 ROR, 4-142
Index-9
Index
Index-10
Index
T V
T register (TR), 3-32
VCC, 2-6
TBLR, 4-184, 5-34
video signal processing, G-19
TBLW, 4-186, 5-34
voice coding, 6-49
telecom devices, G-8 voice synthesizers, G-10
telecommunications applications, G-5 VSS, 2-6
DSP/combo, G-6
temporary register, 3-11
TIM, 3-11 W
TIM register, 3-52
wait-state generator, 6-19
timer, 3-11, 5-25
design, 6-21
timer block diagram, 3-52 memory/peripheral access, 6-20
timer operation, 3-52 timing, 6-22
Index-11
Index
X Z
X1, 2-6 ZAC, 4-191
X2/CLKIN, 2-6 ZALH, 4-192
XDS/22, K-1 ZALR, 4-193
XF, 2-6, 3-56
ZALS, 4-194
XOR, 4-189
XORK, 4-9, 4-190
XSR, 3-11
Index-12
Running Title—Attribute Reference
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the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are
utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each
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Certain applications using semiconductor products may involve potential risks of death, personal injury, or
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