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Reg. No. :

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Question Paper Code : 31114
M.E./M.Tech. DEGREE EXAMINATION, JUNE 2011.

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Common to M.E. — Applied Electronics/M.E. —VLSI Design

Second Semester

252204 — CAD FOR VLSI CIRCUITS

(Regulation 2010)

Time : Three hours

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Answer ALL questions.

PART A — (10 × 2 = 20 marks)

Maximum : 100 marks
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1. What are the entities to be considered for optimisation in VLSI Design?

2. Differentiate sea of gates design and field programmable gate array design.

3. What is the need for layout design rules?

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4. What are the objectives of partitioning?

5. Draw the wheel floor plan diagram.

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6. What are the different metrics used to estimate wirelength?

7. Draw the ROBDD for the function F = ∑ m(0,1,4,5,6) .

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8. How a signal is modeled during gate level simulation?

9. List any two scheduling algorithms used in high level synthesis.

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10. What are assignments and allocations in high level synthesis.

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PART B — (5 × 16 = 80 marks)

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11. (a) (i) Explain depth-first search algorithm with an example and also
write the pseudocode of it. (10)

(ii) Discuss on the three domains in Gajski's Y Chart. (6)

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Or

(b) (i) Discuss on the VLSI design automation tools. (10)

(ii) Explain Breadth first search with an example. (6)

12. (a) (i)

(ii)
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How partitioning is done using Kernighan-Lin algorithm?

Using KL algorithm find two way partitioning for the graph shown
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in Fig. 1 (initially take nodes 1,2,3 in set A and 4,5,6 in set B). (8)
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Fig. (1)
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Or

(b) What are the constraints in placement problem and explain the
placement algorithm based on partitioning with an example. (16)
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13. (a) What is the used of shape functions in floor planning and explain various

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optimisation problems in floor planning? (16)

Or

(b) (i) What is area routing? How does it differ from channel routing? (6)

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(ii) Explain left edge algorithm and show how it is used in channel
routing with an example. (10)

14. (a) (i) Explain compiler driven simulation with an example. (8)

(b)
(ii)

(i)
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Discuss the date structure used to describe switch level simulation
algorithm.

Or
List and explain the steps used in two level logic optimisation.
(8)

(8)
(ii) With Shannon's expansion theorem expand the given function with
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respect to ‘A’.
Z= AB + A' + AC. (8)

15. (a) What is data flow diagram? Explain the various units of data flow
diagram with examples. (16)

Or
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(b) Describe the ASAP scheduling algorithm and explain the role of it in high
level synthesis. (16)

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