reso AT A A) TTL HD74/HD74S Series MIPERFORMANCE (per gate) MIMAIN CHARACTERISTICS (Ta —— 20~+75°C) Performance [HDT4 Series [HD74S Series HDT Propagation 7 Parameter ai, | mas | min | mine bein time | Wm |? Vos tlar man rs Power tomw | 20m Venlo — 4000) | - peedrPower | 9p py mes v | Product v Te == Talon i SELECTION GUIDE @NAND/NOR/AND/OR GATES Function HDTSeres TTS Series Gund, Tapa Poste NAND Gates w= 7 Quad. 2-input Positive NAND Gates (with Open Collector Output) ol | Quad. 2-input Positive NOR Gates o oz Quad, Positive NAND Gates (with Open Collector Output) | 03 03 Hex Inverters 4 os Hex Inverters (with Open Collector Output) { 05 | 05 a Hex Inverter Buffers/Drivers (with Open Collector High-voltege Outpt 06 = Hex Buffers/Drivers (with Open Collector High-voltage Output) { oe Quad. 2-input Positive AND Gates oe Quad, 2-input Positive AND Gates (with Open Colleetor Outpt) oo Triple 3-input Positive NAND Gates 7 a 10- | 0 Triple 3-ingut Positive AND Gates u Triple 2-ingut Positive NAND Gates (with Open Collector Output) | we ve Dual 4-input Schmitt NAND Gates | 13 - Hex Sehmist-trigger Inverters “ Triple 3-ingut Positive AND Gates (with Open Collecor Outpt) T Hex Inverter Baffers/Drivers (with Open Collector High-voltage Output) 6, Hiex Daffers/Drivers with Open Collector High-voltage Output) uv = Daal doinput Positive NAND Gates 0 2 mt Positive NAND Gates (with Open Collector Output) a Deal A-input Positive NOR Gates (with Strobe) = Dual d-input Positive NOR Gates | - Quad, 2-input High-voltage Interface NAND Gates | Triple 3-input Positive NOR Gates | : feinput Positive NAND Gate “Quad. 2-input Positive OR Gates 1 = Quad, Zinput Positive NAND Buffers | Quad. 2input Positive NAND Buffers (with Open Collector Output) Daal A-input Positive NAND Buffers 0 Quad. Bus Buffer Gates with 3-state Output Unverting | : wad. Bus Buffer Gates with 3-state Output (Noninverting) ~ Quad. 2-input Pouitive NAND Schmitt Triggers - 12-input Positive NAND Gate - 1 ~ 12-input Positive NAND Gate (with Sstate Out.) 134 Dual input Positive NAND Line Drivers | uo (to he continued) 268 @HITACHITTL HD74/74S Series Fain [TH Sere |W Seas Tapani Dad Eade Fp AND-ORCINVERT Gor a Dat Zn ina AND-ORCINVERT Cats ae | Erunae fede ino AND-OR-INVERT Gate a | {nade Peper AND-OR-INVERT Gate H : {2-5-2 ut AND-ORINVERT Gate : a ‘taunt AND-OINVERT Gate (vith Opn Cllestor Outpt ae @ EXPANDER Taian WoT Sere] WETS Bers Dal Wig Bees cies : eFLIP FLOPS Funetion HDT4 Series DAS: TER Master-Flip Flop (AND Inputs 7 = Dual J-K Flip Flops | B Dual D-type Edge-triggered Flip Flops ue 4 Dual J-K Flip Flops (with PR and CLR) | 76 = “Dual JK Flip Flops | we | : Dual J-K Negative-edge-triggered Flip Flops (with PR and CLR) - m — Dual J-K Negative-edge-triggered Flip Flops (with PR) na Dual J-K_Negatve-edge-triggered Flip Flops (with PR, Cormon CLR, and Conon CK: = at “Monostable Multivibrator ai _| = ~ Dual Retriggerable Monostable Multivibrators 123 ~ Hex D-type Flip Flops (with CLR 174 | vw Quad, D-type Flip Flops (with CLR) | 175 | 15 Dual Monostable Multivibrators (with Schmitt Trigger l 2a l COUNTERS Funetion HDT Series HDTAS Series Decade Counter 908 = Divide-by-Twelve Counter 928, = A-bit Binary Counter 93a - Presettable Decade Counter/Latch | 176 i - A-bit Binary Counter/Latch 7 | synchronous Decade Counter ~ 160 1 = Synchronous 4-bit Binary Counter 161 \ Fully Synchronous Decade Counter 162 a Fully Synchronous 4-bit Binary Counter 163 S Synchronous Decade Decimal Rate Multiplier 167 - Synchronous Decade Up/Down Counter 190 Synchronous ¢-bit Binary Up/Down Counter - ~ “Ta = Synchronous Decade Up/Down Counter 192 7 - Synchronous 4-bit Binary Up/Down Counter 193 7 Decade Counter 2007 = A-bit Binary Counter L 293 - @ HITACHIaoe > TTL HD74/74S Series ©4-BIT, 5-BIT SHIFT/STORAGE REGISTERS Fonction HDT Series BDTS ‘Chie Righi-shife, Left-shitt Register S-bit Shift Register (Dual Pai A-bit D-type Register (with 3-state Output el-in, Parallel-out ) 4-bit Parallel-in, Parallel-out Bidirectional Shift Register 4-bit Parallel-in, Pavallel-out Shift Register (J-K Inputs for First Stage ©8-BIT SHIFT REGISTERS A 96 173 1 195 Fonction Bb Shift Register B-bit Parallel-out Shift Register Parallel-load 8-bit Shift Register B-bit Parallel-in, Parallel-out Bidirectional Shift Register 8-bit Parallel-in, Parallel-out shift Register (J-K Inputs for First Stage) ‘ENCODERS HDT Series OIA, 1 165 198 19 HDTAS Series Function 10-Tine-to-4-line Priority Encoder S:line-to-3-line Priority Encoder @ DECODERS /DEMULTIPLEXERS HDT4 Series mT 148. DTS Series Function Re Excess $-to-Decimal Decoder Excess 6 I-co-Decimal Decoder y-to-Decimal Decoder 4-line-to-I6-line Decoder/Demultiplexer Dual Dual 2-line-to-4-line Decoders/Demultiplexers (with Open Collector Output ) Iine-to-4-line Decoders/Demultiplexers 4-line-to-I6-line Decoder/Demultiplexer (with Open Collector Output @DECODERS/LAMP DRIVERS/BUFFERS HD? Series RA BA 44a, 154 155 156 159 HD?aS Series Function BCD-to-Decimal Decoder/Driver/iwith 30V Out CD-to-Decimal Decoder/Driver (with 15V Out wven Segment Decoder/Driver (sith 30V Output ) en Segment Decoler/Driver (with 15V. Output) !-to-Decimal Decoder/Driver (with 60V Out. @ LATCHES HD? Series M5 46a wa ML HD?4S Series HDT Series DI4S Series Quad. Bistable Latches Quad. 5-R Latches @RANDOM ACCESS MEMORIES (less than 256-bit) 75 29 Function HDT Series TDTAS Series Gi-bit Random Access Memory (l6w by 4b) 270 @ HITACHI ® (to be continued)TTL HD74/74S Series @ARITHMETIC ELEMENTS Fonction HDT Series, HDS Series Fit Binary Full Rider wat = 4-bit Magnitude Comparator 85 Quad. 2-ingut Exelusive-OR Gates 6 86 Quad. Exclusive-OR/NOR Gates 135 Quad, 2-input Exelusive-OR Gates (with Open Collector Output B-bit Odd/Even Parity Generator/Checker OO } — — = Ait Arithmetic Logie Unit/Fanction Generator = a Look-Ahead Carry Generator (for ALU) we 182 Dual Carty Save Full Adders sa = ‘Q-bit Odd/Even Parity Generator/Checker : T = T 280 — Abit Binary Full Ader (with Fast Carry) ma - S @DATA SELECTORS/MULTIPLEXERS Fraction TDM Series | THIS Series TE-bit Data Selector Maple ie S-tit Data Selector/Multiplexer (with Strobe) Ista 1s Sit Data Selector/Maltiphexer e : Dual 4-line-to-I-line Data Selectors/Maltplexers 13 : Quad, 2-ine-to-I-tine Data Selectors/Noltplexers ee 1st Quad. Pline-torI-line Data Selectors/Mulilexers 78 S-bit Data Selector/Multiplexer (with Stobe and S-state Ostput m1 2st line Data Selectors/Nultiplexers (with Sestate Output) 7 2si/ line Data Selectors/Maltplexers (with S-state Output 258 [pe14] 06-16] [ba-16a [6-20 | @ HITACHI 271