CHAPTER 5 INTERNAL MEMORY BL Semiconductor Main Memory ‘Oyganization DRAM and SRAM Typos of ROM Chip Logie Chip Packaging Module Organization Error Correction Advanced DRAM Organization Synchronous DRAM Rambus DRAM Cache DRAM. Recommended Reading and Web Sites Key Terms, Review Questions, and Problems Key Terms Review Questions Problems438. CHAPreR 5 / INTERNAL MEMORY [ KEY POLNTS The two basic forms of semiconductor random-doces memory ate dynatnic RAM (DRAM) and statie RAM (SRAM), SRAM is faster, more expensive, | and less dense than DRAM, and is used for cache memory, DRAM is used for iain memory, Zi Z ) ‘# Bnior conection techniques are commonly used in memory systems, These involve adcing redundant bits that are a function of the data bits to form an ‘error-corvecting code. If a bit error occurs, the code will detect and, usually, | comrect the error, Z 4 Tocompensate for the relatively slow speed of DRAM, a number of aulvancoe DRAM organizations have beer introduced. The two most common are syn- dhionous DRAM aud RamBus DRAM, Both of these involve using the sys ‘tem clock to provide for the transfer of blocks of dats, ) ‘his chapter bezins with a survey of semiconductor main memory subsystems, Vigeluding ROM, DRAM, and SRAM memories. Then we look at error con- “401 techniques used to enhanee memory reliability. Following this, we look at more advanced DRAM architectures, 5.1 SEMICONDUCTOR MAIN MEMORY In earlier computers. the most common form of random-acvess storage for come puter main memory employed an array of doughnul-shaped ferromagnetic loops relerred to as cores. Teave, main memory was often referred to as core, # term that persists to this day. The advent of, and advantages of, microelectronics has tong since vanquished the magnetic core memory. Today, the use of semiconductor chips for main memory is almost universal, Key aspects of this technology are explored in this section, Organization “The basic element of a semiconductor memory is the memory cell Although a vari- | ely of electronic technologies are used, all semiconductor memory eells share er tain properties: © They exhibit two stable (or semistable) states, which can be used to represent binary 1 and 0) # They are capable of being written into (at least once), to set the state. « They are capable of being read to sense the state.Sal / SEMICONDUCTOR MAIN MEMORY 139) vel Contra! Datain (a) Weite (ib) Read 5.1 Memory Call Operation Figure 5.1 depicts the operation of a memory cell. Mest commonly, the ell has three functional terminals capable of earrying an electrical signal. The select termi- hl, as the name suggests, selects 4 memory cell for a read or write operation, The control terminal indicates read or write, For writing, the other terminal provides an electrical signal that sets the state of the cell to 1 oF 0. For reading, that terminal is used for output of the eell’s state. The details of the internal organization. func- tioning, and timing of the memory cell depenci on the specific integrated circuit t nology used and are beyond the scope of this book, except for a brie! summary. For ‘our purposes, we will ake it as given that individual cells can be selected for read- ing and writing operations DRAM and SRAM : All of the memory types that we will explore in this chapter That is, individual words of memory are dicectly accessed through wired-in ad- cressing logic. Table 5.1 lists the major types of semiconductor memory. The most common, is referred to as randumaceess memory (RAM). This is, of course, a misuse of the term, hecause all of the types listed in the table are random access. One distin- guishing characteristic of RAM is that it is possible both to read data from the mem- ory and to write new dala into the memory easily and rapidly, Both the reading and writing are accomplished through the use of electrieal signals The othor distinguishing characteristic of RAM is that it is volatile. A RAM ‘must be provided with a consiamt power supply. II the power is interrupted, then the data are lost, Thus, RAM can he used only as temporary storage. The two tra- Gitional forms of RAM used in computers are DRAM and SRAM, ¢ random access. Dynamic RAM RAM technology is divided into two technologies: dynamic and static. A. dynamic RAM (DRAM) is mace with cells that store data as charge on eapacitons, The presence or absence of charge on @ capacitor is interpreted as 6 binary | er 0. Because capacitors have 4 natural tendency to discharge, dynamic RAMS require periodic charge refreshing to maintain data storage. The term dynamic refers to this tendeney of the stored charge to leak away, even with power continuously applied,140. CHAPTER 5 / INTERNAL MEMORY ‘Table £1 Semiconductor Memory Types Memory Type category | ‘Write Medi ‘Vokuty Rindonv access a Pleetreally a Beney en, Readwite memory ARTSY | Btecrsaly Volatile Read only ancmiery (ROM) Male Reudonlymemory — | Not possible Feat ROM (PRON) Erssahle PROM UWikhe | Nosoiatle AEPRON) hip level Flectrcaly Flecuicaly Erasable | peeamosaymenery | Pletal PROM (EEPROM) | Resstmosiy mem byte evel Electra, Flash netnory peels Figure 52a is a typical DRAM structure for an indivicual cell that stores one bit, The address line is activated when the bit valuc from this cell is to be read or writion, The transistor acts as a switch that is closed (allowing current to flow) ifa is applied to the address line and open (no current flows) if no voltage is sent on the address line For the write operation, a voltage signal is applied to the bit ine: a high volt age represents 1. and a Jon voltage represents 0. A signal is then applied to the addess line, allowing @ charge to be transferred to the capacitor, For the read operation, when the address line is selected, the transistor turns, il the charge stored on the capseitor is fed out onto a bit line and to a sense amplifier. The sense amplifier compares the capacitor voliage to a reference value sand determines ifthe cell contains a logic | or a togic 0. The read out from the cell discharges the capacitor, which must be restored to complete the aperation, ‘Although the DRAM cell is used to store a single bit (0 or 1), it is essentially aan analog device. The capacitor can store any charge value within a range; & threst- old value determines whether the charge is interpreted as 1 oF 0. Static RAM In contrast, a static RAM (SRAM) is 2 digital device, using the same logic ele- ments used in the processor. Ina SRAM, binary values are stored using traditional flip-flop logie-gate contigurations (see Appendix A for a deseription of tip-fleps). A static RAM will hold its data as long as power is supplied to it Figure 5.2b isa typical SRAM structure for an individual cell, Pour transistors (Ty T,, Ty. Ty) are cross connected in an arrangement that produces a stable logical state, In logic state 1 point C, is high and point (is low. in this state, T, and T, are off and T_ and T; are on,! In logic state 0, point C; is low and point Cis highs in me cites a he hea OCT, nd Ty eat signa nexaton,1 QUYRIS} YA IEIS (D au soupy 4 anor unos) sowed steunny SSupPY ase OP142. CHAPTER 5 / INTERNAL MEMORY this state, T; and T, are on and 1 and Tore off: Doth states are stable-as Tong as the direet current (de) voltage is applied. Unlike the DRAM, no refresh is needed toretain data As in the DRAM, the address line is used to open or close a switeh. The ad dress line controls two transistors (I. and T,). When a signal is applied to this line, the two transistors are switch on, allowing’n rea or write operation, For 2 write ‘operation, the desired bit value is applied to line B, while its complement is appliod to line B. This forces the four transistors (Ty T Ty Tinto the proper sate. For a read operation, the bit value is read from line B. SRAM versus DRAM Both static and dynamic RAMS are volatile; that is, pewer must be contin uously supplied to the memory to preserve the bit values. A dynamic memory cell is Simpler and smaller than static memory cell. Thus. a DRAM is more dense (smaller cells = more cells pes unit area) and less expensive than a corresponding SRAM. On the other hand, a DRAM requires the supporting refrest circuitry. For larger memories, the fixed cost of the refresh circuitry is more than compensated for by the smaller variable cost of DRAM cells. Thus, DRAAMS tend to be favored for large memory requirements. A final point is that SRAMB ure generally somewhat faster than DRAMS, Because of these relative characteristics, SRAM is used for ache memory (both on and off chip), and DRAM is used for ‘Types of ROM As the name suggests, a read-only memory (ROM) contains a permanent pattern bf data that cannot be changed. A ROM is nonyolatile: that is, no power source is required to maintain the bit values in memory. While it is possible to read a ROM it is not possible to write new data into it. An important application of ROMs is microprogramming, discussed in Part Four. Other potential applications include © Library subroutines for frequently wanted functions, * System programs * Function tables For a modest-sized requirement, the advantage of ROM is that the data or program is permanently in main memory and need never be loaled from a secondary stor- age device, A ROMs created like any other integrated cireuit chip. with the data actually ‘sired into the chip as purt of the fabrication process. This presents two problems: + The data insertion step includes a relatively large fixed cost, whether one or thousands of copies of a particular ROM are labricated. + There is no room for error. Ione bit is wrong, the whole batch of ROMs must be thrown out When only a small number of ROMs with a particular memory content is needed. a less expensive alternative is the programmable ROM (PROM), Like the ROM, the PROM is nonvolatile and may be wrilten inte only once. For te PROM, the writing process is performed electrically and may be periormed by a supplier or5.1 / SEMICONDUCTOR MAIN MEMORY 143 time later than the oxiginal chip fabrication, Special equipment is, sequited for the writing or “programming” process. PROMS provide flexibility ant convenience, The ROM remains attractive for high-volume production runs. Another variation on read-only memory is the read-mosily memory, whieh is useful for applications in which read operations are far more frequent than write opetations but for which nonvolatile storage is required. There are three common forms of read-mostly memory: EPROM, EEPROM, and flash memory The opticaily erasable programmable read-only memory (EPROM) is read and written electrically, as with PROM, However, belore a write operation, all the storage cells must be erased to the same initial state by exposure of the packaged chip to ultraviolet radiation, Erasure is performed by shining gn intense ultraviolet light through a window that is designed into the memory chip, This erasure process can be performed repeatedly; each erasute can take as much as 20 minutes to per- form. Thus, the EPROM can be altered multiple times and, like the ROM and PROM, holds its data virtually indefinitely. For comparable amounts ot storage, the EPROM is more expensive than PROM, but it has the advantage of the multiple update capability A more attractive form of read-mostly memory is electrically erasable pro grammable read-only memory (FEPROM). This is a reac-mostly memory that can sing prior contents; only the byte or bytes, addressed are updated. The write operation takes considerably tonger than the read operation, on the arder of several hundred microseconds per byte. The EEPROM combines the advantage of nonvolatility with the fesibility of being updatable in place, using ordinary bus control, address, and data lines. EEPROM is more expen sive than EPROM and abo is less dense, supporting fewer bits per chip. Another orm of semiconductor memory is flash memory (so named because of the speed! with which it can be reprogrammed). First introduced in the mid-1980s, flash memory is intermediate between EPROM and EEPROM in both cost and functionality, Like EEPROM, flash memory uses an electric) erasing technology. An entire flash memory can be erased in onte or a few seconds, which is much faster than EPROM. In addition, itis possible to erase just blocks of memory rather than an entire chip. Flash memory gets its name because the microchip is organized so that a section of memory cells are exased in a single action or “fash.” However, flash memory does not provide byte-level erasuze. Like EPROM, flash memory uses only one transistor per bit, and so achieves the high density (compared with EEPROM) of EPROM. be written into at any time without Chip Logic Ag with other integrated circuit products. semiconductor memory comes in pack- aged chips (Figure 2.7). Each chip contains an array of memory cells, In the memory hierarchy as a whole, we saw thal there are trade-ofls among speed, capacity, and cost. ‘These trade-ofls also exist when we consides the organi zation of memory calls and functional logic ona chip. For semiconductor memories, one of the key design issues is the number of bits of data that may be read!written ata lime. At one extreme is an organization in which the physical arrangement of cells in the array is the same as the logical arrangement (as perceived by the proces: soz) of words in memory, The array is organized into W words of B bits each. For— 144. CHAPTERS / (STERNAL MEMORY example, 4 16-Mbit chip could be organized as 1M 16-bit words. At the other ex: treme is the so-called one-bit-per-chip organization, in which data is readwritten fone bit at a time, We will illustrate memory chip organization with a DRAM: ROM organization is similar, though simpler, Figure 53 shows 1 typical organization of a 16-Mbit DRAM. In this case, 4 bits are read or written at a tims. Logically, the memory array is organized as four square larrays of 2048 by 2048 elements. Various physical arrangements are possible, In any cease. the elemenis of the array are connected by both horizontal (row) and vertical (col- lumn) lines. Each horizontal line eanneets to the Select terminal of each cel in its tows each vertical line connects 10 the Data-In/Sense terminal of each col in its eolumn. ‘Adress lines supply the address of the word 10 be selected. A total ef logs W lines are needed. In out example, 1] address lines are needed to select one of 2048 rows. These I lines are fed into a row decoder, which has I fines of input and 2s Fines For output. The logic of the decoder activates a single one of the 2048 out- puts depending on the bit psttera on the 11 input lines (2" = 2048). ‘An additional 11 address ines sclect ene of 2048 columns of 4 bits per column Four data Lines are used for the input and output of 4 bits 10 and from a data buffer (On input (write), the bit driver of each bitline is activated for a J or (according to the value of the corresponding data line, On output (read), the value of each bit Line is passed through a sense amplifierand presented to the cata fines. The row line selects which row of calls is used for reading or writing. Because only 4 bils arc read/written to this DRAM, there must be multiple DRAMs connected to the memory controller Lo readiwrite a word of data to the bus Note that there are only 11 address lines (A(-A10}, half the mamber you would expect for a 2048 % 2048 array. This is done to save on the number of pins. The 22 required address lines are passed through seleet logic external to the chip and multiplexed onto the LL address lines. First, 1] address signals are passed 10 the chip to define the row address of the array, and then the other 11 address signals are presented for the column address. These signals are accompanied by row acldress select (RAS) and column scldress select (CAS; signals to provide timing to the chip. ‘The write cnable (WE) and output enable (OF) pins determine whether & ‘write or read operation is performed. Two other pins, not shown in Figure 5.3, are ground (Vss) and a voltage source (Vee). ‘Asan aside, multiplexed addressing plus the use of square arrays result in & quadrupling of memory size with each new generation of memory chips. One more pin devoted to addressing doubles the nuntber of rows and columns, and so the size bf the chip memory grows by a factor of 4 Figure 5.3 also indicates the inclusion of refresh circuitry, All DRAMs cequire a refresh operation. A simple technique for retreshing is, in effect, 10 disable the DRAM chip while all data cells are reireshed. The refresh counter steps throuzh all of the row values, For each row, the output fines from the refresh counter sre sup plied to the row decoder and the RAS line is activated. The dats are read out and ‘written back into the same location.’This causes each cell in the row to be refreshed. Chip Packaging ‘As way mentioned in Chapter 2, an integrated circuit is mounted on 4 package that Contains pins for connection to the outside world,es ouniy “2pna9p eURNIAD ea Crxetorx stan deur oy a) 30 aM SYD SYY 145,146 CHAPTER 5 / INTERNAL MEMORY Figare Sida shows an example EPROM package, which is an 8-Mbit chip orga- nized a 1M % 8, In this case, the organization is tated as a one-word-per-chip package. The package includes 32 pins, which is one of the standard chip package sizes. The pins suppoxt the following signal lines ‘The address of the word being accessed, For 1M words, a total of 20 (2 = IM) pins are needed (AG-A19) ‘The data to be read out, consisting of ¥ tines (DO-D7). ‘= The power supply to the chip (Vee). A ground pin (ss). + A chip enable (CE) pin, Because there may be more than one memory chip, ‘each of which is connected to the same address bus. the CE pin is used to indi ‘ete whether or not the address is valid for this chip. The CE pin is activated y logic connected to the higher-order bits of the address bus (i.e., address bits above A19). The use of this signal is illustrated preseatly. ‘+ A program voltage (Vpp) that issupplied during programming (wil operations) A typical DRAM pin configuration is shown in Figure 5.40, for a 10-Mbit chip organized as 4M % 4, There are several differences from a ROM chip. Because a RAM can be updated, the data pins are input/output, The write enable (WE) and output enable (GE) pins indicate whether this isa write of read operation. Because the DRAM is accessed by row and column, and the address is multiplexed, ony address pins are needed to specify the 4M rowécolumn combinations (2! 2!" = Ao Alo als Alz 7 46 as Ma Aa Ad Al a0 pe bi ve (a) 8 Mbit EPROM (b) 16-Mbit DRAM Figure $4 ‘Typical Me sory Package Pins and Signals3.1 / SEMICONDUCTOR MAIN MEMORY 147 2° = 4M), The functions of the row auddress select (RAS) and columm address select (CAS) pins were discussed previously. Pinally, the no connect (NC) pin is provided so thot there are an even number of pins Module Organization Ia RAM chip contains only | bit per word, then clearly we will need at least « num: ber of chips equal to the number of bits per word. Asan example, Figure 5.5 shows how a memory module consisting et 256K &-bit words could be organized. For 256K words, an 18-bit address is needed and is supped to the module from some exter nal source (e4%. the address lines of a bus to which the module is attached), ‘The ies | aon Z| sonny reoner(MAR) ig) eee |48| Ginn g Jel deoder of inaag, Si tseme om aa reise : 2 i Deni t +] Str atsese Lstzuvese_| Bi 3 g| svat ia 512 bits S| cine | {al paaea a Figure $4. 256-Kbyte Memory Organiza148 CHAPTER 5 / INTERNAL MEMORY Memory address register (MAR) D1 Memory baller register coer All chips 312 wordsby ‘512 bits Dermal cells wits Figure 56 -Mbyle Memory Organization 6K ¥ L-bit chips, each of which provides the input address is presented to 8 output of | bit ‘This organization works as jong as the size of memory eq bits per chip. In the case in whieh larger memory is required, an array of chips is needed, Figure 5.6 shows the possible organization of a memory consisting of IM word by 8 bits per word, In this case, we have four columns of chips, each column containing 256K words arranged as in Figure 55, For IM word, 20 address lines are needed. The 18 least significant bits are routed to all 32 modules. The high-order 2bits are inpul to a group select logic module that sends a chip enable signal to one fof the four columns of modules. Is the number of A wmiconductor memory system is subject (0 errors. These ean be categorized as hard failures and soft errors. A hard failure is 2 permanent physical defect so that the memory call of cells affected cannet reliably store data, but become stuck at 0 for | or switch erratically between ( and 1. Hard errors ean De eased by harsh envi- ronmental abuse, manufacturing defects, and wear. A soft error is a random, non~ destructive event that alters the contents of one or more memory cells, without ‘damaging the memory, Soft errors can be eaused by power supply problems or alpba particles. These particles result from radioactive decay and are distressingly com- mon because radivactive nuclei are found in small quantities in nearly all material154. CHAPTER § / INTERNAL MEMORY 5.3 ADVANCED DRAM ORGANIZATION As was discussed in Chapter 2, one of the most critical system bottlenecks when using high-perlormance processors is the interlace to main internal memory. This interface is the most important pathway in the entire computer system. The basic building block of main memory remains the DRAM chip, as it has for decades; until recently. there had been no signilicant changes in DRAM architecture since the carly 1970s, The traditional DRAM chip is constrained both by its internal archie tecture and by its interface to the procestor’s memory bus. We have seen that one attack on the performance problem of DRAM main memory has been to insert one or more levels of high-speed SRAM cache between the DRAM main memory and the processor. But SRAM is much costlier than DRAM. and expanding cache size beyond a certain point yields diminishing returns. In recent years, a number of enhancements to the basic DRAM architecture have been explored, and some of these ate aow on the market, The two schemes, that currently dominate the market are SDRAM and RORAM, CDRAM has abo. received considerable attention. We examine each of these approaches in this section, Synchronous DRAM One of the most widely used forms of DRAM is the synchronous DRAM (SDRAM) [VOGLS4], Unlike the traditional DRAM, which is asynchronous, the SDRAM exchanges datta with the processor synchronized to an external clock signal and run- ning at the full speed of the procossor/memory bus without imposing wait states Ina typical DRAM, the processor presents addresses ancl control levels to the memory, indicating that a set of data at particular location in memory should be either read from of written into the DRAM. Aiter a delay, the access time, the DRAM either writes or seach the data, During the aeceys-time delay, the DRAM per~ forms various internal functions, such as activating the high capacitance ofthe row and column lines, semsing the data, and routing the data out through the outpnt bulfers The processor must simply wait through this delay, slowing system performance, With synchronous ascess, the DRAM moves data in and out uader control of the system clock. ‘The processor or otlier master issues the instruction and acldress information, which is latched by the DRAM. The DRAM then responds after a set number of clock cyeles, Meanwhile, the master ean safely do other tasks while the SDRAM is processing the request Figure 5.12 shovis the intemal logic of IBM's 64 Mb SDRAM [IBMOL} which is typical of SDRAM organization, and ‘Table 5.3 defines the various pin assign- ments. The SDRAM employs burst mocle to eliminate the address setup time and row and column line prechare time alter the frst access, In burst mode. a series of data bits can be clocked out rapidly after the first bit has been accessed. ‘This mode is useful when all the bits to he accessed are in sequence and in the Same row of the array 46 the initial access. In adlition, the SDRAM has a moultiple-bank internal architecture that improves opportunities for on-chip parallelism, The mode register and sssoclated control logic is another key feature differ- entisting SDRAMs from conventional DRAMs. It provides a mechanism 10 cus iomize the S ORAM 10 suit specific system needs. The mode register specifics theSense amplifies [Sesame I cKE—[ERE balter cik— [Ei batter 2 Figure £12 Synchro a156 CHAPTER 5 / INTERNAL MEMORY Table 53. SDRAM Pin Assignments AUIOAIS Address inp Lx F cho na exe Clock enable oS Chip select Row ares azobe Colum advesssiiobe WE Wits enable D a pant bw. Data musk duist length, which is the number of separate units of data synchronously fed onto the bus, The register also allows the programmer to adjust the latency between. of a read request and the beginning of data transfer “The SDRAM performs best when itis transferring large blocks of data seri ally, such as for applications like word processing, spreadsheets, and multimed Figure §.13 shows an example of SDRAM operation. In this case, the burst eth is 4 and the latency is 2. The burst read command i initiated by having CS and CAS low while holding RAS and WE high at the rising edge of the clock “The address inputs determine the starting column address for the burst, and the mode register sets the type of burst (sequential or interleave) ane the burst length (1, 2,4, full page). The delay from the start of the command to when the data from the first cell appears on the outputs is equal to the value of the CAS latency thot is set in the mode x There is now an enhanced version of SDRAM, known as double data rate SDRAM (DDR-SDRAM) that overcomes the once-per-cyele limitation. DDR- SDRAM can send data to the processor twice per clock eyele Rambus DRAM RDRAM, developed by Rambus [FARM92, CRIS97], has been adopted by Intel for jis Pentium and Ltanium processors. IU has become Uie main competitor to SDRAM. RDRAM chips are vertical packages, with all pins on one sie. The chip exchanges data with the processor over 28 wires no more than 12 centimeters long, ‘The bus can address up to 320 RDRAM chips and is rated at 1.9 GBps, The special RORAM bus delivers address and control information using an asynchronous block oriented protocol. After an initial 480 ns access time, this pro: duces the 1.6 GBps data rate, What makes this speed possible is the bus itself, which defines impedances, clocking, and signals very precisely. Rather than being controlled by the explicit RAS, CAS, B/W, and CE signals used in conventional DRAMSs, an RDRAM gels a memory request aver the high-speed bus. This request contains the desired address, the type of operation, and the number of bytes in the operation. Figure 5.14 illustrates the RDRAM layout. The configuration consists of a conuoller and a number of RDRAM modules connecied jogether via a common(© ~ Sonsmygyy “+ — U9] ing) Fue PERL EVA ers FMI ae Cm ee) EE {aox) SH} avvron 1 1 See 137‘sama TPA Tae PH UNE 15854 / RECOMMENDED READING AND WEB SITES. 159 bus. The controller isl one end of the configuration, and the far end of the bus is 4 parallel termination of the bus fines. The bus includes 18 data Lines (16 actual data, two parity) eycling at twice the elock rates that is, one bit is sent at the lead. ing and following edge of each ciock signal. This results in a signal rate on cack data line of 800 Mbps. There is a separate set oF 8 lines (RC) used for address and control signals. There is also a clock signal that starts at the far end from the con- troller propagates to the controller end and then loops back. A RDRAM modale sends data to the controller syachronously to the click to master, and the con: troller sends data to an RDRAM synchronously with the clock signal in the oppo: site direction, The remaining bus lines include a reference voltage, ground, and power sourte. Cache DRAM Cache DRAM (CDRAM), developed by Mitsubishi [HID.A90, ZIIANOI], inte- grates a small SRAM cache (16 Kb) onto a generic DRAM chip, ‘The SRAM on the CDRAM can be used in wo ways. First, it can be used as a true cache, consisting ofa number of G4-bit lines. The cache mode of the CDRAM 's effective lor ordinary randem access to memory ‘The SRAM on the CDRAM ean also be used 26 a bulfer 10 support the serial access of a block of data. For example, to refresh a bit-mapped screen, the CDRAM can prefetch the data from the DRAM into the SRAM buffer. Subsequent accesses 10 the chip result in accesses solely to the SRAM: | RECOMMENDED READING AND WEB SITES |PRINS1) provides & comprehensive treatment of semiconductor memory technologies, induding SRAM, DRAM, and flash memories. [SHAR9?] covers the same material, with ‘more emphasis on testing and reliability isues, [PRIN99| focuses on advanced DRAM and SRAM architectures. For an in-cepth look al DRAM, see [KEETOL] ‘A good explanation of error-eorreeting codes is contained in [MCELSS], For 3 deeper study, worthishile book-length treatments are [ADAMD1] aud [BLAL83}. [SHAR97] con: Tins t good survey of eades used ia contemporiay main memories, ADAMSL Adame, J. Fesndations of Coding, Now York Wiley. 1991, BLAUAS —Bishut,R. Theory ned Pruvsice of Error Consol Codes, Reading, MA: Addison: Wesley, 1983 KEETOL — Keeth, B. and Baker, R. DRAM Circuit Design: A Tutorial. Piscataway, NI TREE Press, 2001 MCELBS McPlicse, R. “The Reliability of Computer Memories.” Sciemufic American, January 1985, RINDI Prince, B. Semiconductor Memories. New York: Wiley, 1991, PRINI Prince, B. High Performance Momaries; New An htecture DRAMs and SRAMS. Esolution and Function New York: Wives, 199, SHARST Sharma, A. Semiconductor Memories: Technology, Testing, and Relibibey. Now Yorks IEEE Press, 1997.