ital Design Nt CTT Un EBRD tat SECOND EDITION Frank Vahid& e | | “Genre sued, Dsnber2, 200 5:2 94 Digital Design with RTL Design, VHDL, and Verilog SECOND EDITION FRANK VAHID University of California, Riverside WILEY AA obn Wiley & Sons, Ine, Publication \s —+/@ Obras protegidas por Direitos de|AutorTH fn Pasi Toss, Doser 2, 209 522 PM To my family, Amy, Erie, Kelsi, and Mava; and to all engineers who apply their skills 10 improve the human condition. VP and EXECUTIVE PUBLISHER Don Fowley ASSOCIATE PUBLISHER Dan Sayre EDITORIAL ASSISTANT Katie Singleton ~~ SENIOR PRODUCTION MANAGER Micheline Frederick Y SENIOR PRODUCTION EDITOR Kerry Weinstein EXECUTIVE MARKETING MANAGER. Chrisiopher Ruel COVER DESIGNER. Jim O'Shea MEDIA EDITOR Lauren Sapira COVER PHOTO Comstock Images/Getty Images. In. iStockphow This book was set in 10/12 Times Roman by Frank Vabid. The text and cover were printed by Donnelley/Crawfonisvile {Copyright © 2011, 2007 Jolm Wiley & Sons, fe, All sighs reserved. No ptf this pblistion may be Fepvaticed stra! in activa syiem e transmit in any form oy any rears clstoni, mecha, Potecop a, resordine cannon ours. excel aspera ener Section 10 of 108 the 1916 Entel Stass Cansei Act witht ether te peer writen pemisson ofthe Publish, or autorzatica Aivough payment of te apprprseporcopy fe tothe Cepyrigt Clearance Center, ne. 23 Rosovood Dane Daners v8. senate wi eopyanscom. Reqrests ie Publis permission shoud he ates fo the Petssions Departent on Wiley & Sons Ine 1 River Sed [Toboken NE [Bahn cob pec a ale ees und room Foe pute Bai fo is ‘o'r cousen during he eat academe your ‘These copies ate Heeased and my tate sold oF leaned toa thd pry Upon completion of therevies pein, please mara te esti copy 10 ‘Wits Rotrn imauctods an seo charge ret sippng label ae sll t wo ey aap returtiabel: Outside ofthe United State pleat enact your lel repesertalive ISuN 9780-47H-S8108-2 Print inthe Unite States of AmericaTE fm Page it Tsay Dssember 222009 $20 Pa Contents Preface ix ‘To Students About To Study Digital Design ix To Instructors of Digital Design ix How to Use This Book xi RTL-Focused Approach xii Traditional Approach with Some Reordering xi Traditional Appenach xii Acknowledgements. ii About the Cover xiv About the Author xiv Reviewers and Evaluators xv > CHAPTER 1 Introduction 1 1.1 Digital Systems in the World Around Us 1 1.2 The World of Digital Systems 4 Digital versus Arwiog 4 Digital Eneodings and Binary Numbers—Osand 1s 9 1.3 Inplementing Digital Systems Microprocessors versus Digital Circuits 22 Software on Microprocessors: The Digital Workhorse 22 Digital Design—When Micropmneessors Aren't Good Enough 2 » CHAPTER 2 Combinational Logic Design 35 2.1 Introduction 35 2.2. Switches 36 Blectronics 101 36 ‘The Amazing Shvinking Switeh 37 ‘The CMOS Transistor 4 2.4 Boolean Logie Gates—Building Blocks foe Digizal Circuits 43, Boolean Algebra and its Relation to Digital Circuits 48 AND, OR, & NOT Cates 46 Building Simple Cirents Using Gates 49 2.5 Boolean Algebra 52 ‘Notation and Temintlogy $3 Some Properties of Boolean Complementing a Function 60 2.6 Representations of Boolean Functions 61 uations 62 Greuits 62 ‘Th Tables 62 Converting among Boolean Furetion Representations 64 nda! Representation and Canonical Horm ‘Muliple-Output Combinational Circuits 71 2.7 Combinational Logie Design Process 73 2.8 More Gates 80 “NAND.&-NOR 80 XOR & XNOR 81 Inceresing Uses of these Adon Gates 82 Completeness of NAND and of NOR 82 ‘Namiber of Possile Logic Gates 83 2.9 Decovders and Munes 84 Decoders 84 ‘Maltiplexers (Maxes) 86 2.10 Additional Considerations 91 Nonideal Gate Behavior—Delay 91 Active Low Inputs 92 Demotiplexers and Encoders 93 Schematic Capture ard Simulation $3 2.11 Combinational Logic Optimizations and Tradsofls (See Section 6.2) 95 2.12. Combinational Logie Description Usin Hardware Description Languages (See Section 02) 95 2.13 Chapter Summary 96 2.14 Exercises 96& Or 4 Pgs Testy, Dose 2,309 5:20 ? Iy > Contents » CHAPTER 3 » CHAPTER 4 Sequential Logic Design: Controllers 105 Datapath Components 167 1 Inteeduction | AdL_Intreduciion 167 3.2 Storing One Lit—Flip-Flops. 106 4.2 Registers 168 Peedhack ~The Basie Storage Method 106 Paralle-Load Register 168 sie SR Latch LO? ‘Shift Register 173 Level Sensitive SR Latch 11 Mukifunction Reghters 175 eset Sins D Latch i bi Register Design Process. 179 Eage-Trigacted D Mip-Flop—A Robus Bit AS shiers: SL “Soe 13 Ader—Cary-Ripple Site 183 44° Comparators 191 Exquality (Kdersity) Comparator 191 Magnitude Comparor—Carry-Ripple Style ‘Clocks and Synchronous Cireaits 117 Basic Register—Storing Muliple Bits 120 33 Finite-State Machines (FSMs) 122 ae ‘Maaiemaieal Fortis for Sequential 45° Muliplier—Amray-Style 195 Behavier—FSMs 124 U6 Subractors ad Signed Numbers How to Capture Desired System Behavior asan 48 ‘Subtoes nd Signet bers 198, ‘Subacter for Positive Numbers Only: 196 — enting Negative Numbers: Two's: 34_Contollee Design 132 “Sepiceea ewan 00 ‘Stand Contes Ambien far Building Subirctr Using an Adder and Two's Ainplementin Complement 203 anfSMas a Seivetl Ciuc 122 Detting Ovartow 205 | Controller (Sequential Logic) Design Process 4.7. Arithmetic-Logic Units—ALUs 207 oe akg 4.8 Shifters 210 | Converting 9 Cire to on PS (Ravers ‘imple Sifters 211 gineering) 140 Barel Shier 214 Common Mistikes when Capturing FSMs 14249. Counters and Timers 215 £SManiConmlle: Comsentions US, Up-Courter 216 3.5 More on Flip-Flops and Controllers 146 Up/Down-Counter 217 Non Ideal Flip-Flop Behavior 146 Counter with Load 218, PlipFlop Reset and Set Inputs 149 ‘Timers 222 “tid Sts of Coatroller 150 4.10 Register Files Non-Adeal Consolle Behavior Ou Glitexes 4411 Datapath Component Tradeoffs (See Section 1st 64) 280 3.46 Sequential Logic Optimizations and 4.12 Datapath Component Description Using “adeotfs ‘Hardware Description Languages (See See Section 6:3) 153 Section 9.4) 230 4,13 Product Profile: An Ultrasound Machine 230 Functional Overview 231 Digital Circuits in an Ulrasoand Machine's 2.7 _ Sequential Logic Description Using Hardware Description Languages (S« Section 9.3) 153 fi tls Beamformer 234 39 Chapter Summary 156 Future Challenges in Ulmasound 237 10 Exervises 157 4.14 Chapter Summary 237 4.15 Exercises 238 Obras protegidas por Direitos de|Autor» CHAPTERS Register-Transfer Level (RTL) Design 247 3.1 Invoduetion 247 5.2 High-Level State Machines 248 3. RTL Design Process 255 Step 2A—Creating a Datayath using ‘Components from a Library’ 259) 2H—Connesting the Datapath toa Controller 262 Step 2C—Deriving the Controller's FSM 263 5.4 More RTL Design 264 ‘Adaltional Datapath Component forthe Library 204 RT. Design Invelving Register Filesor Memories 265 TL Design Pith Involving Storage Upaates am RTL Design Invelving 2 Timer 272 ‘A Data-Dominated RTL Design Example 273 5.5. Determining Clock Frequency 278 5.6 Behavioral-Level Design: C t0 Gates (Optional) 281 5.7 Memory Components 2% Random Access Memory (RAM) 286 Bic Storage ina RAM 288 Using aRAM 260 Read-Only Memory (ROM) 292 ROM Types 294 Using aROM 257 The Blurring of the Distinction between RAM ant ROM 299) 5.8 Queues (FIFOs) 299 5.9 Multiple Processors 303 5.10 Hierarchy—A Key Design Concept 305 Managing Compieity 305 Abstraction 306 (Composing a Larger Component from Smaller Versions ofthe Same Componsat 307 5.11 RTL Design Optimizations and Tradeoffs (See Section 65) 309 5.12 RTL Design Using Hardware Description Languages (See Section 9.5) 310 si 5.13 Product Profile: Cell Phone 310 lls and Basestations 310 How Cellular Phone Calls Work 311 Inside a Celi Phone 312 5.14 Chapter Summary 316 5.15 Exercises 317 >» CHAPTER 6 Optimizations and Tradeoffs 325 6.1 Introduction 325 6.2 Combinational Logic Optimizations and Tradeoffs 327 Two-Level Size Optimization Using Algebraic Methods % [A Visual Method for Two-Level Size (Optimization—K-Maps 329 Don't Care Inpa Combinations: 336 Automating Two-Level Logie Size Optimization 339 Multilevel Logie Optimization Performance and Size Tradeotis: 48 6.3. Sequential Logie Optinn Tradeoffs 351 ‘State Reduction 351 Sute Encoding 354 Moore versis Mealy FSMs 360 6.4 Datapath Component Tradeoffs. 365, Faster Adders. 365 ‘Smaller Multiplier Sequential (Shiftand-Adid) Style 375 6.5 RIL Design Optimizations and Tradeotts 377 Pipelining 377 Concurrency 380 Component Allocation 381 (Operator Binding. 382 (Operon Scheduling 385 ‘Moore versts Mealy High-Level State Machines 386 6.6 More on Optimizations and Tradeofs 386 Serial versus Concurrent Computation 386 (Optimizations and Tradeolfs at Higher versus Lower Levels of Design 387 Algorithm Selection 388. PowerOptimization 389 vations and@ To Pago Tusa, Dacre 2,209 5:20 > Contents 6:7 Product Profile: Digital Video Player! » CHAPTERS Recorder 393 Programmable Processors 461 Digital Video Overview 393 BL Introduction 461 DVD One Form of Digital Video Stomge 393g. Basie Architecture 462 MPEG-2 Video Encoding—Sending Frame asic Datspath 462 Dilferences Using F- P-,and B-Frames 395 ‘Transforming fo the Frequency Domain for Further Compression 396 a 68 Chapter Summary 402 69 Bxerwises 403, Basie Control Unit 465 A Three-Instruction Programmable Processor 469 A Fist lastruction Set with Three Instructions 469 (Coverol Unit and Datapath for the Thies >» CHAPTER 7 Instruction Processor 471 Physical Implementation on ICs 413 84 A Six-Instruction Programmable Processor 7A Introduction 413 475 72 Manufacured IC Types 414 Exending the Instretion Set 475 Full-Custom Integrated Cireits 414 Extending the Control Unit and Dataath 476 Semicustom (Applisation-Sprcitie}Inteprted 5, Example Assembly and Machine Programs Circuits ASICS 415 478 72) Off he Shell eoramunsbie IC 8.6. Further Extensions to the Programmable Type FPGA 423, Procesor 480 Lookup Tables 424 Insintion Set Extensions 480 Mapping a Circuit among Multiple Lookup a Takin oe InpulOurput Extensions 481 5 Performance Extensions 481 rogram Interconnects (Switch Matis eee Switch MES) 8.7 Chapter Summary 482 Configurable Logic Block 44 88 Exercises 483 Oserill FPGA Architevtme 436 7A Other Off-the-Shelf IC Types 438, >» CHAPTERS Off-the-Shelf Logie (SSD IC 438 Hardware Description Languages 487 Simple Programmable Logic Device (SPLD) 9.4 Introduction 487 44 ‘ sri Brogranaacilcisnet Sve 3 9.2. Combinational Logie Description Using. CompexProgamable Logie Deve (CPLD) Medias Descttiont anise: 48 ‘Structure 489 Combinational Behavior 494 Testhenches 498, FPGA-to Siructured-ASIC Flows 445 75 1C Tradeoffs, Trends, and Comparisons 446 Tradeofts Among IC Types 447 IC Technology Trend Moon's Law 448 9.3 Sequential Logic Description Using Relaive Popularity of IC Types 450 Hardware Description Languages. SOL Register 501 IC Types vers Processor Vasities 451 Oseilator 503 FPGAs alongside Microprocessors 452 Contolles 505 76 Product Profile: Giant LED-Based Video 9.4 Datapath Component Description Display with FPGAS 453 Using Hardware Description Languages 7.7 Chapter Summary 457 509 78 Exercises 457 Pull-Adders 509TOR In Page es, ese 22,2009 Cary Ripple Adders $11 Up-Counter 514 9.5. RIL Design Using Hardware Description Languages 517 High-Lovel State Machine of the Laser-Based Disuance Measurer $17 CConollr and Datapath of the Laser Based Distance Measurer $23 9.6 Chapter Summary 532 97 ss $32 » APPENDIX A Boolean Algebras 537 A.1 Boolean Algebra 537 A.2. Switching Algebra 538 A.3. Important Theoremsin Boolean Algebra 540 A.4 Other Examplesof Boolean Algebras 545, A.5 Further Readings 545 » APPENDIX B Additional Topics in Binary Number Sys- tems 547 Bal. Introduction 347 B.D. Real Number Representation 547 B.3 Fixed Point Arithmetic 550 Boating Point Representation 551 “The IEEE 754-1985 Standard 552 B.S. Exercises 556 » APPENDIX C Extended RTL Design Example 557 Cal Inteoduction 557 C.2_ Designing the Soda Dispenser Controller 558 C.3- Understanding the Behavior of the Soda Dispenser Controller and Datapath 562@ | bce Pai Twat Omenbs 2200 $3014 F : ‘Autor Obras protegidas por Direitos de!image not availableimage not availableimage not availableHT ttn ge 4 Tend Desens 8 2008 9:53AM 1 Introduction » 1.2 THE WORLD OF DIGITAL SYSTEMS is signal that atany time ean have one of a finite set of possible values, In contrast, an analog signal can have one of an infinite umber of possible values, and is also known asa continuous signal. A signal is just some physical phenomenon that has a unigue value at every instant of time. An everyday ‘example of an analog signal is the temperature cutsiée, because physical temperature is a continuous value—the temperature may be 92.356666... degiees. An everyday example ‘ofa digital signal is the numer of fingers you hold up, ecause the value must be either 0,1, 2, 3,4, 5,6, 7,8 9, or 10—a finite set of valves, In fac, the term “digital” comes from the Latin word for “digit” (igitus), meaning finger In computing systems, the most commen digital signals are these that can have one of only two possible values, like on or off (often represented as 2 oF 0). Such a two-valued representation is known 2s a binary representation. A digital system is a sysem that takes digital inputs and generates digital outputs, A digital eircuit is a connection of digital com- ponents that together comprise a digital system. In this teatbook, the verm “digital” will refer to systems with binary-valued signals. A single binary signal is known as a binary , or bit for short (binary digi). Digital electronics became extremely popular in the ‘mid-1600s after the invention of the transistor, an electric switch that can be turned on or off using another electric signal. We'll describe transistors further in the next chapter Digital Circuits are the Basis for Computers ‘The most well-known use of digital cireuts in the world around us is prob- ably to build the microprocessors that serve as the brain of general-purpose computers, like the personal computer or laptop computer that you might hhaye at home, illustated in Figure 1-1(a). General-purpose compaters are also used as servers, which operate bebind the scenes to implement banking, airline reservation, web search, payroll, and similar such systems, General- purpose computers take digital input data, such as letters and aumbers ved from files or keyboards, and output new digital data, such as new Figure'.1 (a) General-purpose letters and numbers stored in files or displayed on a monitor. Learning about ‘computer digital design is therefore useful in understanding how computers work “under the hood,” ané hence has been required learning for most computing, and clecirieal engineering majors for decades. Based on material in ‘upeomiing chapters, we'll design a simple computer in Chapter 8, Digital Cireuits are the Basis for Much More Increasingly, digital circuits are being used for much more than imple- menting general-purpose computers, More and more new applications convert analog signals to digital ones, and ran those digital signals through cusiomized digital circuits, to achieve numerous benefits. Such applications, such as those in Figure 1.1(b), include cell phones, automobile engine con- trollers, TV se-top boxes, music instruments, digital cameras and camcorders, video game consoles applications other than general-purpose computers are often called embedded ‘Aout 10.00 unique new dignar S3SHEMS; Because those digital systems are embedded inside another elec~ Grete weredesiqned w 2008." ‘onic device. & & and so on. Digital cirouits found inside (b) Embedded systemsimage not availableimage not availableimage not available@ |-@-arnn ger eat, deters, 0 94a ° | @ T r 8 > 1 Introducion Setaites ovo vaca usta Potaie payers recorders instumens muse players Celiphores Cameras Ws ™ 4998 1997 1998 200120032908 -—«2007 Figure 1.4 Mote and more analog products are becoming primal digital igure 1.4, over the past decade numerous products that were previously analog have convened primarily 10 digital technology. Portable musie players, for example, switched from cassette tapes to digital CDs in the middle 1990s, and recently to MP3s and other digital formats. Early cell phones used analog communication, but in the late 1990s digital communication, similar in idea to that shown in Figure 1.3, became don inant, In the early 2000s, analog VHS video players gave way to digital video dise (DVD) players, and then to hard-drive-based digital video recorders (DVRs). Portable video cameras have bogun to digitize video before storing the video onta tape of a hard sve, while still picure cameras have eliminated film and store photos on digital cards, Musical instruments are increasingly digital-based, with electronic drums, keyboards, and electric guitars including mote digital processing. Analog TV is also giving way to digital TV, Hundreds of other devices have converted from analog to digital in past decades, such as clocks and watches, household thermestats, human temperature ther- ‘mometers (which now work in the ear rather than under the tongue or other places engine controllers, gasoline pumps, hearing aids, and more. Many other devices were never analog, instead being introduced in digital form from tae very start. For example, video games have been digital sinee their inception, ‘The above devices use digitization, and digitization requires that phenomena be encoded into 1s and 0s. Computations using digital circuits also require that numbers be digitized ito 16 and 0s. The next section deseribes how to encode items digitally. The telephone, patented by Alexander Graham Bell in. telegraph was all people needed, the late 18005 (though inverted by Antonio Moucei), + Dell and his assisunt ‘operates using the electomagnetie principle described Watson. diageed_ on carlier—your speech creates sound waves thal move @ how to answer the membrane, which moves a magnet, which creates phone: ‘Watson wanied ccurent on a nearby wire, Run thal wire to somewhere “ellos” which won, | far away put magnet connected to a membrane neat pyr Bell wanted “Hoy that wire, and the membrane will move, producing joy” instead, (Fans of sound waves tht sound ike you wtking. Much of the jh Ty shew The telephone sysiem tndaydigtzes the auio to improve Scans may bave quality and quantity of audio trarsmissions over long FO ME ne itnces, A couple of interesting facts about the poued fat Homers telephone! answers the phone with + Believe it or not, Westem Union actually med cl Sena ‘down Bell's initial proposal to develop the — MY Hoy") BB ee telephone, perhaps thinking that the then-popular {Source of some ofthe above materi: www: pore, ‘womsergt of "The Telephne”image not availableimage not availableimage not available@ 12 > 1 Introduction Indian Exglish has nane for 10" Tak fe Ian cor one lak car” ooo aout $2.50, Me Web search Goegle cnies fromthe wont gogo!” a J pated 09100 npn thar ‘earch a bt of gli speakers use eames far rious qhinttes in ‘se ten, mames that are usefil but ean hamper gaining an intuitive undersianding of base ten. 10" hss iis own name: handed, 10° bas the name ‘Morsaad. Toere is no name (in American English) fee 10! or 108. 10° has the ame milion, and subsequent groups that are multiples of 1,000 have te names illion, rilion, quaditin, ct English speaker also use abbreviated names for groups of tens—the numbers 1), 20, 30, 90 eould be called fone tea, {0 Len, up lo nine ten, but instead have abbrevilted names: one fen a just “ten.” two ten Is “twenty.” upto ine ten being “ninety” You can see how “ninety” is a shortening of “ine ten. Special ‘ames re ako used foe the numbers between 10 and. 20. 1 could be “one ten one” but is invead “eleven: ville 19 could te “one ten nine” but is sea ‘Table Ll indicates ‘ight count in ase ten without these various nares, ‘o emphasize the nature of base ten. 323 might be spoken as “five nde two ten three” rather than “ve hundred twenty-nee” Kids may have a harder time leaming math hecinse af the aebirary hase ten rnames—for example, carrying a one from the ones ohinn to te tens column makes mow seme ifthe foes column sums to “one ten seve ater than to “seventeen—"one ten seve” obriously ads one to the tons column, Likevise, leaming binary may be slightly hander for some students due to a ack of solid understanding of base ten, To he'p remedy the sittation, pethaps when a store clerk tls you “That sill bo sinety-wine cent" you might sey “You mean nine ten nine ents” If enough of us do this, perhaps ‘wll each on? mien” Taw ore “Table 14 Counting in base ten without the abbreviated or short names, re) ‘As usual ero: “WO? an “ine 10 1099 1D, 11, 12, «19: "one ten,’ “one ten one. “one ten wo." . “one wen nine 20, 21, 22, 28 i “vo ten one,” “two ten two.” “Wo ten ine” 30, 40, 0: “nee ten,” “four ten. “nine ten” 100 t© 900 ‘As usual: “one hundred,” “wo hundred”. “nine hundred” Even clearer would be to replace the word “hundred” by “ten the power of 2” 1000 sedup Ad uaa, Even clearer for undewtanding banca: roplace “housand” by “on tthe (power off 3°, “en thousard” by Example 1.1 Using digital data in a cigital system A digital system is desired dha reads the ‘hie of temperature sense and shave the letier “F” (for “freezing”) on a display if the lemperture is 22 degrees Fatrenieit or ‘plow, shows "N° (for “normal ifthe tem: perature is between 32 and 212 degrees, and shows the Teter “RY (for “boiling”) i the Aemperature is 212 or greater, The tempers ture sersor has an S-bie output representing the temperature asa binary number beeen ( and 255. The display has 27-bit input thee accepts an ASCITBit encoding and csplays the comtesponding symbol, Figure 1.13 shows dhe temperature sensor output connected to the iaput of the desired digital system, Each wire can have “ten to the 4," ete, eliminating the various names, p [i Digital System \tlingut 90100000" 4/92" utp = "1000110" 77" else input "1 10101004) // 212" ‘output = *s000050"// “8 outpu iii ‘isp [N Figure 1.13 Digital system with bit eneoded input {an 8-it binary rumber) and 7-bit ouput (ASCID. “The dosiod behavior of the digital systom i shown, Obras protegidas por Direitos del Autorimage not availableimage not availableimage not available‘HT into) Page 16 esd, Desember 8. 200 958 ANE 16 > 1 Introduction Desired value: 73 » HAUUAWW \ ‘84 tina =ingy } \ gat / \ os / cotng tn = 2 / \ |e Se a P Figure 1.17 Decioal to binary convesion fara DIP awiteh: (a) ceiling fan with remate contr both having DIP switches set theireommunication channel, (b) setting the fan's channel 10 “73 requites fist converting 73 0 binary, hen setting the DIP switeh to present that binary value (c) esting fan module only ouiputs 1 ifthe received channel matches DIP switch setting. Instead, he/she can open the ceiling fan module and the remote controller of one pair, and simply change the DIP svitch settings for tha pait, ensuing that both DIP switches mach afer the change While this section introduced the addition method for converting from decimal binary, many books and web resources introduce the subtraction method, whorein we start by seting a current number to the desired decimal number, put a 1 in the highest binary number phace that doesn’t exceed the current number, subtract that place's weight Fram the carrent number, and repeat until the current number reaches zer0. The two methods are fundamentally the same; the addition method may be more intuitive when ‘converting by hand Base sixteen numbers, knows as hexadecimal numbers or just hex, see also popula in digital design, mainly because one base sixteen digit is equivalent o four base two digits, _making hemadecimal numbers a nice shorthand representation for binary numbers. In base siateen, the first digit represents up to fifteen opes—the sixteen symbols commonly used are 0, 1, 2,5 9, A:B, C, D, E, F (so A = ten, B = eleven, C = twelve, D = thirteen, digit represents the number of groups of 16!, the next digit the number of groups of 16%, ete., as shown in Figure 1.18. So BAF, equals BH16? + 10°16! + 15°16", oF 2223, ee —o|@ Obras protegidas por Direitos de|Autorimage not availableimage not availableimage not available"HT ino) Pgs 20-Tesdy, Deeb 8, 2009 9:5 ANE 20 > 1 Intraduetion Becimal Birary (6) 1. Divide decimal number by 2 Incetremaincer inf he binay number Continua since quoient 6) = greater then 0 (curentvaiue: 0) 2, Divi quotient by 2 ave 20 ye crclcn (a tose one = 27 ice eneeguice 6) ey caer co (currentvalue: 0) 1 3, Divide quotiont by 2 evo eek ives t oan tb: Be Shen Tine =a 421 Cee seen ea iegeere | 10 (ouenvaie 4) 4. Dive quotient by 2 at tiga ed die cee ay epee a42t Siete, done 1 (euent value 12) Figure 1.21 Converting the decir number 12 t binary using the divide-by 1120, Checking the answer shows that 1210 is corect: 1#2°+ 1822+ 192! 082! = 8442 u To comert © to binary, the process is the same but natrally akes mone steps: 99/2 remainder 1. 49/2 = 24, remainder 1. 2472 = 12, remainder (. 122 = 6, remainder 0. 6/2 = 3, remainder 0. 3/2 = 1. remainder 1. 1/2 0, remainder 1. Combining the remainerstopether pisos us the binary number 110001..We know from Exemple 1.3 that this isthe coreet answer We can use the sume basic method to convert a base 10 number to a qumber in any ‘base. To convert a number from base 10 t0 base #, we repeatedly divide the number by 1 and place the remainder in the new tase number, starting from the least significant digit, The method is called the divide-by-n method, Example 1.9 Decimal to arbitrary bases using the divide-by-n method Conver: the number 3439 to base 10 snd to base 7. We know the number 3439 is 3439 in base 10, but ler's use the dvide-by-n method (where ns 10) to ilastrate that the method works far any hae. We start by dividing 499 by 10: 3430110, 343, remainder 9. We then divide the quotient by 10: 345/10 = 34, reminder 3, We do the same Wilh the new quotient 34/2 = 3, remainder 4, Finally, we divide 3 by 10: 3/10 = 0, mainder 3 ‘Combining the remainders, least significant digit first, gives us the base 1) number 3439. “To comert 3439 w base 7, the approach is similat, except we now divide by 7. We begin by viding M4 by 7- 2130/7 = 491, remainder 2 Continuing or eaeulaons, we got 407 = 70, semainder 1. 70/7 = 10, eomainder 0, 10/7 = I, remainder 3, 1/7 =, remainder 1. Thus, 3439 in base is 13012. Checking the answer verifies that we have dhe correct resus 167! 4 5078 = OT 4 eT! 207 = 2401 + 1029 +7 + 2= 3439, Conversion between any two bases can be done by first converting to base ten, then converting the base ten number to the desired base using the divide-by-n method, Obras protegidas por Direitos d 8 @image not availableimage not availableimage not available| Sirsa serine ncn sw en 24 > 1 Intraduction Fae Las erou in meanpte ot the ves of sigan, Ban F over a time, wth Une. prceeding to the Tish As time proceeds, cach simal y¢ | may be citer 0 or 2, iltsinted by titer iow or high, We ads a egal € too unl me 705, when we mage a 796, wen we made a rturn back Oo. Wemadew sty unt 9:0, when wwe made a become 2 again, and then Wemale a heceme 0 at 201. On the i ta eae fear a 6 asa Rs lol Vg ON sung shows wha the vale of F would be given the © progam excesting on the mlerpro- tesso-—hen als 1 and b io (rom’?05 to 206) F mill be 2A diagrn with tine rvcadlog ey Ad igh afd da als OF all erate icky ght he ag Enown a adiming dagrem. We draw the input ins (2 and 8 tobe whatever valves we sant, Dut then te outpt line(F) must deserve the behvlor Othe gla sytem, Figure 125 ‘Timing diagram of motion in-the- dak deector system, . Soar Sp a ns rats? | > Lasse the basic microprocessor of Figure @ 128 to implement a system that sounds to Fo =) biszor whom mction ir detected t any of Aer! unter tice motion sersors outside « house. We tg Pe) connect the motion sersors o microprocessor te § ro) input pins 1, 17, and I2, and econec: output 4 § Pal pin PO toa buzzer (Fguce 1.26). (We assume 15 3 Ps) the nol Geos eel care have ap is * Fe) priate electronic intrtces to the iP Inieroprocesoe pins.) We cin then waite te following C prope © |Qroven sensor void nain() { Figure 1.25 Motion sensors connected to, white (0) { mieroprocessox po = 10 || a2 || 12; } } “The program exccites the statement inside the while loop repeatedly. Tha statement will set PO 01 if) ist ar orien as || inthe C language) I is 1 er 1? 62. othorwise the sttoment sets PO 0. es . | r @ Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not available| Si rsia sername ei ? 32 > 1 Intraduction 1.22 Conver the following hewslecimal numbers to binary: (a) ASE (by SPAD (6) 3E2A (@) DEED 1.23 Conver the following hexadecimal nambers t binary’ (a BOCS by 1EFOS (e) Pon (@) BEEP 1.24 Conver he following hexadecimal numbers wo decimal: (a) FF by Poa (©) OF 00 (a) 100 1.25 Conves the following hexadecimal n (a 10 (by a3 () FPO (@) 200 1.26 Conver the decimal mumber 128 to te following number systems: (a) binary (b) hexadecimal | {e) base dee 2 (0) base five « {) base filteen 127 Compare the number of digits ncesssnry to cepreteat the following decimal ushers binary. octal, desimal, and hexadecimal representations, You need not determine the actual representatons-—just the number of required digits. For example, representing the decimal ‘number 12 requtes four dizts in binary (1100 is the actal representation} two digits in octal (14), 180 digits in decimal (12), and one digit in hexadecimal (C) cas (h) 60 {) 300 (a) 1000 {} 998,999 1.28 Determine the decimal number ranges thet can he represented in binary, octal, decimal, an hhoxadecimal using the following numbers of digits. For example, 2 digits ean represent seeimal number range 0 through 3 in binary (0 through 11), 0 through 63 in octal (00 through 77), 0 through 99 in desimal (00 throuth 99), and O through 255 in hexadecimal (00 through FP wt 3 wo as ners to decimal: Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not availableimage not availableimage not available2 ? 40 > 2 Combinational Lovie Design 1 you took a pencil and made the smallest dot that you could on a sheet of paper. that dot’s area would hold ‘many thousaeds of transistorson amodern silicon chip. ow can chip enakrs esata aich tiny transidors? The key lies in photographie methods. Chip makers lay a special chemical onto the chip—special because the chemical changes when expesed to light. Chip mskers then shine light through a Tens that fecuses the light down to extrmely small rogions on the chip similar to how a miesoscope’s lens leis us see tiny things by focusing light, butin reverse. The chemical in the small iMluminased region changes, and then a solvent washes away the chemical—hut some regions stay because of the light that charged that region, Those remaining ‘tegions Form parts of tansisiors, Repeating this process foyer and over again, with different chemicals at cliferent steps, results not only in transistors, bat also ‘wires connecting the tansitors, and insulators preventing crossing wires from touching. Photograph of a Pentium processor's silicon chip, hhoving millions of Iransisiors. Actual size is ‘ahout 1 em vach side, Atom or Celeron processor, requites only about $0 million transisors, and the processor ina cell phone, like an ARM processor, may have only a few million tansisors, Many of today’s high-end chips, like chips inside Internet routers, contain tens or hundreds of such microprocessors, and can conceivably contain thousands of even smaller microprocessors > of 1 ent ey 18 oe lyin oe Mow Law tamed as Goon & ‘number of components per IC would double every year or so. At some point, chip makers ‘won't be able to shrink transistors any further. After all, the transistor has to at least be wide enough te let electrons pass through. People have been predicting the end of Moore's Law for two decades now, but transistors keep shrinking, though in 2009 many observers noted a slowdown, Not only do smaller transistors and wires provide for more funetionality in a chip, Dut they also provide for faster circuits, in part tecause electrons need not travel as far to ‘get from one transistor to the next. This inereased speed is the main reason why personal ‘computer clock speeds have improved so drastically over the past few deeadss, from kilo- hertz frequencies in the 1970s to gigahertz frequencies in the 2000s. > 2.3 THE CMOS TRANSISTOR ‘The most popular type of IC transistor is the CMOS transistor. A detailed explanation of how a CMOS transistor works is heyond the scope of this hook, but nevertheless a sirmpli- fied explanation may satisfy much curiosity A chip is made primarily from the element silizon. A ehip, also known as an inte ‘grated eltcnit, or IC. is typically about the size of a fingermail. Even if you open up a computer or other chip-based device, you would not actually see the silicon chip, since chips are actually inside a larger, usually black, protective package. But you certainly Obras protegidas por Direitos de!Autorimage not availableimage not availableimage not available@ | Srrsawrcnnarmancsne nan ? — C) 44 © 2 Combinational Lovie Design ‘ba sorthand for © Example 21 + OR retums 1 if either or both of its operand are 1, So the result of a OR bis 1 in any of the following cases. ab=01, ab=10, ab=11. Thus, the only time 4 OR bis 0 is when ab-09, + NOT reuens 2 if its operand is 0. So NOT(a) retwens 2 if a is 0, and rewrns 0 if ais. Wo use Boolean logic operators frequently in everyday thought, such as in the sate- ment “I'll go to lunch if Mary goes OR John goss, AND Sally does not go.” To represent this using Boolean concepts, let F represent my going 10 lunch (F=1 means I'll go to lunch, F=0 means I won't go). Let Boolean variables m, j, and s represent Mery, John, and Sally exch going to lunch (so s=1 would represent Sally going to lunch, else s=0) ‘Then we can translate the above English sentence into the Boolean equation: FS (m OR 3) AND NOT(s) So F will equal 1 if either mor 5 is 2, and s is 0. Now that we've translated the English sentenes inte a Boolean equation, we ean perform several mathematical activities ‘with that equation. One thing we ean do is determine the yalue of P for different values of m,j,and s: + mei, $=9, 891+ F=(1OR 0) AND NOT\1)=1 AND 9 + mea, Jan, 820-4 F = (1 OR 2) AND NOT(0)=1 AND 2 = In the first case, I don't go to lunet; in the second, 1 do, A second thing we could do is apply some algebraic rules (dissussed later) ty moditty the original equation to the equivalent equation: F = (mand Nor(s)| OR (j and NoT(s)) In other words, Hl go to lunch if Mary goes AND Sally does not go, OR if John goes AND Sally does not go. That statement, as different as it may look from the earlier sate- ‘ment, is nevertheless equivalent to the earlier statement A third thing we could do is formally prove properties about the equation, For example, we could prove that if Sully goes t lunch (s=2), then I don’t go to Tunch (P=0) ino matter who else goes, using the equation: e (m OR j) AND No(i) = (m OR 3) AND 0 [No maiter what the values of m and 3, F will equal o. Noting all she mathematical aetivities we can do using Boolean equations, you ean Sturt to see what Boole was trying to accomplish in formalizing, human reasoning Converting a problem statement to a Boolean equation ‘Cenver the following problem statements 1 Boolean equations using AND, OR, aad NOT opera- tos. F should equal 1 only if 1 ais and is. Answer: @ =a ANDb 2. cither of aor bis 1.Answers P = 2 OR —e— Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not availableimage not availableimage not availableimage not available@ | Srsawcimamanrcn nan 52 > 2 Combinational Lovie Design Example 2.8 Seat bolt warning light with intial jlumination L's farther extend the previous example, Awomo- Dik typically Tight up all their warning Tights wes uon the key. so thal you ean check that al the ‘receives an input t that is 1 for the first 5 seconds after = {ey fy inserted into the ignition, and © afervacd {Gen't soy aboat whoo what wis tin hat way) Bo the sysem shoul! set wei wh pel and 9-9 and seen, OR when C1, Note hat when 3, the ecu Should illuminate the Tight. regariless of the values of Figace 225 Extended seat 1p. and i. The new eicuit equation i Wek Warar iret ‘BakWarn a ae w= (p AND NOT(s) AND E) oR t The cireuit is shown in Figure 2.25. as shown in Figure 2.2¢ 7 UL ERE AES @ | + Logic gates have one or more inputs and one a is | wire—what would be the value of that one wire ©) If the incoming two wires had different values? Figure 2.25 Circuit crawing rues » 2.5 BOOLEAN ALGEBRA Logic gates are useful for implementing circuits, but equations are better for manipulating citewits. The algehrsic tools of Roolean algebra enable ws to manipulate Boolean equa tions so we can do things like simplify the equations, check whether two equations are equivalent, find the inverse of an equation, prove properties about te equations, ete Since a Boolean equation consisting of AND, OR, and NOT operations ean be straight- Forwarlly transformed into a circuit of AND, OR, and NOT gates, manipulating Boolean equations can be considered as manipulating digital circuits. We'll informally introduce some of the most useful algebraic tools of Boolean algebra, Appendix A provides a formal definition of Boolean algebra. 4 e- 8 - @ Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not available@| Srsawrcnmanmancsne nan es . 56 > 2 Combinational Lovie Design © Hominy ‘The following examples apply these basic properties to some dig O+anatdna Ltascatina ‘This one should be intuitive. ORing a with o (a+0) just means that the result will be whatever a is. Afterall, 2+¢ is 2, while 0+0 is 0. Likewise, ANDing with 2 (a*1) results in a. 2*2 is 1, while 0*1 is 0, Complement ‘This also makes intwitive sense, Regardless of the value of a, a' isthe oppesite, So you get 4.0 and a 1, or you get a 1 and a 0. One of (a, a!) will always bea 1, ‘so ORing them (2+a") must yield a 2. Likewise, one of (a, 2) will always be a 0, 59 ANDing them (a4a") must yield a 0 design examples to see how the properties ean help. © Example 2.11 Applying the basic properties of Boolean algebra Uwe the properties of Boolean algebra forthe following preblems Show that abe! is equivalent cba. The commutative property allows swapping the operanis elng ANDed, so atbtc! = atc!*b = citath = c!#bta = clba Show tharabe 4 abe! = ab. The fist disirbutie property allows factoring out the ab erm: abe ¥ abe! ab(cec"| Then, the complement propery allows replacing the c+c" byt: ab(ete!) = ab(2). Fimily, the identity property allows removal ofthe 1 from the ANDtermiab(1) = abt2 = ab Show that the eatin ¢ + 2" 2 ie equivalent vox + 2: ‘The second distributive propery (he tricky one) allows replacing xix! 2 by Geen") + Gace). The complement property allows replacing (2crc") by 1. and the ide tity property allows replasing 1* (x+2) by x42. Show that (242) be isjust be. TThe complement propery states that (ava | is 1 then results in be lelding 1c. The identity property Muhiply out (¥ 4 x) (y + 2) imo sum-of produts form. Trst writing (we + 3) a8 A will make clear that the distributive property ean be applied: A(yez). The first distibutive property yields Ay + a2. Expanding A back yields (we) y + (wix)2. Applying the fist distibutive property again yields wy + xy + Wz + 32, which isin sum-oF proguets form, 2 Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not availableimage not availableimage not availableimage not available@ | Prsawrcnnaimancsinnan 64 > 2 Combinational Lovie Design ‘output for every possible input, Thus, notice that truth tables were used in Figure 28 10 describe in an iatuitive manner the behavior of hasic logic gates A drawback of truth tables is that for a large number of inputs, the number of truth table rows can he very large. Given a finetion with inputs, the number of input combi- nations is 2", A function with 10 inputs would have 2° = 1024 possible input ccombinations—you can’t easily see much of anything in a table having 1024 rows. A function with 16 inputs would have 65.536 rows in its truth table Example 2.18 Capturing 4 function as ¢ truth table TABLE22 ‘uth table for Create trth table describing function tht detects whether & S.or-greatortu tee-bit inputs’ value, represerting a binary rumber, is 5 or ‘greater, Table 2.2 shows a tath table forthe function, We Fist a Be | Fist all possible combinations af the thes input bes, which © © | © weVelabeled a, and c. We then eater a2 in the cutpul row DB Efe ithe inputs represent 5, 8, oF 7 in binary, meaning the lst Da ef etree rows, We enter s inal the other rows, o 1 aie 10 of aa ofa | ta a9fa | Given the abore representations, converting. from ‘ ‘one representation to another is sometimes necessary ci™ or uselul, For the tree representstions discussed so Evelons M7 Couts 2 far (equations. circuits, and truth tables). there are ( ~s oe ) six possible conversions from one representation to, : another, as shown in Figere 2.36, whica will now be ° described " ‘= "tran tates! <7 Figure 2.36 Possible conversions 1. Equattons to Cireuits ffom.ove Boolean function Converting an equation 1 a eireuit ean be done presentation so ancther. stmaightforvardly by using an AND gate for every AND operator, an OR gate for every OR operator, and a NOT gute for every NOT oper- ‘ator. Several examples of sch eorversions appear in Section 2.4 2. Cireults to Equations Converting a circuit into an equation can be done by starting ftom the cireuit’s inputs, and then writing the output of each gate as an expression involving the gate’s inputs. The expression of the last gave before the ouiput represents the expression for the eizcult’s funetion —@- —o| @ Obras protegidas por Direitos de|Autorimage not availableimage not availableimage not available"Tso Pe 6 Tus, Dba 2008 1118 PR 68 > 2 Combinational Lovie Design Outputs Figure 2.42 Truth table for the cireut's equation, From the Role aqusion, we can naw constr the th Siace our cieuit has te input-—a, band c—there awe 2°=8 possibls combinations of inputs (is, ane=000, 002, 010, 011, 100, 191, 110, 112),$o the uth table hs the ight rows shown in Figure 22. For each inpul, we compute the value of # and fil in the core sponding enry inthe truth table. For example, when a=0, b=0, and c=0, ? is |00)'*0" = (o) "+1 = +1 = 2. Wo comput the crei’s op forthe renining combinations of iypus using a tut table with termediate wales, shown in Figue 242. se for he combinational crew Standard Representation and Canonical Form Standard Representation—truth Tables As stated exiles, although there ave many equation epresentations and elreult represe tations of a Boolean function, there is only one possible truth table representation of a Boolean function. Truth tables therefore represent a standard representation of a func~ tion—for any function, there may be many possible equations, and many possible ccteuits, but there is only one truth table. The truth table representation is unique. One use of a standard representation of a Boolean function is for comparing wo Tunctions 9 see if they are equivalent. Suppose you wanled w cheek whether Iwo Boolean equations represented the same function. One way would be to try io manipulate ‘one equation to be the same as the other equation, like we did in the avtomatie sliding door example of Example 2.13, But suppose we were not successful in getting them w be the same—is that because they really are net the same, or because we just didn’t manipu- late the equation enough’ How do we really know the two equations do not represent the same function? A conclusive way to check whether two items represent the same function is to create fa uth table foreach, and then check whether the truth tables are identical. $o to determine whether F = ab + a! is equivalent 10 F a'b! + ath + ab, we could generate fruth tables for each, using the method described earlier of evaluating the Function For each ouput row as Figure 2.43 F T 1 ° 1 Figure 2.43°Truth tables showing equivalence. —4|@ Obras protegidas por Direitos de|Autorimage not availableimage not availableimage not available“HT som Page 72 Toe 5 Desa 8 2009 LIK PN 72 > 2 Combinational Lovie Design Example 223. Binary number to seven-sogmvent display converter er is expt starting fom more ncural ‘eguatios Many electron appliances display a number for us to read. Example applianees include a elock, a mmierowave oven, and a telephone answering machine. A papular and simple device for displaying a Single cigit umber is a seven-segment display, illustrated in Figure 246. ive ( I i ( a SN Gem? 9 Vm. 6 bese initio 0119000 tr0Ht01 ) ®) (1 Figuro 2.48 Seven segmont display: (a) connections of npus to segment, (b) input values for ‘numbers 0,1, and2, ard (c)a pair of ral seven-segment display componeats Tre display consists of seven light segments, each of which can be illuminated independently ‘ofthe others, A desited digit can be displayed by seting the signals a, b,c, d.e, £, and g appro- Prately, So display the digit all even signals mast be set 1. To display the digit 3, and © are each Seto 1. A few letters can be displayed 100, lke slower case “b” Commonly. 4 misoprocessor oxtpats abit binary number intended to be shown fon a sevensiegment display as decimal ‘have ten) digit Outpung four ether 1 seven signals conserves scarce pins en the imieroprocesior, Thus, a aseful combina sional circuit coments four bits x,y, and 2 of a binary number othe seven-segment ‘Bopha’ signals ag, oe in Fire 2.47 ‘The desired circuit behavior is easily captured as tabi, shown in Tele 24, In cease the mieroprocesser outputs a number greater than 9, no segments are activated. We can ereae a custom logic circuit to implement the converte, Nove thet Table 24 is in the fom: of a teh table having mutiple outpats (a through g). We ean treat each ouput sparsely designing a circuit for a, then for b, ete. Summing the terms corresponding to the 15 in the coluinn (as was done in Figare 240) ead o the following equation foro: 3 |Convener Figure 2.47 Binary to seven segment converter as wixtylg! e wixty2! 4 whxtyz + wixytz + wlayz! + owheyz to wetyte! 4 wxly!s Litewise, summing the ters forthe 3s inthe b column leads tothe following equation for b bos wielyla! s wlxty!z + wix'yz! 4 wix'yz + wixy!2! fwieyz weryte 4 weyts Equations could similarly be ereated for the remssnng oupputs ¢ ough g. Finally, a eet could be created for a having 8 4-ingut AND gates and an 8-input OR gate, another circuit for b having 8 4-inpat AND gates and an $-ingut OR gate, and so on for ¢ through g. We could, of course, have minimized the logic foreach equation before ereating exch ef the circuits. ‘You may’ notice that the equations fora and b have several terms in eomamon, For example, the tem wx" "2" appears in both equations, So it woukd make sense for both outputs to share one Obras protegidas por Direitos de!Autor eeimage not availableimage not availableimage not available@)| Srsawrcnamancsne nan ? 76 » 2 Combinational Lovie Design Step 24: ‘Create equations. We ereale equations (as was done in Figure 2.40) for each output as follows = atbe 4 able + abe! + abe 2 = able + a'be! + abie! + abe ‘We can simply the fist egeation algebraically: y = albe + able + able! +c) = a'be + able + ab Step 2 Implement as a gate-based elreait, We thon crsate the Final cxeuits For the eo ouput, ts ahown in Figure 2.9. =I) ¢ Figure 2.49 Number-of-1 counter gate-based circuit a ‘Simplifying Circuit Notations ‘Some new simplifying notations were used i the circuits in the previous example. One simplifying notation is to list the inputs multiple times, as in Figure 2.50(a), Such listing reduces lines ina drawing erossing one another. An input listed multiple times isassumed to have heen branched from the same input. Seo) Soe ea > a > >i} @° ® Figure 250 Simpl fying circuit notations: (a listing inputs multile times to reduce drawing of crossing wire, (b) using inversion bubbles or complemented input to reduce NOT gates drawn, Another simplifying notation is the use of an imersion bubble at the input of @ gate, rather than the use of an inverter, as in Figure 2.50(b). An inversion bubble is a small circle drawn at the input of a gate as shown, indicating that the sigral is inverted. An external input that has iaversion bubbles at many gates is assumed to feed through a single inverter that is thea branched out to those gates. Aa alternative simplification is to simply list the input as complemented, like b* shown in the figure, 4 o 8 —o|@ Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not availableTAT som Page 8 Tossa, Dicer 209 1118 PN 80 > 2 Combinational Lovie Design > 2.8 MORE GATES NAND & NOR NAND NOR Designors use several other types of gates heyond just AND, OR, and NOT. Those gates include NAND, NOR, XOR, and XNOR. ANAND gate (short for “not AND) his the opposite output of an AND gate, oulputting © only when all inputs are 2, and outputting a 1 otherwise (meaning at least one input is 0). ANAND gate has the same behavior as an AND gate followed by a NOT gate, Figure 2.54(ay illustrates @ NAND gate. ANOR gate (“not OR”) has the opposite output as an OR sete, outputting a 0 if at least one input is 2, and owputting 2 if all inputs are 0. A NOR gate has the same Ibchavior as an OR gate followed by a NOT gate. Figure 2.54(b) shows a NOR gate Whereas Boolean algebra has the symbols “*” and “+” for the AND and OR opera tions, no such commonly-used operator symbols exist for NAND and NOR. Instead, the NAND operation on variables a and b would be writen at (a*b) * of just (ab) * and the NOR operation would be written as (a +b) * NaNO NoR XNOR ‘p> p> Figure 2.54 Additional gates (a) ‘AND, (b) NOR, (e) XOR, (2) XNow ra Section 2.4 wamed that the shown CMOS transistor implementations of AND and. OR gates were not realistic. The reason is because PMOS tnsistors don’t conduet os very well, but they conduct 15 just fine. Likewise, nMOS transistors don't conduct 18 Well, but tey conduct os just fine, The reasons for these asymmeties are beyond this book’s scope, The implications are that the AND and OR gates in Figure 2.8 are not fea sible, they rely on pMOS transistors to conduct os (but pMOS conducts cs poorly) and AMOS transistors to conduct 1s (but nMOS conducts 2s poorly). However, if we site the locations of power and ground in the AND and OR circuits of Figure 28, the results are the NAND and NOR gate ciresits shown in Figure 2.54(a) and Figure 2.54(b), . 8 @ ras protegidas por Direitos de! Autorimage not availableimage not availableimage not available@) | Psawicnnamancne nan 84 > 2 Combinational Lovie Design Nevariable function will hove 2" rows in ite truth table Then, note that each row can output one of two possible values. Thus, the umber of possible functions will be 2°22 4—2" times. Therefore, the total number of functions is ables, and 2! = 65536 possible functions of 4 variables » 28 DECODERS AND MUXES Decoders Two additional components, a decoder and a multiplexer, are also commonly used as digital circuit building blacks, though they themselves can be buill from logic gates A decoder is a higher-level building block commonly used in digital circuits. A decoder {decodes an input s-bit binary oumnber by setting exactly one of the decoder’s 2° outputs io 1 For example, a 2-input decodes illustrated in Figure 262(a), would have 2° = 4 outputs, a3, 42, di, d0. Ifthe two inpats $10 are 00, do would be 1 and the remaining outputs would be 0. 1230-02, dh would be 2. If 1210-10, a2 would be 1. If i21¢=12, d3 would be 41. One and only one outpet of a desodler will ever be 1 at agiven tine, corresponding to the paticular carrent value ofthe inputs, as shown in Figure 2.62(a. The iniemnal design of a decoder is staightforward, Consider a 2x4 decoder, Each output do, 42, 42, and 43 isa distinet function. do should be 1 only when i1=0 and io=0, so do = i2'i0', Likewise, d=i1'io, d2=i1io', and d3-izio. Thus, we build the decoder with one AND gate for each output, connecting the trve oF compl ‘mented values of 41. and 10 to each gate, as shown in Figure 2.62, pa ah a0 who oho rat o-fo afc rio a1 oi abo + t oft apo oi dato 14H eat 1H dao Hore whe 43-0 aso srt a3 @ = io 0) Figure 262 24 decoder (a) outputs for possible input combinations, (b) internal design b @- 8 @ Obras protegidas por Direitos de! Autorimage not availableimage not availableimage not availableimage not availableimage not availableimage not available"Tso Pa 9 Tus, Dba 2008 1118 PR 94 2 Combinational Lovie Design Tikely to he comect, However, sometimes designers start with an equation rather than & truth table, as in Example 2.24. A designer can reverse engineer the circuit to an equation, but that equation may be different than the original equation, especially if the designer algebraically manipulated the original equation when designing the citcuit, Furthermore checking that two equations are equivalent may require converting 0 canonical form (sum-of-minterms), which may result in buge equations if the function has @ large ‘number of inputs In fact, even if a designer didn’t make any mistakes in converting a mental under Standing of the desired funetion into a truth table or equation, how does the designer koow that the original understanding was correct? A commonly used method for checking that a circuit works as expected is called. simulation, Simulation ofa circuit is the process of providing sample Inputs to the circuit and running a computer program that computes the circuit's output for the given inputs. A designer ean then check that the output matches what is expected. The computer program tha performs simulation is called a slmudawor To use simulation to check s cireuit, a designer must describe the circuit using a ‘method that enables computer programs to read the circuit. One method of describing circuit is to draw the circuit using a schematic capture tool. A schematic capture toot orgie Figure 2.75 Display stapshot cf commercial schematic rea eapture tool ite allows a user to place logic gates on a computer screen and to draw wires connecting those gates, The 1901 allows users to save their circu drawings as computer files, Al the circuit drawings in this chapter have represented examples of schematies—for example, the cireuit drawing in Figure 2.621b), whieh showed a 2x4 decoder, was an example of a schematic, Figive 2.75 shows a schematic for the same design, drawn using # popular ‘commercial schematic capture tool, Schematic capture is used not only to capture circuits for simulator tools, but also for tools that map our circuits to physical implementations Which will be discussed in Chapter 7. Once « designer has created a circuit using schematic capture, the designer must provide the simulator with a set of inputs that will be used to cbeck for proper oulput One way of providing the inputs is by drawing waveforms for the circuit's inputs. An input's waveform is a line that goes from left to right, representing the value of the input astime proceeds to the right. The line is drawn high to represent 1 and low 10 represent 0 protegidas por Direitos de|Autorimage not availableimage not availableimage not availablecomo Pays 99 Tusky, Domb 8,209 1118 2.14 Exercises < 99 2.04 Forthe function F = ald! + ales bied! 4 (a) List all the varices, (by List all the Heras () List ll the product terms. Let variables 7 represent being tall, Feing heavy, and F being fast. Le’s consider anyone who is act tall us short, sot heavy as Tight, and not fast os sow. Weite a Boolean equation to represent each ofthe Following (a) You may nde a particular amusement park ride only if you are ether tll and light, or short and heavy. (b) You may NOT ride an amusement park ride if you are ether tall and light, or short and Heavy: Use algebra to simplify the equation 0 sum of produets (6) You ar elzible to phy on a psrticulae hesketball team if you are tall and fas, or wall and slow. Simpify this equation (2) You are NOT eligible to play on particular football team if you are short and slow, orf ou ae Hight. Simplify to sum-of-products Form, (©) You are eligible 16 play on both the basketball and foctbal tas above, based on the ine the two equations into one equation by ANDing thee. 2.26 Let variables § represent a package being smull, F being heavy, and & being expensive. Le’s ‘consider a package that & sot mall ts big, aot heavy os light, and not expensive a¢inenpen sive. Write a Boolesn eqaation to represent each of the following (2) Your company specializes in delivering packages that ate both sal and inexpensive (a Fackage mast be small AND inexpensive for us to Geliver if; you'll also deliver packages that are big but only if they are expensive (8) A paniculse truck can be loaded with packages only ifthe packages are small ad light, ‘small and leas, oF big and light, Simply the equation, (6) Your above-mertioned company bus the above-mentioned tuck, Weite an equation that describes the packages your company can deliver. int: Appropriaely combine the equa tions from the above two parts, Use algetraie manipulation w convert ihe following equation 1 samo produets fox = a(b +c) (4!) + ach(b +4) shove ete, Hint: eon 2.28 Use algebraic manipulation to comert the following equation to sam-of products form: Feane+ a) + abi +c) +ade me 2.29 Use DeMorga's Law to find the inverse ofthe following equation: ° = abe + ab, (abe + a'b)! 2.80 Use DeMorgan’s Law to find the inverse of the following equation: Fo = ac! + abd! + acd, Redwe to sum-of-produets form Redece te sum-of-produets form, Hint: Start with 2" SECTION 2.6 REPRESENTATIONS OF BOOLEAN FUNCTIONS, 2.31 Convert the following Boolean equations toa digit cireuit: @) Tla.b.c) = athe + ab @) F(a)b,e) = atb © rable) = abe + abs arnse @ ra,b.e) + b @- —o|@ Obras protegidas por Direitos de|AutorA C) 100 > 2 Combinational Logic Design Figure 2.78 Combinational crest for F TABLE 29 Truth table =e > oo afi o 10 oad 10 0 ao asa 110 aaati TABLE 2:10 Truth table, TABLE2.11 Truth table, =e ooo ‘Eso Pe 1) Tue, Beers 200 1 Pt i igure 2.78 Combinaticnal circuit for 6. 2.32 Cweatea Boolean equation representation of the digital ciouitin Figure 2.78. 2.38 Creale a Hoolean equation zepresentation forthe digi eireut in ™, 2.M Convert each of the Boolean equations in Exercise 231 toa trath table. 2.35 Comert each of te folowing Boolean equations to a truth table (a) F(a,b,e) = at + Be! (b) F(a,b,e) = (ab)! + act + be (©) Faybic) = ab + ac + abic! + ct @ Fabled) = athe sat 2.36 Fallin Table 2.8 columns forthe equation: F = ab + bY 2.7 Convert the function F shown in ‘TABLE 28 Teuth table. ap tpt fon me ett oem Sp | 2.38 Use algebraic maniputation to —+— ‘minimize the equation obtained in Exercise 2.37. 2.59 Convert the funetion F shown in the uth able in Table 2.10 tan equation. Don't minimize the equation, {Uw algebraic manipulation 1 minimize the equation obtained in Exercise 2.38 (Conver the function F shown in the tuth lable in Table 2.11 to an equation, Don't minimize the equation, Use algebraic misipltion to minimize the equation obtained in Exercise 2.41 ‘Create tui table forthe cireuitof Figute 2.78, ‘Create tut table forthe cireuit of Figure 2.7 Conver the function P shown in the truth table in Table 29 to digital iru, 2.46 Convert the function # shown inthe tuth tble in Table 2.10 ta digital seul. 2.47 Convert the function & shown inthe tut tble in Table 2.11 w a digital sieui. 2.48. Convert the following Boolean equations to canonical sum-of-minterms form: (a) Fla,b,c) = atbe + ab (b)Fla,bye) = a'b ()Flaibie) ~ abe bab bas be (a)Flasbe) =e Obras protegidas por Direitos de|Autor114 Exercises 101 2.49 Determine whether the Roolevn functions ® = (a + b)'#a and = a 4 BY ane ‘equivalent, using (a) algebraic manipulation and (6) truth tales 2.50 Determine whether the Boolean furctions @ = ab’ aniG = (a' + ab) are equivalent, using (a) algebraic manipulation and (b) truth tables. 2.51 Determine whether the Boolean function G aibic + abic + abe! + abe isequi alent to the function represented by the eircait in Figure 2.80. 2.52 Determine whsther the ‘wo circuits in Figere 2.81 are equivalent cireuits, using (a) algebraic ‘maniputation aad (b) tru Ladies. Figure 289 Combinational circuit for I. sa a yD 4 a4 ‘FigureZ¥ Combinational cireuis Tor F and G. | 5 2.93 © Figure 2.82 shows two circuits whose inputs are unlabeled, ah 2 (@) Determine wheter the to circuits are equivalent. Hint Try all possible labelings of the eo inputs for both circuits, (b) How many cireit comparisons would nosd tobe performed to determine whether two ci ‘its wth 10 unlabeled inputs sre equivalent? L Figure 282 Combinaional eireuits for Fand G. JON 2.7: COMBINATIONAL LOGIC DESIGN PROCESS 2.54 A museum has thre rooms, exch with a motion sensor (m0, m2, and m2) that outputs wher ‘motion is detested. At night, the only person in the museum is one security guard whe walks from room to room. Create 2 cireait that sounds an alurm (by setting an output A 2) if motion isever detected in more than one room at 2 ime (Le, in two oF three rooms), meaning there must he one or more intaiders in the maseurm. Start wilh a truth tle Create circuit for the museem of Exercise 2.54 that deteess whether the guard is properly patising the muscum, detected by exactly one miction sensor being 1. (If ne motion sensor is 1, the guard may be sitting, sleeping, or absea.) — @ 9 | r Obras protegidas por Direitos de! Autor102 > 2 Combinational Logic Design 2.56 Consider the muscu security slarm function of Exercise 2.56, but for'a mascurn with 10 rooms. A trth table is nots good staring point too many rows), nor is an equation deserbing ven the alarm should sound (tow many terms). However the inverse of the slam Function ean he straightforwardly captured 2s an equation. Desig the circuit fr the 10-room seeurity system by designing the invese of the function, and then jst ading an imerter before th eireui’s output. A network router connects multiple computers together ard allows them to send messages to ech oer. If to oF more computers send messages simsltancously, the mestages “collide” ard! must be resent, Using the combinational design process of Table 25, create a collision detection cixeut for a router that connects 4 computers. The circuit has 4 inguts beled 0 through M3 that are 1 when the corresponding computer is sending a message and 0 ether- wise. The circuit has one output labeled that is 1 when a collision is detected and 0 colterwise 2.58 Using the combinational design process of Table 25, create a 4-bit prime number detector ‘The circuit has four inputs—W3, N22, and No—that correspond to a 4-bit number (13 is ths most significant hit) an one exspat P that is 2 whon the inp isa prime mamher an that is 0 otherwise. ‘car asa fat-vel detector that outputs he cern fueblevelat a thin mumbo. With (000 meaning ery sod 131 meaning fl Cente acre tha amines ow fel” ind- ator lit (Gy seing tn onpa tt 2) when he fu level drops Blow evel 3. 2.60 A ca is owe pesire S80 a OPUS Me CUE He SSE 38 8S. nary numb. Crate a crt dat ilies “ow te presure indsaor it (by sting an Chip Ft 1) when he ie prewre dope below 16. Hint you igh find it air were | ‘it a tet the ven fueton Yu can en jee! spealan iret te up of ha | ag cicut & SECTION 2.8: MORE GATES 2.61 Show the conduction paths and outpat value of the NAND gate trnsisor circuit in Figure 254 when: a) xe — sandy = Othe = sandy = 3 2.42 Show the conduction paths and output valve of the NOR g When: a)x = andy = 0,(b)x = candy = 0 263, Show the conduction paths and eutpul value oF the AND gate tesitor rch when: (a) x = andy = 1,(b)x = oandy = 1. 2.64 Two people, denoted using variables A. and B, want to side with you en your motoreycle Write + Boolean equation that adieats that exactly one of thew pecple can come means A can come: A=0 means & ean't come). Then use XOR to simplify your equation 285 Simplify the following equation by using XOK wherever possible: F = a'e + ab! + cd! + cld + ac, fe transistor circuit in Figure 2.54 in Figure 2.85 2.66, Use 2-input XOR gates to eeatea b,c. dis ob 2.67 Use 2-input XOR or XNOR gates to create a circuit that detects whether an even number of the inputs a b,c, d ae 4s, iret that outputs a 1. when the number of 1 on inputs, SECTION 29: DECODERS AND MUXES 2.068 Design 3x8 deender using AND, OR, and NOT gates. 2.60 Dasigna 4x16 decoder using AND, OR, and NOT estos. 2.10 Dasigna 3x8 decoder with enable using AND. OR, and NOT gates 1 Design an 81 multiplexer using AND, OR, and NOT gates. Obras protegidas por Direitos de|Autor114 Exercises 103 2.72 Design a 16x multiplexer using AND. OR, snd NOT gates 2:73 Design a Dit 4x1 multiplexer using four 4x1 muliplevers, 2.74 A house has fur external doors, each with a sensor that outputs + if its door is open, Inside the houte isa single LED that a hamecwmer wishes to axe ta indicite whether a doce is open or closed. Because the LED can only show the stitus of one sensor, lhe homeowner buys a that has a 2-bi ouput representing the switch pos tion in binary. Crea a circuit to connect the four sensors, the switeh, and the LED. Use at least one mux (a single mux or an N-bit mux) or decoder. Use block symbols, each with a clearly defined function, such as “2x1 mux.” *8-bi 2x1 mux" or “3x8 decoder”: do nat show the internal design of a mux or decoder. 2.13 A vieo system can accept video ftom one pf 180 Video sources, bu! ean only display one source ata given tine. Each source outputs a stream of digitaed video on its own 8-bitoutpa ‘A switch with a single-bit output chooses which ofthe wo 8-bit streams will be passed on a slisplay"s single 8:bi inpat. Create a citeuit to eomect the 1Wo video sourees, the switch, and the display. Use at east one mux (@ single max oran -bit mux) or decoder, Use block sya hols, cach with a clearly defined fi it AML mun” oF “38 ‘witch that ean be set 100, 1,2, 0F 3a fon, such as “2x1 mux, decoder": do not show the internal design of a mus or decodes, 2.76 A store owner wishes to be able to indicate io customers that the items in one of the store's sight aisles are temporarily discounted ("an sale"), The store owner thes masts alight shows teach aisle, and each light has ssingle-hit input shat turns on the light when 2. The store owner thas swich tha ean be st 10, 1,2, 3,4, 3,6, 07, ad that has 2 3-bit output representing the switeh postion in binary. A second switch can be set ap or down and hat ‘output that is 1 when the switch is up: the store owner ean sei this switch down if currently discounted. Use at ast one mux (a single max or an N-hit mux) oF decoder: Use block symbols, eack with a clearly defined funetion, such as “2x! mun,” "Sit 2x1 mux." or “3x decoder” do not show the internal design of a mux or decoder SECTION 2.10; ADDITIONAL CONSIDERATIONS 2.77 Determine the erties! path ofthe following specified circuits. Assume that each AND and OR sate has 2 delay of | ns, each NOT gate has a delay of 0.75 ns and each wire has a delay of 051s. (a) The circuit of Figure 2.37. (b) The ecuitof Figure 2.41 2.78 Design a 1x4 demultiplexer using AND. OR, and NOT gates 2.79 Design an 8x3 encoder using AND, OR, and NOT gates. Assume that only one input will be 1 atany given time, 2.80 Design a 4x2 priosty eneoder using AND, OR, and NOT gates. If every input is 0. the encoder output should be 0°. + b @- —o|@ Obras protegidas por Direitos de|Autor1 Sriram ie + 104 > 2 Combinational Logie Design Samson enjoyed physics and math in college, and focused his advanced studios on integrated circuit (IC) design, believing the industy t0 have a great future Years later, he realizes his belief was true “Looking back 20 years in high tech, we have experienced four major revolutions: the PC revolution, digital revolution, communication revolution, ard Internet revolution—all four enabled by the IC Indust. The impact of these revolutions t out daily lite is profound” He has found his job to be “very challenging, imeresing, and exciting. T continually learn now skills to keep up, and to do my job more efficiently. (One of Samson's ley design projects was for dial television, namely, high-definition TV (HDTV), involving ‘companies The Zenith, Philips, and Intel. In paticular, he led tho 12-porson design team that built Ins first Liquid cesta on Silicon (LCoS) chip for rear-projection HDTV. “Traditional LCoS chips are analog. They apply different analog voltages on each pisel ofthe display chip so it can produce an image. But analog LCoS is very sensitive to noise and tempersture variation, We used digital signals to do pulse width modulation on each pixel” Samson is (aite proud of his team's secomplistment: “Our HDTV. Picture quality yas mech better” ‘Samson also worked on the 200-member design team fer Ines Pontium IL processor That was very different ‘experience. “For the smaller team project, each person had more responsibility, and overall efficiency was high, For the large team projec, each person worked on a specific par of the project—the chip was divided into clusters, each cluster into units, ard each unit had a leader. We relied heavily on design flows and ‘methodologies.” Samson has seen the industry's peaks and valleys daring the past two decades: “Like any iadustry, the IC jd market has its. ups and downs.” He believes the Industry survives the low points in large part due t imovation. “Brand rames sell products, but without innovation, markets go elsewhere, So we bave io be very imovative, creating new products so that we ae alvays ahead in the global competition” ‘But “innovation doesn't grow on tees.” Samson points foul. “There are two kinds of innovations. The first is invention, vhich requires a good undersanding of the plysies behind technology. For example, to maky an analog TV into « digital TV, we must know how haan {eyes perceive video iniages, which parts can be dighized, how digital images can be froduced ca a silicon chip ete ‘The second kind of innovation reuses existing technclogy for s now application, For example, we can couse advanced space technologies in a new non-space product serving a bigget market. e-Bay is another example—it teased Intemet technology for online auctions, Tmovations lead to new products, and thus new jobs for many years ‘Thus, Samson points out that “The industry is counting fon new engineers from college 10 be innovative, so they ‘ean continue fo drive the high-tech industry forward, ‘When you graduate from college, it's up to you to make things beter” Obras protegidas por Diraitos del + @ [Autor‘seq Pa 108 Thurso, Ds 14,2909 1 3 Sequential Logic Design: Controllers ® 3.1 INTRODUCTION The ouput of x cmmblnaton ceo sa function of he cet’ present ipa A com- basta iui ka 0 memory fs of «cee strug ew arsed eng those is overtime for later ae Comblnatonal deus alone ae o linited astute Designers typelly ue combina! cheul as pat of lager eat elles sequen | streulemeltta tat bave memory. A seguendal cess a creat whose capt depend ot only on he ekcults pate Ipus, but abo on te cells presen st which is all the bits currently stored in the cireuit, The circuit's state in wen depends on the past sequence of the circuit's inpat values, ‘An everyilay sequential system example is a lamp that toggles (changes from off 10 fon, or from on to off) when its button is pressed, as was shown in Figure 2.1(e). After plugging in the lamp, push the lamp's button (the input) a first time, and the lamp tars ‘on, Push the dation & second dime, ahd the lamp qwrhs off, Push the buwon a thied dine, and the lamp turns on again. The system’s output (whether the lamp is on or off) depends fon the input and on whether the system is currently in the state of the lamp being on or Off. That state in turn depends on the past sequence of input values sinee the xystem was initially powered on, In contrast, an everyday combinational system example is a basic doortell, as was shown in Figure 2. 1a). Push the button (the input) now, andthe bell (the output) rings, Push the button again, and the bell rings again, Push the button tontorrow and the bell rings the same each time, A basic doorbell has no state—its ontput value (ovhether the bell rings or not) depends solely on its present input value (whether the button is pressed or not). “Mos! digital systems with which you are likely familiar involve sequential circuits. A calculator contains a sequential circuit to store the numbers you enter, in order to eperate oon those numbers. A digital camera stores pictures. A traffic light eontroller sores infor- ‘mation indicating which light is presently green. A kitehen timer that counts down from a set time to 7e10 stores the present count value, to know what the next value should be. This chapter describes sequential circuit building blocks called flips-flops ané regis ters, whieh can store bits. Htther introduces a sequential cireult design process in whe a designer first captures desired behavior, and then converts that behavior to a type of sequential cireuit known asa controller, comprised of a register and combinational logic. 10s ee —o|@ ras protegidas por Direitos del AutorQD | Oat rp 16-009 HA 7 106 > 9 Seq Lg esgr: Convales ® 3.2 STORING ONE BIT—FLIP-FLOPS Sequential civcit design ie aided by a Duilding block that enables storing of a bit, call Bie light much like combinational circuit design was | “0” & ® aided by the AND, OR, and NOT gate Cancel one building blocks. Storing a bit means that we | uMlen a can save ether a 0 or a 2 in the block and Fai37 Fight anda call ton : : at waa system. Pessirg Cl uns on he gh cxampe, consider designing the fight ate~ hich stay nate alls oeased dant cal-btton system in Figure 3.1. An Preing Canal tins ofthe fet ailing passenger can push the Call button to tum on a small blue light above the passenger’ seal indicating t a fight attendant h the passenger needs service The light says on even ale the eal tn is Felesed, The Tight can be tured off by pressing the Cancel button. Because the light must stay on even afer thecal button is released, a mechanisn is needed o “remember” thatthe ell button was pressed. Thi mechanism can be abit storage bleck, in which a2 wil be lored when the eal bution is pressed an a © sored when the caictl bution i presse. The inpus of this bt storige block wil be connected to the ell and eancel buttons, and the oufpat to the Dl light, asin Figure 3.1. The light iltuinates when the Block's outpat . This section introduces the inlernal design of such abit storage lock by inraducing several increasingly complex circuits able to store a bit—a basic SR fateh, a level-sensitive | Si latch, a leve-snstive D latch, and an edge-iggered D fp-lop. The D flip-flop will a» then be used to crete a block capable of storing muliple bis, Known asa register. which ve will serve as the main Bit storage Block nth restof the book, Each suocsssive circuit lim inates some problem of the previous one, Be aware that designers today rarely use bit storage blocks other than D flip-flops, We introduce the other blocks to provide the reader ‘with an underlying intuition of the D flip-flop’s internal design, Feedhack—The Basic Storage Method ‘The basie method used to storea bitin a digital circuit is feedback. You've surely experienced Feedback in the form of audio feedhack, when someone talking into a microphone stood in Front ofthe speaker, caus ‘umn causing everyone to cover theit ears and snicker). The talker generated a sound that was picked up by the micraphone, came out o the speakers (amplified), was picked wp again by the mieroptone, came out the speakers again (amplified even mere), cle. That's feedback Feedback in audio systems is annoying, but in digital systems is extremely useful. Intuitively, we know that g. ° somehow the output of a logic gate must feed back into. the gale self, so that the stored bit ends up looping around and around, like a dog chasing its own tail. We might try the circuit in Figure 32. Figure 3.2 First ated) Suppose intially Q is 0 and Sis 0. At some point, suppos? attempt at using ‘we set S to 1. That causes Q to become 1, and that 1 feeds back feedback to storea bit. ino the OR gate, causing @ to be 2, ete, So even when 5 returns 3g loud continuous hurting sournd to come out oF the speakers (in 90 ras protegidas por Direitos de! Autor@)| Sserseinsansainicnn aie 0 po. a o} 0 0 ft a fm 1 So. a ° 4 24 @ stays Forever 1033 Tracing the behavior of our fist attempt at bit sto (0 0,Q stays 2. Unfortunately, @ stays 1 from then on, and we have no way of resetting Qt0 ©. But hopefully you understand the hasic idea of feedback now—we did successfully store 61 using Feedback, but we couldn't store 0 again Figure 3.3 shows the timing diagram for the feedback eircuit of Figure 32. Initially, Wwe set both OR gate inputs to 0 (Figure 3.3(a)). Then we set $ to 2 (Figure 3.3(b)), whieh causes @ to become 1 slightly later (Figure 3.3(c)), assuming the OR gate has 2 small delay as discussed in Section 2.10. 9 becoming 1 causes t to become 1 slightly later (Figore 3.3(d), assuming the wire his a small delay to. g will stay at 2. Finally, when | | we change 8 back to 0 (Figure 3.3(¢)), @ will continue to say 2 because ie 1. The fist | 7 curved line with an arrow indicates that the event of & changing from 0 t0 2 causes the a 1 event of Q changing from 10 1, An event is any change on abit signal from 0 10 2 oF from 1.10 0. The second curved fine with an arrow indieates that the event of Q changing from 0 to 2 in turn eauses the event of t changing from 0 10 2. That 1 then continues to loop around, forever, with no way for $ to reset O10 0, Basic SR Latch 11 tums out thatthe simple circuit in Figure 3.4, ealed a bast SK laich, implements ihe bit storage building block that we seek. The circuit consists of a pair of cross-coupled NOR gates, Making the circuit's input equal to 1 causes Q 10 become 1, while making Kequal 1 1 causes Q {0 beCOME 6. Making both $ and R equal to 0 causes Q's eurrent valve to Keep looping around. Ia otker words, $ “sets” the lateh to 1, {Sicen sRiate] ° é Vand R “resets” the laich to O—hence the letters 5 (for set) and TA Gesey iene Paes eat FRE jakecsrom, send ne Moon Rane 2a ie ek one al ope} lin WOH pa if behave. 4 e- 8 - @ Obras protegidas por Direitos de! Autor@)| Srrsererisansainicns aie 108 > 3 Sequential Logic Desigr:Contallers Suppose we make $0 and in the SR latch cireuit of Figure 36, and that the values of @ and t are initially lurknown. Beeause the hottom gate of the citeuit has at least one input equal to 2 (8), the gate outputs 9—in the timing dia ‘gram, ® hecoming 1 causes © to become 0. In the eieuit, o's 0 feeds back t0 the top NOR gate, which will have both its inputs equal to 0, anil thus its output will be 2. In the timing diagram, @ becoming © causes © 10 become a. In the circuit, that 3 feeds back to the bottom NOR gate, Fi" 36 SR Tach when S=0 and Which has at least one input (actually, beth) equal to 2, so the bottom gate continues to output 0. Thus the output 9 equals 0, and all valves ae stable, meaning the values won't change as long es no extemal input changes. Now suppose we keep S=0 and 1 change R from 1 back to 0, as in Figure s 3.7. The bottom gate still has at least one input equal to 2 (the inpat coming from /_ ths tap gat), £0 the baiom gate cow ay tines. to output 0. The top gate | centnves to hate both inputs equal to © ; BS fan contioacs to ouput 1. The cutpor @ : a , will thus still be 0. Therefore, the earlier 2 siored 30 into the SR lath, aio : Known as mserting the latch, and that © ° remains stored even when R is changed back to 0. Note that Ret will reset the lateh regardless of the initial value of ©. Consider making $=1 and R=0, as in Figure 38, The top gate in the circutt ‘now has one input equal to 1, so the top gale outpuis a 0—the timing diagram shows the change of $ from © Wo 1, causing ¢ to change from 1 to 0. The top {gate’s 0 ouput feeds back to the bottom Bate, which now has both inputs equal 0 and thas outputs 2—the timing diagram shows the change of € from 1 to 0, causing @ to change from 0 to 1, ‘The bottom gale's 2 output (Q) feeds back to the top gate, which has at least Figure 38 SR latch when. cone input (actually, both of its inputs) equal 10 4, $0 the top gate continues to output 0. The output @ therefore equals 1, and all values are stable, Figura 3.7 SR latch when $=0 and 2-0, afer R was previously L 4 Sie —@- —o|@ Obras protegidas por Direitos de|Autor‘HE seq Paps 109 Thr, Ds 1,209 1 Next, consider making 8-0 snd again, as in Figure 3.9. The top s gate still has at least one input equal to 4. (ihe input coming from the gate], so the top gate continues to ‘output 0, The botiom gate continues to hhave both inputs equal to 0 and con ‘inues to output 2. The ouput Q is sill 2 stored 21 into the SR latch, also known as setting the 1. Thus, the earlier s: 32 Storing One Bi bottom latch, and that 1 remains stored even e when we return (© 0, Note that = will set the laich regardless of the int value of 0 ca 5 buten Bluelight careel e wutlon 7 Fi basie SR tte 0 3.10 Flight atendan all-button system using a ‘might store a 2, it might store a 0, or its output might oscillate, changi 1 to 0, and soon, In particular, f $= 1 and R= 1 (written as “SR=1 NOR gates have at least one input equal to 4, and thus both gates output 0, as in Fi Figure 3.8 SR latch when S=0 and R=0, after S ‘was previously 2. The hasie SR latch can be used to implement the {Tight attendant eall-button system as shown in Figure, 3.10, by connecting the eall bution 1» &, the cancel bution to R, and © to the light. Pressing the call button sels @ to 1, thus turning on the light. Q stays 1 even ‘when the call button is relessed, Pressing the cancel bution resets to 0, thus turning off the light. Q stays: @ even when the cancel button is released. Problem when SR=11 in a Basle SR late AA problem with the basic SR latch is that if Sand R me both 2, undefined behavior results—the tateh 1g from 1 10 010 "for short), hoth the 3.1 la). A problem occurs when $ and Rare made 0 again. Suppose $ and R return 10 0 ft the same time. Then both gates will have 98 at all their inpuis, s9 each gate’s ovtput will change from 0 to 2, as in Figure 3.11(b), Those as feed back to the ga inputs, causing the gates 19 output 9s, as in Figure 3.1 I(e), Those 0s feed back to the gate inputs again, causing the gates to outpat 1s And so on Going from 1 40 0 to 1 to 0 repeatedly aid selon. Orilaon snot a ssnble fetus of i storage lok = 4 ° t—— ° @ oes o—tJUL Figure 3.11 The situation of and 2=1 causes problems—g oscillates when SR return to 06, ® —e|@ ras protegidas por Direitos del Autor| reer ncn i sain. ws ? 110 > 5 Sequential Logi esr: Contos Ina real citeuit, the delays of the wpper andy lower gates and wires would be slightly different trom one another, So after some time af oscilla 5 tion, one of the gates will get ahead of the other, , outputting a 1 before the other does, then a0 before the other does, until it gets far enough ul lo ease the circuit to entera stable sit tion of either Which situation will happen is unknown beforehand. A situation in which the final output of a sequential circuit depends on the delays of gates and wires is a race condition, Figure 3.12 shows a race condition involving oscillation ‘but ending with a stable situation of Q=1. Therefore, S and must never be allowed wo simul ‘taneously equal 1 in.an SR latch. A designer using, Call mm Cy Ss ‘SAlatch] an SR latch should add a eireuit extemal to the SR burton Tateh that strives 10 ensure thet 8 and R never simultaneously equal 2. For example, in the flight attendant call-button system of Figure 3.10, a pas- senger pushing both buttons atthe same time might Figure 3.12 Q eventually stl to either 9 0F 1, due to race condition. External ereult al Soe ectscr ne ga mew sor nas Canoat - | blinking light. The SR latch will eventually settle butten Ce to 1 oF 0, and thus the light will end up either on or eect ne cdsmiamuaig fA WAgE aon Ceenee aces mau Ga RRMA LASER EES caditen ecu wus mlUOL As OW ous scomaerier Iront of $ and Ras shown in Figure 3.13. should be 1 if the call button (denoted as Ca11) is pressed and either the cancel hutton (Cacl) is pressed or not pressed so S = Call*cnel + Cali*Cnel' = Call. 8 should be 2 only if the cancel button is pressed and the call bution is not pressed, meaning R = Chel * Call’, The circuit in Figure 3.13 is derived diveetly from these equations. Exen with such an external circuit, $ and could still inadvertently both become 2 cue to the delay of real gates (see Section 2.10), ‘Assume the AND and NOT gates in Figure BAS have delays of 1 ns each (ignore wire delays for now). Suppose the caneel button is being pressed and hence $2=01, as in Figure 3.14, and then the call batton is also pressed 8 will change from 0 t 1 almost immedi ately, but & will remain at 1 for 2 ns longer, due to the AND and NOT gate delays, before cal rel changing to 0. SR would therefore be 12 for 2 R ns A temporary anintended signal value cused by circuit delays is called a glitch NESSIE coe devaysvan cause s=31 —@— —e| @ Obras protegidas por Direitos de|Autor@)| rmersenisanseainine aie Significantly, glitches eam also cause an uniniended latch set of reset, Assume that the wire connecting the cancel button to the AND feate in Figure 3.13 hasa delay of 4 ns (perhaps the wire is very long), in addition t the 1 ns AND and NOT gate delays. Suppose both hutlons are pressed, s9 SR=10, and then the buttons are both released—sR should become 00. $ will indeed change to 0 almost immedi ately. The top input of the AND gate will become after the Ine dy ofthe NOT gt oy The bovem put of tax AND a wil ean Dn 1 for 3 ns more, due to the 4 ns wire delay, thus. + causing ® to change 1. After that bottom inpat finally changes to 0, yet another 1 as will pass due to the AND gate delay before R returns io 0. Thus, & experienced a 4 ns glitch, whieh resets the latch to 0—yeta reset is clearly not what the designer intended. Figure 3.15 Wire delay leading to a glitch causing eset. Level -Sensitive SR Latch | {A partial solution to the glitch problem is to | extend the SR latch to have an enable input Level-sensitve SR latch Cas in Figure 3.16. Wien C=, the $ and R signals pass through the two AND gates to the $2 and RE inputs ofthe hasie SR latch, hecause $#1-5 and RYI-R. The hatch is _ |e enabled, But when C0, the two AND gates anise $1 and R1 10 be 0, regardless of the al Salues of $ and % The liteh is disabled, — | p ) if ‘The enable input can be setto 0 when S and m7 might change so that glitches won't prop- agate through to Sx anal Ra, and thea set to only when S and 2 are sable, The ques- tion then remains of when to set the enable input to 2, That question will be enswered in the upeoming sections Figuee 3.17 shows the call bution system from Figure 3.13, tis ime using an SR latch with an enable input c. The timing diagram shows that if Cac is 2 and then Cullis changed to 1, gliteh of $812 occurs, as was already shown in Figure 3.14. However, hhecause C0, G1R2 stay at 00. When wo later set the enable input to 3, the stable SR salues propagate through to S282. An SR latch with an enable is called a fevel-sensitire SR latch, because the latch is nly sensitive © its $ and R inpats when the level of the sable input is 2. It is also called a transparent SR latch, because seting the enable input to 2 makes the imermal SR lateh transparent 0 the $ and R inputs. It is also sometimes called a gated SR latch. st Figare $16 Level sensitive Sk lateh—an SR latch with enable input ©. 4 Sie —@- —o|@ Obras protegidas por Direitos de|Autor@ | Srmerseinanseainicns wre 112 > 3 Sequential Logic Desigr:Contallers call S oe s one a h ° xt L o ; | vane arg 1} erabled Nate Notice tha the top NOR gate ofa SI atch outputs | the opposite value as the boitom NOR gate iat outputs. | Thus, en output 9" ean be included on an SR latch simost 8 se for free, just by connecting the top gate to an output e + named Q'. Most latches come with both @ and 9 out: puts. The symbol for a level-sensitive SR latch with such figure 3.18 Symbol for dua: dual outputs is shown in Figure 3.18, z ‘ouput level-sesitve SR lich, Level-Sensitive D Latch—A Basic Bit Store ‘A designer using a level-sensitive SR latch input is 1. One way to relieve designers of St The tr gies ei ype ow fe natn Belong D tat, shown Figure 319 iene be |Z, 1 input of a level-sensitive SR latch, and con a_/ nects through an inverter to the & input of the SSR latch. The D latch is thus either setting Figure3.19. Dlatch intemal ecuit (when D=2) oF resetting (when D=0) its internal basic SR latch waen the enable input Cis 1. 4 Sie —@- —o|@ Obras protegidas por Direitos de|Autor‘seg Pas 113 Thurso, Ds 14,2909 1 Pt 32 Storing One Bit—Fipfops 113 A level-sensitive D latch thus stores what. ever value is present at the lateh’s D input when 0.) FS 1, and remembers that value when =< Figure 3.20 shows. timing diagram of D tach g for sample input values on D and Cz artows indie” © cate which signal changes cause other signals tot change. When D is 1 and ¢ is 2, the lateh is set to 1, because $1 is 1 and 81 is 0. When Dis 0 and Cis 2, the latch is reset to 0, because Ra is at F Land 81 is ¢, By making R the opposite of s, ® the D latch ensures that S and Rwon't both be2 — gt at the same time, as long as D is only changed 9 when Cis 0 (even if changed when C is 2, the Figure 320 D latch timing diagram, inverter’s delay could cause and R to both be 2 briefly, but for too short of time to cause a problem), 1 The symbol for a D latch with dual-outpats =p ap (@.and 0°) is shown in Figure 321 Figue 31 Dick =e gh symbol Edge-Triggered D Flip-Flop—A Robust Bit Store Fig many lates will ¥ propagate for each pulse of clea? For Cl The D latch still has a problem that can cause unpredictable circuit behavior—namely, signals can propagate from a laich output to another latch's input while the clock signal is 1. For example, consider the circuit in Figure 3.22 and the pulsing enable sigrals—a pulse is « change irom 0 to 1 and back to 0, and a pulsing enable signal is called a clock signal, When Chie 1, the va ippese at that latet’s output. If CL still equals 1, then that value will also get loaded into the second latch, The value will Keep propagating through the latches until CLE rewens © ©. Through how many latches will the value propagate for a pulse on C1k? It's hard to \y—Wwe would have to know the precise timing delay information of each latch, ueon ¥ will be loaded into the first lateh and Y¥—01 er 4o2 a2}—Jos aso a oka 1 cxeILil Figure 325 illustrates this propagation problem in more detail, Suppose DL is in sially 0 for a long time, changes to 1 long enough to be stable, and then CLI becomes 1, 1 will thus change from 0 to 1 after about three gate delays, and thas D2 will also Change from 0.10 1, us shown in the lef dining diagram. If 2k Is still 3, value for D2 will propagate through the AND gates of the second latch, causing $2 10 change from 0 to 1 and R2 from 2 t 0, thus changing Q2 from @ t0 2, as shown in the lett uming diggeam hen tha new ® —e|@ ras protegidas por Direitos del AutorTHE sean Pap 114 Try, Der 18,2900 HEA 114 > 3 Sequential Logic Desigr:Contallers ct con 6 © Figure 3.23.4 problem with level-sersitve latches: a) while C= 2, 92's new value may propugate to 02, (b such propagation can cause an enknovn number of latches along a chainto get updated, fe) tying to shorten the cloek’s | lime at + ta avoid propagation tthe next latch, but long enough to allow latch to reach a stable fedbsck sialon, | + 's hard because making the clock’s high time to short prevents proper leading ofthe latch, 4 . ‘You might suggest making the clock signal such that the clock is 1 only far a short ‘amount of time, so there's not encugh time for the new output of a latch to propagate to ‘the next latch’ inputs, But how short Is short enough? 50 ns? 10198? 1 ns? O.1 ns? Aad At ‘we make the clock’s time at 2 too shor, that time may not be long enough for the bitat a lateh’s D input to stabilize in the lutch’s feedback cireuit, and we might therefore not sue~ cessfully store the bit, as illustrated in Figure 3.23(¢), A good solution isto design 2 more robust block for storing a bit—a block that stores the bit at the D input at ‘the insane that ihe clock rises from 0 19 2. Note that we didn’t say that the block stores the bit instantly. Rather, the bit that will eventually get stored into the block is the Dil that was stable aD al the instant tat the elock rises from ¢ t 2. Such a bleck is called an edge-triggered D flip-flop. The word “edge” refers to the yertieal part of the Fine representing the clock Signal, when the signal tansiions from 0 t9 1. Figure 3.24 shows three eycles of 2 clock signal, and indicates the three rising clock edges of those eyeles ok lock edges ip-Flop Using a Master-Servant Design, One way wo design an edge-wiggeced D fip-flop is to use fwvo D latches, as shown in Figure 3.25, ‘The first D latch, known as the master, is enabled (can store new values on Dm) when Ome —> @ ras protegidas por Direitos de! Autore\® oo € The common maser-save Stes chome instead 0 ase the tie mary Deore fining the form “itave ‘emive. Others tue tetera secondars AT sea Pas 115 Tray, Dacre 1309 HH PM 3.2 Staring One it—FlipFons 115 Ditip-top os 1 Diatch | [Daten orom_f as jo Jp : pe ope ET cw tL }Cm_ cs as 2 ‘OmiDs. i i A raster ||| senant cs 1 * an Figute 3.25 \ D flip.op implementing an edge-triggered bit storage block, intemmlly using wo D laiches ina master-servant arringement, The master D latch sores is bn input while CL = 0, but the new value appearing st on, and hence at Ds, dees not get stored int the servant latch, because the servant latch is disabled when CLI =0, When CLie becontes 1, the servant D hich becomes enabled and this ges lod with whatever vie was inthe master fate atthe instant shat C2 changed from 010 when CLk is 1. Thus, while Clk is 0, the bit on D is stored into the master latch, and hence Qu and Ds are updated—but the servant latch des not store this new bit, because the servant latch is not enabled sinee CL& is not 1. When C1k becomes 2, the mastor latch becomes disabled, thus holding whatever bit was atthe D input just before the clock changed from 0 t 1. Also, when Clk is 1, the servant Tateh becomes enabled, thus Storing the bis that the master is storing, and that hit isthe bit that was at the D input just before CLk changed from 0 t 1, The two latches thus implement an edge-triggered storage block—the bit that was at the inpat wien CL changed from 0 to 1 gets stored, The edgestriggered block using two intemal y__[5y oatpe oallos oa a a latches thus prevents the Stored bit from propagating through more than one flip i Hop when the clock is 2. Consider the chain of fi gg LI] owe SL flops in Figure 3.26, whieh is similar to the chain in Figure 3.22 bat with D flips Hlops in place of D latches. We know that ¥ will propagate through exactly one flip-flop on each clock eycle. The drawhack of 3 master-servant approach is that two D latches are needed to Store lone bit, Figure 3.26 shows four flip-Tops, but there are two latches inside each flip-flop, for a total of eight latches. Many alternative methods exist other thon the i method for designing an edge-iriggered flip-flop. In fuet, there are hundreds of different designs for latebes and Hlip-llops beyond the designs shown ahove, with those designs differing in terns of their size, speed, power. ete. When using 2n edge-triggered flip-flop, a designer usually doesn't consider whether the flip-flop achieves edge-riggering using the master-servant method or using some other method. ‘The designer need only know that the flip-flop is edge-trig wiry {oro apsuy sowrey om, Figure 3.26 Using D flp-fops, we now know through Bow many flip-flops ¥ will propsgate for Cik_A/and for Ck_—one Mp: flop exactly per pulse, fr ether clock signal, ~|@ Obras protegidas por Direitos de! Autor| Srserscrnnineaseicns ware ? 116 > 3 Sequential Loge Cesgr: Contoles cemonty refer Blip steps asus “Pope. ‘eered, meaning the data value present when the clock edge is rising isthe value that gers loaded into the flip-flop and that will appear atthe fip-flop’s outpat some Hime later. The above discussion is for what is known as positive or rising eige-riggered Mi flops, which are triggered by the elack signal changing from 9 to 2, There are also lip-fops krown as negative or falling edgo-triggered flip-flops, which are triggered by the clock changing from 1 to 0. A negative edge-triggered D flip-flop can be buill using a master- servant design where the second flip-flop’s clock input is inverted, rather than the first hi Hlop's, Positive edgesriggeredfhp-lops are drawn using a small triangle at the clock input and negative edge-triggered flip-flops are drawn using a small triangle along with an imersion bubble, as shown in Figure 327. Because those symbols identify the clock input, those inputs typically are not given & name Bear in mind that although the master- servant design doesn’t change the output until the falling clock edge, the flip-flop is sil posi tive edgetriggered, because the flip-flop stored the value that was atthe input at che instant that the eleck edge was ising. igure 3.21 Postive (shown on the left) and negative (right) edge-riggered D Flip-flops. The sideways tangle inpat represents an edge-tiggersd clock input Lotches versus Flip-Flops: Various textbooks define the terms latch and flip-flop differ- cently, We'll use what seems to be the most common convention among designers, namely: +A latch is te +A ip-ftop is edge-tr So saying “edge-triggered flip-flop” would be redundant, sines flip-flops are, by this definition, edge-triggered. Likewise, saying “level-sensitive lat latches are by definition level-sensitive Figure 3.28 user a timing diagram to t H illustra the difference between level-sensi 1 tive (Latch) and edge-triggered (Hip-tlop) bit ck | stomge blocks, The figure provides an sensitive, and red, is redundant, since example of a elock signal and a value on a od] | eee, = le : ouput of aD laich, which is levelsensitive em The latch ignores the first pube on p O10 8M) 7 e (labeled as 3 in the rigure) because C2K Is low, However, when CLK becomes high (1). @ (0 tipsop) the latch output follows the D input, so when D changes from 0 t 2 (4), So does the lateh output (7). ‘The ketch igneres the next cchanges on D when Clk is low (5), but then follows D again when CLE is high (6, 8) Figure 3.28 Larch versus flip-top timing. b @- 8 @ Obras protegidas por Direitos de! Autor@ | Gan neti mtn nent is © @ = = The circuit's desited bofavior can he captured as the TABLED tnth tale for ‘auth table in Table 3.1, If CalL=9 and CneL=0 (the first call-buton system. ‘wo 10W), D equals Qs value If Ca221=0 and cne2=3 (ihe = next 0 Ws) D=0,IFCal-1 and Cnel=0 (ie nexttwo aE eeel a TB 10S), D=L. Atdif both Cal i=1 and Cuci=1 (the last two, See rows) the Ca11 ution gets priority. s0 ‘ier some algebraic simplification. we obtain the fo oto fo lowing equation for 5: —— or D = cnel'g + call HH a es ‘We can then convert the equation tothe ircuitshown in a> Figure 334(b). That circuit is more rokust than the ealier circuit using an SR latch in Figure 3.10, But ais sill not as 00d as it could be: Section 35 wil explain why we might want fo ad additional flip-flops atthe Call and crcl inguls. Furthermow, our design process in this example was ad hoe; the Following ‘00 eetions will introduce better method for capturing desired betavior and converting toa src " ‘The above sections went through severil intermediate hit storage block designs before arriving at the robust D flip-Top design. Figure 3.35 summarizes those designs, Including features and problems of each. Notice that the D tip-tlop relies on an aterral SR latch to maintain a stored bit Between clock edges, and relies on the designer to intro- duce feedback outside the D flip-flop {0 mainiain a stored bit across clock edges. Se5a) [TET om oem Ptr Be 1 es 83 Diateh| [later] 7 i" poo xg T {om Ics ap Sh ol | lo, Jol | Alemcterl| [servant [F (reset) BY il 4 Feature: S-1 Feature: S and A only Feature: SR can'tbe 11. Feature: Only loads D value fete Qo 1,1 have effest whon G-1, Problom’G-1 or tos long_prosent at ring eleek edge, feeets Q100. Aneterral circuit can will propagate naw values £0 values cant propagate fo Probiom: prevent =17 when through too many latches, othr fp tls during same ‘SA=t1yields Om fortoo short may net clock cyele. Tadeo uses Undetired @, —-Probfem:avolding —_—resutin tie Bibelng more gales Inornaly, ard oer gitches _SF=11 can bea burden, stored. requires more external gates ray seureset than SA—buttransstore toeay Inadvertent are more pleniul end cheaper. Figure 3.35 Increasingly better bit storage blocks, leading to the D flip-top, Obras protegidas por Direitos de!Autor@) Sener snia maine ae 120 > 8 Sequential Logi esigr: Contos Maay testbooks, espectlly those with origins in the 1970s and 1980s, introduce several types of latches and flipflops and use many pages to deserie how to design sequential cireita wing thot dilfercet typon. Is the 1980s, transistors en ICs were mere costly and scarcer than today. The D Hip-ilop-based design for the call bution system in Figure 3.34b) uses more transistors thar the SR-lstch-based design in Figure 3.10—not only does aD flip-flop contain sore teunsatons intemal, but it may require more extermal logic to set D to the appropriate value, Other fip flop types included a IK {ip fop that acts Tike an SR flip-Fop pus the behavior ‘means change from 010 1,oFftom 2 fo 0).andaTflip- Flop witha single input that togales the Mi-flop when 1, Fora given desired bebavio, using a particule ip. Tlop type could save tamistors. Designing sequent circuits for any flip-flop type as a challenging task, Involving something calles “escitation tables’ and ccompatison of different designs, and was helpful for reducing cicuit transistors. But today, in the era of billion-trnsistor ICs, the savings of auch flip-flops axe trivial. Nearly all modern sequential ceuits use D flp- ops and hence are created wing the more ‘Sajghforward design process invoduced in his chapter thatthe flip-flop toggles if both inputs are 1 (oggle Basic Register—Storing Multiple Bits A register is « sequential component that can store multiple bite, A basic register oan be built simply by using multiple D flip-flops as shown in Figure 3.36. That register ea hold four bits. When the clock rises, all four flip-flops get loaded with inputs £0, 11, 72, ‘and 12 simultaneously. | A A a > L = regster e 1998) af or rel], Cea & ee a eo (a) (6) Fi 1@ 3.35 A basic {it epister: (internal design, (B) block syenbol. Svch a register, made simply from multiple flip-flops, i: the most basie form of a ser—so basic that some companies refer to such a register simply as a "4-bit D flip- flop.” Chapter 4 introduces more advanced registers having additional features and operations Example 32 Temperature history display using registers ‘We want to design a system that recerds the ouside temyeratre every’ hour andl displays the last, thee recorded temperatures. so that an observer can see the temperature trend An architecture of the system is shown in Figure 3.37 ‘A timer generates pulse om signal € every hour. A temperatire sensor outputs the present temperature asa $-bit binary number ranging from 0 to 31, eoresponding to those temperatures in Celsius. Thee displays coment their S-bit binary inputs ino a numevical displ. —o|@ Obras protegidas por Direitos de|Autor@ | rere min maine ae 32 Storing One Bi Fops «121 thow age _ 2 hours age. Display Display Display temperature fea ad adagar ac bebse2bi bo e4 ed e221 e0 i “TemporatureHiton/Storage by ————— | Figure 37 Temperature (in practice, wo would actualy avoid connecting the tmer output history dsplay system. © bra cbck input, nstead ony conectig an escilator output fo clock input.) We can implement the TemperatureistoryStorage component using three S-bit ogisers, as shown in Figure 338, Each pulse on signal ¢ loads 2a with the present temperature on inputs set. x0 thy leading the 5 flip-flops inside Ra with the S input bis), the same time that repiser Ra gets loaded with that present temperature, rogisicr Rb gets loaded with the vale that was in Ra Likewise, Re gets cased with Rb’s value. All thee loads happen at the sae tine, namely, 0 the rising edge of ©. The effect i hat the valites that were in Ra and Rb just before the elack edge are shifted into Rb and 2c, respectively. tate toe tt tthe t A 4 Ee befasho pe bsbefor fo ststeferfn i alse on} iso [Hels os} —t is a3 3 G3 Bele ca noel 2 Fiawease felt 8h ot Ti ci Intsma cesign of > tea Tio co the tempernne _ e — Hiswry Storage Oh “TemperatweHisiorysiorage component FFiguse 3.39 shows sample values inthe registers for several clock eycles, assuming alle reg. shown athe top ofthe timing diagram, dally held 08, and assuming that at time proceeds the is imply 24. 20 have the valuos 10- BREAR Figure 239 Example of i Lf a a = ‘ales inthe TemperatureHistory Storage resisters. One particular dataitem, 18, shown moving throggh the registers on each clock evel. Obras protegidas por Direitos de|Autor@ |G ss ona nt oat 96 sh 4 122 > 8 Sequential Logi esigr: Contos This example demonstrates one of the desircble aspects of synchronous crets built from edge triggered ip ops—many things happen atonce, yet we need note concerned about signals propa ging bo fast through a epster io another register. The reason we need net be eoncemed s because registers only get loaded on the rising clock edlg, which effectively is an iafinitly small period of time. so by the time signals propagate thro ister toa second riser itso Tno—that saconel ste is no longer paying atention to is data inputs In practice, designers avoid connecting anything but an oscillator’s output to the clock input of a register. A key reason is so that automated tools that analyze a circuit's timing eharacteristies can work properly; such tools are beyond the scope of this book, We connected a timer’s output, which pulsed once per hour, in the above example for the purpose of an intuitive introd cr implementation would ins hhave an oscillator connected to the clock input, and then use the “load” input of a register when the timer output pulsed. The load input of a register will be introduced in Chapter 4, ion to registers. A het > 3.3 FINITE-STATE MACHINES (FSMS} Registers store hits in a digital cirewit. Stored bits mean the eireuit has memory resulting in sequential citcuits. A circuil’s tate is the value of all a cireuit’s stored bits. While & register storing bits happens to result ina eireuit with state, state can be intentionally used to design cireuits that have a specific behavior over time. For example, we can speciti- cally design a circuit that omtputs a1 for exactly three cycles whenever a button is Dressed, We could design a circuit that olinks lights n a specific pattern. We could design 2 circuit that detects if three buttons get pushed in a particular sequence and then unlocks 1 door. All these cases make use of state to create specific time-ordered behavior for a circuit Example 33 Threa-cycles-high laser timer—a poorly done first design Conse the design of pat oF «as eurgery sytem, sich a ase for ser renova or SB [Goce ‘corrective vision. Such systems work by turn- g seer ion laser fora presse amount of ime (see ow does it work?—Laser surery” on page 123). A goneral architecture of such a Systems shown in Figure 340 ‘Asurgconactivats the Taser by pressing Fgwre 340 Laser ner system, the butions Assume thatthe laser shou then stay onfor exactly 30. Asume thatthe systems chck period is 10 s,s that 3 clock eyes lst 30 ns. Assume thom the ballon is synchronic wih the Cock and say high for exatly 1 sleck cycle, We need to design controller componct th, onse destin tha b= holds igh for exacly 3 clock eyes, tus tring on the lner for 30s. Tas sone example for which x micoprosessar soln may ik work. Us icopto= cessor programming statement that red inpt ports and witeoatpt pots may not ove ae to hold an utput por high for exact 30 as—forextmple, when the microprocessor clock fe of alefe ae } f : Figure 3.41 First oad) attempt to implement the laser timer system, We did poor job implementing this system. Fist, what happens if the surgeon presses the bution a Second time before the three eyeles are completed? Such a situation could case the laser to stay on too long. Is there a simple way to 8x our circuit to account for that behavior? Second, we didn’t use any orderly process for designing the cirevit—we came up with the ORing of ilip-flop outputs, but how did we come up with that? Will thar method work for all time-ordored bshavior that nzeds to be designed? 2 Two things are required to do a better job at designing circuits having time-ordered “ behavior: (1) a way te explieitly capture the desired time-ordered behavior, and (2) a technique for converting such behavir to a sequentia Laser surgery has become very popular in the past two decades, and has heen enabled due to digital systems, Lasers, imented in the carly 1960s, generate an intense narow beam of eoherent light, with photons Imaving a single wavelengih and being in phase (ike being in aythm) with one another, In contrast, a regula Tights photons fly out i all direcdons. with a diversity of wavelengihs, Think of a laser as a platoon of soldiers marching in synch, while a regular Hight is more like Kids running out of school at the end-of-the ay bell. laser's light can be so intense as to even cit steel. The ability of w digital cieuit to carefully control the location, intensity, and duration ofthe laser for surgery js what mates lasers so useil ‘One popular use of lasers for surgery is for scar removal. The laser is focused on the damaged cells slightly below the surface, causing those cells 0 be saporized. The laser ca also be used to saporize shin cells that frm bumps onthe skin, due to sears or moles. Similarly, lasers can reduce wrinkles by smocthing the skin around the wrinkle to make the erevises more grads aed hence less obvious, or by stimulating tissue Under the skin o stimulate new collagen grow Another popular use of lasers for surgery is For comecting vision. In one popular laser eye surgery ‘method, te surgeon uses a laser to cut open 2 lap on the surface of the comes, and then uses a laser 0 reshape the cornea by thinning the comea ina particular patern, with such thinning accomplished throvgh vaporizing cells. A digital system controls the laser's location, energy, land duration, kused on programmed information of the esited procedure, The availability of lasers, combined with low-cost highspeed digital creuits, makes such precise ara useful surzery now pos Obras protegidas por Direitos de!Autoroa, seq.fn Page 126 Thrsiny, December 10, 2900 1148 PH 2 ? 126 > 8 Sequential Logi esigr: Contos ‘The shove examples illustrate that « finitestate machine or FSM is 4 mathematical {formalism consisting of several items: +A sot of states, The above sample had four states: (On, On2, On3, Off) + A-set of inputs and a set of outputs. The example had one input: {}, and one output: 1) + An initial state: the state in which to start when the system ie fist powered on, An FSM’s initial state can be shown graphically by a directed edge (an edge with an arrow at one end) stariing from no state and pointing to the initial state, An ESM ‘ean only have one initial state, The example's initial state wag the state named Off Note that Offs just a name, and does not suggest that the sysiem’s power is off (rather, it suggests that the laser is olf). + A sot of transitions: An indication of the next state based on the current state and the current values of the inputs, The example used directed edges with associated input conditions, which is a Boolean expression of input variables, ty indicate the next state, Those edges with conditions are called transitions, The example had several (ransitions, such as the edge with conition b*cLk" + A description of what output values to assign in each sate, The example assigns a value to x in every state, Assigning an output in an FSM is known as an action. Aer being defined, an FSM ean then be executed (even if just meatally}—what computer programmers might call “running” the FSM. The FSM starts with the current state being the initial state and then transitions to a different state based on the current Slate and input values, continuing as time proeseds. In each state, the FSM seis output values, Mentally executing an PSM is akin to mentally evaluating @ Boolean equation for sample input values. The FSM in Figure 3.43 wovld be interpreted as follows. The system starts in the initial state Off. The system stays in state Off uetil one of the state’s two oulgoing transi- tions has a true condition, One of those transitions has the condition of b' #¢1k*—in that cease, the system transitions right back to state Of: The other transition has the condition of b¥clk~—in that case, the system transitions to state Onl. The system stays in state Oat until its only outgoing transition’s condition ¢Lk™ becomes true—in which ease the system transitions 10 state On2. Likewise, the system stays in Or2 unt the next rising clock edge, transitioning to On3. The system stays in On3 until the next rising clock edge, transitioning back co state Off State OIf has associated the action of setting While the states Onl, On?, and On3 each set 21. Finite-state machines, or FSMs, have a ther “machine” is used in its mathematical or computer twhward name that sometimes causes confesion. The science sense, being a conceptual object that can term “finite” is there to contrast FSMs with a similar execute an abstract kanguage—spectiall, that sense represeniation used in mathemalies thit can have an of machine is ot hardware. Finile-slle machines are infinite number of states: that representation is not also known as finite-state automata, FSMs are used very useful in digial design, FSMSs, ip contrast, have for many things other than just digital desig, limited, oF finite, umber of staes, The term oO | @ Obras protegidas por Direitos de|Autor‘seg Pape 127 Thr, Dace 14,2909 HL Pt 33 Finte State Machines [FSMs) 127 ‘The FSM in Figure 3.45 precisely describes the desired time-ordered behavior of the laser timer system from Example 3.3. Icisinteresting to examine the behavior of this FSM if the button is pressed a second time while the laser is on. Notice tha the transitions among the On states are independent of the value of b. So this system will always tuen the laser on for exactly three cycles and, then retum to the Of state 1 await another press of the button. aes ‘Simplifying FSM Notation: Making the Rising Clock Implicit ‘Thus far the rising clock edge (c1k*) has OO edie enton ot ey FSM tie ME, ee tion, because this book only considers the design a fof sequential cireuits that are synchronous and that use rising edge-triggered flip-flops to siore bits. Synchronous circuits with edge-riggered Figuro3.48 Simplifying _flip-Flops make up the majority of sequential cie- rotation: implick rising cuits in modern practice, As such, to make state sloskedgeonevery —giggrams. more eadable, most textbooks and eansiton, designers follow the convention shown in Figure Figure 47 Laser timer state diagram 3.46 wherein every FSM transition is implicitly “SOME Sie weANDed ANDed with a rising clock edge, For example, a transition labeled “a'” actually means ‘yeLk* Subsequent state ciagrams will not include the rising clock edge in transi- tion conditions, instead following the comention that every transition is implicitly ANDed with a rising clock edge. Figure 3.47 illustrates the laser timer state diagram from CoO Bite 355 seinen sng imple tay lok ofp Figure 348 Transition {A transition with no associated condition as in Figure 3.48 simply transitions on the istaken onnext ising nextrising clock edge, because of the implicit rising elock edge. lock edge, Following are more examples showing how FSMs can describe time-ordered behavior, Example34 Secure car key Have you noticed tht the Keys for many new automobiles have 2 thicker plastic head than in the past ee Figure 3.49)? The reason i that believe it or nt, there ica compiler chip inside the head of the kes, implementing a secure car key. Ina basic version of such a secure car key, when the iver urns the ey inthe ignition, the eats computer (whichis under the hood and ecmmunicaes sing whar's called the basestation) sends ou racio signal asking the ear key's chip to respond by sending an idemitier via a radio signal, Th chip inthe key then responds by sending te identi eo =>—- Figure 349 Why are the teas oF caF keys geting ticker? Note tht the key on the right is thicker than the key onthe left The koy onthe right has a computer chip inside that sends an identiir to the ears computer, thus helping to reduce car tells Obras protegidas por Direitos d -@ | Oss net ty. ooate 96 sh oe t t 128 > 5 Sequential Logi esigr: Contos (ID), using what's known asa transponder (a teansponder “transmits” in “esponse" fo a request). IF the basestation does not receive a response oF the key's response hasan ID different than the ID pogeammed into the eas computer, the computer shuts down and the eat wont Sul Les design the contoller for sueh 3 ‘ey, having an ID of 1021 eal IDs ave typ Inputs: Outputs ically 22 bits long oF more, not just 4 its Assume the contoller has sm ingut that 4 when the car's compater requests the key's ID. Ths the contoller initially waits forthe input a to Become 1, The key should the send its ID (1011) serially starting with the => rightmest bit, on an output x; the key sends 11 om the fint clock eyele, 1 on the second cycle, 0 on the third eyele, and finally 1. on the fourth eyele, The FSM for the controller is shown in Figure 3.9). Note that the FSM sends the its stating from the bt on the right, which is known as the least significant bit (LSB). ‘The computer chip in the cw key has cireuty that converts radio signals to bits and vice verse. 5 i Figure 3.0 Secure car key FSM. Real that each ‘ge’ condition includes a implicitsising clock lee. Figure 3.51 proves a ting dagran for the FSM fora puriciler sition When 9 st «he FSM enters sate and ouputs r=. The FSM then proceeds throngh K2. Ki. and Kd, uputing r=. 0, and 3, spectively. eventhough we retuned input a 0 “Timing dag represent a partcslar situation fined by how we st the np, What woul tv happened if wo hed bold a= for many more clock eydee? The timing dingram in igure | 352 lists hit sittaton, Notice how in hit cass the FSM after returning to tate Wat, pro- | by ceeds to state K/ again on the next cyte & "So my car key may someday need . its batteries replaced?” you might sk. Actually, no—those chips in keys daw = ™ SLE LILILI LULL thie power, as wll a their elock, from Inputs the magnetic component of the radio-re- ———— dqveney field senerated from the state [Wan] wah] Ra [RE] Wa] 4 [mn computer basestaton, as in RFID chips. The exiremely low power requirement Quputs imckes custom digital circuitry, rather : Le than instructions on a microprocessor, ‘pefebed kaolerentaton Figure 351 Secure car key timing diagram. Computer chip keys make stealing cas a bt harder—no more "hotwiting” Sant aerate de o's omer = a’ LEI PLPLIL ALN ‘won't work unless it also receives the inputs coroctidenier And the metho above [—— is acuully an overly simplistic method-—many cas hove more sophisi- Stet [Wat] wat] Wr W2[K2 | KA [wall] cited comeninization tweet the computer and the key, involving several communications bom diectons, een = tT LS LS ‘sing enerypied commiicaon—making fooling the car's eamputer even harder. A vic of scum cr kaye is that you igure 2.82 Secure carey timing diagram for a different sequence of values on inpst a, Obras protegidas por Direitos de|Autor“seg Pape 129 Thurso, Dace 1,209 1 Pt 33 Finte State Machina FSMs) 129 ant just an doven the local arvsare store and eopy those keys for SS any longer—copying keys requies special tools tht today ean run $50-5100. A commen problem while computer chip keys were becoming popelar vas dat low-cost loeksmitis did realize ube keys had chips in them, so copies were male and the car owners went home and later eould’t figure out why their ear would’t Start, even though the Key fc in the i i . Example 35 Flight-attendant call button Tlcmeesniipiebinhd games: sane behavior of the flight-uttendant call button system " from Figure 3.1. The FSM hss inputs Cal and Lo all Ly Taconic carruiltegaa pany oGIC@HOH if beh batons are pressed. The FSM has two states, LigtO, which ses & 10 0, and LighOn, which ses 1 102, as shown in Figure 383. Light” Figure 259 FSM fr fligheatendan eal Offs tho iil state. The FSM stays in that soto juton system until CaLL is 2, which causes 4 tasition to LightOn- if a1. 0, the FSM Stays in LightOf In sate LightOn, te only way’ transition hack to LightOff is if cnet is 2 and call is 0 (because the call bution has priory), meaning Gnci*Cal1' I that contin is fie, ie, (Cnet *Cal") "iste, the FSM says in LightOn Notice how clsly the FSM capture the behavior of the fight stendint cll button syste. | Once you undestand FSMs, an FSM desripion is Hikely to be more concke and precise han an English descrpion. ener Cait How to Capture Desired Sysiem Behavior as an FSM The previous section showed FSM examples, but how were those FSMs originally er ated? Creating an FSM that captures desired system behavior can be a challenging task for adesigner. Using the following method ean help + List states: First list all possible states of the system, giving each a meaningful mame, and denoting the intial state, Optionally add some transitions if they help indicate the purpose of each state + Greate transitions: For each state, define all possible transitions leaving that state + Refine the FSM: Exceute the FSM mentally and make any needed improvements ‘The method desctibed above is just a guide. Capturing beliavior as an FSM may oquice some creativity and trial-and-error, as is the cas? in some other enginesting tasks, like computer programming. For a complex system, a designer may at frst list a few states, apd then upon defining wransitions the designer may decide that more states are required. While ereating an FSM, the preciseness of the FSM may eause the designer to realize that the systems behavior should be different than originally anticipated, Note ‘also that many different FSMs could be created that describe the same desired behavier one FSM may be easier t0 understand while another FSM may have fewer states, for example. Experience can help greatly in creating correct and easy-co-undersiand FSMs ‘hat capture desired system behavior. —e|@ bras protegidas por Direitos de|Autorimage not available@ Sree sin maine aie —e 33 Finte-State Wachinas FSMs) 131 the FSM should go t9 state Red; we'd already added that transition (a=). Ha bution is pressed and ‘that button is not the red button (2x), then the FSM stould somehow enter a “fail” mode and not unlock the dour. At this poini, we might consider adding another state ealled Fail Instead, we ‘decide thatthe FSM should go back to the Wai sete and just wait for the start burton to be pressed ‘again, so We add such a tansiion with condition ax as shown, The pattem af three transitions for sate Start ean be replicated for states Redl, Blue, and Green, mod ified to detect the cormet colored ‘huton press as shown in Figure 3.57 Finally. we must decide what the PSM should do after the FSM reaches stile Red2 snd unlocks the door. For simplicity ofthis example, we decide 10 have the FSM. just return to state Wat, which locks the door again; areal system would keep the door unlocked for a fixed period Figure 3.57 Code detector FSM with complete tansitions of time before locking it again. Refine the FSM: We ean now menlly execute the FSM to see iit behaves as desired; Inputs sr9.ba Outputs u + Tho FSM bogins ia the Wai state. As lang asthe sat baton is not pressed (=) the FSM stays {in Wai; when the start buttons i pressed (and a tsing clock edge arrives, of couse), the FSM goes tothe Start sate, + Reng inthe Start state means the PSM is now ready to detsetthe sequence rod, blu, grsen, re ao button s pressed (a) the FSM stays in Stan. Ira button is pressed AND that button is the red button (az), the FSM goes fo state Redf,Instead, ia buton is pressed AND that ton is ‘ot the red bation ax), the FSM retums tothe Wa state—note that when inthe Wat state, furtherpresses of he colored buttons would be ignored, untithe srt buttons pressed again. +The FSM stays imstate Ret as Jeng as no button is pressed (a *). If button is pressed AND that buton is blue (ai), the FSM goesto stte Ble: if that huttow is not Bue (ab), the FSM reiuensto ste Wait, Athis point, we detect. potential probiem—what if the red button i ill being prssed as prt ofthe fist button press when the nxt rising clock edge ariven? Tho FSM ‘would go to state Wait, which is not what we want, One soluion to add smother sta, Red!_Release. tat te FSM rarsitions to after Red | and in which the FSM stays unl For sinpliciy. well instead assume that each baton has a special ciguit that synetyonizes the bution with the clock signal. That circuit sets its cutput to 1. for exactly one clock eyele {or ouch unique poss of the button, This is necessary to enaure that the current tate doesn't inadvertently change to another state ia button press lasts longer than a Single clock eyele ‘We'll dssign sucha synchronization cizeuitin Example 3. 1+ Likewise, the PSM stays i state Blue ae long as no bation i prested (a). and goes to state Green on condition ag.and state Wait en cordon ag + Finally, the FSM stay’ in Green ino button is pressed, and poes to state Re? on condition ax, snd to ate Wait on corition a> + Ifthe FSM makes it to state Red2, that means thatthe ser presed the butions in the correct sequence—Red? will sel u=1, thts unlacking the door. Note thatal oer siatles set t=0. The FSM thon rotirnsto se Wi Obras protegidas por Direitos de!Autor‘seq Pas 132 Try, Dace 14,2909 1 Pt 132 > 3 Sequential Logic sige: Contallers The FSM works well for noxmal hruwon presses, but let's mentally execute the FSM for unustal cases, ‘What happens iF the user presses the Sturt button and then presses al three colored buttons simultaneously, four times in a row’? The way the PSM is defined, the door would unlock! A. solution to tis uadesived siuation is to mosify the trarsitions heween the states that detect correct colored ‘baton presses © detect not only the Figure 358 Improved code detector FSM, correct colored button press but also that the other colored butions ave nor pressed. For example, forthe transition leaving state Start with condition ax, the vondion should instzad be a ("9"). Th change also means that the transition going back 19 state Wai should have the condition a (rb'g*) *. The intuitive meaning of that con- sliéon is thata bution was pressed, but it was not just the red bution. Similor changes an be mae to Inputs: sra.ba Outputs: the other tratsition conditions too esting inthe improved FSM of Figure 3.58. » 3.4 CONTROLLER DESIGN Standard Controller Architecture for Implemei an FSM as a Sequential Circuit Te previous section provided examples of capturing sequential behavior using FSMs This seotion defines a process to convert an FSM ta sequential eireui. The sequential circuit that immplzments an FSM is common called a controller. Converting an FSM to controller ix gute staightforward when a standard pattem, commonly called a standaed architecture, fs uscd for the wontrollr. Other ways exist for implementing an FSM, but using te standard architeetore reals ina sraightforward design proces. ‘standard contol architecture for an aaa PSM consists of «register and combinational fy ‘ logie. For example, the standard controller] ggq™| Conbintonal lay —— Faq] architecture for the laser timer FSM of Figure inputs |__!@9'¢ outputs: 345 is shown in Figure 359. The controller's uth: "| register stores the curent FSM sate and is thus called a state register Each state isrep- redented ae a. unique bit encoding. Por Gramps he ler tines Of ste col te encoded as 00, Ont as 22, On2 as 29, and Figure 359 Standard eontollerarchtecture (On3 a8 12 the our states thus requiring 82- fori lner nee bit state resister The combisational Ingle computes the output values forthe present sate, and also compures the next site based on the eatrent state and current input valves, Is iapus are thas te slate register bits (22 and 20 in the example of Figure 3.59) and the FSM's sternal inputs forthe example). The combleatonal logis ouput are te oulpus oF ick, | state register —4|@ Obras protegidas por Direitos de|Autorimage not availableimage not available@ |G ss ens rt. oeate 96 sb ? Example 38 34 Cantor Design 135 We then obtain the sequen Figure 3.62 implementing the FSM, Laser timer corivorer b ‘Combinatonalogic lat ne Figure 3.62 Final implementation ofthe ‘three-cycles-high laser timer controller. Many textbooks use different table organizations fron that in Table 3.3. However, we intentionally organized the table so that it serves both as a state table, which is iabular representation of sn PSM, and as a truth table that can be used t0 design the combina- tional logic of the controller Understanding the laser timer control's behavior ‘To aid in understanding how a coatroller implements an FSM, this example traces thiough the behavior of the these-cyeles high laser timar sontoller Assume the system is initially in sate 09 (9120200), bis 0, and the clock is currently low. As shown in Figure 3.632), tased on the com Dinational logic, x will be O (the desired output in state 00), 24 will be O, and 20 will be 0, mea ing the value 09 will be waiting atthe state registers inputs. Thus, on the nex! clock edge, 90 will ‘ne Touded into the state register, meaning the system stays in state 00—which is coreect. Now suppose b becomes 1. Ac shown in Figure 363(b), > will ill be ©, ae desired. 21 will be 0, but no will be 2, meaning the valuo 02 will be waiting tthe state register’ inputs. Thus, on the next cinek edge, 02 willbe loaded info the sale register as desired. As in Figure 3.63(c), soon alter 01 is losded into the state register, x will become 2 (after the regiser is loaded, there's a sight delay as the new values for si and 20 propagate throsgh the combinational lopic gates). That ouput is eortct—the system shoald output e=1 when in sate 01 Also, ni will become v and n0 will equal 0, meaning the value 10 will be waiting at the state register inputs. Thus, on He next clock edge, £0 will be Toaded io the state rezbter, a desired, ‘After 10 is loaded into the state register, x will uy 1, and ning hecomes 11. When another clock edge comes, 12 will be oaded into the register, x wll stay L, and nino becomes 06, When another clock edge comes. 0 willbe loaded into the register Sona afta, will hecome 0, and if b is 0. nino will sty 00; if is 1, nino will heceme 01, Notice thatthe system is back in the state where Ht sane, Understanding bow a state register sid combinational logic implement a state machine can tke while, sine in a particular state tindicaed bythe value presently inthe state register, we generste \¢ Obras protegidas por Direitos de! Autorimage not available‘seg Pas 137 Thurso, Dace 12909 1 34 Cantor Design 137 bom again, so that bo was 2 for just one eye, a desired. ‘The FSM goes from B to A if'b$ retumed w 0. bi is stil 2, the FSM goes to state C, where the FSM waits for bi 1 re1rn 0, causing a uaasition back 10 state Set up the architecture. Besause the FSM has three bit sate register a in Figure 3.65(b) Encode the slates. The three slaes can be straightforwanlly ercoded a 00, 02, and 10. as in Figure 3.65(6, Fill n the truth table. We convent the FSM with encoded staes to truth table forthe ‘controllers combinational logic, as shown in Figure 3.93(¢). For the unused state 12, we have chosen to output bo=0 and resurnW state 00. ates the architecture has a 160: Step 2D: Implement the combinational log We derive the equations for ech combination logic output, as showa in Figure 3.65(¢), and ten ereae the fal iret as shown. FSM inputs bi: FSM eulpus bo oO —e|@ protegidas por Direitos de|Autor‘seg Page 136 Thurso, Dest 10,2909 1 138 > 3 Sequential Logic Desigr:Contallers Example 3.10 Sequence gonerator ‘This eample designs » sequential citcuit with four out- IMputs:(none) —Ouputs w, x.y, 2 puts: 36 y, and 2. The eireuit should generate the fol- yuxyz=0001wxyz=-1000, Towing sequence of output gatteras: 0901, 0021, 2200, = . ‘and 1090, one por clock eyele, After 1000, the circuit should repeat the sequence, Sequeree generstors are common in a varoty of systems, such as a system that blinks «sot of four lights ina pantieular patern for a fo eB tive Tights display. Asother example is 2 system that roes an electric motor a fixed number of degrees each clock eyele by powering magnets around the motor in a Figure 346. Sequence generator FSM. specific sequence to atracl the magnetized motor tothe noxt position in the rotation —known 38a sper motor, bocause tho motor rotates in stops ‘The sequence generator controler can be designed using the controller design proces: Es vwey2=0011—_wxya-1100 Skp 1: Cape the SM Figue 366 shows an || Combnaona FSM having four states labeled A, B,C, and D eae int (leg) corse urea moet woade) | LB Jt nto ene he died sequence af fie Step 24: Sel up the architecture. The stand con. | (size regater troller archvctae forthe sequence generator SM) > wil ane a 2-bit state reer 9 repesert the i four pessble sas, no its to the lope, and ‘ culpats m3 from the Tog, slog ov Fire 67 Sequence genertor oviputs at and nd, ashown in Figue 367, cooler arcitsture Step 2B: Encode the states, The stites can be encodedas follows: 90, B02, C: 10, D 3. {Any otter encoding with a unigne code for ach ate would alo be fine Step 2¢: Flin the truth table. Table 34 shows the table fr the FSM with encoded state. Step 2D: Implement the combinational loge. An equation canbe derived for ech ouput ofthe cemblitiona loge dey from the uh able: Afr some alba sinplition, the caiatcn are those shown below. The final cite is shown in Figure 3.68 a TABLE.4 State tableforsequence we on generator conteller. x = sie0' Inputs Ouipus y= s1'so el so|w x ze sit sales nb a nore 2 22 no = 0! Boiljooiaiao oz a 0024 Dialioovoo aan Figure 288 Sequence generator elke 1st 7291 sootrller with implemented sombinitional logic o— b Sie —e— ee @ bras protegidas por Direitos de|Autor@)| Sse aasaine aie F es ¢ Combinational toaie sil so ate register 44 Cantor Design 139 Example 3.11 Secure car key controller (continued) Les complete the design for she secure cat key controler from Example 34, We already carried ‘out Step 1: Capture the FSM, showa in Figure 3.80, The remaining steps areas follows, Step 2A: Set up the architecture. The FSM has five states, and thus requires a 3-Sit state res ister, which can represent eight states; thee states’ will be unused. The inputs to the ‘combinational logie are a and the three sate hits #2, 81, ars 80, while the outputs are signal x and next state outputs2, n1, and m9. The architecture is shown in Figure 3.69, ‘Step 28: Encade the states. Let's encode the sates using a staightforward binary encoding of (009 through 100. The FSM with sate encodings s shown in Figure 370. ‘Step 2C: Fill in the truth fable. The FSM converted oa trath table fer the logic is shown in Table 3.5 For the unesed state, we Have chosen to st = 0 ad the next state to 099. Inputs a Outputs: r a ie = mi mT Figure 3.70 Secure carkey FSM with encoded sates. Figure 369 Secure car key ccontotteragehectre TAGLE 35 Truth table for cura car key controllers combinational logic implement — the combinational Inputs Outputs logic, We can design four cireuis, one = —~—~=ea gi BO a En? nl nd for eich oatput, to implement th combine —§ AS TT Step 21 ional logic. We leave this step as an wa 2 © 2 9/9 9 9 0 ‘exercise forthe reat ed ee do 2 ota 10 Hy oaalaoro Dao olzo0 1a do tle ond me bt else 0 o1d0 220 0fza00 1oorj1o0 90 1020/0090 1011/0090 1100/0000 vmect > yo 1lo 0 9 0 1211/0090 Obras protegidas por Direitos de! Autor@ wera re rn. panes we ? 140 > 3 Sequential Logic esigr:Contallers Converting a Circuit to an FSM (Reverse Engineering) We showed in Section 2.6 that a circuit, truth table, and equation were all forms able to represent the same combinational function. Similarly, a circuit, state table, and FSM are all forns able we represent the same sequential function. The process in Table 3.2 for convecting an FSM to a circuit ean be applied in reverse to convert a circuit to an PSM. In general, converting a circuit t© an equation or PSM is known as reverse enginesring the bshcvior of the eitewit, Not only is reverse engineering useful to help develop a better understanding of sequential circuit design, but it ean also be used to understand the behavior of a previously-designed circuit such as a circuit created hy a designer who is no longer at 2 company, and also t0 check that a cireuit we designed has the correct behavior, . Example 312 Converting 2 sequertial circuit to an FSM Given the sequential circuitin Figure 3.71, find aan equivalent FSM, We start from step 2D in Table 3.2. The combinational cireuie already exists. Step 2C fills in a truth table. The combi- rational loge in the controller architecture has thee inputs: two inputs 0 and 62 represent the contents of the state register and x is an fexoenal input. Thus th truth table will havo & rows because there are 2°=8 possible combina tions of inputs. After Isting the truth able and cenomerating all combinations of inputs (e., sis0x=000, .., sis0x=111), the Ech cy niques in Ssction 2.6 can bo wed to fil in the lues of the oulputs. Consider the outpst y. ‘The combinational cieuit shows that y= 91 Koowing ths, we place a 1 in the v column of the teuth able in every row where 22 = 0, and place 8.0 in the remaining spaces in they column. Considse no, which the eireit shows ae having the Boolean equation 20 =51' s0'x. Accordingly, we set 20 to 1 whe 61=0 and 60 =C and ‘We fll n the columns for z and asing similar analysis and move on fo the next step. Step 2B encodes the states. The states have TABLE. Tuth able for circuit. + Figure 3.71 Circuit with unknown behavior, jaca ea ad bo nape oes a name to encoded state. We arbitrarily choose the Inputs Outputs tamer 4 6. Ds acenin ble er aor Same tind anh tu. Ths ep reqs no work sic theConollr 6 zi. architecture was already defined. oe see al ce | crows A FSM, Rae) —g 6 ‘can set up an FSM diagram with the four states Boo i o 1 0 eee ee beria sont age 373G. New, welist he vaevoftheFSMouputsy C2 § 9/9 8 9 2 SO aan a enae P41 if0 000 —@- —o|@ ras protegidas por Direitos de! Autor@)| Srserscia caineasricns aie ? — C) 34 Cantor Design 143 A designer can verify the above two properties using Boolean algebra. The exclusive transitions property can he verified by ensuring that the AND of every pair of conditions on a state's transitions always results in 0. For example, if state has wo transitions, one with condition > and the other with condition xy, transformations of Boolean slgebra ccan he used as follows: xe xy feexyry ont: =a Ifa state has three transitions with conditions C1, C2, and C3, the designer ean verily that C7 *C2=0, C/"C3=0, and finally that C2°C3=0, thus verifying that every pair yields 6, Note that verifying that C1°C2*CI=0 does not verily thatthe transitions are exclusives for example, if C/ and C2 were exclusive but C2 and C# were not, CI#C2#C3 would still equal 0 because 0*C3=9. The second property of complete transitions ean be verified by checking that the OR of all the conditions ona state’s transitions results in 1. Considering the same example of ‘state that has to transitions, one with condition x and the other with condition 2’ y, transformations of Boolean algebra can be applied as follows: ae Sole) + sty x+xytx'y x + GORY, exey The OR of those two consitions is not 1 but rather x+y. If x and y were both 0, neither condition would be tue, and so the next state would not he specified in the FSM. Figure 375(b) fixed this problem by adding another transition, xy". Checking these transitions yields xe xty se wyt =x 4 xt (yey) x4 KIL Ifa state has three transitions with conditions C7, C2, and C3, the designer can verify that CI4C24C3= Proving the propesties for the transitions of every state can be time-consuming. A. ‘200d FSM capture tool will verify the above two properties automatically and inform th designer of any problems, Obras protegidas por Direitos de! Autorimage not availableimage not available@)| Srsrciaainsseicns ware ? 146 > 3 Sequential Loge Desigr: Contallers > 3.5 MORE ON FLIP-FLOPS AND CONTROLLERS ‘Non-Ideal Flip-Flop Behavior When first learning digital design we assume ideal behavior for logic gates and flip-flops, Jjuit Tike when first learning physics of motion we assume there's no Trietion oF wind resistance. However, there is a non-ideal behavior of fip-flops—mietastability—that is such a common problem in the practice of real digital design, we feel obliged to discuss the issie briefly here, Digital designers in practice should study mets sible solutions quite thomughly before doing serious designs. Metastability comes from failing fo meet flip-flop setup or hold times, which are now introduced. Setup Times and Hold Times Flip-flops are built from wires and logic gates, and wires and logie gates have delays, ‘Thus, a real flip-flop imposes some restrictions on when the fip-flop’s inpuss ean change relative 00 the clock edge, In order to ensure correct operation despite those delays. TWo important restritions are tability and pose + Setup time: The inputs of 2 flipslop (e.g, the D input) must be stable for a minimum amount of time, Known as the setup time, before « clock edge atrives. 1 ‘This intuitively makes sense—the input values must © { | have time to propagate through any flip-flop internal ts at | logis and be waiting at the intemal gates’ inputs aves al before the clock pulse arrives. e + Hold time: The inputs of a flip-flop must remain ok stable for a minimum amount of time, known as the hold time, afer a clocs edge arives. This also makes intuitive sense—the clock signal must have time t0 propagate through the internal gates wo create & stable situation, Fee A relted restriction is on the minimum clock pulse fittetivine oneont Wwidth—the pulse must be wide enough to ensure dt the values propagate through the internal logie and ercate a stable feedback situation, Aflip-lop typically comes with a datasheet describing sotup times, held times, and aninimam clock pulse widths. A datasheet isa dneurneot that tells a designer what a com ponent does and how to properly ase th Figure 3.80 illustrates an example ofa setup time violation. D changed 10 0 too close to the rising clock, The result is that R was not + long enough to ezeate a stable feedback situation in the cross-coupled NOR gates with @ being 0, Instead, Q glitches to 0 briefly ‘That glitch feeds back to the top NOR gate, catsing Q' to glitch to 2 briefly That glitch feeds tack to the hotiom NOK gate, and so on. The escllation would likely continue until somponent Gi con ones otseble ste, ich vend dure ® —@- —o|@ Obras protegidas por Direitos de|Autorimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage not availableimage -not availableimage not availableTan Page 50 Tsay, Dosember 22,2009 448 PM T 520, > Index Event 103,167 Gate delay 91 event (in VIIDL) $02 GatedD latch 112 Exact slgorthm 339 Gated SR fetch TL Eccitaion table 120 Gbyte 21 Exclusive (cansions) 142 General purpose computer Exclusive OR ST General-purpose processor 461 Execute 465 Genenate 370 Expand operation 346 Generic ary logic (GAL) 444 Expanding (aterm) 340 Gigabyte 21 Expresion 62 Glitching 151 Global register 303 F Global signal 03 Fabrication plant (fab) 415 Google 12 Factoring 350 Ground 36,439 Fahrenheit 213 Talling edge-triggered ip-Top 146 4H Fanout 225 Hai’ Law 453 Feature Size 449 Halladder 183, 190,417 Field programmable gate array 424 acd core 452 FIFO irst-in Hist-out) 300 Hazdware description language (HDL) 489 FIFO queue 300 EDL x, 95, 489 Filter 278 Hertz 118,278 Filtering 313 Heuristic 330) Finite Impulse Response filer 276 Hex 6, Finite stale automata 126 Hoxsdscimal 16 | Finite-state machine 124, 126, 5 Hierarchical carty-lookahead adder 374 | | TR filler 276,313. 384, 597 Hierarchy 305 —@ FIR filer (pipelined) 379 High-level state machine 248 Pisstin fistout (FIFO) 307 HESM 238 Fixed. point arithmetic $50 Hold ime 136, Fash memery 296 Hz (tera) 118 Floating point number $52 Flop is 1 Fw-ofcortol instruction 480 Ie 39, 40,413 FPGA 424,445,446, 448 IC capacity 448 Frame 303 Iegpe AI Frame (video) 267 empotent 531 Frequency 117 Tempatent aw 38 FSM 124,26 entity comparator 191 FSM sith dita 253) IWeniy element 538 FSMD 253 entity property 36, Falladder 184 Uther statement 282 FallevstomIC 414 Tther-olse statement 282 Fall-subiractor 197 Inplicant 40 Function cover 340 Implication ble 383 Functions (of aregistee) 175 Trerement 215 Fuce-hased PLD sid Inerementer 190 Fuse-bused ROM 294 Indirect addressing 480 intial procedure in Nerlag) 409 s Iritial state 125, 150 GAL (genetic array logie) 444 Taput (in Verilog) 491 Gate 6 Instance 259 Gate (ot a tansisor) 41 Instaniate 259 Gate aray 424 Instruction memory 465 Gate atray ASIC 417, 448, Insteuction register 466 Autorimage not availableimage _ not availableimage - not available€ Tn Page 574 stay December 22,200 448 PM ® @ (S14 Index Sensitive Gin Verne) 496 sinzes 466 Sensitive Gir VHDL) 493 Snr achitetre (for sequential siewt) 132 sensitive po in Sytem) 503 Standard all ASIC. 116, 418 Sersitviy Ist Gn Verilog) 436,504 Sadar representation 8 Sersitvig ist (in VIIDL) 495,304 Sate 122 Sensor 9 State diagram 128 Sequetil cea 35 State encoing 338 Sequential mullpic 375 State minimization 351 Sera 386 State eduction 351 Seri commauniation 195,179 Sate ister 132,168, 505 Seratsing. 383 Site ule Servant Satie 289 Set(abich) 102 Satie RAN 288 Set ip flop npst) 9 Logie VHDL) 480 Setup time 1a SieLlogie 1164 vn VIL) 489 Sevensegment play 72 silogiearit Gn VIIDL) 517 Shannon, Caude #5 {icogic_usigned in VDL 517 Sharedbus 227 Sil-fogie-yector (in VHDL) 301 shift 210 Stepper meson 138 Shi ister 175,436 Store operon 463 Shifter 211,214,259 Storing (ina repster) 168 Shing (rept) 173 Soring ht Li Stitt snd ads 212 Seam 275 Shockby, Willian, 38 Stuctire 489 site VDL 519, Sirti ASIC 418 446 | Sign bi 202 Subection metiod 16 Seal in VIL) 490 Subtctor 106 Signed number 202,212 sam 33 1 ed: magnitude repwesenstion 200) ‘Su of absolute differences (SAD) 281 Signifisand $52 Sum of minterms. 71 Silicon il 42 ‘Sum of absolute differences (SAD) 267 Silicon dioxide 41 ‘Sum-cf-minterms 69. 340 Silicon Valley: 42 ‘Sumo preauets 5,69, 74, 327, 4 Simple PLD 44 Superscalar processor 482 Simulation 2 Swited 36 Simulator Sk Switeh mavix 432 Single precision 552 Switching algebra 537, $38 Single purpmae procenor 461 Synchronized processots 304 Sue 336 Synclronous circuit 117 ‘Sliding average 211 Shncleonoes clear 180, 216 ‘Small-scale integration 438 Synelvonous reset 150 SOC 50 Synetronoes set 150, 180 Soda machine dispenser 248 Synthesis 282 Sott core (on an FPGA) 451 System-on-a-chip (SOC) 450 Software 22 Solid sate 39 1 Source (of atransiston) 1 ‘Thlip flop 120 Spin (in IC fabrication) 415 ‘Tabular melhod 341 SPLD 444 “Tap in FIR fies) 314 Spurious value 187 Thyte 21 SRAM 288 ‘Technology mapping 417,427 ssi 36 Telephone 8 Sslenp 429 Terabyte 21 Stuble 108 Term 55 ‘Stage (oF pipeline) 378 ‘Terminal count 215 Obras prc das por Direitos del Autorimage not available