PROJECT REPORT

ON
DESIGNING OF PARALLEL PREFIX ADDERS
USING VERILOG
Submitted in partial fulfillment of the
requirement for the award of the Degree of

BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING

By
S.AKHILA (R131463)

Under the guidance of

B.Bhaskar
Lecturer,Department of ECE
RGUKT,RK-Valley

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Rajiv Gandhi University of Knowledge Technologies
RGUKT RK-Valley Campus
Kadapa(dist), Andhra Pradesh, 516330
 CERTIFICATE OF PROJECT COMPLETION

This is to certify that the project entitled “DESIGNING OF

PARALLEL PREFIX ADDERS USING VERILOG” was successfully
carried out by S.AKHILA(R131463) in the partial fulfillment for the degree
of Bachelor of Technology in Electronics & Communication Engineering at
RGUKT- RK Valley.

To the best of our knowledge, the results embodied in this dissertation

work have not been submitted to any university or institute for the award of any
degree.

Project Guide Head of the Dept.

Mr.B.Bhaskar , Mr.A.Sreekanth Reddy,

Lecturer, Head &Asst. Professor ,
ECE Department , ECE Department,
RGUKT,RK-Valley. RGUKT,RK-Valley.
 ACKNOWLEDGEMENT

We wish to express our sincere thanks to Mr.H.Sudarsana Rao

Director of RGUKT, RK-Valley, for providing us with this opportunity and
for his constant support.
We take this opportunity to express our deep sense of gratitude and
indebtedness to our guide ,Mr.B.Bhskar , Department of ECE for his valuable
support, suggestions and constructive criticisms throughout this project.
We would like to thank Mr.A.Sreekanth Reddy, Head of the
Department, Department of ECE, for providing us with this opportunity and for
his constant support.
We would like to place on record the continuous support, encouragement,
advice and help that our parents and friends have gave us throughout the
duration of the project, and we should always being grateful to them for this.
Finally we thank everyone who has contributed in any way for the
successful completion of the project work.
 TABLE OF CONTENTS

Name of the contents page no

1.Abstract 1
2.Introduction 2-6
2.1.Parallel prefix adders
2.2.Black cell and Gray cell
2.3.Kogge stone adder
2.4.Ladner fischer adder
3.Circuit diagram 7-8
3.1.Kogge Stone adder
3.2.Ladner fischer adder
4.Verilog code 9-13
4.1.Kogge stone adder
4.2.Ladner fischer adder
5.Simulation Results 14-15
5.1.Kogge stone adder
5.2.Ladner fischer adder
5.3.Comparison
6.Advantges 16
7.Disadvantages
8.Applications
9.Conclusion 17
10.References 18
 1.ABSTRACT

In today’s digital world, adder plays an important role in most of the

digital circuits because of their use as basic entity in other operations such as
subtraction, multiplication and division. Now-a-days, where everybody is
working in the direction of miniaturization,three important aspects of design i.e
area, power and delay needs to be balanced optimally.So,improving the
performance of basic component(adder) would greatly advance the performance
of the whole digital system,which is the ultimate goal of VLSI Design.In this
paper we proposed a carry lookahead adder circuit in which carry generation
network is implemented in the form of prefix trees,which leads to two types of
Parallel Prefix Adders, Kogge Stone Adder and Ladner Fischer adder. In ripple
carry adder each bit of addition operation is waited for the previous bit addition
operation. In efficient Ladner - Fischer adder, addition operation does not wait
for previous bit addition operation and modification is done at gate level to
improve the speed and to decreases the memory used.

1
 2.INTRODUCTION
Addition operation is the main operation in digital signal processing
and control systems.The fast and accuracy of a processor or system depends on
the adder performance. In general purpose processors and DSP processors the
addition operation addresses are taken from simple ripple carry adder.
Ripple carry adder is used for the addition operation i.e., if N-bits
addition operation is performed by the N-bit full adder. In ripple carry adder
each bit full adder operation consists of sum and carry, that carry will be given
to next bit full adder operation, that process is continuous till the Nth bit
operation. The N-1th bit full adder operation carry will be given to the Nth bit
full adder operation present in the ripple carry adder.
For 16-bit ripple carry adder, the first bit carry is given to second bit
full adder, second bit carry is given to the third bit full adder, similarly the
operation is continue till fifteenth bit carry is given to sixteenth bit full adder.
The addition operation is performed from least significant bit to most significant
bit in ripple carry adder. Configuration logic and routing resources in Field
Programmable Gate Array.

2.1.Parallel prefix adders

Parallel-Prefix adders perform parallel addition i.e. most important
in microprocessors, DSPs, mobile devices and other high speed applications.
Parallel-Prefix adder reduces logic complexity and delay thereby enhancing
performance with factors like area and power. Therefore the Parallel-Prefix
adders are requisite element in the high speed arithmetic circuits and popular
since twenty years.
The parallel prefix adder employs the 3-stage structure of the CLA
adder .They are pre-processing stage, carry generation stage, post-processing
stage.

Pre-processing stage:

In the pre-processing stage, generate and propagate are from each pair of
inputs. The propagate gives “XOR” operation of input bits and generates gives
“AND” operation of input bits . The propagate (Pi) and generate (Gi) are shown
in below equations

2
 P[i]=A[i] XOR B[i]

G[i]=A[i] AND B[i]

Carry generation stage:
In this stage, carry is generated for each bit and this is called as carry
generate (Cg). The carry propagate and carry generate is generated for the
further operation but final cell present in the each bit operation gives carry. The
last bit carry will help to produce sum of the next bit simultaneously till the last
bit. The carry generate and carry propagate are given in below equations

Cp = P1 AND P0

Cg = G1 OR ( P1 AND G0)

The above carry propagate Cp and carry generation Cg in equations 6&7 is

black cell and the below shown carry generation in equation 8 is gray cell. The
carry propagate is generated for the further operation but final cell present in the
each bit operation gives carry. The last bit carry will help to produce sum of the
next bit simultaneously till the last bit. This carry is used for the next bit sum
operation, the carry generate is given in below equations .

Cg = G1 OR ( P1 AND G0)

Post processing stage:

It is the final stage of an efficient Ladner-Fischer adder, the carry of
a first bit is XORed with the next bit of propagates then the output is given as
sum and it is shown in equation

Si = Pi XOR Ci-1

It is used for two sixteen bit addition operations and each bit carry is undergoes
post-processing stage with propagate, gives the final sum. The first input bits
goes under pre-processing stage and it will produce propagate and generate.
These propagates and generates undergoes carry generation stage produces
carry generates and carry propagates, these undergoes post-processing stage and
gives final sum.
3
2.2. Black cell and Gray cell:
Black cell operates with three gates i.e. two AND gates and one OR
gate.Gray cell operates with two gates i.e. one AND gate and one OR gate.

2.3.Kogge stone adder:

Kogge-Stone adder is a parallel-prefix form carry lookahead adder.

Kogge-Stone adder was developed by [3] Peter M. Kogge and Harold S. Stone
which they published in1973. KS adder is a fast adder design as it generate
carry signal in O(log2 n) time and has the best performance in VLSI
implementations. KS adder has large area with minimum fan-out which
increases its performance. Kogge- Stone adder is widely used in high
performance 32-bit, 64- bit, and 128-bit adders as it reduces the critical path to
great extent. In fig.3 each vertical stage produce propagate and generate bits.
Generate bits are produced in the last stage and XORed with initial propagate
and generate bits to produce sum.

Carry Stages: log2 n;

The number of cells: nlog2 n;
Maximum fan-out: 2.

4
 Fig :complete schematic of 8-bit KS adder

2.4.Ladner Fischer Adder:

Ladner- Fischer parallel prefix adder was developed by R. Ladner and M.
Fischer in 1980.It is the parallel prefix adder to perform the addition operation.It
is looking like tree structure to perform the arithmetic operation. The Ladner-
Fischer adder consists of black cells and gray cells. Each black cell consists of
two AND gates and one OR gate . Multiplexer is combinational circuit which
consists of multiple inputs and a single output. Each gray cell consists of only
one AND gate.

5
 The proposed Ladner-Fischer adder is flexible to speed up the binary
addition and the structure looks like tree structure for the high performance of
arithmetic operations. In ripple carry adders each bit wait for the last bit
operation. In parallel prefix adders instead of waiting for the carry propagation
of the first addition, the idea here is to overlap the carry propagation of the first
addition with the computation in the second addition, and so forth, since
repetitive additions will be performed by a multioperand adder
Carry Stages: log2 n;
The number of cells: (n/2).log2n;
Maximum fan-out: n/2.

6
 3.CIRCUIT DIAGRAM
3.1. 8-bit Kogge stone adder:

7
3.2. 8-bit Ladner Fischer adder:

Here, from the circuit diagrams,

Xi and Yi are inputs
Pi and Gi are propagate and generates
Where,
Pi = Xi XOR Yi and Gi= Xi AND Yi
Carry:: Ci = Gi OR (Pi AND Ci-1)
Sum:: Si = Pi XOR Ci-1

8
 4.VERILOG CODE
4.1. 8-bit Kogge stone adder:
module ks8(s,c,cout,p,g,x,y,cin);
input [7:0]x,y;
input cin;
output [7:0]s,c,p,g;
output cout;
wire [26:1]w;
*/PRE-PROCESSING STAGE*/
hf12 h1(p[0],g[0],x[0],y[0]);
hf12 h2(p[1],g[1],x[1],y[1]);
hf12 h3(p[2],g[2],x[2],y[2]);
hf12 h4(p[3],g[3],x[3],y[3]);
hf12 h5(p[4],g[4],x[4],y[4]);
hf12 h6(p[5],g[5],x[5],y[5]);
hf12 h7(p[6],g[6],x[6],y[6]);
hf12 h8(p[7],g[7],x[7],y[7]);
*/CARRY GENERATION STAGE*/
gc12 g1(c[0],p[0],cin,g[0]);
bc12 b1(w[1],w[2],p[0],p[1],g[0],g[1]);
gc12 g2(c[1],w[1],c[0],w[2]);
bc12 b2(w[3],w[4],p[1],p[2],g[1],g[2]);
gc12 g3(c[2],w[3],c[0],w[4]);
bc12 b3(w[5],w[6],p[2],p[3],g[2],g[3]);
bc12 b4(w[7],w[8],w[1],w[5],w[4],w[6]);
gc12 g4(c[3],w[7],cin,w[8]);
bc12 b5(w[9],w[10],p[3],p[4],g[3],g[4]);
9
bc12 b6(w[11],w[12],w[3],w[9],w[4],w[10]);
gc12 g5(c[4],w[11],c[0],w[12]);
bc12 b7(w[13],w[14],p[4],p[5],g[4],g[5]);
bc12 b8(w[15],w[16],w[5],w[13],w[3],w[14]);
gc12 g6(c[5],w[15],c[1],w[16]);
bc12 b9(w[17],w[18],p[5],p[6],g[5],g[6]);
bc12 b10(w[19],w[20],w[9],w[17],w[10],w[18]);
gc12 g7(c[6],w[19],c[2],w[20]);
bc12 b11(w[21],w[22],p[6],p[7],g[6],g[7]);
bc12 b12(w[23],w[24],w[13],w[21],w[14],w[22]);
bc12 b13(w[25],w[26],w[6],w[23],w[10],w[24]);
gc12 g8(c[7],w[25],cin,w[26]);
*/POST-PROCESSING STAGE*/
assign s[0]=p[0]^cin;
assign s[1]=p[1]^c[0];
assign s[2]=p[2]^c[1];
assign s[3]=p[3]^c[2];
assign s[4]=p[4]^c[3];
assign s[5]=p[5]^c[4];
assign s[6]=p[6]^c[5];
assign s[7]=p[7]^c[6];
assign cout=c[7];
endmodule

Test bench:
module kstb;
reg [7:0]x,y;
reg cin;
10
 wire [7:0]s,c,p,g;
wire cout;
/*wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10;*/
ks8 a1(s,c,cout,p,g,x,y,cin);
initial
begin
x=11001100;y=11110000;cin=1;
#10 x=00111100;y=00110001;cin=0;
#10 x=00101010;y=10100101;cin=1;
#10 x=00111010;y=10001010;cin=0;
#10 x=10101010;y=00011100;cin=1;
#10 x=00001111;y=10111000;cin=1;
#100 $finish;
end
initial

$monitor("time=%t,x=%b,y=%b,cin=%b,p=%b,g=%b,cout=%b,s=%b,c=%b",$
time,x,y,cin,p,g,cout,s,c);
endmodule

4.2. 8-bit Ladner fischer adder:

module lf8(s,c,cout,p,g,x,y,cin);
input [7:0]x,y;
input cin;
output cout;
11
 wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10;
output [7:0]s,c,p,g;
*/PRE-PROCESSING STAGE*/
hf12 h1(p[0],g[0],x[0],y[0]);
hf12 h2(p[1],g[1],x[1],y[1]);
hf12 h3(p[2],g[2],x[2],y[2]);
hf12 h4(p[3],g[3],x[3],y[3]);
hf12 h5(p[4],g[4],x[4],y[4]);
hf12 h6(p[5],g[5],x[5],y[5]);
hf12 h7(p[6],g[6],x[6],y[6]);
hf12 h8(p[7],g[7],x[7],y[7]);
*/CARRY GENERATION STAGE*/
gc12 g0(c[0],p[0],cin,g[0]);
gc12 g1(c[1],p[1],c[0],g[1]);
gc12 g2(c[2],p[2],c[1],g[2]);
bc12 b1(x1,x2,p[2],p[3],g[2],g[3]);
gc12 g3(c[3],x1,c[1],x2);
gc12 g4(c[4],p[4],c[3],g[4]);
bc12 b2(x3,x4,p[4],p[5],g[4],g[5]);
gc12 g5(c[5],x[3],c[3],x4);
bc12 b3(x5,x6,x3,p[6],x4,g[6]);
gc12 g6(c[6],x5,c[3],x6);
bc12 b4(x7,x8,p[6],p[7],g[6],g[7]);
bc12 b5(x9,x10,x4,x7,x4,x8);
gc12 g7(c[7],x9,c[3],x10);
*POST-PROCESSING STAGE*/
assign s[0]=p[0]^cin;
assign s[1]=p[1]^c[0];
12
assign s[2]=p[2]^c[1];
assign s[3]=p[3]^c[2];
assign s[4]=p[4]^c[3];
assign s[5]=p[5]^c[4];
assign s[6]=p[6]^c[5];
assign s[7]=p[7]^c[6];
assign cout=c[7];
endmodule

Test bench:
module lftb;
reg [7:0]x,y;
reg cin;
wire [7:0]s,c,p,g;
wire cout;
/*wire x1,x2,x3,x4,x5,x6,x7,x8,x9,x10;*/
lf8 a1(s,c,cout,p,g,x,y,cin);
initial
begin
x=11001100;y=11110000;cin=1;
#10 x=00111100;y=00110001;cin=0;
#10 x=00101010;y=10100101;cin=1;
#10 x=00111010;y=10001010;cin=0;
#10 x=10101010;y=00011100;cin=1;
#10 x=00001111;y=10111000;cin=1;
#100 $finish;
End
13
 initial

$monitor("time=%t,x=%b,y=%b,cin=%b,p=%b,g=%b,cout=%b,s=%b,c=
%b",$time,x,y,cin,p,g,cout,s,c);
endmodule

5.SIMULATION RESULTS
5.1.Kogge stone adder:

14
 5.2.Ladner fischer adder:

5.3 Comparison:
PARAMETERS KOGGE-STONE LADNER FISCHER
1.AREA Large Small
2. NO.OF CELLS More Less
3.DELAY High Low
4.FAN-OUT 2 N/2
5.WIRING More Less
COMPLEXITY
 6.ADVANTAGES
1. The main advantage of the design is that the carry tree reduces the number
of logic levels (N) by essentially generating the carries in parallel.
2. The parallel-prefix tree adders are more favourable in terms of speed due to
the complexity O(log2N) delay through the carry path compared to that of
other adders.
3. The Parallel Prefix Adder (PPA) is one of the fastest types of adder that had
been created and developed.

7.DISADVANTAGES
1. The drawback with the Kogge- Stone adder implementation is the large
area consumed and the more complex routing (Fan-Out) of interconnects.

8.APPLICATIONS
1. High speed implementation of parallel prefix adders for low power
VLSI applications.
2. Offers improved performance in terms of speed and power over DSP-
based and microprocessor-based solutions for many practical designs
involving mobile DSP and telecommunications applications and a
significant reduction in development time and cost over Application
Specific Integrated Circuit (ASIC) designs.

16
 9.CONCLUSION

In this paper, a new approach to design parallel prefix adders such as efficient
ladner fischer adder and kogge stone adder concentrate on gate levels to
improve the speed and decreases the memory.These are like tree structures and
cells in the carry generation stage are decreased to speed up the binary addition.
The proposed adders addition operation offers great advantage in reducing
delay.
 17

10.REFERENCES
[1] R. Ladner and M. Fischer,”Parallel prefix computation”,Journal of ACM.
La. Jolla CA, Vol.27, pp.831-838,October 1980.

[2] Kogge P and Stone H, “A Parallel Algorithm for the Efficient Solutions of a
General Class of Recurrence Relations”, IEEE Transactions on Computers, Vol.
C-22, No.8, 1973.

[3] S. Knowles,” A family of adders,”proc.15thsymp. Comp. Arith, pp. 277-

281, June 2001.

[4] Pakkiraiah. Chakali, madhu Kumar. Patnala “Design of high speed Ladner -
Fischer based carry select adder” IJSCE march 2013.

[5] Y. Choi, “Parallel Prefix Adder Design,” Proc. 17th IEEE Symposium on
Computer Arithmetic, pp 90-98, 27th June 2005.
18