S MOTOROLA SEMICONDUCTORS Pee eo ROM mR MC6809 8-BIT MICROPROCESSING UNIT The MC5809 is a revolutionary high-performance -bit microprocessor \which supports moder programming techniques such as position indepen- dence, reentrancy, and modular programming “This thid-generation addition to the M6800 Family has major architectural improvements which include additional registers, instructions, and addressing modes. The basic instructions of any computer are greatly enhanced by the presence of powerful addressing modes. The MCG808 has the mast complete Set of addressing modes available on any B-bit microprocessor today. “The MCBE0B has hardware and software features which make it an ideal processor for higher level language execution or standard controller applica M6800 COMPATIBLE © Herdware — Interfaces with All M6800 Peripherals © Software — Upward Source Code Compatible Instruction Set and Addressing Modes ARCHITECTURAL FEATURES © Two 16-Bit Index Registers © Two 16:Bit Indexable Stack Pointers © Two &Bit Accumulators can be Concatenated to Form One 16-Bit Accumulator © Direct Page Register Allows Direct Addressing Throughout Memory HARDWARE FEATURES © On-Chip Oscillator (Crystal Froquency=4% E) (© OMATEREG Allows OMA Operation on Memory Refresh © Fast Interrupt Request Input Stacks Only Condition Code Register ‘and Program Counter © MADY Input Extends Date Access Times for Use with Slow HMOS (HIGH DENSITY N-CHANNEL, SILICON-GATE) esiT MICROPROCESSING UNIT L SUFFIX Ye sureix s SUFFIX CASE TS PIN ASSIGNMENT Memory vss]i @ so pract Interrupt Acknowledge Output Allows Vectoring by Devices amd me fXTAL inc Acknowledge Output Allows far Synchronization to External Sine Acknowiedae Output Allows or Syetronation i aad hea Single Bus-Cyole RESET ROY 7 PRESET © Single 5-Volt Supply Operation shMroY {Ri ntited Att RESET Unt After Fist Load of Stack Pointer ss | © Early Address Valid Allows Use with Slower Memories Bays ssa © Early Write Data for Dynamic Memories veel? othe SOFTWARE FEATURES ao lee ‘© 10 Addressing Modes aide sehr ‘6800 Upward Compatible Addressing Modes netho 31 foo ‘© Direct Addressing Anywhere in Memory Map S he Long Relative Branches ‘© Program Counter Relative sage ze fto2 ‘© True Indirect Addressing ass 2afios ‘© Expanded Indexed Addressing: . ‘ 0, 5, &, of 16-it Constant Offsets nef a7 fos 8 ‘or I-Bit Accumulator Offsets arths zs fos ‘Auto Inccement/ Decrement by 1 or 2 peak os foe © Improved Stack Manipulation (© 1464 Instructions with Unique Addressing Modes ao? 24107 © 8 x 8 Unsigned Multiply avol}is 2s pais © 16.81 Arithmetic anti zpau © Transfer/Exchange All Registers . ‘© Push/Pull Any Registers or Any Set of Registers aretfz0 2ipars © Load Effective Address ENOTOROIA RE, TeerMAXIMUM RATINGS Taig Smibol | Vaue [Unt Supp Votooe Eee eosteT=70// av is device conta. cxcutry to protect the z inputs ogarst damage sue to hgh state Input Voge Vin [=030 70 V Yolages or secre els nowever, ad Dperaing Temperature Range Tet wed that oral preceutons be taken to ‘ceo, MCSEA09, MICEEBOD ta | ator7 | oc voi application af any watoge higher than icesnoc, MCBBADEC, MoaaB0aC =O +85 imanimum vated votages to this hgh Storage Terpereture Range Tay | 0 +10 | betes creat elit of ep ‘THERMAL CHARACTERISTICS Proptate loge valle levels (eg, ether ‘Chasetriie Sriba[Vaue [une] “Sr Voc! Thermal Reasionce Ceramic ol Codie fun a. Paste 100 POWER CONSIDERATIONS ‘The average chip-unction temperature, Ty, in °C can be obtained from Ty=TA+ (POA) o Where Tas Ambient Temperature, °C 04 Package Thermal Resistance, Junction-to-Ambient, °C/W Pp=Pint+PPoRT PINT=ICC VCC, Watts — Chip Internal Power PponT=Port Power Dissipation, Watts ~ User Determined Fox most applications PPORT-«PINT and can be neglected. PPORT may become significant if the device is configured to ‘rive Darlington bases ar sink LED loads ‘An approximate relationship between PD and Ty {if PpoRT is neal Pp=K~(Ty+273°) 21 Solving equations 1 and 2 for K gives: K=PpeiTa +273°C)+ 8jae? 2 a Where K is a constant pertaining to the paiticular part. K can be determined from equation 3 by measuring Pp (at equilibrium) fora known T,., Using this value of K the values of PED and T,j can be obtained by solving equations I1! and (2) iteratively for any value of TA. ELECTRICAL CHARACTERISTICS (Vcc=50\V #54. Vg5#0, Ta Tt Th us thon noted Chace Simbol] — Min —[ Typ [war | Un ae Toxe TAC] Vin | Vage20] — | vec] ar Han Vota meset| vam | vegra0| — | vee Tnput Low Vonage ‘Logic, EXTAL, RESET Vu | Vss-03 | = | Vss+08 7 V Tap Laage Care t 5 Win =0 to 5.25 V, Vor — fin . _ cc ” % Ouiat Fgh Votane MLoad = — 206 wA, Voc = min) 0-07 Vsst+24] — oF eee esha vecmmnl sone nmar| You! ystegfo] 2 |v tees Tt ka vegas Bags vgse24| | % Output Low Vlogs = Thesosl v seye20m oem ot | ss Tha Por Dipaon IMeosued a TAOS Say Ss Opa ear == | ew Capture" | Nine Ta=25°C 2106 woonmeser| Gn | - | wl os | oF Logic Inputs, EXTAL, XTAL = 10 ud AOA8, A, ba, 88 [Ca | [= [ea [ Fegsey of Operon WO ae (Ghote np woreame | xr. ot |_| 6 [ane = cso | oe es FEZ (OW Siaiel input Carent Door} oie eae (Vin=04 to 2.4 V, Voe= maxi AO-AIS, B/W Tet - - 100 = * Cepactances are periodically test ra 1 han 100% tested ___§_ ® MOTOROLA Semiconductor Products Inc. ————!FIGURE 1 US TIMING RA, Ades, T BABS 4 | Ko feos Oota MPU Read Osta © Nowe 3 a | k—®@ BUS TIMING CHARACTERISTICS (Sse Notes 1 and 2) "dent. Mics MCeBATE | MOBSEDS Number eee Symbol Fis [MOE | Min [Mio [ Min Wox | U% 1_| Gyaie Time Soo Nove ‘e_[ 10 | 10 [oss] wo [os | 0 [a Z| Falke Wid, ELow Five «30 | Sooo] af wT] 70 | BOOT [ as [Poe wi, € Ta Piven [aa [ison] 260 [roo] 220_[T7G0 [ns @ | Glock Rise and Fal Tne -« [-[ =| - [| -|[™ [os S| Pasa Ws, OF Pion |e [SoM] 80 [SOOO] FO | SOOO ns | Paes Wises, Low PWvqx_| #60 |i6600| 260 [15700] 220 [ero | ns 7 [ Daly Tims, Ero 0 Fice Tavs [200 | 250 | 1a] 165 | 8 | 1% | as [Adare oid Tima” S00 Now an | [= Pet = [ey fos To A, 8S, RI, and Recess Vand Tie 100 Fie mow Pps p= pet fe 17] Reed Gata Soup Tene wosa | — |||] — [as 18 | ead Osta Hold Teme [iowa D0 = [of — [0 = [Bata Dany Tina from [poe Fo 2 | Winte Oata Hol Time Toom [== po p- [ep [os | Ussbie cess Time (See Nove oT ‘ace [oe] = [ew] = [oT — | as roseasor Cone! Setup Tine IMADY,_lnterupts, OMATBREG, ACT, RESET) (Figures 68,9, 10, 2, and 1 tees | 20 | - | wo] | mo} = | oe iytalOsilator Start Te (gues 6 and 7) TAC To] = [eo] — fio [we Processor ContlFise and Fal Time (Figures 6 and 6 we. ery = | HOT — POT | 108 | as Notes: sabe * Adress and data hold ties are perodialy tested rather than 1008 tested, Moximum teye ducing MADY or DMTA/BREG is 16 ps Voltage levels shown are Vi<0.4 V, Vii22.8 V, unless otherwise spectiod Measurement points own a 08 V and 2.0 V, unis otherwise specified ® MOTOROLA Semiconductor Products Inc. 3Iles) FIGURE 2 — MC5800 EXPANDED BLOCK DIAGRAM ooo Avats : : <—Vee ss 16 3 KJ ec >| Inston Tenis fe v Le» - s ke ae -™ 7 Le» : Trerapt. FRG Convol_ fe —ina Kj x K+ ¥ = DWATERED +——of ieee nm k>| ¥ aus ART or | co fel | conto! [58a t Tes aL vt ext aw feo Ting [e—ssnov . C_y« eral Tre Sate Cont larg FIGURE 3 — BUS TIMING TEST LOAD nawo5i50 of Eauv. amo7000 or Eauv. F = 11,7 k@ for 00.07 185 KO for AD-ANS, €, 0, R/W A for 8, BS 30 pF for 8A, BS 130 pF for 00.07, E 0 pF for AO-AIB, A a iW 4 PROGRAMMING MODEL {As shown in Figure 4, the MCE809 adds three registers to the set availabe in the MICB8O0. The added registers include a direct page register, the user stack pointer, and a second index register. ACCUMULATORS (A, B, D) The A and 8 registers are general purpose accumulators which are used far arithmetic calculations and manipulation of data, Certain instructions concatenate the A and 8 registers to form a single W:bit accumulator. Ths is referred to as the D register, andisformad with the A register as the most signi cant byte. DIRECT PAGE REGISTER (DP) The direct page register of the MC8809 serves ta enhance the direct addressing made. The content of this register ap pears at the higher address outputs (A8-AA15) during dec ‘addressing instruction execution. This allows the direct ‘made to be used at any place in memory, under program Control, To ensure M6800 compatibily, all bits of this register are cleared during processor reset | | | MOTOROLA Semiconductor Products Inc. —___]16 FIGURE 4 — PROGRAMMING MODEL OF THE MICROPROCESSING UNIT X= index Rogier ¥ = Index Register U = User Stack Pointe Pointer Registers Hardware Stack Pointer Program Counter Accumulators oP Direct Page Register Pc ——————— ° 1 r aan CC ~ Consition Code Register INDEX REGISTERS (x, Y) The index registers are used in indexed mode of address: ing. The 16-bit address in this register takes part in the calculation of effective addresses. This address may be used to point to data directly or may be modified by an optional Constant or register offset. During some indexed modes, the Contents of the index register are incremented or decrement fed to point to the next item of tabular type data. All four pointer registers (X, Y, U, S} may be used as index registers. ‘STACK POINTER (U,S) The hardware stack pointer |S) is used automatically by the processor during subroutine calls and interrupts. The stack pointers of the M8809 point to the top of the stack, in Contrast to the MC8800 stack pointer, which pointed to the next free location on the stack. The user stack pointer (UI is Controlled exclusively by the programmer. This allows {arguments to be passed to and from subroutines with ease. Both stack pointers have the same indexed mode addressing capabilities as the X and Y registers, but also support Push {and Pull instructions. Ths allows the MC6809 to be used effi ciently as a stack processor, greatly enhancing its ability to Support higher level languages and modular programming. PROGRAM COUNTER The program counter is used by the processor to point to the address of the next instruction to be executed by the pro- ‘cessor. Relative addressing is provided allowing the program ‘counter to be used like an index register in some situations. CONDITION CODE REGISTER The condition code register defines the state of the pro- ‘cessor at any given time. See Figure 5 5 FIGURE 5 ~ CONDITION CODE REGISTER FORMAT ele[e) [sfzpvye TC cary Overtiow Zero Negative IRQ Mask Half Cary FIR Mask Entre Fog CONDITION CODE REGISTER DESCRIPTION BIT oc) Bit O is the carry flag, and is usually the carry from the binary ALU. C is also Used to represent a ‘borrow’ from subtract-lke instructions (CMP, NEG, SUB, S&C) and isthe ‘complement of the carry from the binary ALU. air (vy Bit 1is the overflow flag, and is set to a one by an opera tion which causes a signed twos complement arithmetic ‘overtiow. This overflow is detected in an operation in which the carry trom the MSB in the ALU does not match the cary from the MSB-1 Bir 22 Bit2 isthe zero flag, and is set to a oneif the result ofthe previous operation was identically zero, &® MOTOROLA Semiconductor Products Inc.BIT 3(N) Bit 3is the negative flag, which contains exacty the value of the MSB of the result of the preceding operation. Thus, 2 Negative twos-complement result wil leave N set to 2 one. Biraa Bit is the INO mask bit. The processor will not recognize interrupts tom the IRC line if this bit is set to @ one. NMI FIRG, TRO, RESET, and SWI all sot | to a one. SWI2 and ‘SWIS do not affect I BIT 5 (H) Bit 6 is the half-carty bit, and is used to indicate 2 carry from bit 3 in the ALU as a result of an &-bit addition only (ADC of ADD). This bit is used by the DAA instruction to perform @ BCD decimal add adjust operation. The state of this flag is undefined in all subtract-ika instructions BIT 6(F) Bit 6 is the FIG mask bit. The processor will not recognize interrupts from the FIR line if this bit is @ one, NM, FIRD, Swi, and RESET all set F to @ one, 170, SWI2, and SWI do not attect F BIT 7(€) Bit 7 isthe entre flag, end when sot toa one indicates that the complete machine state (al the registers) was stacked as opposed to the subset state |PC and CC). The E bit of the stacked CC is used on a return from interrupt (RTI) to deter mine the extent of the unstacking. Therefore, the current E left in the condition code register represents past action, PIN DESCRIPTIONS POWER (Vss, Vcc} Two pins are used to supply power to the part: Vs is ‘ground or O volts, while Vee is +5.0 V +556 ‘ADDRESS BUS (A0-A15) Sixteen pins are used to output address information from the MPU onto the address bus. When the processor does ot require the bus fora dats transfer, it wil output address FFFF 1g, R/W = 1, and BS = 0; this isa "dummy access” or VW cycle. Addresses are valid on the rising edge of Q. All address bus drivers are made high impedance when output bus available (BA) is high. Each pin will dive one Schottky ‘TTL load oF four LSTTL loads, and 90 pF DATA BUS (D0-D7) “These eight pins provide communi bidirectional data bus. Each pin will = load or four LSTTL loads, and 130 pF ion sith the system 2 Schottky TTL 6 READ/WAITE (R/W) This signal indicates the direction of data transfer on the dota bus. A low indicates that the MPU is writing data onto the data bus. R/WW is made high impedance when BA is high. R/T is valid on the rising edge of Q. RESET A low level on this Schmit-trigger input for greater than ‘one bus cycle will reset the MPU, 2s shown in Figure 6. The reset vectors are fetched from locations FFFE(g and FFFF 5 {Table 1) when interrupt acknowiedge is true, (BA®BS = 1 During intial power on, the RESET line should be held low ntl the clock oscilator is fully operational. See Figure 7. Because the MC6809 RESET pin has a Schmitt-nager in put with a threshold voltage higher than that of standard Doripheras, a simple R/C network may be used (0 reset the entire system. This higher threshold voltage ensures that all peripherals are out of the reset state before the processor ALT ‘low level on this input pin will cause the MPU to stop running at the end of the present instruction and remain halted indefinitely without loss of data. When halted, the 8A, ‘output is driven high indicating the buses are high im- pedance. 8S is also high which indicates the processor isin the halt or bus grant state, While halted, the MPU will not respond to external real-time requests (FINO, TRO) although OWA) BREG wil always be accepted, and NM or RESET wall, be latched for later response. Ouring the halt state, Q and E ‘continue torun normaly. If the MPU is nat running (RESET. (DMA/BREO), a halted state(BAeBS-= 1) can be achieved by pulling HALT low while FESET is stil low. If DMA/BREQ ‘and HALT are bath pulled low, the processor will reach the last cycle ofthe instruction Iby reverse cycle stealing) where the machine will the become halted. See Figure 8 BUS AVAILABLE, BUS STATUS (BA, BS) The bus aveilable output is an indication of an internal ‘control signal which mskes the MOS buses of the MPU high impedance. This signal does nat imply that the bus will be ‘available for more than one cycle. When BA goes low, 3 t ce NewPC+1 Now PCs 1 ona : Senos 7 FRE FFE FARE FFE FFE FFF FFF’ Nowe FFP FFF Now PC nw Tew FC ex Naw PC ae HiByte TRA xe HiBye VaR 7 Tat Naw PC Fst Ba = fe _tnstuction 4, Lo Byte _tnsiretion Bs NOTES: 1. Parts with date codes prefixed by 7F or BA wil ome out of RESET one cycle sooner than shown, 2. Timing measurements are reerenced to and from a iow voltage of ©.8 vols and a high vollage of 2.0 volts, unas otherwise noted, 53. FEFE appears on the bus during RESET low time. Following the active transition ofthe AESET ine, three more FFFE cycles wil ppea followed by the vector fetchFIGURE 7 — CRYSTAL CONNECTIONS AND OSCILLATOR START UP —_|—__x. Ti = b<—"tac. form measurements fr al inputs and outputs are speciied at logic high 2.0 V and logic low 0.8 V unless otherwise specified. cesoe TLS =] » emne | 18 oF {Tk em | 200F | 205F ft | Nominal Cystal Parameters = ‘3eoMiiz | 800MM: | 60MH2 | 8OMHE as 00 sa aa | 2400 oo 35 pF 65 pF 46 9F opr cr corer | aaasar | ooroczer | oorocz er a >aOk >2k 220k Al paranaiow a0 1% | NOTE: These are representatve AT-out cvs types of cut may als be used iv. Crytas of ot Typical PC Board Layout Fama HM ay I ela 20 me mae. wD A other Signa | Not We In 2 2 @) MOTOROLA Semiconductor Products Inc.FIGURE 8 ~ HALT AND SINGLE INSTRUCTION EXECUTION FOR SYSTEM DEBUG 2nd To Last Last Gyele cycie of OF Dead Inst Instruction Osea eo im Pe ae fn eng Se aes ee ela else leis 7) a | | leres ISllebec ct recs Current Cuetant Dead Hatt e ATT ee an ee) End Fach aaa eee | ae Instruction Spcote NOTE: Waveform meosurmen fora inputs and ouput a sce at gic high 20 Vand logic lw O18 ures otis spect INTERRUPT ACKNOWLEDGE is indicated during both interrupt cannot be inhibited by the program, and also has a ‘yes of a hardivare-voctor fetch (RESET, NWI, FIR. IFC, SWI, SWI2, SWIG). This signal, plus decoding of the lower ‘our address lines, can provide the user with an indication of which interupt levels being serviced and allow vectoring by device. See Table 1 SYNC ACKNOWLEDGE is indicated while the MPU is waiting for extemal synchronization on an intertupt line HALT/BUS GRANT is true when the MBGOS is in a halt or bus grant condition TABLE 1 —~ MEMORY MAP FOR INTERRUPT VECTORS ‘Memory Nap For Vector Locations Interupt Vector Descroton Ms. 1s FFE FF ESET FFF FFD wi FFA Fra Swi Fre Fer mm Fre FET FRG Fra 5 swe frre era sw fro ff Reserved NON MASKABLE INTERRUPT (NIAI)* ‘A negative transition on this input requests that @ non ‘maskable interrupt sequence be generated. A non-maskable higher priority than FIEG, TRO, or software interrupts, Dur- ing recognition of an Ni, the entire machine state is saved (on the hardware stack. After reset, an Nfl will not be recog. rized until the fist program load of the hardware stack pointer (S). The pulse width of NTI low must be at least one Ecycte, if the NMI input does not meet the minimum set up with respect to Q, the interrupt will nt be recognized until the next cycle. See Figure 9 FAST-INTERRUPT REQUEST (FIRG)* ‘A low level on this input pin wil initiate a fast interrupt se quence, provided its mask bit (F) in the CC is clear. This se ‘quence’ has priority over the standard interrupt request {NFO}, and is fast in the sense that it stacks only the contents of the condition code register and the program counter. The interrupt service outine should clear the source of the inter rupt before doing an AT. See Figuee 10. INTERRUPT REQUEST (iFG)* A low level input on this pin wil initiate an interrupt 1 ‘quest sequence provided the mask bit (I) in the CC is clear. Since IRC stacks the entire machine state it provides @ slower response to interrupts than FIRO. IFO also has a lower priority than FIRQ. Again, the interrupt service routine should clear the source ofthe interrupt before doing an RT! Soe Figure 9 “Wf FIRG, and TRO requests are sarmped on the fang edge of Q. One cycle is required fr synchroniztion before these interupts ae ec "ized, The pending interrupts will not be service unt competion ofthe current insirtion unis a SYNC or CWAI conditions resent {and FIR do not remain low unt completion ofthe curent instruction they mey not be recognized. However, NBT i latched and need one main Jew for one cyee. No interrupts are recognized or latched betwoon the fang edge of RESET and the rising edge of 8S indicating RESET scknowosge ® MOTOROLA Semiconductor Products Inc. a—__——. 9 syonpoig J0}onpuodWes YWTOHOLOW FIGURE 9 ~ IRGAND Ni INTERRUPT TIMING Last evele restueton — Leese ee ee eee le el ee ee ee eee ie eS Ls Ul el ee ee lee ele eae eee, ae eXent) ea (ema aK ame ICI x i| | “no X fe ee des oe ee epee ne pte ye ey I ru PL XX —_ mm = en ae een (ees) Yess NOTE: Waveform measurements for al inputs and outputs © spaced at logic high=2.0 V and logic low = 0.8 V ules otherwise specifies E clock shown for relerence only eelXTAL, EXTAL registess onto the stack and then awaits an intereupt “These inputs are used to connect the on-chip oscillator to During this waiting period, itis possible to place the an external parale-resonant crystal. Alternately, the pin MPU into a halt mode to three-state the machine, but level input for external timing MRDY wil not stretch the clocks. EXTAL may be used as a T The mask set for @ particular part may be determined by by grounding XTAL. The erystal or external frequency is four times the bus frequency. See Figure 7. Proper RF layout ‘examining the markings on top of the part. Below the part techniques should be observed in the layout of printed circuit ‘umber is string of characters. The frst two characters are boards the lest two characters ofthe mask set code. If there are only | four cigits the partis the G7F mask set. The last four dais, Ba the date code, show when the part was manutactured These four digits represent yoar and week. For example a is similar to the MC6800 bus timing signa phase 2; Qs @ Si heageaere prc ely py eedat ps ceramic part marked! quadrature clock signal which leads €, Q has no parallel on the MC5800. Addresses from the MPU will be valid with the leading edge of Q. Data is latched on the faling edge of E Timing for E and Q is shown in Figure 11 roy" This input control signa slows stretching of E and Q to extend dataaccess time. E and © operat normally while @ TBA mask sot made tho twalfth week of 1960. MADY ishigh, When MRDY istow, End O may be stretch. ed in integral multiples of quarter (%41 bus cycles, thus allow- DMATBREG ing interface to slow memaris, 25 shown in Figur TZ The DITATERED input provides a method of suspending During non-vald memory access (VAIA cycles, MRDY hes _—_exaoution and acquiring the MPU bus ler another use, 28 no effect on stretching E nd O, this inhibits slowing the pre Shown in Figure 12. Typical uses indude DMA ond dimomic cessor during don't car bus accesses MRDY may aso be retary retesh Used 10 stretch clocks (or sow memory when bus contol ‘low level on this pin wistop instruction execution atthe has buen Wansfered to an external deve though the use end ofthe current cycle unless preempted by sel-etesh, of RALT and DHPA7EREO) The MPU wil ecknowiedge DMATBREG by setting BA ond Note BS 10.2 one. The raquesting devi wll now have to 15 Four ofthe esty production mask sets (G7. TSA, bus oyeles before the MPU rotiovs tho bus fr sa-ettesh PF, TEM) require synetronzaton of the MRDY input Set otresh requires one bus cycle with aeading and taiing with thea lock. Te synchronization necessitates an dead cycle Seo Figure 14. The set retesh counter is only exteral oscllotor a6 shown in figure 12{b) The Cieored if BHTATBREG is inacive for two or more MPU regatve tanston of the MADY signal, normaly evel. dened tom the chip select decoding, must meet the Typical, the DMA controller wil request to use the bus tPCS timing. With these four mask sets, MRDY's by asserting DMA7BREO pin low on the leading edge of E. | Dose transiton mst occur with the rising edge of \Whon the MPU reps by setting BA and BS toa ore that i cele wil bea dead cyte used fo transfor bus mastrship to In ation, on thess seme mask sets, MRDY wil the DMA controler not stitch the € and © signals it the machine i & Falee memory accesses may be prevented during any de teuting ier 8 TER or EXG Instruction during the cyces by developing 2 system ONAVIE signal wivch is FIRCT high-low trantion. i the MPU executes 8 LOW in any oye when BA has changed WAI instruction, the machine pushes the internal FIGURE 11 — £/0 RELATIONSHIP Stat of Cyale End of Cycle (Latch Data i | I | . a be—tavs 4 | al (3 a | 1 ras Vad 1 NOTE: Wavelorm mossurements for al inputs and outputs are specie at logic high 2.0 V and loge low 0.8 V unless otherwise specifi ‘The om board clock generator furnishes E and. to both the system and the MPU, When MRD is pulled lw, both the system clocks andthe Internal MPU clocks ae stretched. Asserton of BWA/BRED input soos the internal MPU clocks wl allaning the external system cocks to RUN (2, eleaso the bus toa DMA controler. The internal MPU clocks resume operation ster OMA, BRE® i leased or after 16 bus cyces I'4 DMA, two dead!, whichever ccours fist, While DMA/BREG i asserted it is sometimes necessary to pal MAOY low to alow OMA to/from slow memory/peripherais. As both MADY and DHA/BREG sonra the internal MPU close, care must be exetcoed not to wolate | the maximum teyesoectcaton tor MRDY or DHA BREG, (Maximum tye Gurng MAD or DHA, BREG is 18 ps) | | ® MOTOROLA Semiconductor Products Inc, ——————_ 2When BA goes low {either as a result of OMATBRES HIGH of MPU sel-rettesh, the OMA device should be taken off the bus. Another dead cycle will elapse before the MPU: ‘accesses memory to allow transfer of bus. mastership without contention. MPU OPERATION This sequence begins after FESET and is repeated indetinite- Iy unless altered by a special instruction or hardware occur rence. Software instructions that alter normal MPU opera tion are: SWI, SWI2, SWI3, CWAl, RTI, and SYNC. An in terupt, ALT, or DHA7EREG can also alter the normal ex ‘cation of instructions. Figure 15 illustrates the flowchart for the M809, During normal operation, the MPU fetches an instruction from memory and then executes the requested function. FIGURE 12 ~ MRDY TIMING AND SYNCHRONIZATION (0) Synchronization “0 Mie Osciator ] 760504 RATES | cm | extat |e ar of [ a et cur MICEEID ypoy|a5_MADY Sweten o roy | 3 |srconetin 778 ob Active Low Chip Select {or Slow Momory Values 4 Pome fp ea rarer | L (as Rent saan LARS tal | q MADY Sten suwuieh = 07 Ac To Memory ® MOTOROLA Semiconductor Products Inc.FIGURE 13 — TYPICAL DMA TIMING (<14 CYCLES) s4eu—she— pose oma — “few : \L r ! WATERED f 14 CYCLES) (REVERSE CYCLE STEALING) | " DRTAVHTA ica signa which is developed externalv, but is 2 system reautement for DMA, Reler to Apel NOTE: Waveform mes rements fo all inputs and outputs ave specified at ogi high 2.0'V and logic low 08 V unless otherwise specified MOTOROLA Semiconductor Products Inc. —___|FIGURE 15 — FLOWCHART FOR MCB80S INSTRUCTIONS ()) MOTOROLA Semiconductor Products Inc.‘The basic instructions of any computer are greatly enhanc fd by the presence of powerful addressing modes. The M06809 has the most complete set of addressing modes avaiable on any microcomputer today. For example, the M6809 has 69 basic instructions; however, it recognizes 1464 differant variations of instructions and addressing modes. The addressing modes support modern program’ ming techniques. The following addressing modes ere avail ‘able on the MC5808, Inhorent (includes accumulator Immediate Extended Extended Indi | Direct Register Indexes Ze10-Ofset Constant Offset Accumulator Offset ‘Auto Increment/ Decrement Indexed Indirect Relative ‘Short/Long Relative Branching Program Counter Relative Addressing INHERENT (INCLUDES ACCUMULATOR) In this addressing mode, the opcode of the instruction Contains all the adcress information necessary. Examples of inherent addressing are: ABX, DAA, SWI, ASRA, and cLRe, IMMEDIATE ADDRESSING In immediate addressing, the effective address of the data is the location immediately following the opcode lie, the data to be used in the instruction immeciataly following the ‘opcode of the instruction). The MCB8D9 uses both 8- and 16-bit immediate values depending an the size of argument specified by the opcode, Examplas of instructions with im mediate addressing are: LDA #820 LOX #3F000 Loy #caT NOTE # signifies. Immediate addressing; $ signifias hexa: decimal value. EXTENDED ADDRESSING In extended addressing, the contents ofthe two bytes im mediatoly folowing the opcode fully specify the 16-bit effec tive address used by the instruction. Note that the adaress {generated by an extended instruction defines an absolute address and is not position independent. Examples of ex tended addressing include: LDA CAT STx MOUSE LoD $2000 —_—_——— (Sy MOTOROLA Semiconductor Products Inc. 6 ADDRESSING MODES EXTENDED INDIRECT — As in the special case of indexed addressing (discussed below), one level af indirection may be added to extended addressing, In extended indirect, the two bytes following the postoyte of an indexed instruction Contain the address of the data, LOA {cat} LOX (SFFFE] STU (00G) DIRECT ADDRESSING Direct addressing is similar to extended addressing except that only one byte of address follows the opcode. This byte specifies the lower eight bits of the address to be used. The Upper eight bits of the address are supplied by the direct page register. Since only one byte of address is required in direct addressing, this mode requires less _memory and ‘executes faster than extended addressing. Of course, only 256 locations (one page) can be accessed without redefining the contents of the DP register. Since the DP register is sot 0 900 on reset, direct addressing on the MCBBOY is compat ble with direct addressing on the M6800, indirection is not allowed in ditect addressing. Some examples of ditact addressing are: LOA $90 SETOP $10 {assembler directive) Loe $1090 uoD << caT Nore < is an assembler directive which forces direct addressing. REGISTER ADDRESSING Some opcodes are followed by a byte that defines @ register or set of registers to be used by the instruction. This is called 2 postbyte. Some examples of register addressing TR X,Y “Transfers X into ¥ XG AB Exchanges A with B PSHS 4,8, X.Y Push, X, Band A onto S PULU X/¥,0 Pull, X, and ¥ from U INDEXED ADDRESSING In all indexed addressing, one of the pointer registers (x, Y, U, S, and sometimes PC) is used in calculation of the ef- fective address of the operand to be used by the instruction. Five basic types of indexing are avaiiabia and are discussed bboiow. The postbyte of an indexed instruction specifies the basic type and variation of the addressing mode as well 2s the pointer register to be used. Figure 16 lists the legal fr. ‘mats for the postbyte. Table 2 gives the assembler form and the number of cycles and bytes added to the basic values for indexed addressing for each variation,URE 6 — NODLED ADoRESsING FOSTEYTE ZEROLOFFSET INDEXED — In ths mode, the eloctd cise or SoS exer oper conare cea ets ole stato ee = Betend byte inoweton Taste fetes nceung med, TTS 8] 4] 3]2 [1] © Acree ee Mode. LoD OX atatatstsfelels| eons Savoie aa ttarepetetetete ae ed CONSTANT OFFSET INDEXED — nts mode tw0= et epetetetttet — a conpunent et snd te cones of oe oe poe trerettete te tet rags‘ todo To Terr tw tein bodes! the TPRE RL Lop TO] 1 [ea =A + ACC Offset by the addition TPR TRT POT TPo ps eka Acca ta] of fet ae avaible trata, s[ 1] oo] 0] cA= A +8 Bit Offset ea TPA] Ali | | 0] 0] 1 | EA=_R +16 Bit Offset oF tebe e Pop a= ao ie The rs complanet 5 oats nue nthe post TAT AP ETT TOPOS SEROTT] fan tee om font nano es Tee fol eke re ca Of" The tee conplomen Bt aloe conta ha Sige bye (towne posto Tha wor conparont ie elt ate wo te ton te posto Actening Mode Fld ost cae tho prograer nee not be concerned with the ou Sevcttns ole se he sar wi ee apa ripiere | | ee Sapte of esata indoxing | Ton ax ava as w= Dot one x ty sox d= Offset Bit =U wou CAT. "ABLE? ~ NOEKED ADDRESSING MODE Ten was svo0 ras Tate | teaare| +) + Remar] roe | «|e an | Soo | *[3 | “em” | eee | 2: mart e Font | Wear SP amos [oft Tarn Se oie ae Tabi ote Co Tamra Oe Fan [Regs Sa ee cme tet earn | o (23 Complement Offsets) 'B Register Offset BR amor [1 [0 18, A) arrioi | 4fo. Sessa Oa Serato ea Lemon Doo Tas rawr Bosoran ® [sors BVT a oo | a] [or atoed | sea oe A inom af a | ama poe ea ee ed Sane BE TES pea | mT ae Toman Sin Fon Fe Lear ee arate erate La {28 Complement Offsets) 16-8it Offset, ooriot | 6 [2 | in, PCAL ioition_T ef2 Eater ce 7 a intel Tee ‘i ‘Land nate te umber of addins x end bytes fr he pare vrion MOTOROLA Semiconductor Products Inc. 7ACCUMULATOR.OFFSET INDEXED — This mode is similar to constant offset indexed except that the twos: complement value in one of the accumulators (A, B, oF D} and the contents of one of the pointer registars are added to form the effective address of the operand. The contents of both the accumulator and the pointer register are unchanged by the addition. The postbyte specifies which accumulator to use as an offset and no additional bytes are required. The advantage of an accumulator offset is that the value of the offset can be calculated by a program at run-time, Some examples aro: LOA BY lox DY LEAK 8x AUTO INCREMENT/DECREMENT INDEXED — In the auto increment addressing mode, the pointer register con: tains the address of the operand. Then, after the pointor register is used is incremented by one or two. This address ing mode is useful in stepping through tables, moving data ‘or for the creation of software stacks, In auto decrement, the pointer register is decremented prior to use asthe address of the data. The use of auto decrement is similar to that of auto increment; but the tables, etc, ae scanned from the high 0 low addresses. The size ofthe increment/ decrement can be either one or two to allow for tables of either 8 or 16-bit data to be accessed and is selectable by the programmer. The predecrement, post-increment nature of these modes allows them to be used to create additional software stacks that behave identically to the U and $ stacks. ‘Some examples of the auto increment/ decrement ad dressing modes ar: LOA X+ sto lye woe i-Y ea Care should be taken in performing operations on 16-bit pointer registers (X, Y, U, S) where the same register is used to calculate the elfective adress. Consider the folowing instruction: STXO.X+ + (X initialized 10 0) ‘The desired result is to store zoro in locations $0000 and 30001 then increment X to point to $0002. In reality, the following occurs O-tomp calculate the EA; temp is @ holding register X+2-=X perform auto increment X-rltemp) do store operation INDEXED INDIRECT ~ All of the indexing modes, with the exception of auto increment/decrement by one or a :4-bit offset, may have an additional level of indirection pectied. In indirect addressing, the effective address is con tained at the location specitied by tha contents of the index register plus any offset. In the example below, the A ac Ccumulator is joaded indirectly using an effective address Calculated from the index register and an offset MOTOROLA Semiconductor Products Inc. 8 Betore Execution A= XX (don't catel X= $F000 30100 LDA [S10,X]_ EA is now SFO10 sro SF 3F180 is now the sro $50 now EA SFI SAA After Execution ‘A=SAA Actual Data Loaded = $F000 All modes of indexed indirect are included except those Which are meaningless (e.g., auto increment/decrement by ‘one indirect]. Some examples of indexed indirect are: LOA LX) Loo [to,s) LOA [B,¥1 LoD 1X+41 RELATIVE ADDRESSING The bytels! following the branch opcode is (ae) treated as 2 signed offset which may be added to the program counter. Ifthe branch condition is true, then the calculated address (PC + signed offset) is loaded into the program counter. Program execution continues at the new location 3s in- dicated by the PC; short (one byte offset! and long {two bytes offset relative addressing modes are available. All of ‘memory can be reached in long relative addressing as an et fective address is interpreted modulo 26. Some examples of relative addressing are: BEQ CAT. ishont) BGT 0G Ishon) CAT LBEQ.RAT thong) DOG = LBGT RABBIT thong) RAT NOP RABBIT NOP PROGRAM COUNTER RELATIVE ~ The PC can be used 2s the pointer register with 8- or 16-bit signed offsets. As in relative addressing, the offset is addad to the current PC to create the effective address. The effective address is then sed as the address of the operand or data, Program countar relative addressing is used for writing position indepandent programs. Tables related to a particular routine will maintain the same lationship after the routine is moved, if referenced relative to the program counter. Examples a LOA CAT, PCR LEAX TABLE, PCR Since program counter ralative is a type of indexing, an ‘additional level of indirection is availabe LDA CAT, PCR LOU {006, PCAThe instruction set of the MCBBOSE is similar to that ofthe 'MCBS00 and is upward compatible atthe source cade level The number of opcodes has been reduced from 72 1068, but because of the expanded architecture end additional ac dressing modes, the umber of available opcodes (with di ferent addressing modes) has risen from 197 to 1464, Some of the new instructions are described in detail below. PSHU/PSHS The push instructions have the capability of pushing onto ‘ither the hardware stack (S) or user stack (U) any single register or set of registers with 2 single instruction, PULU/PULS The pull instructions have the same capability of the push instruction, in reverse order. The byte immediately folowing the push ‘or pull opcade determines which register or registers are to be pushed or pulled. The actual pushy pull s- {quence is fixed; each bit defines a unique register to push or pull, as shown below. PustvPul Posto Stacking Order ul Order | tC cer n _ 8 Der oP : xwi Hy xt a ve fe Yo Uist UIS to PCH PC Lo ! uth Order treeaing ‘Memory TFR/EXG. Within the MCSB096, any register may be transferred to.or ‘exchanged with another of like size, i.e, 8 bit 108 bit or 16 Dit to 16 bit. Bits 4-7 of postbye define the source register, while bits 03 represent the destination register. These are denoted as follows: INSTRUCTION SET ‘Teanster/Exchange Postoyte "Source | Onstfanen Rogier Fels 000=0 1A:8 1000 oor = x 101 onx 1010=cca ooneu o1= DPA roo. o1at= Pc NoTE Al other combinations are undefined and INVALID, LEAX/LEAY/LEAU/LEAS The LEA (load effective address) works by calculating the effective address used in an indexed instruction and stores that address value, rather than the data at that addrass, in a pointer register. This makes all the features of the internal ‘addressing hardware available to the programmer. Some of the implications of this instruction ar illustrated in Table 3. The LEA instruction also allows the user to access deta and tables in a postion independent manner. For example: LEAX MSGI, PCR LBSR_PDATA (print message routine! MSGI FCC “MESSAGE This sample program prints: "MESSAGE. By writing MSGI, PCR, the assembler computes the distance between the present address and MSGI. This result is placed as @ Constant into the LEAX instuction which will be indoxed ‘rom the PC value atthe time of execution. No matter where the code is lacatad when its executed, the computed offset from the PC wil put the absolute address of MSG into the X pointer register. This code is totally position independent. The LEA instructions are very powerful and use an internal holding register Itemp!. Care must be exercised when using the LEA instructions with tha auto incremant and auto decrement addressing modes due to the sequence of internal operations. The LEA internal sequence is outlined as follows: LEAa b+ ——lany of the 16-bit pointer registers X, Y, U, oF S may be substituted for a and bi 1. b-temp {calculate the EA) 2 btt-b ——Imadity b, postinererent 3. temp-+3 {load al LeAa > 1. b+ I-+temp 2 b-I-rb 3. temp 3 {calculate EA with predecrement) Imodity b, predecrement) Aload al TABLE 3 — LEA EXAMPLES. Testruction | Operation Comment TEAK 10. | K+ 10 =X ‘Adds 6 Bi Constant 10 16 eax son. x | x + 500 = x ‘Ades 16-8 Constant 800 ta X LAY AY Yea =Y ‘Ades 8-81 A Accumulator 19 Y LAY DY) Y+0 —Y ‘Adés 16-81 O Accumulator 10 Y Leau-1o.u | u-10 =u Substacts 10 from U Leas 10.8 | s-10 ~s Used to Reserve Area on Stack LEAS 10.8) S+10 +s Used 1 Clean Up’ Stack LEAK 5.8 | S+5 =x Transfers As Well As Ads MOTOROLA Semiconductor Products Inc. 19iVless} ‘Auto increment-by-two and auto decrement-by-two instruc tions work similarly, Note that LEAX ,X+ does not change X; however, LEAX, — X does decrement; LEAX 1, X should 'be used to increment X by one MUL ‘Multiplias the unsigned binary numbers in the & and B ac: ccumulator and places the unsigned result into the 16-bit D ‘accumulator. The unsigned multiply also allows multiple: precision multiplications LONG AND SHORT RELATIVE BRANCHES The M5809 has the capability of program counter relative branching throughout the entire memory map. In this mode, if the branch is to be taken, the 8 or 16-bit signed offset is | added to the value ofthe program counter to be used 3s the effective address. This allows the program to brench ‘anywhere in the 64K memory map. Position-independent ‘code can be easily generated through the use of relative branching. Both short (bit) and long (16-bit) branches are availabe, SYNC After encountering a syne instruction, the MPU enters 3 syne state, stops processing instructions, and waits for an intertupt. If the pending interrupt is nor-maskable (NFA or ‘maskable FIRO, IR) with its mask bit (For) clear, the pro ‘cessor will clear the syne state and perform the normal inter. tupt stacking and service routine. Since FIO end IFO are ‘ot edge triggered, a low level with a minimum duration of three bus cycles is required to assure that the interrupt will be taken. If the pending interrupt is maskable (FIFO, TRO) ‘with its mask bit (For set, the processor wil clear the sync state and continue processing by executing the next in-line instruction. Figure 18 depicts sync timing ‘SOFTWARE INTERRUPTS ‘A software interrupt isan instruction which will cause an interrupt and its associated vector fetch. These software in- Terrupts are useful in operating system calls, software debugging, trace operations, memory mapping, and soft: ‘ware development systems. Three levels of SWI are avalable fon the MCBEC9, and are prioritized in the folowing order: Swi, Swi2, SWI3 16-BIT OPERATION The MC5ED® has the capability of processing 16-bit data ‘These instructions include loads, stores, compares, adds, subtracts, transfers, exchanges, pushes, and pulls. CYCLE-BY-CYCLE OPERATION ‘The address bus eycle-by-cycle performance chart (Figure 18) ilustrates the memory-access sequence corresponding to each possible instruction and addressing mode in the ‘M6809. Each instruction begins with en opcode fetch. ‘While that opcode i being internally decoded, the next pro ‘gram byte is always fetched. (Most instructions will use the naxt byte, so this technique considerably speeds through: put.) Next, the operation of each opcode will follow the flowchart. MA is an indication of FFF g on the address bus, R/W=1 and 85=0. The following examples ilustr s@ of the chart. m MOTOROLA Example 1: LBSR (Branch Taken) Before Execution SP= FOO 98000 Lesh CAT A000 CAT « CYCLE-BY-CYCLE FLOW Cyele # | Adress] Data [R/W]Descrption T | e000 | 17 | 1 ]Opcode Fetch 2 | aur | 2 | > foriser righ aye 3 | am2 | op | 1 jortset Low ayte a | ree | + | 1 [oma cee 5 | sree | + | 1 |umacyoe 6 | 2000 | + | 1 [Computed Branch Address 7 | ree | + | 1 |omacyce 2 | FFF | a | 0 [stock High over Byte of Return adress | ere | a3 | 0 [stack Low Order Byte of Return Adress Example 2: DEC (Extendod) soo DEC $000 sasoo0 $80 CYCLE-BY-CYCLE FLOW Gye F [Accra] Gata [RI W [Description T {e000 | 7A | 1 [Opcode Fetch 2 | aor | a0 | 1 [operand Acdress. High Byte 3 | so02 | 00 | 1 Joporand address, Low Byte 4 [eee | * | 1 [UMA cyce s | acco | 2 | 1 |Reod the Oate 6 | ree | * | 1 |WMA cycle 1 _| Aono |_7¢ | 0 |store me Oecrementes bata * The data bus has the dat at that particular adress. INSTRUCTION SET TABLES: The instructions of the MCBB09 have been broken down into five different categories. They are as follows: B.bit operation (Table 4 16-bit operation (Table 5! Index reqister/stack pointer instructions (Table 6) Relative branches (long or short! (Table 7) Miscellaneous instructions (Table 8) Hexadecimal values for the instructions are given in Table 9. PROGRAMMING AID Figure 19 contains a compilation of data that will assist in programming the MC5B09, Semiconductor Products Inc.@w— iz “ou] sjonpold 4O}ONPUDTIWIES WTOHOLOW FIGURE 17 ~ SYNC TIMING Lost oyele OF Syne Lost Cycle Previous Opeode of Syne Instruct Inst Fetch.) Execute 5 Syne Acknowledge rsrution, "Fateh lL lal E ota RW [> >xX =X Sono a rs Os amr | ay 2B im ARO a Notes: 1. Ifthe associated mask bt terrupts accepted INK or 2, H mask bits are clear, THO a the processor out of SYNC. See Note 2 fetes sot when the interrupt is requested, his cycle willbe an instuction fetch from address location PC+ 1. However ifthe fn unmasked FIRG or TRG) interupt processing continues wth this eyele a8 m on Figures 9 and 10 (Intarupt Timing) nd FRG must be hel low fr three cyoles to guarantee iterupt tobe taken, although ony one cycle is necessary to bring 3, Waveform measurements forall inputs and outputs are spactid at logic high 2.0 V and logic low 0.8 V unless otherwise soeced CocFIGURE 18 ~ CYCLE-BY.CYCLE PERFORMANCE (Shoot 1 of 6) 2a oe tt MOTOROLA Semiconductor Products Inc. 2FIGURE 18 — CYCLE-BY.CYCLE PERFORMANCE (Sheet 2 of 5) MOTOROLA Semiconductor Products Inc. 2(S) MOTOROLA Semiconductor Products Inc. .FIGURE 18 ~ CYCLE-BY.CYCLE PERFORMANCE (Shoot 4 of 5) one EET TEL a = = ees: == = See z MOTOROLA Semiconductor Products Inc. %FIGURE 18 — CYCLE-BY.CYCLE PERFORMANCE (Shoot 5 of 5) ® MOTOROLA Semiconductor Products Inc. | Pe‘TABLE 4 ~ 81IT ACCUMULATOR AND MEMORY INSTRUCTIONS. Tinemonieta ‘Dperation IADGR, ADCS: ‘Ads rerrary To accurultor with Garry [ADDA. ADE ‘Ade memory to seeumulsor JANDA. ANDB ‘Ang memory with accumulator [ASL ASLA, ASLB | _Auithmotic shift of accumulator or meron [ASR ASRA, ASRE | Animes shift of accumulator rmemery nah ira, errs Bi rast memory with apoumulator [CuR. CURA, CURE | Cher accumulator or memery cain [cura cma ‘Compare memory fom acourultor [COM, COMA, CONTE | Compemant accumulator or memory Goaian Joan. Decimal adjust A accumuator [DEC. DECK, DECE | Decrement accumulator or memory Tocaton IEORA, FORE. Exchisive or memory wih accumulator IExG ay, Re Exchange AT with AZT, A2 = A, 6, CC, DPT [NC INCA, NCE Tnererent accumulator or memery oeaton [IORI Toad ascoruator Tort memory ISL, CStA, CSTE | Logics shi ot accurrulator or Reriony BERTON ESR. LSRA, LSB | Logical ahift ight eccumulstor or memory location Mo Unsigned ratio 1A xB — DI INEG. NEGA NEGE | Negate accumulator or memory [ona ona. ‘OF memory wih aesurulator JROL, ROLA, ROLE | Rotate accurulato or memary Re JROR. RORA, HORS | Rotate accumlbtor or memory rant Seca, seco Subtact memory from sacurulator Wi DoroW [Sta STs, Store aocumulior to eon [susA, sue Subtract memory fom accumulate ST, TSTA, TSTS | Tost sceumulator or merry locaton [TER Ai, Re Transfer Rio #281, RE = A 8, CC OB) NOTE: A, 8, CC, or DP may be pushed to (pulled fom| stack with either PSHS, PSHU {PULS, POLUD instructions ‘TABLE 5 — 16BIT ACCUMULATOR AND MEMORY INSTRUCTIONS Nitemoncis) Operation RODD. ad eon 16 D sea UMUIaTON leweD. ‘Compare memory trom D accumulate exc Oa Exchange D with X, YS, U or PC. LoD Lead 0 accumulator rom momary (sex ‘Sign Exiond 8 sssumuator nto A ACCU [sto Sioie 0 accumulate 19 memory IsuB5 Subtract memory trom D sccumulator Tra Oe Transfer D to X,¥. S.U_ or PC Fran. o Transfer, ¥, $.U,or PCO. NOTE: D may be pushed Ipulled) to stack with either PSHS, PSHU {PULS, PULUD instructions, increment MOTOROLA Semiconductor Products Inc. rsTABLE 6 — INDEX REGISTER/ STACK POINTER INSTRUCTIONS. Tnsrcton Devcon fevPs, cw Coripre aay Hom stack poner CPR. CHPY Compare mama fam dex ops FXG A, 2 recharge D.X¥_X, Uo PC wih XV STW PE TEAS, LEAU Tad steve aces nfo snc one TEAK LEAT Toad effec aos no nde psi 10s. 10u. Load sack ponter rom rarer (ORLY Coad nex opair Fon marr PSR Puan A,B, Oc, OP, 0, XV, U, & AC ona hardvare sek PSH Bush AB CC_DP.O.X-¥.§.or PC onto ven sack POU PUTA. 8, €6_OP.D.X.¥. 5.07 PC om tarware stack SIS, 57 Slot sabe saver © menory xan, Sie nox rite to menor [rem RE Fianwer 0... §, Wor PCO Sw PC 7x add acount 10 hnmgned TABLE 7 — BRANCH INSTRUCTIONS. Tract ‘scription “SIMPLE BRANCHES. OLE Tana ava BRE_LBNE rane not oa ‘BW LoM Branen anus BFL, L8PL Branenit us| 3cs_ 180s Branch teary cc_uBce Bach teary ox | BvS_LBVS Bien ove ot VC. LBC Bren overt ea SIGNED BRANCHES [ears Janeane sae v5. 15v5 Branenifivoid Ze conalat auT G¢_LBGE Bianchi grater tan en feared 0, U8E0 Branch at BRE LONE, Biach tno ea Be Lae Beach dies han oy Sed ave Lave Trosch wid 2s corp su act. 1aUT Bronchitis ma feared ‘UNSIGNED BRANCHES Ta Trac pre unsigned ‘ct, Boe Branch hgher ose unsgea rs, Lons Branch Figher a sare unsared 30,180 Branch east BRECON, Branch ot ea ais, Lous Brann tower or Sm REGED aCS_L8CS ror tower (unsireal 810-1810, Branch ener lunsgned ‘OTHER BRANCHES Benes Taner io ssrouine BRA, LBRA Brann ave = ‘RN. LaRN Bane never — = ‘TABLE 8 — MISCELLANEOUS INSTRUCTIONS Treen Besson a NDE "AND onan coe 9st ‘awa [AND condition coon rege hen wok Tomas NOP Te operator ‘Once ‘OR condion cade rage 58 “lure i aoe aT Fetus rom ner ATS: etn rom subrosine Sit ST, SWE | Softwore nie soit ROTC SNE Synchro win mierupt toe m MOTOROLA Semiconductor Products Inc.TABLE 8 — HEXADECIMAL VALUES OF MACHINE CODES (OP | Mem ‘Mose [- | [OP | Mra Mode [=]? [OP | Miner moses [- [oe | NEG Dies [6 | 2 | 20 | teax indged]e+ [2+] eo | NEG Thassos [o> | 2 of Leay as foe] oi |» 4 a] a2 | Leas 4: [2] a] 3 | com 6 | 2 | | eau Indes | 4+ [2+] 63 | com jos | 2+ of | LR 6] 2 | x | psus Immed |5+ [2° | ot | ise jes | 2+ 6] + 3 | puts Immed 5+ 2 J os | = 05 | Roa 6 [2 | | esau immed |5+ |2 | 66 | Aor es | 2+ a7 | asa | Je] 2 Jar | eu immed [6+ ]2 | or | ase e+ | 26 oe | Ast, Lst | Je|2 Jaul- s ee | Ast. Lst } Jee | 2 3 | AOL 6 | 2 |x| ars inherent] [1 [9 | ow | Jes | 2+ oa | oc 6 [2 | sa] asx 3 [1 | 68] occ | fox | 2 os | + 38 | ant eis}? | 68 | + oc | inc 6 fz | ac] ova 22]2 J sc | inc 6+ | 2+ 09 | tsr 6 }2 | 30] mu tonerene| 11] 1 | 60 | rst je | 2+ oe | ump a}2 [a+ = se | ame ¥ foe | 2s oF | cr over fo | 2 sw tenerent] 1@ [1 [oF | cu Indoved ax | 2+ 10 | Page 2 |e NEGA veneren|2 [1 [70 | nes lexendes]7 | 3 11 | Page 3 zie . nfs 4 12 | Nop tnverent| 2 4 . nl 3 | syne iiverons| 24 | 1 coma 2 |1 | | com 7 | w | UsRA 2 |i | om | tsa pda as | * : | we | tena Reaivels | 3 RORA 2 |r | zw | aor 7 /s 17 | tase Reaivels | 3 ASRA 2 |1 | 7 | ase > | ws ASLA, LSLA, 2 |r | ow] asuuse 7/3 19 | paw lenerent| 2 OLA 2 we | ROL > Ja 1a | once immed }3 | 2 | aa] oeca 2 |i | va] oec al w |? ” * | wal 1c | anoce immed }3 } 2 | ac} inca 2 |r Ja] we ya 10 | sex inverent| 2] 1 | a | tsTA 2 [1 | 9] tst 7 13 ie | exc Immos |3 | 2 : ze | ame a [3 F | ee immed fo] 2 cuRA tonaront] 2 ff 76 | cua 7s | saa Relarve | 3 NEG toner: 2 [1 | eo | susan Bale 21 | Ban 3 + at | cea, a |2 |2 22 | BH 3 }2 . 2 | seca ale 3 | 5s a]2 |] come 1 |e | sua a fa 26 | BHs, acc 3} 2 | a] csr 1 | 2% | anos ale 2 | 810, acs af2 [al- | as | aia aie 25 | ane 3] 2 | %| sons 2 |r | a | toa 2 [2 z | a0 a [2 |e] asra 2 |i fal: w | ave 3} 2 | sw] asis,isis 2 |i | a | cora 2 |2 | avs 2 [2 | @| roe 2 a | aoca, 2 | 2 20 | 8PL 3 [2 | sa] oece 2 8a | ona 2 |2 28 | ami 3] 2 Joel 88 | acon 2 |2 2c | 8ce a]2 | sc} ince 2 ac | cMex immed [3 | 3 20 | But 3 ]2 | 50] tste 2 |1 | 0 | asa Relaiwe|7 | 2 ze | ect 3]2 [el]: ae | Lox immed [3 | 3 2 | oe rewtive|3 | 2 | 5 | cine toners] 2 [1 fae | + LEGEND: ~ Number of MPU cycles tess possible push pul or indexed-mode ete) 4 Number of program bytes * Denotes unused opcode MOTOROLA Semiconductor Products Inc. 2TABLE® ~ WOXADEEMAL VALUES OF MACHINE CODES (CONTINUED) OF Mew ode [=| ¢ [oF | trom ‘ode [=[_# [or [woem ‘weds [= [Te fe —SuBe Bree fF co] sue vores [2 | 2 91 CMPA Ala j2 ci | cMre 2] 2 Page 2 and 3 Machine m Seca s|2 | &| Stee a) 2 Codie se sue 6 |2 | | xo a] 3 st aNDA a ]2 | | anos 2 | 2 [on Jom romwe]s | se ama a ]2 | oe one swoned [2] 2} soaa)iam — | sie] ¢ se ta | fe ]2 | co] we tame 2 | 2 J toos)teis | s)| « jy Sta lle jz Joys * toat | Lens, vace| | ¢ secon 442 | co] cone 2| 2 | tas |iscs, cots | « so ADCA e]2 | | face 2 | 2 | toes [lane 2 | 4 oa Ona © 1/2 | cal one 2) 2 | tao |tece 9 | 4 fe RDDA a |2 | cs| sop 2| 2 | tom|tave 30| « 8 CwPx 6 |2 | cc] too a] 3 | tom |tovs ba 4 ssa > 12 | cols waa tare | foe] Woe tox 1 tible |e as Pimeltom —) | fee & er St one | [2 | reac) ace sisi] ¢ tezo| tact sie] « AO) SUBA Indexed | 4+ | 2+ 00] sues eo 1026 | LBGT sie} 4 Al CMPA A fas] 2+ fl | dog Blea 102F | LBLE Relative | 5161] 4 ‘A2 SBCA aie Foci boa bot alee 103F | Swi2 inherent }20 | 2 a3 SUBD 6+ | 2+ | pens Wie 1083 | CMPD. immed 15 | 4 Ad ANDA pee eit oe S13 | tec] cmey 1 js |4 AS BITA a bs) ae. le ose | LOY immed ]4 | 4 }AB LDA 4+] 2+ > lee 1093 | CMPD Direct }7 | 3 AT STA 4+] 2+ 7 | ste lee yoac | CMPY. 7 13 ‘AB EORA 4+] 2+ ee et 109€ | LOY 6 | 3 9 ADCA ae | a+ ate | 1) 3) | sox | sty je | 3 AA ORA as | 2+ | OA) one J UE] 2 | rossfeneo 34] JAB A008 az] 22 | 98] A008 | || 3. | tosclemer 34| AC CMPX er} 2- J 9C} Loo BY) 3 | toae|uor | 34]} aD sa pi} 2 512 [ioarlsry | names ox J 34 JAE LOX V [5+ | 2+ ot : 1083 | CMPD. Extended] 8 | 4 JAF STX Indexes [5+ } 2+ = prec) BEES yosc| CMPY la | a | sues Tedged] so] z= | tose iby a |e eo sue fxesns]s fs | et | cure e:] 2° | at sev pall Bi cuba A'ls | | @ | Secs fe] 22 | toce|tos far ee saca bjs 3 | | ao e:| 2° toce|ios e [3 3 susp > }3 |e] anos | 25 | toor| srs eee |e | 3 Bt ANOA o]3 | el ens #3] 2! | foee [bs vrdnea [> | 3 sana 5 [3 |e] tos | Jes} 25 | foer sts indeed [= | 34 8 WDA es |3 Jel sre | [as] a renaee]?” | 4 Br sta ls [3 | a | con eo] 22 | soe [sis erorane|? | 2 aa oR Bp | 3 |e | aoce ec] 25 | itr [Swe zo | 2 Be AOCA ep | 3 | ta] on eo] 2s | te fenru e | 8 an Ona B |3 | el] soe | 22 | hiac fens tamed |b | 8 8 A008 ep [3 | cc] to e-] 2s | es fone ree [7 | 3 Be Cure p }3 | e| so s-] 22 | Hac fours Oren |? | 2 a isk e|s | e| to ¥ [5s] 2: | as}oure rare? | 34 a ie e |3 |e | sw indmed| se] 2+ | Tac|eus trans |7= | 24 ee serve |S ro | suse exenaeals | 2 | M83)/cMeU oer ie 5 | eure es | 3 fa | soca Bb] 3 8 | aoo0 7| 3 re | anos ep] 3 fs | one eB] 3 re | tbe sp] 3 | sta eB] a odes are both undefined | F® | EORB ele Wore Ala eta ae em ucond | | SOME 5] 3 ra one ¥ [5] 3 fe | x00e teceanals | 2 | re| too 5] 3 ro | sro e] 3 | fe | Lou je] 3 | | sw eneadfs | 3 |FIGURE 19 PROGRAMING AID ‘a We a 7 slalal tesweton| rome LOTT TT Oe TFL Oot et FLO =| Tool 1 F peecioion putz Aon Ba] 3 | 1 [B+ X—x Unsigned [lel ae PTA STE ET aey STs rene Thy moce_jeo| | 2| oe] «| a| ealscl a+] vo) 3 | 3 Brwscse HAAG aos Fase peste] zy me] zp Aa] 2*] 88] of 8 aoa TTT Roce [ee[z| | cx [2 | 2| e2/s+| 2-|r0] s| 3 ecnce tlie sBos_| 23 2{ 3| ose | 2| cafes ze] v3] 7] 3 Biwi i= BRE ao amo Y AY BPEL AY EY BPS] S ian SHH mos ferfz| 2| oe [ | 2| es] 2+] a] 5 | 3 ban sys fanoec [56] 3 3 feaice aa Yast apy aye ase B[2[ 1) Nocormre fels]i|: ast we le | 2| oslee[z+| m| 7] 0 we eit BSR aS az = aT a Bl 2) a Sel ele se oro | 2| orfee| 2+] | 7] 2 i pllals ar jars meta eye ap see] | To arena wa HTH Brees >| 2] os] «| 2] ele[ 52165) 3 | 3 Bites Wass HAE CURR pepe Sonn cine | 2| tome 2]5)1]3 cia o|e|: z-[r| >| s ook fo} fo cae Tene Parpa pap ar peye FTape]s Tenpoa Tone apy ees fe ]2| 3] os] 2] 2 sll e| Corpse tom @ HABE tire [oe] a] t0|> | 3 S[to] 8] « eaeazuarriiem> [ols [ala s s = ewes JS ]s] «ft [> | s a|n| el 4 conoueuntsttoms fo] 1{a] a]: ee « ee eweu |" [5 «fi |>] 2| tlr-faefnf el « congue ete riomy — fel stale] & 2 & & curx [Sc [+] 3] se) 6 | 2| Aeler] 2-f ec] 7] 2 compuemmerivon fella fale eer JSS [5] 2] se] | 3] coy se| o-| | a | 8 SeresemMetrem sy — fefel tale fe x Ae sc cor] oom apap ee shat coue | 2| tle-e ris] con wfe|2| osle-|z-| [7] iar BHA owe ERT ER WAITEC Wor To oT ORR SLT [ocr aE =r oes] oe mapa ee arr Dect we] 2) tent oT bee |_| of] 2] oafee|z-fra] >| s one oth eR Jeune RTS P EL SLE] Ey les] we STS Ha steps fono [eal zl 2| os] «| 2| él ec|#s [90] 5 | 3 vice sel: whe | 2| tlet=e aye Re ocfa| a| sclesl2|2e] >] 2 fon BHHAE ae te [steteelse[a-[vep apa eat—Fo tbls ry stop epeotstasfaop ss So OS EEE EE A nRBCae me Taye wee [8/2] 3) oel«| 2| elec|ze| ve] s| 3 woe HARE 183 Jee | 5} 3] oc] s | 2| celse] ax] rel 6 | 3 Nie r= taal 132 |S |e] a] Soe | 3} soles ax] 1 9 | timeics oye] iyo] & o Fd tt vou [ee|s] 3] be] s| 2] é]se|2-fee] 6] 2 sem ety Jf fol« tx S/S] 3] Ses | af aelse|zc| eel e| 3 wa ioe syefeye} er |S a] a1 5 |e | 3] Toles] ax) v0] >| & taste syefefol* ee 2 i a oe ape] aa helt tae Beye Bag BARRE tax lal] eax seed tea alele tay HHHEB re comple ot 7 Ten ord set fue, Gere athens OF Operation Code(Hoxadecis) = Tranter nto + Nov Ateces = Number of MPU Cycles Mata om ba 2) ¢. Cordtion Code Regier 1 Number of Program Bytes Negative tsign bt Coreatration + ithe Plus 2 ze reast VLoges! or tte Min V Ovetfow, 2 content A aes + Multi © Cony trom ALU Lopeal Excuse or MOTOROLA Semiconductor Products Inc.FIGURE 18 ~ PROGRAMMING AID {CONTINUED | . ae Wes | Tes | — Bias T et ea — at slalelslo, | tarctin| rome POET] TL Oo FT OF ert or oescon ae ist Tse 7 T [atat effi iste | } Js] 2fi sftle tt o2| s| 2} colon! 2-| m5] >| 5 | shel | over | 21/7] ef: ie _| ce| of 2] orfos| 2of vel 7] 9 ABH Ta SoA eo rea sete Teo fre | SPT tt Neco [| [epi p fei if: | nee wl s|2 al |ols a Stith we t [EDEL Ts oso etfs rr Foe Pa a] psa wy sp ay wee Ther | fore [eal 2 [a] oa] s| 2] en]sclacl cal El 3 ivuce (pplsyst | 14 feroo (Sal 3 [3 [aeye| LET BMS ce i | es eat t jeux teases mS sua Y= | rate _|Sofese|2 ram negaescxysee |: FL fous sleet 2 2 Pal Retes ton Sse] puwu_| ses] 2 | Putrepsies tome Saat woe SIahTs oil mows | TT Vey] Tac Te |: | rot | 2] ler ze mw] 713 pee | waR—Frons arte : | ole lia 2 Gr |: fon es| 6 2 eoleo| ze] w| 7] 3 wet | a t Bee rm a t Bs Lior supe i sees tet topes ats oa i | feca_|e| 2 |2| | «| a3 ponte be t t DLT [Tsar ew EAS i foe ste =13] a a |e] «| afal | / | Jee. | | 0] § ] 3] | Be | | | pers | 2] | | oF 2 sw | | | |Befs) 2] tele-/2-/ #/ 6| 3] vom! ge) | | [Ses] a) se]ssiec] erie] 3) |p Somat) FLT Perper yay Ff suas! | Lf elt | alee se/er| “| “| | sus [susa [a] FPP HL a] 2] Ada a>] so] STs ay | suse |e] 2 ]2|o0|*|z [ales ss] 00/8) 3 Buco | [Sono_[ssl & 3] 816 [3/3162 22/681 $ | 3 [poMar 1p aw . Sh a | sw | | | [las] 2 ome cme vs | [ya] | | | ¥ SYNC T — ia 13 [24] 7 [Synchronize 19 Interrupt eer rr] | ware ep ef fons SEH ate wpa peas aaah | sve 2/2] 1 fea TBE fst w]e | 2[eofesf+| 70] >| 3 rn SHAG |S} NOTES 1 Thigclumnpesaose yee ancbyecount, Tobin cou, the valves bara om ne INDENED ADDRESSING MODE tb, Tied 2. Rand R2 ay be any pt of 8 tay pa of 18 eps ‘hesmeropstes yo 43, 00.Be Ihe tot regotes we 4-0, 50, PC 2. Eis ne efecive eens, 4 The PSH and PUL nsttons requ 5 yes ps cy for ach be puss of eles 5 51) means ccs rare not taken, oes taken ranch msc) | & Swianst and bc: SW2 and SWI a est | 7. Consors Cae sta det et othe stucton | 8. ave of hata tg urges | 8. Speciai Case — Carry set tb? is SET. | | | MOTOROLA Semiconductor Products inc. —————! :ie FIGURE 19 — PROGRAMMING AID (CONTINUED) Branch Instuetions oe “coe | — aa venir] toms [TMT] omen HIEHEITIE 2c | Jeane [10/5161] 4 long Brancn Jelefelele x l ter. [fata] 4 [org ancy us |e [tye] ef soa ; ea |e leila pests 7 a coche i]t es | ale) BE asa eee apy SIMPLE BRANCHES ee SIMPLE CONOMTIONAL BRANCHES (Not 1.) BRA cle Tru oF False OP. LBA eee ‘BMI 2B BPL 28 eng 2 sone fin wat ae oe srt es Boece fe 8G SIGNED CONDITIONAL BRANCHES (Notes 14 UNSIGNED CONDITIONAL BRANCHES (Note 1-4 Tat The OP be OP Tet Tue OP Fae OF om get ae BEF ee mm ge eat anos om ae eae ese 2 2 a a aed a 8S Boe NOTES: 1. All conditional branches nave both short and long variations. 2. All short branches are two bytes and require three eves 2. All eancitonal ong branches are formes by prethang the short branch opcode with $10 and using 8 16-bit destinstion ost. 44. Al conaitonal ong branches require four bytes and six cyces ifthe branch i taken oF five cycles if the branch isnot taken. MOTOROLA Semiconductor Products Inc.PACKAGE DIMENSIONS [—jmccmerensy—wewes —) MAX MA] ier [sea 1s 2a TaRnTTT | -—A tin A aa oe naiertace Rema earns Stee mst ae ab ae Harare @ o [ox [oss Toor | oar Leer Ss : rae aa ie Hehe iat bie 2 nn OLN FOR EAU. sure Shaem ata) {CASE T1505 2. FE) ssearine rane. {oMmeNSION “L" TO CenTeR OF LeA05 [WHEN FORMED PARALLEL ‘DIMENSIONING AND TOLERANCING eR aNS! 45,1973 ae we) ) | ‘oom an [ax [WNT WA) i Ara fase . i we die Lh x = ore vores She Tomes oxo una cae fonts CG Treas S 'S SUFFIX TAO) CERDIP PACKAGE 2 Co ssearne nae casemeee & Gheasoucro cares SPtechncn anes 5 Bibisowaaqo sretacve (AR En & MOTOROLA Semiconductor Products inc. elORDERING INFORMATION Package Type _| Frequency | Temperature Range Ceramic | TOMHe | 0°C 10 70°C Usufix | LoMHe | 40°C 10 asec ce ee 1eMHz | 40°C 12 85°C 2omHe | ocr 70° 2omHe | —40°C tos TOMHs | 0°C w 70°C TOMHe | —40°C 1 85H SMHz | 90°C %0 70°C 15MHe | ~a0°C 1 85H 2omHe | o°C 170°C ome | ~a0-c 85%c TOMHs | 0°C 0 70°C Ssufix | 10MHe | —a0%c roas%c 15mnz | acto 7c | wiceBaogs 15Maz | —a0°C asec | mceaacncs zomHe | oxcro70°c | stoseboas ome | avec roasec_| micesacocs @® MOTOROLA Semiconductor Products Inc. Pa® MOTOROLA Semiconductor Products inc. IN. TEXAS