Class D Amplifier Design Basics II

02/19/2009
Rev 1.0

1
Contents

Chapter 1
Getting Familiar with Class D Audio Amplifier

Chapter 2
Latest Class D Audio Amplifier Technology Trend

Chapter 3
Identifying Problems ~ Performance Measurement of Class D Amplifier

Chapter 4
Reducing Distortion ~Dead-time ~ LPF Designs

Chapter 5
Reducing Noise ~ Isolation Technique ~ PCB Design

APPENDIX
Simulation of a Simple Class D Amplifier

2
 Chapter 1:
Getting Familiar with Class D Audio Amplifier
Audio Amplifier Market Trend

• More Channels
• Smaller Box
• Lighter Weight

A Wire with Gain • More Functions

(Digital Input, Diag)

• Smaller Size
Device Technology • Lower Cost Control Technology
• Audio Performance

4
Why Class D Now?

Audio Market Trend

• More Channels
Class AB • Smaller Size

• Smaller Size
IR
Class D
• Higher Performance
Device Technology
• MOSFET
• High Speed HVIC

5
Basic Concept of Class D Audio Amplifier

Class D
COMP LPF
Switching Stage

Analog signal Î PWM Amplify PWM Î Analog signal

VOUT = B (2D-1)
In concept, Class D amplifier is linear; i.e. 0% distortion.

6
 PWM: Heart of Class D Operation
Audio signal Î PWM PWM Î Audio signal

10 10

5 5

0 0
V

V
-5 -5

-10 -10

60 80 100 120 140 60 80 100 120 140

Time/uSecs 20uSecs/div Time/uSecs 20uSecs/div

7
Class AB vs. D Energy Point of View

Similar to a variable resistor

Class AB

PLOSS depends on output

IIN = IOUT power factor

Similar to a transformer with

variable turn ratio

Class D

VIN x IIN = VOUT x IOUT Bi-directional energy flow

Note that input current and
output current are not equal.

8
Class AB vs. D Characteristic Comparison (1/2)

Feature Class D Advantage Class AB

Superior efficiency
Efficiency can be improved with device technology Efficiency is fixed.
Extremely inefficient when
Suitable to drive lower impedance load
Efficiency driving lower impedance load.
Can drive reactive load without significant degradation of Extremely inefficient when
efficiency driving reactive load.
Requires smaller power supply
Bi-directional energy flow; any energy reflected from the
All the reflected energy from
load is recycled to the power supply. Suitable to drive
reactive components and back
Energy flow
highly reactive load, such as woofer, speaker system EMF are consumed dissipating
with dividing network, piezo speaker, etc. heat
The output device has high
impedance, ~tens of k ohm.
Inherently has low output impedance (m ohm range) With a strong voltage feedback,
Class AB can achieve low
output impedance.
Power supply current = load
Drivability current. For a given output
Lower impedance loading does not burden power supply. power with decreased load
(Power supply current) ≠ (load current). impedance, the supply current
and heat dissipation in the
output device increase.
Wide power bandwidth; no extra effort to drive high Cross conduction limits high
frequency rated power. frequency power bandwidth.

9
Class AB vs. D Characteristic Comparison (2/2)

Feature Class D Advantage Class AB

Output device is non-linear;
exponential in BJT, quadratic in
Topology is inherently linear without feedback MOSFET. Strong feedback is
necessary to achieve good
Linearity linearity.
Cross over distortion is at where
load current crosses zero,
Cross over distortion is not in zero crossing area
which is most critical point of
operation.
Output devices in linear
operating mode has strong
Thermally stable; gain of the Class D stage, bandwidth,
temperature coefficient in gain.
Stability loop-gain are independent of output device temperature.
Loop-gain is changing
dynamically with output power.
No bias-current thermal compensation
Because of strong non-linearity
Inherently immune to incoming noise; low drive in device and 'exposed'
Noise immunity
impedance, inductor between the load and amplifier. feedback node, weak to RF
noise.
Higher reliability from less heat. Less metal fatigue in
Reliability
solder joints.

10
Class AB vs D Comparison
Loss
Loss in Class AB
2
VCC
Pc = 0.2 ⋅
π 8 ⋅ RL
PC =
1
⋅∫
Vcc
(1 − K sin ω ⋅ t ) Vcc K sin ω ⋅ t • dω ⋅ t
2 ⋅π 0 2 2 ⋅ RL
Vcc 2 ⎛ 2K K 2 ⎞ Note that this is
= ⋅ ⎜⎜ − ⎟⎟
8π ⋅ RL ⎝ π 2 ⎠ independent to
device parameters.
K=2/π K=1

Loss
Loss in Class D
Efficiency can be
PTOTAL = Psw + Pcond + Pgd improved further!

RDS (ON )
Pcond = ⋅ Po Pgd = 2 ⋅ Qg ⋅ Vgs ⋅ f PWM
RL
Psw = COSS ⋅ VBUS ⋅ f PWM K=1
2

K is a ratio of Vbus and output voltage.

To learn more about power losses in Class D, refer to AN-1070 Class D

Amplifier Performance Relationship to MOSFET Parameters.

11
 Practical Class D Amplifier

Perturbation
Supply impedance Nonlinear inductance /
Limited Gain & BW Bus Pumping +VCC
Noise Figure Capacitance
DC Resistance

Audio PWM Gate Driver

source
F/B

-VCC

Dead-time Finite RDS(on)

1. Non-linearity in the switching stage due to timing
errors added, such as dead-time, ton/toff, and tr/tf Vth and Qg
Body diode recovery
2. Limited amount of error collection capability due
Stray inductances
to limited gain and bandwidth in PWM modulator
3. Audio frequency band noise added in PWM RDS(ON)
modulator
4. Unwanted characteristics in the switching
devices, such as finite ON resistance, finite Note that 0.01% of non-
switching speed or body diode characteristics.
ON delay OFF delay linearity corresponds
5. Parasitic components that cause ringing on to10mV out of 100V DC
transient edges
bus, or 0.25ns in 400kHz!
6. Power supply voltage fluctuations due to its finite
output impedance and reactive power flowing
through the DC bus Finite dV/dt
7. Non-linearity in the output LPF.

12
MOSFET Basics

A MOSFET is a device to switch In switching transition, stray

electronic current. A driving MOSFET
charges/discharges a capacitor (Gate
to Source, Gate to Drain).
A MOSFET does not require any
energy to keep it on-state.
impedance in each terminal slows
down switching and generates
unwanted rings.

To learn more about power MOSFETs, refer to AN-1084 Power MOSFET Basics.

13
Driving MOSFET for PWM
• Only one side, either high-side or low-
side, MOSFET is ON at a time.
• The ratio of ON time between the high-
High-side ON side and low-side MOSFETs
determines the output voltage.

Driving a high-side MOSFET

• A floating power supply that referenced
to switching node drives the gate of the
high-side MOSFET
Alternating at Switching • The floating power supply is charged
Frequency when the low-side MOSFET is ON.
(Bootstrap power supply)

Low-side ON
Driving a low-side MOSFET
• A bias voltage that refers to negative
bus voltage –B drives the gate of the
low-side MOSFET.

NOTE: In a practical design, a dead-time

where both high- and low-side MOSFETs are
off is inserted to prevent simultaneous ON
state. Refer to chapter 4 for more details.
14
Bootstrap High Side Power Supply

High-side ON
• I4 turns off the low-side MOSFET.
Then, I5 turns on the high-side
MOSFET, lifting VS up to +B. As
long as the high side is ON,
bootstrap diode DBS isolates the
floating power supply VBS and
bootstrap capacitor CBS retains VBS
voltage.

• After the high-side MOSFET ON

state, I1 turns off the high-side
Low-side ON MOSFET, then I2 turns on the low
side MOSFET. As soon as
switching node VS reaches
negative supply –B, the bootstrap
diode DBS turns on and starts
charging bootstrap capacitor CBS
with current I3 from VCC.
• Note that VBS = VCC – (forward drop
voltage of DBS).

15
 Example of a 100W Class D Amplifier

Optional switching noise filter

VAA supply
Feedback resistor

High-side OCP

Input resistor Startup resister

Bootstrap floating
supply charging path
6V

4.7 Ω
R8
20 V
ENABLE

DC blocking Bootstrap floating

capacitor
6V

supply capacitor

C11 10 µF
Demodulation LPF
2nd order integrator

20 V
VSS supply

Low-side OCP

Dead-time

16
 Chapter 2:
Latest Class D Audio Amplifier Technology Trend
Class D Amplifier Innovations

Device Technologies Packaging Technology Signal Processing Technologies

• MOSFET FOM (Figure of • Smaller • Feedback techniques

Merit) improvements
• Higher voltage capability
• Faster and accurate
switching time
• High gain low noise
process
• High GBW (Gain Band-
Width) process
• Low stray inductance • Self-oscillating
topologies
• Surface mount
• Digital domain PWM
• Dual sided cooling
processing
• Hybrid module
• Multi chip module

Higher Performance + Smaller Size + Lower Cost

At The Same Time !
18
1. MOSFET Technology Trend

A MOSFET has inherent trade-offs

between ON resistance and gate International Rectifier Mosfet R*Qg Trend
charge, RDS(on) vs Qg. In device 1.2

design, this translates into Conduction 1.1

Planar Stripe Technology

loss vs Switching loss trade-off. 1

0.9

0.8

Normalized R*Qg
The objective of optimization for Class 0.7
IR Mosfet Technology Constant Improvement Trench Technology

D applications is to achieve minimal 0.6

power loss. 0.5

0.4

0.3

Newer platforms show better FOM 0.2

2000 2001 2002 2003 2004 2005

(Figure of Merit)
Fiscal Year

Î This is what makes Class D keep

improving!

19
MOSFET Evolution

The latest trench MOSFET technology shows 7 times better figure of merit.

Higher cell density

Planar MOSFET Structure Trench MOSFET Structure

IRF540 IRF6665
100 V 100 V
66m ohms RDS(on) x Qg=3300 53m ohms RDS(on) x Qg=445
50 nC 8.4 nC

20
 Trade-offs in MOSFET Design

There is a best die size for a given Optimal MOSFET die size ⇒Optimal MOSFET Parameters
output power. Optimum die size for
minimal PLOSS depends on load Total Loss = Conduction Loss + Switching Loss
impedance, rated power and switching
frequency. Total Loss
A more advanced platform with better
FOM acheives lower PLOSS.
Optimal MOSFET
Die Size

Conduction Switching
Loss Loss

To learn more about MOSFET selection, refer to

AN-1070 Class D Amplifier Performance
Relationship to MOSFET Parameters.

21
Importance of Packaging

How the package affects the design? To utilize benefits from a newer
generation MOSFET, new package
with reduced stray inductance is
necessary.
1. Amplifier size
• Increase efficiency
• Increase current capability
• Improve the MOSFET thermal
efficiency

⇒
2. EMI considerations
• Better control of current and voltage
transients

D2/S1
G1
D1
G2
S2
TO-220 Full-Pak
5 PIN

3. Amplifier linearity
• Decrease switching times
• Narrow the MOSFET parameter
distribution

22
Stray Inductance

A MOSFET has capacitive elements.

Stray inductance is where excessive
energy is stored, causing over/under
shoots and rings.
Stray inductance in Source returns
feedback voltage to gate, slowing
down switching speed significantly.

The smaller the parasitic components

the better performance!

To learn more about MOSFET switching behavior, refer to

AN-947 Understanding HEXFET Switching Performance.

23
Package Comparison

• Lower inductance at frequency than SO-8, D-Pak, MLP and D-Pak

• TO-220 inductance package is ~ 12nH
• DirectFET® is 0.4nH
24
 EMI Comparison

• DirectFET® amplifier shows better EMI performance than TO-220 amplifier

• Over 2MHz, DirectFET amplifier shows approximately 9dBuV lower Peak,
Quasi-Peak and Average noise than TO-220 amplifier
• Both PCB’s meet audio amplifier EMI standards limits (CISPR13)

DirectFET TO-220 (w/DirectFET die)

Frequency (MHz) Frequency (MHz)

CISPR13 CISPR13
Quasi-Peak Limits Quasi-Peak Limits
Average Limits Average Limits

25
2: Gate Driver IC Technology Trend

• More integration to realize smaller footprint

Gate driving
Analog signal processing
Power switching
Level shifting

Feed back

AUDIO PWM
SIGNAL Level
Level Speaker
Shift Shift
Down Up
Dead Shut
Time Down

Over Current

Protection Control Logic

Protection functions

26
What The Gate Driver IC Does?

Four Essential Functions in Gate Driver IC

• Level Shift • Gate Drive

• Deadtime Generation • Under Voltage Lockout

Gate Driver IC

To learn more about High Voltage Gate Driver IC,

refer to AN-978 HV Floating MOS-Gate Driver ICs.

27
How Internal High Voltage Level Shifter Works

Operation Principle
A pair of SET and RESET signals are
generated at the PULSE GEN block.

The SET and RESET pulses drive the

high voltage MOSFET to send these
signals to circuitries in a floating high-
side well.

Pulse Gen Waveform Example

HIN
The high-side circuitry reconstructs
PWM from SET and RESET pulses.
SET

RESET This method minimizes power

dissipation in the high voltage
HO MOSFETs in level shifter.

28
Floating Well and Noise Isolation

INPUT SECTION HIGH SIDE GATE DRIVE

LOW SIDE GATE DRIVE

LEVEL SHIFTERS Note

• Translate PWM signal to • Level shifter rates supply voltage ranges
different voltage
• Level shifting is useful to drive high-side the
potential
MOSFET whose source is tied to switching node.
• Isolate circuit blocks that
• Level shifting blocks switching noise coming into
are in different voltage
sensitive input section.
potentials

29
Dead-time Generation

With Dead-time
Dead-time (or blanking time) is a
period of time intentionally inserted in
between the ON states of high- and
low-side MOSFETs.

This is necessary because the

MOSFET is a capacitive load to the
gate driver that delays switching time
and causes simultaneous ON.
NO DEADTIME
Without Dead-time
Lack of dead-time results in lower
INPUT efficiency, excessive heat and
potential thermal failure.

HIGH-SIDE

Usually, dead-time is realized by

delaying turn on timing.
LOW-SIDE

SIMULTANEOUS ON

30
Under Voltage Lockout

• Under voltage lockout (UVLO)
prevents the MOSFET from
entering the “half-ON” region when
the gate bias voltage is reduced.
• The “half-ON” condition of the
MOSFET creates excessive power
loss due to increased RDS(on) that
could lead to MOSFET failure,
therefore must be avoided.
UV
CSH
DETECT
VB
• During the UVLO, gate drive stage
keeps HO/LO low in order to
prevent unintentional turn-on of the
MOSFETs.
• UVLO in VCC resets shutdown logic
and causes CSD recycling to start
over the power up sequence.
• The IR Class D audio gate driver
family is designed to accept any
power sequence.

UV
HIGH
Q
SIDE
CS
HO

UVLO of VBS shuts down HO and

VS
HV
FLOATING HIGH SIDE
HV disable high-side current sensing
LEVEL LEVEL
SHIFT SHIFT

31
 Inside of High Voltage Gate Driver IRS2092
High Voltage Isolation

FLOATING INPUT CSH

UV

PWM Modulation
DETECT
CLICK NOISE
VAA ELLIMINATION VB

Pop Noise 6.5V

HIGH
SIDE
UV
Q

Elimination
` `
IN- VAA+VSS CS
2 COMP HO

20.4V
OTA

GND PWM MODULATOR

ENABLE High Speed,

HV
LEVEL VS
SHIFT HV HV
COMP
UV
LEVEL
SHIFT
FLOATING HIGH SIDE
LEVEL
SHIFT
Low Distortion
6.5V

Level Shift
DETECT 5V REG VCC
UV
VSS
DETECT

DEAD TIME Dead Time

Control
CSD LO
Shut down CHARGE/
DISCHARGE
SD DT

20.4V
HV
Recycle LEVEL
SHIFT
COM

Control Over Current

PROTECTION
CONTROL HV
LEVEL VREF
SHIFT LOW SIDE CS
OCSET Sensing
DT

32
3. PWM and Feedback Technologies
PWM modulator’s functions
• Convert analog or digital audio
signal (PCM) to PWM that has
reasonable switching frequency for
power MOSFET
• Error corrections to improve audio
performance
Demands
• Feedback to reduce DC offset,
distortion and noise floor
• Larger loop gain for lower distortion,
higher power supply rejection ratio
(PSRR)
• Post filter feedback for higher
damping factor
• Switching frequency control for
reduced EMI
33
Natural PWM vs. Self Oscillating PWM

Natural PWM
• Open loop or closed loop
• Fixed frequency

Optional feedback

Self-oscillating PWM
• Closed loop
• Frequency changes with
modulation
• High loop gain
• Fewer components

34
Modern PWM Topologies

Self-oscillating PWM with 2nd order integration Self-oscillating PWM with pulse width control

Global feedback from speaker output Inductor-less PWM

35
IRAUDAMP5 Functional Block Diagram

Typical IR audio evaluation board based on self-oscillating PWM

with 2nd order integration
*
FEEDBACK
IRF6645
VOLUME IC DirectFET
CS3310 ERROR AMP +
INPUT

+ -
+

*
LPF
PWM COMP. L /S L/S

DT SD *

Micro
-
controller
*
CS
OTP DCP

PROTECTION LOGIC
IRS2092

PROTECTION
CONTROL

36
 Chapter 3:
Identifying Problems ~ Performance Measurement
of Class D Amplifier
Identifying Problems

• Proper audio performance measurement is crucial to identify potential

problems.
• Frequency response and THD+N are the minimum basic measure of audio
performance.

Problem Possible Causes

Low frequency response
High frequency response
High harmonic distortion
High noise floor
Audio input, feedback network
Audio input, feedback network,
LPF design
Shoot-through, dead-time,
switching noise coupling
Analog input, switching noise
coupling

38
1. Frequency Response

• Use resistive dummy load.

• Set reference voltage level to 1W output power at 1kHz.
• Sweep sinusoidal signal from 20Hz to 100kHz.
• Take frequency response with various load impedances and without
loading.
International Rectifier A-A FREQUENCY RESPONSE 08/15/06 10:56:54

+1

+0.5

+0

-0.5
d
B
r -1

A
Reference 1kHz=0dB, usually set to 1W output power
-1.5

-2

-2.5

-3
20 50 100 200 500 1k 2k 5k 10k 20k 50k 100k
Hz

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Red Solid 1 Anlr.Level A Left 8Ohm, 1W, 80kHz BW

Frequency Response from 20k to 20 Hz. F4 first to set 0 dBr at 1kHz. The 2 Ch Ampl Function Reading meter BW is
set to <10 Hz & >500kHz so the bandwidth is the same as the Level meter. Optimize for detail.

A-A FREQ RESP.at2

39
Check for..

R117
3.3k 1w
+B
R17
R22 75k
10K R18
U1 C11
9.6k D4 CP8
CP4
Low Frequency
R19 0.1uF,100V 470uF,100V
1 16
R8 VAA CSH
10k
100k 22uF CP6 FET1
R11
2 15
GND VB

5
RCA1 CP1
R2
270R 22uF
20R
High Frequency
3 14 4
IN- HO L1
10uF 3.3k 22uH
1nF 1nF VS1 R24 CH_OUT SPKR1
C7 1nF +
4 13 3
COMP VS 1 CH1
2 -
C4 C6
R3 C12 R30 R31
5 12 D3
SD CSD VCC R20 10, 1W 2.2k
0.47uF, 400V
D1 100R
10uF 4.7R
CP3 20R
6 11 2
VSS LO C13
CP2 -B R25 -B 0.1uF, 400V
22uF R13 7 10
VREF COM

1
10k R21 R23 LED1
R118
3.3k 1w 8 9 R26
OCSET DT 10R 4.7K Blue
10k C14 CP7
R12 IRS2092S DIP 0.1uF 470uF,100V
8.7k R27 CP5
10k 22uF VCC

-B

40
2: THD+N

• THD+N is a sum of harmonic

distortion components and Fundamental THD
noise, i.e. anything except 2nd order harmonic
fundamental spectrum. 3rd order harmonic

• THD is a measure of linearity.

Î Refer to Chapter 4 frequency

Fundamental THD+N
• Noise is a measure of added 2nd order harmonic
errors not depending on the 3rd order harmonic
input signal
Noise
Î Refer to Chapter 5

frequency

41
What is Distortion?

• THD is a simple way to measure non-linearity of the amplifier.

• If the amplifier is not linear, it generates harmonics.

Any repetitive waveforms can be

expressed as a sum of sinusoidal
signal as

Harmonic distortion is a ratio of

rms value of the harmonic
component and the original
waveform.

Total harmonic distortion is a ratio

of rms value of sum of the all
harmonic component and the
original waveform.

42
How to Read THD+N vs. Power

100
T

IRAUDAMP4 THD+N • THD+N vs. Power spells

±30
10 V out noise floor, distortion
and output power in a
1 ±25 shot.
V
%
• Noise floor dominant part
±35
0.1
V has 20dB/dec slope.
0.01 • Reading above noise floor
slope is dominated by
0.001
harmonic distortion.
100m 200m 500m 1 2 5 10 20 50 100 200
W
• To trouble shoot, better to
Noise floor Distortion Clipping start with single channel
operation.

43
Check for..

R117
3.3k 1w
+B
R17
R22 75k
10K R18
U1 C11
9.6k D4 CP8
CP4
dead-time
R19 0.1uF,100V 470uF,100V
1 16
R8 VAA CSH
Ceramic? 100k
R11
22uF
2 15
10k
CP6 FET1
GND VB

5
RCA1 CP1
R2
270R 22uF
20R
LPF
3 14 4
IN- HO L1
10uF 3.3k 22uH
1nF 1nF VS1 R24 CH_OUT SPKR1
C7 1nF +
4 13 3
COMP VS 1 CH1
2 -
C4 C6
R3 C12 R30 R31
5 12 D3
SD CSD VCC R20 10, 1W 2.2k
0.47uF, 400V
D1 100R
10uF 4.7R
CP3 20R
6 11 2
VSS LO C13
CP2 -B R25 -B 0.1uF, 400V
22uF R13 7 10
VREF COM

1
10k R21 R23 LED1
R118
3.3k 1w 8 9 R26
OCSET DT 10R 4.7K Blue
10k C14 CP7
R12 IRS2092S DIP 0.1uF 470uF,100V
8.7k R27 CP5
10k 22uF VCC

-B

Switching noise coupling

44
Audio Measurement Setup

Amplifier
Output

20KHz LPF

Amplifier Output
Filtered

Amplifier
Input

For more information on Class D audio measurement, refer to white paper,

Measuring Switch-mode Power Amplifiers by Bruce Hofer, from //ap.com

45
Audio Measurement Setup with IRAUDAMP7D

Audio Precision System Two with AES-17 Filter

46
AP Substitute

• Old audio analyzers are not designed to

tolerate high frequency noise that is from
carrier signal residual from a Class D
amplifier.
• Place a 3rd order LPF to remove the
switching carrier ingredients in front of the
audio analyzer
• Check measurements are correct by
changing scaling range manually

An Example of an additional pre-LPF for HP8903B

470 680 1K

R1 R2 R3

8
R4 4.7n 2.2n 1n
C1 C2 C3

To HP8903B
Dummy Load

47
 Chapter 4:
Reducing Distortion ~dead-time ~ LPF Designs
Trade-off 1: Dead-time and Distortion

40
34

30

20
1 Positive half cycle: Hard Switching
10

2 4 Cross over region: ZVS

Vout( t ) 0

10

20

30
3 Negative half cycle: Hard Switching
− 34 40
5 .10
4
0 0.001 0.0015 0.002
0 t 0.0021

• Dead-time reduces volt-second therefore voltage gain.

• There is a region that dead-time does not affect around
zero crossing (regions 2 and 4).
• The smaller the dead-time, the lower the distortion.
• Too narrow dead-time could cause shoot-through from
unit-to-unit, temperature and production variations, that
could seriously affect product reliability.
• Audio performance and reliability is NOT a trade-off.

49
Gate Drive and Switching Output

ZVS Region Hard Switching Region

Turning off of the previous MOSFET Turning on dictates output switching
dictates transition in switching waveform.
waveform.

High-side VGS Low-side VGS

Switching Node VS

50
 PWM Switching Cycle

1 High Side ON
+B
+B
VBS

-B
VCC

4 Dead-time 2 Dead-time
? ?
+B +B
VBS VBS

-B -B
VCC VCC

-B
+B
VBS

-B
VCC

3 Low Side ON

51
During Dead-time

• Polarity of IL is always
toward the load
1 • VS follows high side switch
status

• Polarity of IL alternates

2 • VS follows turning off

edges of both high and low
sides
4 • ZVS Î No influence from
dead-time insertion

• Polarity of IL is always
toward the amp
3
• VS follows low side switch
status

Note: Dead-time insertion reduces volt-second of VS. Dead-time inserted in the rising edge of
the high side affects the operating region 1. Dead-time inserted in the rising edge of the low
side affects the operating region 3. As a result, output voltage gets lower than it should be,
causing non-linearity in the output stage.

52
Trade-off 2: Inductor and Distortion

THD characteristic with various inductors

• The quality of the output inductor TTT
100
T TTTT
is crucial to achieve not only the 10

target audio performance but

also efficiency.
1

% 0.1

• Inductance changes with load

current, which causes distortion.
0.01

0.001

• Core saturation increase inductor

ripple significantly that can trigger 0.0001
100m 200m 500m 1 2 5 10 20 50 100 200
W
over current protection.

Inductance

Soft saturation core

Hard saturation core

Load current

Frequency characteristic of IRAUDAMP4

53
LPF Design

• Set corner frequency according to

Inductance and inductor ripple
the bandwidth requirement.
Vbus
• Design LC-LPF with Q=0.7 for a I L PP =
L ⋅ f SW
nominal load impedance to attain flat
frequency response.

Inductor ripple current dictates ZVS region

Note that Lower Switching Frequency

- The higher the corner frequency the

higher the switching carrier leakage
Higher Ripple Current
- The lower the corner frequency the
Higher Corner Frequency
bigger the inductance size

Higher Ripple Current

54
LPF Design

1. Decide the order of the filter based on the ⎧⎪ ⎛ f ⎞ 2 N ⎫⎪

attenuation of the switching frequency given At = 10 ⋅ log ⎨1 + ⎜⎜ ⎟⎟ ⎬
⎪⎩ ⎝ f C ⎠ ⎪⎭
by:

2nd order LPF 3rd order LPF 4th order LPF

2. Design Butterworth filter

# of Order Lk1 Ck1 Lk2 Ck2

RL
Ln = Lk n
2 ⋅ π ⋅ fC
2 1.414214 0.707107 - -

Ck n 3 1.5000 1.3333 0.5000 -

Cn =
2 ⋅ π ⋅ f C ⋅ RL 4 1.530734 1.577161 1.082392 0.382683

3. Design Zobel network

55
Choosing Inductor for LPF

Air Coil Large, High DCR, Low

distortion, Leakage flux

Drum Core Small, Leakage Flux, Low DCR

(Ferrite, Open Circuit)

Drum Core Small, Hard saturation, Low

DCR
(Ferrite, Closed Circuit)

Toroidal Core Soft saturation, Lower iron loss

(Iron Powder)

NOTE • Determine IRMS rating for temperature

rise condition with 1/8 rated power
• Ferrite core is suitable for smaller size
• Determine peak current (ISAT) based
• Iron powder is suitable for high power
on maximum load current

56
Choosing Capacitor for LPF

Polyester film, winding Small, High ESR

Ceramic High dielectric type has large

distortion, lower AC ratings

Polyester, non-inductive Small, lower AC voltage rating

Polypropylene, non-inductive Low dissipation factor, large

size, low distortion

NOTE
• Do not use winding structure types. Use stacked structure.
• Check AC voltage ratings at highest audio frequency.

57
LPF Design Example

+
4

Corner frequency: 40kHz +

2
8Ω
+

Load impedance: 4 ohms d 0

B
4
-
Ω
r 2

Output power: 250W (32Vrms, 11Apeak) A

-
4
-
6

22uH -
8

-
10 2 5 10 20 50 1 2 5 10 20 50 200
0 0 0 0 0 k Hz k k k k k k

0.1uF 4
0.47uF
10

Sagami 7G17B220 EPCOS B32652A4474J

22µH, 13A, 10mΩ Polypropylene, 0.47µF, 400VDC
Ferrite, closed circuit with
inner gap
58
 Chapter 5:
Reducing Noise ~ Noise Isolation Technique ~ PCB
Design
Sources of Noise in Class D Amplifier
Switching noise
Switching noise is generated by the
output MOSFET switching in wide
range of frequency spectrum above
the audible range. The amount of
switching noise depends on:
• Switching speed
• Size of the MOSFET
• Load current
• PCB layout
• Locations and quality of bypass
capacitors
Audio noise
Audio noise is a noise ingredient in
audible frequency range in the speaker
output. Major causes of audio noise
includes:
• Noise figure (NF) in the front-end
error amplifier
• Jitter in switching time
• RFI noise from switching noise
injection
• Thermal noise from resistors
• Hum noise (AC line 60Hz and its
harmonics) from ground loop
60
Noise Reduction Strategy

1. Minimize noise source in switching stage

2. Maximize noise immunity in analog stage

3. Minimizing noise coupling from switching stage to analog stage

61
1: Minimizing Noise Source

Self-commutation at idling. If rings,

check for shoot-through, check dead
time.
Idling (ZVS) Hard-switching
Reverse recovery charge, Qrr, causes
hard switching that triggers resonance
in stray reactance. Rings triggered by Qrr

Qrr is a function of di/dt, drain current

and die temperature. Slower switching
helps to reduce Qrr.
Stray inductance is where excessive Low dV/dt driven by High dV/dt driven by
energy is stored. Look for optimum inductor and Coss MOSFET turn on

trace layouts to minimize stray

inductance.
Careful component selection is key to
minimize stray reactance.

62
Reducing Noise with RC Snubber

RC voltage snubber is used to

suppress voltage spikes in switching
and power supply nodes.
Resistor in RC snubber absorbs
energy from reactance by damping
resonance.
To maximize effectiveness of a
snubber
- Resistance should be close to
impedance of resonant element.
- Capacitance should be larger than
resonant capacitor.
- Capacitance should be small
enough not to cause too much
dissipation in the resistor.
Power dissipation from the resistor
P= 2*f*(½CV2)

63
Snubber and THD

Adding snubber usually improves

THD+N.
Change should be in hard switching
region.
Basic approach: Make all efforts to
minimize stray inductances and current
loop areas (minimize resonant energy), 1

then tailor snubber values. 0.5

Pay attention to dissipation at snubber. 0.2

0.1

0.05

%
0.02

0.01

0.005

0.002

0.001
100m 200m 500m 1 2 5 10 20 50 100 300
W

Sweep Trace Color Line Style Thick Data Axis Comment

1 1 Red Solid 2 Anlr.THD+N Ratio Left original+150p+10ohighside

2 1 Blue Solid 2 Anlr.THD+N Ratio Left original (low side snubber onl

64
2: Maximizing Noise Immunity

NOTE
• Ground can be
a route of noise
Input RF Filter injection to error
Feedback LPF
• Filter out HF amplifier
Differential Input RFI Filter
noise and • Weed out high
reduce node • Prevent RFI causing frequency
impedance audio frequency spectrum to
at high interferences from avoid TIM
frequency switching rings distortion in the
error amplifier

65
RFI

Analog stage uses non-linear Diode amplitude detector

components such as diode, BJT and

FET.
When a non-linear component
receives high frequency components, it
detects envelop information that could
fall into audio frequency range
(amplitude modulation envelop
detector).
When non-linear components receives
high frequency components along with
audio signal, it could shift operating
bias point and cause distortion in audio
signal.

66
3: Minimizing Noise Coupling

There are functional blocks that

generate noise. There are functional
blocks that are sensitive to noise. The
PCB designer should identify them and Noise Sensitive Nodes
find out the best combination of the
placement based on these facts and
mechanical and thermal requirements.
Noise sensitive functions:
- The audio input circuitry
- The PWM control circuitry
- Noise generating functions
- The gate driver stage Noise Generating Nodes
- The switching stage

67
Switching Noise Injection Example

Noise Coupling from VS

Insufficient Bypass Cap
Original Design
(IRAUDAMP7D)

68
PCB Design Tips

The first and most important step for

PCB designers is to group components
dedicated to a common purpose, such
Key Components Layout Example
as: (IRAUDAMP7D)

- the audio input circuitry

- the PWM control circuitry
- the gate driver stage
- the switching stage

By identifying which components

belong together, place the remaining
circuitry by coupling them appropriately GATE MOSFET LPF
PWM
DRIVE
into open areas of the board.
Placement Determines Maximum Performance !

69
PCB Layout Example

Audio Input, Error Amplifier

Note that
• Separation
between analog
and switching
sections
• Minimized trace
impedances with
planes in power
section
• No overlap
between switching
nodes and analog
nodes

Gate Switching Nodes Load Current Paths

Analog Section Drive Power Section
Section

70
APPENDIX
Simulation of a Simple Class D Amplifier (SIMetrix)

Feedback
47k 0
IC
R1

1n 1n

C1 C2
E2-N
220
10u 3.3k R2

C8 R8
10k 2.5*(1+tanh(1e4*v(n1,n2)))
ARB1 HC04D HC04D
N1OUT DELAY
ARB1-OUT U5 HO S1
N2 250n D3
U1 U2 IDEAL 50
AC 1 0 Sine(0 1 5k 0 0) E3 LO V4
V5

18u

L1
470n 4 sp out
S2 C3 R6

Integrator Comparator Delay Gate Driver D4

IDEAL

Note LPF
50
V1

• Disable initial DC operating point MOSFET

analysis Simulation set up with SIMetrix

• Add initial value in the feedback loop

to start off oscillation
• Get into further work once basic ideal
Trial version of SIMetrix can be downloaded from:
model is confirmed http://www.catena.uk.com/

72
Simulation Result Example

100

80
Switching Node

60

40
V

20
Gate and other internal nodes

-20
Speaker Output

-40

150 200 250 300 350 400 450

T im e / µ S e c s 5 0 µ S e c s / d iv

73
END

February 19, 2009