COA MCQs

I .
Multiple Choice Questions on Microprocessors

1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
Explanation: Machine language instruction format has one or more fields. The first one is the operation
code field.
2. A machine language instruction format consists of

a) Operand field
b) Operation code field
c) Operation code field & operand field
Explanation: Machine language instruction format has both the fields.
3. The length of the one-byte instruction is

a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Explanation: This format is only one byte long.
4. The instruction format ‘register to register’ has a length of

a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Explanation: This format is 2 bytes long.
5. The R/M field in a machine instruction format specifies

a) another register
b) another memory location
c) other operands
d) all of the mentioned
Explanation: The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies another
register or memory location i.e. the other operand.
6. In a machine instruction format, S-bit is the

a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned.
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of
operation.
7. The bit which is used by the ‘REP’ instruction is

a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Explanation: The Z-bit is used by the REP instruction to control the loop.
8. If a W-bit value is ‘1’ then the operand is of

a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-bits.
9. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
Explanation: The sequential control flow instructions follow sequence order in their execution.
10. The instructions that transfer the control to some predefined address or the address specified in the
instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
Explanation: The control transfer instructions transfer control to the specified address.
“Addressing Modes of 8086”
11.The instruction, MOV AX, 0005H belongs to the address mode

a) register
b) direct
c) immediate
d) register relative
Explanation: In Immediate addressing mode, immediate data is a part of instruction and appears in
the form of successive byte or bytes
12. The instruction, MOV AX, 1234H is an example of
a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
Explanation: Since immediate data is present in the instruction.
13. The instruction, MOV AX, [2500H] is an example of

a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
Explanation: Since the address is directly specified in the instruction as a part of it.
14. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
Explanation: Since register is used to refer the address.
15. The instruction, MOV AX,[BX] is an example of

a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
Explanation: Since the register used to refer to the address is accessed indirectly.
16. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest of
them, address is stored.
17. The addressing mode that is used in unconditional branch instructions is

a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
Explanation: In intrasegment indirect mode, the branch address is found as the content of a register
or a memory location.
18. If the location to which the control is to be transferred lies in a different segment other than the current
one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
Explanation: In intersegment mode, the control to be transferred lies in a different segment
19. The instruction, JMP 5000H:2000H; is an example of

a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
Explanation: Since in intersegment direct mode, the address to which the control is to be transferred
is in a different segment.
20. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
Explanation: The effective address is formed by adding the contents of both base and index registers
to a default segment.
“Instruction Set of 8086/8088 – 1”
21. The instruction that is used to transfer the data from source operand to destination operand is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
Explanation: These instructions are used to copy and transfer the instructions.
22. Which of the following is not a data copy/transfer instruction?

a) MOV
b) PUSH
c) DAS
d) POP
Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

23. The instructions that involve various string manipulation operations are
a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
Explanation: The string instructions perform operations on strings such as load, move, scan,
compare etc.
24. Which of the following instruction is not valid?

a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
Explanation: Both the source and destination operands cannot be memory locations except for
string instructions.
25. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Explanation: The actual current stack-top is always occupied by the previously pushed data. So,
the push operation decrements SP by 2 and then stores the two bytes contents of the operand onto
the stack.
26. The instruction that pushes the contents of the specified register/memory location on to the stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
Explanation: Since PUSH operation transfers data to stack from a register or memory location.
27. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Explanation: The actual current stack top is poped into the specific operand as the contents of
stack top memory is stored in AL&SP and further contents of the memory location pointed to by
SP are copied to AH & SP.
28. The instructions that are used for reading an input port and writing an output port respectively are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
Explanation: The address of the input/output port may be specified directly or indirectly.
Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose address
is in DX and stores it in AX
Example for output port: OUT 03H, AL; This sends data available in AL to a port whose address
is 03H.
29. The instruction that is used for finding out the codes in case of code conversion problems is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
Explanation: The translate(XLAT) instruction is used to find codes.
30. The instruction that loads effective address formed by destination operand into the specified source
register is
a) LEA
b) LDS
c) LES
d) LAHF
Explanation: The instruction, LEA loads effective address and is more useful for assembly
language rather than for machine language.
31. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to observe
the status of all the condition code flags(except overflow flag) at a time.
32. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF
Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the stack.
33. The instruction that loads the flag register completely from the word contents of the memory location is
a) PUSH
b) POP
c) PUSHF
d) POPF
Explanation: POPF is pop flags to stack.
34. The instruction that adds immediate data/contents of the memory location specified in an
instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV
Explanation: ADD instruction adds the data.
35. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.
36. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
Explanation: The DEC instruction decrements the contents of a specified register/memory

location by 1.
37. The instruction that enables subtraction with borrow is

a) DEC
b) SUB
c) SBB
d) None of the mentioned
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the
destination operand.
38. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.
39. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
Explanation: The source operand is the element which is data or data stored memory location on
which operation is performed.
40. In general, the destination operand of an instruction can be

a) memory location
b) register
c) immediate data
d) memory location and register
Explanation: Since the destination should be able to store the data, immediate data cannot be
considered as a destination operand.
41. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
Explanation: For comparison, the instruction CMP subtracts source operand from destination
operand.
42. During comparison operation, the result of comparing or subtraction is stored in

a) memory
b) registers
c) stack
d) no where
Explanation: The result of subtraction operation is not stored anywhere during a comparison.
43. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are
called as “Unpacked BCD arithmetic instructions”.
44. Which of the following is a mnemonic?

a) ADD
b) ADC
c) AAA
d) ADD & ADC
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.
45. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before dividing the two
unpacked BCD digits.
46. The expansion of DAA is

a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
Explanation: This instruction performs conversion operation.
47. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid
BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
Explanation: In this conversion, the result has to be only in AL.
48. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.
49. The mnemonic that is placed before the arithmetic operation is performed is
a) AAA
b) AAS
c) AAM
d) AAD
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL.
50. The Carry flag is undefined after performing the operation

a) AAA
b) ADC
c) AAM
d) AAD
Explanation: Since the operation, AAD is performed before division operation is performed, the
carry flag, auxiliary flag and overflow flag are undefined.
51. The instruction that performs logical AND operation and the result of the operation is not available is
a) AAA
b) AND
c) TEST
d) XOR
Explanation: In the TEST instruction, the logical AND operation is performed and the result is
not stored but flags are affected.
52. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed
into LSB and the MSB of the operand is pushed into carry flag.
53. . The instructions that are used to call a subroutine from the main program and return to the main
program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto the
stack, before the control is transferred to the procedure. At the end of the procedure, the RET
instruction must be executed to retrieve the stored contents of IP & CS registers from a stack.
54. The instruction that unconditionally transfers the control of execution to the specified address is
a) CALL
b) JMP
c) RET
d) IRET
Explanation: In this the control transfers to the address specified in the instruction and flags are
not affected by this instruction.
55. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of the
‘halt’ state.
56. NOP instruction introduces

a) Address
b) Delay
c) Memory location
Explanation: NOP is the No operation. It means that the processor performs no operation for the
clock cycle and thus there exists a delay.
57. Which of the following is not a machine controlled instruction?

a) HLT
b) CLC
c) LOCK
d) ESC
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry
Flag.
“Assembler Directives and Operators”
58. The assembler directives which are the hints using some predefined alphabetical strings are given to
a) processor
b) memory
c) assembler
d) processor & assembler
Explanation: These directives help the assembler to correctly understand the assembly language
programs to prepare the codes.
59. The directive used to inform the assembler, the names of the logical segments to be assumed for
different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.
60. The directive that marks the end of an assembly language program is
a) ENDS
b) END
c) ENDS & END
Explanation: The directive END is used to denote the completion of the program.
61. The directive that marks the end of a logical segment is

a) ENDS
b) END
c) ENDS & END
Explanation: The directive ENDS is used to end a segment where as the directive END is used to
end the program.
62. The directive that updates the location counter to the next even address while executing a series of
instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
Explanation: The directive updates location counter to next even address if the current location
counter contents are not even.
63. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
Explanation: If an ORG is written then the assembler initiates the location counter to keep the
track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H
64. The directive that marks the starting of the logical segment is
a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
Explanation: The directive SEGMENT indicates the beginning of the segment.
65. The recurrence of the numerical values or constants in a program code is reduced by
a) ASSUME
b) LOCAL
c) LABEL
d) EQU
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed
instead of the numerical value in the entire program code.
66. The labels or constants that can be used by any module in the program is possible when they are
declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used by
any module in the program.
“Do’s and Don’ts While Using Instructions”
67. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
Explanation: The logic required for implementing a program must be visualized clearly which is
possible by flowchart and algorithm.
68. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register
Explanation: Only one memory operand can be specified in one instruction.
69. The instruction that is not possible among the following is

a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H
Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.
70. The instruction that is not possible among the following is

a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].
Explanation: Both the operands cannot be memory operands.
71. Both the operands source and destination of an instruction cannot be

a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location
Explanation: Since destination operand should not be immediate data.
72. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers
Explanation: Segment registers are not allowed as operands for arithmetic and logical
instructions.
73. The operands of an instruction cannot be

a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands
Explanation: Both the operands should not be immediate operands and memory operands.
“Programming With An Assembler”
74. The disadvantage of machine level programming is

a) time consuming
b) chances of error are more
c) debugging is difficult
Explanation: The machine level programming is complicated.
75. The coded object modules of the program to be assembled are present in
a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It contains the
coded object modules of the program to be assembled
76. The extension that is essential for every assembly level program is
a) .ASP
b) .ALP
c) .ASM
d) .PGM
Explanation: All the files should have the extension, .ASM.
77. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
Explanation: Before starting the process of entering a small program on PC, ensure that all the
files namely Norton’s editor, assembler, linker and debugger are available in the same directory in
which work is been done.
78. The listing file is identified by

a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
Explanation: The listing file is automatically generated in the assembly process and is identified
by the entered or source file name and an extension .LST.
79. . The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid object
file.
80. The listing file contains

a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.
81. DEBUG.COM facilitates the

a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble shooting.
82. DEBUG is able to troubleshoot only

a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
Explanation: The DEBUG may be used either to debug a source program or to observe the results
of execution of an .EXE file
“Stack”
83. The Stack follows the sequence

a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
Explanation: The stack follows last-in-first-out sequence.
84. If the processor is executing the main program that calls a subroutine, then after executing the main
program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is
transferred to the subroutine address.
85. The stack is useful for

a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
Explanation: Stack is used for temporary storage of contents of registers and memory locations,
status of registers.
86. The Stack is accessed using

a) SP register
b) SS register
c) SP and SS register
Explanation: The stack is accessed using a pointer that is implemented using SP and SS registers.
87. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
Explanation: The data is stored from top address of the stack and is decremented by 2.
88. While retrieving data from the stack, the stack pointer is
a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
Explanation: The data in the stack, may again be transferred back from a stack to register. At
that time, the stack pointer is incremented by 2.
89. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
Explanation: The data is pushed into the stack while loading the stack.
90. The reverse process of transferring the data back from the stack to the CPU register is known as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
Explanation: The data retrieved from stack is called popping off.
91. The books arranged one on the other on a table is an example of

a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
Explanation: If the books are arranged one on the other, then the book that is placed last will be
the first out.
92. The PID temperature controller using 8086 has

a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
Explanation: Since PID temperature controller has steps that need to be sequentially executed
such as sampling the output, conversion of a signal with ADC, finding errors, deriving control
signals and applying the control signal to control flow of energy.
“Stack Structure of 8086/8088”

93. The stack pointer register contains
a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
Explanation: The stack pointer register contains the offset of the address of the stack segment.
94. The stack segment register contains

b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
Explanation: The stack segment register contains base address of the stack segment in the
memory. The stack pointer register (sP) and stack segment register (SS) together address the
stack-top.
95. PUSH operation

a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Explanation: Each PUSH operation decrements the SP (Stack Pointer) register.
96. POP operation

a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
Explanation: Each POP operation increments the SP ( Stack Pointer) register.
97. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last
Explanation: The data can be retrieved by POP operation and as in stack, the data that is pushed
at the end must be popped off first.
98. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK

the ASSUME directive directs to the assembler the
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
Explanation: The directive ASSUME facilitates to name the segments with the desired name that
is not a mnemonic or keyword.
99. When a stack segment is initialized then

a) SS and SP are initialized
b) only SS is initialized
c) only SP is initialized
d) SS and SP need not be initialized
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be initialized.
100. The number of PUSH instructions and POP instructions in a subroutine must be
a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
Explanation: The number of PUSH instructions must be equal to the number of POP instructions.
101. 8086 does not support

a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
Explanation: The 8086 microprocessor does not support direct BCD packed operations.
102. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K bytes.
“Interrupts and Interrupt Service Routines”
103. While CPU is executing a program, an interrupt exists then it

a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
Explanation: An interrupt function is to break the sequence of operation.
104. An interrupt breaks the execution of instructions and diverts its execution to
a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After executing
ISR, the control is transferred back again to the main program.
105. While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
Explanation: If an interrupt occurs while executing a program, and the processor is executing the
interrupt, if one more interrupt occurs again, then it is called a nested interrupt.
106. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to handle
them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt
processing ability.
107. NMI stands for

a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
Explanation: NMI is the acronym for nonmaskable interrupt.
108. If any interrupt request given to an input pin cannot be disabled by any means then the input pin
is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request at
NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.
109. The INTR interrupt may be

a) maskable
b) nonmaskable
c) maskable and nonmaskable
Explanation: the INTR (interrupt request) is maskable or can be disabled.
110. The Programmable interrupt controller is required to

a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip
called programmable interrupt controller is required to handle them.
111. The INTR interrupt may be masked using the flag

a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If
interrupt flag, IF=0, then the processor ignores the service.
“Interrupt Cycle of 8086/8088”
112. If an interrupt is generated from outside the processor then it is an

a) internal interrupt
b) external interrupt
c) interrupt
Explanation: If an external device or a signal interrupts the processor from outside then it is an
external interrupt.
113. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
Explanation: The internal interrupt is generated internally by the processor circuit or by the
execution of an interrupt instruction.
114. Example of an external interrupt is

a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
Explanation: Since the keyboard is external to the processor, it is an external interrupt.
115. Example of an internal interrupt is

a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
Explanation: Since the interrupts occur within the processor itself, they are called internal
interrupts.
116. The interrupt request that is independent of IF flag is

a) NMI
b) TRAP
c) Divide by zero
Explanation: These requests are independent of IF flag.
117. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the
type of the interrupt that may be passed to the internal structure of the CPU from an interrupt
controller in case of external interrupts
118. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.
119. After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
Explanation: If the trap flag is set then the processor enters the single step execution mode. After
the execution, the trap flag is cleared.
120. At the end of ISR, the instruction should be

a) END
b) ENDS
c) IRET
d) INTR
Explanation: After the execution of the ISR, the control must go to the previous program (maybe
main program) which was being executed. To execute it, IRET is placed at the end of ISR.
121. When the CPU executes IRET,

a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which were
saved at the stack by the CALL instruction are retrieved to the respective registers.
“Non Maskable Interrupt and Maskable Interrupt (INTR)”
122. The interrupt for which the processor has the highest priority among all the external interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the
external interrupts.
123. The interrupt for which the processor has highest priority among all the internal interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts
except the Divide By Zero (Type 0) exception.
124. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
Explanation: When NMI is activated, the current instruction being executed is completed and
then NMI is served. In the case of string instructions, it is served after the complete string is
manipulated.
125. The NMI pin should remain high for atleast

a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
Explanation: The NMI pin should remain high for at least 2 clock cycles and need not be
synchronized with the clock for being sensed.
126. The INTR signal can be masked by resetting the

a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
Explanation: The INTR signal can be masked by resetting the interrupt flag.
127. For the INTR signal, to be responded to in the next instruction cycle, it must go ________ in the
last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
Explanation: The INTR signal must go high in the clock cycle of the current instruction in order
to respond in the next instruction cycle.
128. The status of the pending interrupts is checked at
a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
Explanation: At the end of each instruction, the status of the pending interrupts is checked.
129. Once the processor responds to an INTR signal, the IF is automatically

a) set
b) reset
c) high
d) low
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If the
processor wants to respond to any type of INTR signal further then, the IF should again be set.
130. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then till the
start of the next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.
131. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and remains in
it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
Explanation: The INTA (active low) goes low and remains low for two clock cycles before
returning back to the high state.
“Interrupt Programming, Passing Parameters to Procedures, Handling Programs of Size More

Than 64KB”
132. The method of defining the interrupt service routine for software is
a) same as that of hardware
b) difficult than hardware
c) easier than software
Explanation: For both software and hardware, the method of defining the interrupt service
routine is the same.
133. While programming for any type of interrupt, the interrupt vector table is set
a) externally
b) through a program
c) either externally or through the program
d) externally and through the program
Explanation: The programmer must, either externally or through the program, set the interrupt
vector table for that type preferably with the CS and IP addresses of the interrupt service routine.
134. To execute a program one should

a) assemble the program
b) link the program
c) apply external pulse
Explanation: To execute a program, first assemble it, link it and then execute it. After execution, a
new file RESULT is created in the directory. Then external pulse is applied to IRQ2 pin, and this
will again cause the execution of ISR into the file.
135. Procedures are also known as

a) macros
b) segment
c) subroutines
d) none
Explanation: Procedures are also known as subroutines.
136. Procedures, for their execution, require

a) input data
b) output data
c) constants
d) input data or constants
Explanation: Procedures require input data or constants for their execution. Their data or
constants may be passed to the subroutine by the main program.
137. The technique that is used to pass the data or parameter to procedures in assembly language
program is by using
a) global declared variable
b) registers
c) stack
Explanation: The techniques that are used to pass the data or parameter to procedures are by
using global declared variable, registers of CPU, memory locations, stack, PUBLIC & EXTRN.
138. If a procedure is interactive, then
a) it accepts inputs directly from input devices
b) it uses global declared variable technique
c) it uses stack
d) it uses memory locations
Explanation: If a procedure is interactive, then it accepts the inputs directly from input devices.
139. For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must be
declared PUBLIC in the
a) subroutine
b) procedure
c) main routine
d) main routine and subroutine
Explanation: For passing the parameters to procedures, it must be declared PUBLIC in the main
routine and the same should be declared EXTRN in the procedure.
140. The technique to estimate the size of an executable program, before it is assembled and linked is
a) memory location technique
b) global variable technique
c) stack
d) none
Explanation: There is no technique to estimate the size of an executable program before it is

assembled and linked
141. To estimate the size of an executable program before it is assembled and linked, the
programming methodology concerned is by writing
a) programs with more than one segment for data and code
b) programs with FAR subroutines each of size up to 64KB
c) programs with more than one segment for stack
Explanation: By writing programs with more than one segment for data, code or stack or by
writing programs with FAR subroutines each of size 64KB, the size of an executable program can
be estimated.
“Macros”
142. If a number of instructions are repeating through the main program, then to reduce the length of
the program, __________ is used.
a) procedure
b) subroutine
c) macro
Explanation: For a certain number of instructions that are repeated in the main program, when
macro is defined then the code of a program is reduced by placing the name of the macro at which
the set of instructions are needed to be repeated.
143. The process of assigning a label or macroname to the string is called

a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
Explanation: The process of assigning a label to the string is called defining a macro.
144. A macro within a macro is called

a) macro-within-macro
b) nested macro
c) macro-in-macro
Explanation: A macro may be called from inside a macro. This type of macro is called nested
macro.
145. A macro can be defined as

a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
Explanation: A macro can be defined anywhere in a program.
146. A macro can be used as ________

a) in data segment
b) to represent directives
c) to represent statements
147. The end of a macro can be represented by the directive.

a) END
b) ENDS
c) ENDM
d) ENDD
Explanation: The ENDM directive marks the end of the instructions or statements sequence
assigned with the macro name.
148. Inserting the statements and instructions represented by macro, directly at the place of the
macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
Explanation: Inserting the statements and instructions at the place of macroname, in the program,
is known as calling a macro.
149. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
Explanation: The time required for execution of a macro is less than that of procedure as it does
not contain CALL and RET instructions as the procedures do.
150. Which of the following statements is incorrect?

a) complete code of instruction string is inserted at each place, wherever the macroname appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
Explanation: Macro does not require stack memory and hence has less time for execution.
“Timings and Delays”
151. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the
microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
Explanation: The duration of execution of the loop is the product of number of clock cycles and
the period of the clock cycle at which microprocessor is running.
152. The number of instructions actually executed by the microprocessor depends on the
a) stack
b) loop count
c) program counter
d) time duration
Explanation: As the microprocessor executes each instruction corresponding loop counter value
decreases and the microprocessor executes the instructions till the loop counter becomes zero.
153. The step included in generating delays is

a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
Explanation: The delays can be generated step wise.
154. The Count, N can be defined as

a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
Explanation: The count N can be defined as the required time delay by the duration for execution
of the loop once. Count, N = required delay (Td)/duration for execution of the loop once (n*T).
155. The maximum count value of 16-bit count register puts a limitation on
a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the
limitation on the maximum delay that can be generated using the instructions.
156. When large delays are required, then to serve the purpose
a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used
Explanation: One or more count registers can be used to serve large delays.
“Semiconductor Memory Interfacing”
157. The semiconductor memories are organized as __________ dimension(s) of array of memory
locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
Explanation: The semiconductor memories are organised as two dimensions of an array which
consists of rows and columns.
158. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
Explanation: The bits in a selected location are accessible using data bus.
159. To address a memory location out of N memory locations, the number of address lines required
is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For
addressing 4K bytes of memory, 12 address lines are required since log(4KB)
=log(4*1024)=log(212)=12.
160. If the microprocessor has 10 address lines, then the number of memory locations it is able to
address is
a) 512
b) 1024
c) 2048
d) none
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.
161. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.
162. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.
163. In most of the cases, the method used for decoding that may be used to minimise the required
hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
Explanation: In general, linear decoding is used to minimise the required hardware.
164. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.
165. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in
RAM.
166. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are
selected.
“Dynamic RAM Interfacing”
167. The advantage of dynamic RAM is

a) high packing density
b) low cost
c) less power consumption
Explanation: The dynamic RAM is advantageous than the static RAM as it has a higher packing
density, lower cost and less power consumption.
168. Whenever a large memory is required in a microcomputer system, the memory subsystem is
generally designed using
a) Static RAM
b) Dynamic RAM
c) Both static and dynamic RAM
d) ROM
Explanation: Dynamic RAM is preferred for large memory.
169. If a typical static RAM cell requires 6 transistors then corresponding dynamic RAM requires
a) 1 transistor along with capacitance
b) 2 transistors along with resistance
c) 3 transistors along with diode
d) 2 transistors along with capacitance
Explanation: The hardware complexity of dynamic RAM is lesser than that of static RAM.
170. To store the charge as a representation of data, the basic dynamic RAM cell uses
a) resistor
b) capacitor
c) diode
d) transistor
Explanation: The basic dynamic RAM cell uses capacitance to store the charge as a representation
of data. This capacitor is manufactured as a diode that is reverse biased so that the storage
capacitance is obtained.
171. The process of refreshing the data in the RAM to reduce the possibility of data loss is known as
a) data cycle
b) regain cycle
c) retain cycle
d) refresh cycle
Explanation: The data storage in RAM which is capacitance (reverse-biased diode) may have a
leakage current that tends to discharge the capacitor giving rise to possibility of data loss. To
avoid this, the data must be refreshed after a fixed time interval regularly.
172. The field in which dynamic RAM is more complicated than static RAM is
a) complexity
b) interfacing circuit
c) execution unit
d) cost
Explanation: The refresh mechanism and the additional hardware required makes the interfacing
circuit of dynamic RAM more complicated than that of static RAM.
173. Memory refresh activity is

a) initialised by processor
b) initialised by external bus master
c) initialised by refresh mechanism
d) initialised either by processor or by external bus
Explanation: The refresh operation is independent regular activity that is initialised and carried
out by the refresh mechanism.
174. The number of memory chips that are enabled at a time for refresh activity is
a) 2
b) 4
c) 8
d) more than 1
Explanation: More than one memory chip can be enabled at a time to refresh activity to reduce
the number of total memory refresh cycles.
175. A timer that derives pulse for refreshing action or time for which a dynamic RAM cell can hold
data charge level practically constant is
a) constant timer
b) data managing timer
c) refresh timer
d) qualitative timer
Explanation: Refresh timer derives a pulse for refreshing action after each refresh interval which
can be qualitatively defined as the time for which a dynamic RAM cell can hold data charge level
practically constant.
176. If ‘n’ denotes the number of rows that are to be refreshed in a single refresh interval, ‘td’ denotes
the range of time it may take then, refresh time (tr) can be defined as
a) n*td
b) td/n
c) n/td
d) tdn
Explanation: Refresh time is the ratio of time duration taken for refreshing to the number of rows
that are refreshed. Refresh frequency is the reciprocal of refresh time.
“Interfacing I/O Ports”
177. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
Explanation: Since joystick is an input device, it reads data from the external devices.
178. The example of output device is

a) CRT display
b) 7-segment display
c) Printer
Explanation: The output device transfers data from the microprocessor to the external devices.
179. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
Explanation: The input activity is similar to read operation and the output activity is similar to
write operation.
180. The operation, IOWR (active low) performs

a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
Explanation: IOWR (active low) operation means writing data to an output device and not an
input device.
181. The latch or IC 74LS373 acts as
a) good input port
b) bad input port
c) good output port
d) bad output port
Explanation: If the output port is to source large currents, the port lines must be buffered. So, the
latch is used as it acts as a good output port.
182. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
Explanation: More current should not be sourced or sinked from data lines while reading to avoid
loading.
183. To avoid loading during read operation, the device used is
a) latch
b) flipflop
c) buffer
d) tristate buffer
Explanation: A tristate buffer is used as an input device to overcome loading.
184. The chip 74LS245 is

a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be used
as an 8-bit input port. But while using as an input device, only one direction is useful.
185. . In 74LS245, if DIR is 1, then the direction is from

a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).
187. In memory-mapped scheme, the devices are viewed as

a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and are
addressed likewise.
187 . Which of the following is not correct?
a) Bootstrap is a technique or device for loading first Instruction

b) An instruction is a set of bits that defines a computer operation
c) Bus is a group of wires
d) an interrupt signal is required at the start of every program.
Explanation: An interruption is required fr interruption of main program to perform a

subroutine. It may be used at the start of some program as per requirement but it is not
mandatory at start of every program.
188. The number of output pins in 8085 Microprocessor are
a)40
b) 27
c) 21
d) 19
Explanation: 8085 there are 40 pins out of which 27 pins are output pins and rest 13 are including
clock input , power supply and other inputs.
189 Which of the following statements for Intel 8085 is correct?
a) PC specifies the number of instructions executed so far

b) PC specifies the address of the instruction being executed
c) PC specifies the address of the instruction last executed
d) PC specifies the address of the instruction to be executed.
Explanation: PC always indicates the address of the instruction to be fetched
190 Which language could be used for programming FPGA?
a) Both Verilog and VHDL

b) Verilog
c) VHDL
d) None of these
Explanation: Both Verilog and HDL are used for programming FPGA , these are case insensitive
hardware descriptive languages.
191 FPGA means
a) Field Programmable Gate Array

b) Forward Programmable Gate Array
c) Forward Parallel Gate Array
d) Field Parallel Gate Array
Explanation: Field Programmable Gate Array (FPGA) is the re-configurable hardware, which
consists of millions of logic gates which could be arranged according to the user's demand. They
also have much higher frequency compared to micro controllers.
192. Which of the following can be accessed only sequentially?
a) Floppy disk
b) Hard disk
c) Magnetic tape
d) ROM
Explanation: Magnetic tape can be accessed only sequentially.
193. 8085 has 6 sign flags.
a) True
b) False
c)
Explanation: It has one sign flag S.
Sign Flag (S) – After any operation if the MSB (B(7)) of the result is 1, it indicates the number is
negative and the sign flag becomes set, i.e. 1. If the MSB is 0, it indicates the number is positive
and the sign flag becomes reset i.e. 0.
From 00H to 7F, sign flag is 0 (7F)16 = (01111111)2
From 80H to FF, sign flag is 1 (FF)16 = (11111111)2
1- MSB is 1 (negative)
0- MSB is 0 (positive)
194. JCOKE = 3
JCOKE = JCOKE + 1
GO TO (5, 8, 9, 11, 15, 16 18, 20) JCOKE.
After the execution of above statement, the control is transferred to statement number
a) 8
b) 11
c) 16
d) 20
Explanation: It is a computed GO TO statement. Since J COKE = 3 + 1 = 4, the control is

transferred to statement 11.
195. . Binary number 1101.101 is equivalent to decimal number?
a) 13.5
b) 13.75
c) 13.625
d) 13.875
Explanation: Binary .101 equals 0.625 in decimal.

196. Expression ++i is equivalent to
a) i = i + 2
b) i = i + 1
c) i = i - 1
d) i = i + i + i
Explanation: i is incremented by 1.
197. To multiply a number by 8 in 8085 we have to use RAL instruction
a) once
b) twice
c) thrice
d) four times
Explanation: When RAL instruction is used once, the number is doubled.
198. The size of cache memory in most microcomputers is about
a) a few bytes
b) a few kilobytes
c) a few megabytes
d) a few gigabytes
Explanation: Size of Cache memory varies from about 16 K bytes to about 256 K bytes.
199.. During processing the instructions, data, intermediate results and final results in a computer are
held in
a) CPU
b) ALU
c) Primary memory
d) Secondary memory
Explanation: Primary memory holds these during processing of instructions.
200. Z flag is reset if an ALU operation results in 0.
a) True
b) False
Explanation: Z flag is set if ALU operation results in zero.
II.Micro-controller Multiple Choice Questions &Answers (MCQs)
TOPIC 1 : “Introduction to Microcontroller”.
201. A microcontroller at-least should consist of:
a) RAM, ROM, I/O ports and timers
b) CPU, RAM, I/O ports and timers
c) CPU, RAM, ROM, I/O ports and timers

d) CPU, ROM, I/O ports and timers
Explanation: A microcontroller at-least consists of a processor as its CPU with RAM, ROM, I/O ports
and timers. It may contain some additional peripherals like ADC, PWM, etc.
202. Unlike microprocessors, microcontrollers make use of batteries because they have:
a) high power dissipation
b) low power consumption
c) low voltage consumption
d) low current consumption
Explanation: Micro Controllers are made by using the concept of VLSI technology. So here, CMOS
based logic gates are coupled together by this technique that consumes low power.
203. What is the order decided by a processor or the CPU of a controller to execute an instruction?
a) decode,fetch,execute
b) execute,fetch,decode
c) fetch,execute,decode
d) fetch,decode,execute
Explanation: First instruction is fetched from Program Memory. After fetching, instruction is decoded to
generate control signals to perform the intended task. After decoding, instruction is executed and the
complete intended task of that particular instruction.
204. If we say microcontroller is 8-bit then here 8-bit denotes size of:
a) Data Bus
b) ALU
c) Control Bus
d) Address Bus
Explanation: If we say a microcontroller is 8-bit it means that it is capable of processing 8-bit data at a
time. Data processing is the task of ALU and if ALU is able to process 8-bit data then the data bus should
be 8-bit wide. In most books it tells that size of data bus but to be precise it is the size of ALU because in
Harvard Architecture there are two sets of data bus which can be of same size but it is not mandatory.
205. How are the performance and the computer capability affected by increasing its internal bus width?
a) it increases and turns better
b) it decreases
c) remains the same
d) internal bus width doesn’t affect the performance in any way
Explanation: As the bus width increases, the number of bits carried by bus at a time increases as a result
of which the total performance and computer capability increases.
206. Abbreviate CISC and RISC.
a) Complete Instruction Set Computer, Reduced Instruction Set Computer
b) Complex Instruction Set Computer, Reduced Instruction Set Computer
c) Complex Instruction Set Computer, Reliable Instruction Set Computer
d) Complete Instruction Set Computer, Reliable Instruction Set Computer
Explanation: CISC means Complete Instruction Set Computer because in this a microcontroller has an
instruction set that supports many addressing modes for the arithmetic and logical instructions, data
transfer and memory accesses instructions. RISC means Reduced Instruction Set Computer because here
a microcontroller has an instruction set that supports fewer addressing modes for the arithmetic and
logical instructions and for data transfer instructions.
207. Give the names of the buses present in a controller for transferring data from one place to another?
a) data bus, address bus
b) data bus
c) data bus, address bus, control bus
d) address bus
Explanation: There are 3 buses present in a microcontroller they are data bus (for carrying data from
one place to another), address bus (for carrying the address to which the data will flow) and the control
bus (which tells the controller to execute which type of work at that address may be it read or write
operation).
208. What is the file extension that is loaded in a microcontroller for executing any instruction?
a) .doc
b) .c
c) .txt
d) .hex
Explanation: Microcontrollers are loaded with .hex extension as they understand the language of 0’s and
1’s only.
209. What is the most appropriate criterion for choosing the right microcontroller of our choice?
a) speed
b) availability
c) ease with the product
Explanation: For choosing the right microcontroller for our product we must consider its speed so that
the instructions may be executed in the least possible time. It also depends on the availability so that the
particular product may be available in our neighboring regions or market in our need. It also depends on
the compatibility with the product so that the best results may be obtained.
210. Why microcontrollers are not called general purpose computers?
a) because they have built in RAM and ROM
b) because they design to perform dedicated task
c) because they are cheap
d) because they consume low power
Explanation: Microcontrollers are designed to perform dedicated tasks. While designing general purpose
computers end use is not known to designers.
TOPIC 2: Microcontroller Questions and Answers – Von Neumann and Harward Architectures
211. How many types of architectures are available, for designing a device that is able to work on its own?
a) 3
b) 2
c) 1
d) 4
Explanation: There are basically two main types of architectures present, they are Von Neumann and
Harvard architectures.
212. Which architecture is followed by general purpose microprocessors?

a) Harvard architecture
b) Von Neumann architecture
c) None of the mentioned
Explanation: General purpose microprocessors make use of Von Neumann architecture as here a simpler
design is offered.
213. Which architecture involves both the volatile and the non volatile memory?
Explanation: In Harvard architecture, both the volatile and the non volatile memories are involved. This
is done to increase its efficiency as both the memories are being used over here.
214. Which architecture provides separate buses for program and data memory?
Explanation: Harvard Architecture provides separated buses for data and program memory to fetch
program and data simultaneously. By doing this access time is reduced and hence performance is
increased.
215. Which microcontroller doesn’t match with its architecture below?

a) Microchip PIC- Harvard
b) MSP430- Harvard
c) ARM7- Von Neumann
d) ARM9- Harvard
Explanation: MSP430 supports Von Neumann architecture.
216. Harvard architecture has _____________

a) dedicated buses for data and program memory
b) pipeline technique
c) complex architecture
Explanation: Harvard Architecture has dedicated buses for data and program memory and pipeline
technique because of this architecture is complex.
217. Which out of the following supports Harvard architecture?

a) ARM7
b) Pentium
c) SHARC
Explanation: SHARC supports harvard architecture for signal processing in DSP.
218. Why most of the DSPs use Harvard architecture?

a) they provide greater bandwidth
b) they provide more predictable bandwidth
c) they provide greater bandwidth & also more predictable bandwidth
Explanation: Most of the DSPs use harvard architecture because they provide a wider predictable
bandwidth.
219. Which of the following supports CISC as well as Harvard architecture?

a) ARM7
b) ARM9
c) SHARC
Explanation: SHARC supports both the CISC and the Harvard architecture.
220. Which of the two architecture saves memory?

a) Harvard
b) Von Neumann
c) Harvard & Von Neumann
Explanation: As only one memory is present in the Von Neumann architecture so it saves a lot of
memory.
TOPIC 3: Architecture
221. 8051 microcontrollers are manufactured by which of the following companies?

a) Atmel
b) Philips
c) Intel
Explanation: 8051 microcontrollers are manufactured by Intel, Atmel, Philips/Signetics, Infineon, Dallas
Semi/Maxim.
222. AT89C2051 has RAM of:

a) 128 bytes
b) 256 bytes
c) 64 bytes
d) 512 bytes
Explanation: It has 128 bytes of RAM in it.
223. 8051 series has how many 16 bit registers?

a) 2
b) 3
c) 1
d) 0
Explanation: It has two 16 bit registers DPTR and PC.
224. When 8051 wakes up then 0x00 is loaded to which register?

a) PSW
b) SP
c) PC
Explanation: When 8051 wakes up, Program Counter (PC) loaded with 0000H. Because of this in 8051
first opcode is stored in ROM address at 0000H.
225. When the microcontroller executes some arithmetic operations, then the flag bits of which register are
affected?
a) PSW
b) SP
c) DPTR
d) PC
Explanation: It stands for program status word. It consists of carry, auxiliary carry, overflow, parity,
register bank select bits etc which are affected during such operations.
226. How are the status of the carry, auxiliary carry and parity flag affected if the write instruction
MOV A,#9C
ADD A,#64H
a) CY=0,AC=0,P=0
b) CY=1,AC=1,P=0
c) CY=0,AC=1,P=0
d) CY=1,AC=1,P=1
Explanation: On adding 9C and 64, a carry is generated from D3 and from the D7 bit so CY and AC are
set to 1. In the result, the number of 1’s present are even so parity flag is set to zero.
227. How are the bits of the register PSW affected if we select Bank2 of 8051?
a) PSW.5=0 and PSW.4=1
b) PSW.2=0 and PSW.3=1
c) PSW.3=1 and PSW.4=1
d) PSW.3=0 and PSW.4=1
Explanation: Bits of PSW register are CY, AC, F0, RS1, RS0, OV, -, P so for selecting bank2 RS1=1 and
RS0=0 which are fourth and third bit of the register respectively.
228. If we push data onto the stack then the stack pointer
a) increases with every push
b) decreases with every push
c) increases & decreases with every push
Explanation: If we push elements onto the stack then the stack pointer increases with every push of
element.
229. On power up, the 8051 uses which RAM locations for register R0- R7
a) 00-2F
b) 00-07
c) 00-7F
d) 00-0F
Explanation: On power up register bank 0 is selected which has memory address from 00H-07H.
230. How many bytes of bit addressable memory is present in 8051 based microcontrollers?
a) 8 bytes
b) 32 bytes
c) 16 bytes
d) 128 bytes
Explanation: 8051 microcontrollers have 16 bytes of bit addressable memory.
TOPIC 4: “Jump, Loop and Call Instructions”.
231. “DJNZ R0, label” is ________ byte instruction.

a) 2
b) 3
c) 1
d) Can’t be determined
Explanation: DJNZ is 2-byte instruction. This means jump can be of -128 to +127 locations with respect
to PC. Here -128 means upward or backward jump and +127 means downward or forward jump.
232. JZ, JNZ, instructions checked content of _______ register.

a) DPTR
b) B
c) A
d) PSW
Explanation: JZ and JNZ instructions checked the content of A register and if condition was satisfied or
true then jump to target address.
233. Calculate the jump code for again and here if code starts at 0000H
MOV R1,#0
MOV A,#0
MOV R0,#25H
AGAIN:ADD A,#0ECH
JNC HERE
HERE: INC R1
DJNZ R0,AGAIN
MOV R0,A
END
a) F3,02
b) F9,01
c) E9,01
d) E3,02
Explanation: Loop address is calculated by subtracting destination address and the address next to the
source address.
So here if we start with 0000H
then source address is 0008H and the destination address is 0004H
So loop address is 04-0A=E9
234. When the call instruction is executed the topmost element of stack comes out to be
a) the address where stack pointer starts
b) the address next to the call instruction
c) address of the call instruction
d) next address of the stack pointer
Explanation: The topmost element of the stack is the address of the instruction next to the call instruction
so that when RET is executed then PC is filled with that address and so the pointer moves to the main
program and continue with its routine task.
235. LCALL instruction takes

a) 2 bytes
b) 4 bytes
c) 3 bytes
d) 1 byte
Explanation: LCALL instruction moves the pointer to a 16 bit address so it is a 3 byte instruction.
236. Are PUSH and POP instructions are a type of CALL instructions?
a) yes
b) no
c) none of the mentioned
d) cant be determined
Explanation: PUSH and POP instructions are not CALL instructions because in POP and PUSH
instructions the pointer does not move to any location specified by its address which is the fundamental of
CALL instruction, so it is not a type of CALL instruction.
237. What is the time taken by one machine cycle if crystal frequency is 20MHz?
a) 1.085 micro seconds
b) 0.60 micro seconds
c) 0.75 micro seconds
d) 1 micro seconds
Explanation: Time taken by one machine cycle is calculated by the inverse of a (crystal frequency) /12
238. Find the number of times the following loop will be executed
MOV R6,#200
BACK:MOV R5,#100
HERE:DJNZ R5, HERE
DJNZ R6,BACK
END
a) 100
b) 200
c) 20000
d) 2000
Explanation: It will be executed 200*100 times.
239. What is the meaning of the instruction MOV A,05H?

a) data 05H is stored in the accumulator
b) fifth bit of accumulator is set to one
c) address 05H is stored in the accumulator
Explanation: If we need to store the address in the accumulator, then directly the address is moved to it
unlikely of using # used for storing data in any register.
240. Do the two instructions mean the same?
1) BACK: DEC R0
JZ BACK
2) BACK: DJNZ RO, BACK
a) yes
b) no
c) cant be determined
d) yes and the second one is preferred
Explanation: In the first statement, when the decrements approach zero then the jump moves back and
in the second statement, when the result after decrements is not zero, then it jumps back.
TOPIC 5 : “I/O Port Programming and Addressing Modes”.
241. To initialize any port as an output port what value is to be given to it?
a) 0xFF
b) 0x00
c) 0x01
d) A port is by default an output port
Explanation: In 8051, a port is initialized by default in its output mode no need to pass any value to it.
242. Which out of the four ports of 8051 needs a pull-up resistor for using it is as an input or an output port?
a) PORT 0
b) PORT 1
c) PORT 2
d) PORT 3
Explanation: These pins are the open drain pins of the controller which means it needs a pull-up resistor
for using it as an input or an output ports.
243. Which of the ports act as the 16 bit address lines for transferring data through it?
a) PORT 0 and PORT 1
b) PORT 1 and PORT 2
c) PORT 0 and PORT 2
d) PORT 1 and PORT 3
Explanation: PORT 0 and PORT 2 are used as the 16 bit address lines where PORT0 act as lower bit
address lines and PORT 2 as higher bit address lines.
244. Which of the following registers are not bit addressable?

a) SCON
b) PCON
c) A
d) PSW
Explanation: PCON register is not a bit addressable register.
245. Which instruction is used to check the status of a single bit?

a) MOV A,P0
b) ADD A,#05H
c) JNB PO.0, label
d) CLR P0.05H
Explanation: JNB which stands for Jump if no bit checks the status of the bit P0.0 and jumps if the bit is
0.
246. Which addressing mode is used in pushing or popping any element on or from the stack?
a) immediate
b) direct
c) indirect
d) register
Explanation: If we want to push or pop any element on or from the stack then direct addressing mode
has to be used in it, as the other way is not accepted.
247. Which operator is the most important while assigning any instruction as register indirect instruction?
a) $
b) #
c) @
d) &
Explanation: In register, indirect mode data is copied at that location where R0 or R1 are present, so @
operator is used ex. MOV @R0,A
248. What is the advantage of register indirect addressing mode?

a) it makes use of registers R0 and R1
b) it uses the data dynamically
c) it makes use of operator @
d) it is easy
Explanation: Register indirect addressing mode is useful if a series of data is to be assigned to that
address, with the help of this quality the number of instructions decreases as a result of which
performance increases.
249. Which of the following comes under the indexed addressing mode?
a) MOVX A, @DPTR
b) MOVC @A+DPTR,A
c) MOV A,R0
d) MOV @R0,A
Explanation: Indexed addressing mode stands for that instruction where the bits of the accumulator is
also indexed with the 16 bit registers.
250. Is this a valid statement?

SETB A
a) yes
b) no
Explanation: SETB is used to set a bit of a register. A stands for accumulator which is an 8 bit register, so
it is an invalid instruction.
TOPIC 6 : “Arithmetic and Logic Instructions”.
251. When we add two numbers the destination address must always be.
a) some immediate data
b) any register
c) accumulator
d) memory
Explanation: For addition purposes, the destination address must always be an accumulator. Example-
ADD A,R0; ADD A, @R1; ADD A,@ DPTR
252. DAA command adds 6 to the nibble if:

a) CY and AC are necessarily 1
b) either CY or AC is 1
c) no relation with CY or AC
d) CY is 1
Explanation: DAA command adds 6 to the nibble if any of the nibbles becomes greater than 9.
253. If SUBB A,R4 is executed, then actually what operation is being applied?
a) R4+A
b) R4-A
c) A-R4
d) R4+A
Explanation: SUBB command subtracts with borrow the contents of an accumulator with that of the
register or some immediate value. So A-R4 is being executed.
254. A valid division instruction always makes:

a) CY=0,AC=1
b) CY=1,AC=1
c) CY=0,AC=0
d) no relation with AC and CY
Explanation: When we divide two numbers then AC and CY become zero.
255. In 8 bit signed number operations, OV flag is set to 1 if:

a) a carry is generated from D7 bit
b) a carry is generated from D3 bit
c) a carry is generated from D7 or D3 bit
d) a carry is generated from D7 or D6 bit
Explanation: In 8 bit operations, if a carry is generated from D6 or D7 bit, then OV flag is set to 1.
256. In unsigned number addition, the status of which bit is important?

a) OV
b) CY
c) AC
d) PSW
Explanation: If unsigned numbers operations are involved, then the status of CY flag is important and in
signed number operation the status of OV flag is important.
257. Which instructions have no effect on the flags of PSW?

a) ANL
b) ORL
c) XRL
Explanation: These instructions are the arithmetic operations and the flags are affected by the data copy
instructions, so all these instructions don’t affect the bits of the flag.
258. ANL instruction is used _______

a) to AND the contents of the two registers
b) to mask the status of the bits
c) all of the mentioned
Explanation: ANL instruction is used to AND the contents of the two registers and is also used to mask
the status of the bits of the register.
259. CJNE instruction makes _______

a) the pointer to jump if the values of the destination and the source address are equal
b) sets CY=1, if the contents of the destination register are greater then that of the source register
c) sets CY=0, if the contents of the destination register are smaller then that of the source register
Explanation: In CJNE command, the pointer jumps if the values of the two registers are not equal and it
resets CY if the destination address is larger then the source address and sets CY if the destination
address is smaller then the source address.
260. XRL, ORL, ANL commands have _______

a) accumulator as the destination address and any register, memory or any immediate data as the source
address
b) accumulator as the destination address and any immediate data as the source address
c) any register as the destination address and accumulator, memory or any immediate data as the source address
d) any register as the destination address and any immediate data as the source address
Explanation: These commands have accumulator as the destination address and any register, memory or
any immediate data as the source address.
TOPIC 7 : “I/O Port Programming and Addressing Modes”.
261. What is the clock source for the timers?

a) some external crystal applied to the micro-controller for executing the timer
b) from the crystal applied to the micro-controller
c) through the software
d) through programming
Explanation: Timer’s clock source is the crystal that is applied to the controller.
262. What is the frequency of the clock that is being used as the clock source for the timer?
a) some externally applied frequency f’
b) controller’s crystal frequency f
c) controller’s crystal frequency /12
d) externally applied frequency/12
Explanation: The frequency of the clock source for the timer is equal to f/12(where f is the frequency of
the crystal).
263. What is the function of the TMOD register?

a) TMOD register is used to set various operation modes of timer/counter
b) TMOD register is used to load the count of the timer
c) Is the destination or the final register where the result is obtained after the operation of the timer
d) Is used to interrupt the timer
Explanation: TMOD is used to set various operation modes of timer/counter by the programmer.
264. What is the maximum delay that can be generated with the crystal frequency of 22MHz?
a) 2978.9 sec
b) 0.011 msec
c) 11.63 sec
d) 2.97 msec
Explanation: For generating the maximum delay we have to multiply the maximum number of counts
with the time period required to execute one machine cycle( 65536*1/22MHz).
265. Auto reload mode is allowed in which mode of the timer?

a) Mode 0
b) Mode 1
c) Mode 2
d) Mode 3
Explanation: Auto reload is allowed in the Mode 2 of the timer because here in this mode, we don’t need
to load the count again and again in the register.
266. Find out the roll over value for the timer in Mode 0, Mode 1 and Mode 2?
a) 00FFH,0FFFH,FFFFH
b) 1FFFH,0FFFH,FFFFH
c) 1FFFH,FFFFH,00FFH
d) 1FFFH,00FFH,FFFFH
Explanation: For Mode 0 13 bit value is used so 1FFFH is chosen to be the roll over value. Similarly for
Mode 1 FFFFH and for Mode 2 FFH is the roll over value for the timers and counter.
267. What steps are followed when we need to turn on any timer?
a) load the count, start the timer, keep monitoring it, stop the timer
b) load the TMOD register, load the count, start the timer, keep monitoring it, stop the timer
c) load the TMOD register, start the timer, load the count, keep monitoring it, stop the timer
Explanation: When any timer is to turn on, then firstly we have to load the TMOD register and the
count. Then the timer is to get started. After then, we need to monitor the timer properly and then when
the roll over condition arises then the timer is to be stopped.
268. If Timer 0 is to be used as a counter, then at what particular pin clock pulse need to be applied?
a) P3.3
b) P3.4
c) P3.5
d) P3.6
Explanation: If Timer 0 is to be used as a counter, then a pulse has to be applied at P3.4 and if it is for
Timer 1 then the clock pulse has to be applied at the pin P3.5.
269. In the instruction “MOV TH1,#-3”, what is the value that is being loaded in the TH1 register?
a) 0xFCH
b) 0xFBH
c) 0xFDH
d) 0xFEH
Explanation: Negative value is loaded in 2’s complement form. -3 represented in 2’s complement form as
FDH.
Steps to convert into 2’s complement:
3 → 0000 0011 Binary Equivalent of ‘3’
→ 1111 1100 1’s Complement of decimal ‘-3’
→ 1111 1101 2’s Complement of decimal ‘-3’
F D Hex Equivalent of ‘-3’
270. TF1, TR1, TF0, TR0 bits are of which register?

a) TMOD
b) SCON
c) TCON
d) SMOD
Explanation: All of these bits are part of TCON (Timer Control) register. TF0 and TF1 are used to check
overflow of timer 0 and timer 1 respectively. TR0 and TR1 are timer control bits used to start and stop of
timer 0 and timer 1 respectively.
TOPIC 8:” Serial Port Communication”.
271. Which devices are specifically being used for converting serial to parallel and from parallel to serial
respectively?
a) timers
b) counters
c) registers
d) serial communication
Explanation: Some registers like the parallel in serial out and serial in parallel out are used to convert
serial data into parallel and vice versa respectively.
272. What is the difference between UART and USART communication?

a) they are the names of the same particular thing, just the difference of A and S is there in it
b) one uses asynchronous means of communication and the other uses synchronous means of communication
c) one uses asynchronous means of communication and the other uses asynchronous and synchronous
means of communication
d) one uses angular means of the communication and the other uses linear means of communication
Explanation: UART stands for Universal Asynchronous receiver-transmitter and USART stands for
Universal Synchronous and Asynchronous receiver-transmitter.
273. Which of the following best describes the use of framing in asynchronous means of communication?
a) it binds the data properly
b) it tells us about the start and stops of the data to be transmitted or received
c) it is used for error checking
d) it is used for flow control
Explanation: In data framing in asynchronous means of communication, the data is packed between the
start and the stop bit. This is done so as to tell the other computer about the start and the end of the data.
274. Which of the following signal control the flow of data?

a) RTS
b) DTR
c) RTS& DTR
Explanation: RTS is a request to send control signal which is a control for the flow of data. On the other
hand DTR is a Data Terminal Ready control signal which tells about the current status of the DTE.
275. Which of the following is the logic level understood by the micro-controller/micro-processor?
a) TTL logic level
b) RS232 logic level
d) TTL & RS232 logic level
Explanation: TTL logic or the transistor logic level is the logic that is understood by the micro-
controllers/microprocessors.
276. What is a null modem connection?

a) no data transmission
b) no MAX232
c) the RxD of one is the TxD for the other
d) no serial communication
Explanation: In null modem connection the RxD of one is the TxD for the other.
277. Which of the following best states the reason that why baud rate is mentioned in serial communication?
a) to know about the no of bits being transmitted per second
b) to make the two devices compatible with each other, so that the transmission becomes easy and error
free
c) to use Timer 1
d) for wasting memory
Explanation: To make two devices compatible with each other baud rate is mentioned in the serial
communication so that the transmission becomes easy and error free.
278. With what frequency UART operates( where f denoted the crystal frequency )?
a) f/12
b) f/32
c) f/144
d) f/384
Explanation: UART frequency is the crystal frequency f/12 divided by 32, that comes out to be f/384.
279. What is the function of the SCON register?

a) to control SBUF and SMOD registers
b) to program the start bit, stop bit, and data bits of framing
c) to control SMOD registers
Explanation: SCON register is mainly used for programming the start bits, stop bits and data bits of
framing. As it consists of bits like RB8, TB8, SM0, SM1, SM2 etc.
280. What should be done if we want to double the baud rate?

a) change a bit of the TMOD register
b) change a bit of the PCON register
c) change a bit of the SCON register
d) change a bit of the SBUF register
Explanation: PCON register consists of SMOD bit as its D7 bit, so if we set this bit then the baud rate
gets doubled
TOPIC 9 :“Interrupt Programming”.
281. When an interrupt is enabled, then where does the pointer moves immediately after this interrupt has
occurred?
a) to the next instruction which is to be executed
b) to the first instruction of ISR
c) to a fixed location in memory called interrupt vector table
d) to the end of the program
Explanation: When an interrupt occurs, then it jumps to a fixed memory location in memory called the
interrupt vector table that holds the address of the Interrupt Service Routine.
282. What are the contents of the IE register, when the interrupt of the memory location 0x00 is caused?
a) 0xFFH
b) 0x00H
c) 0x10H
d) 0xF0H
Explanation: When interrupt of 0x00 is caused (the reset interrupt) then all the other interrupts will be
disabled or the contents of the IE register becomes null.
283. After RETI instruction is executed then the pointer will move to which location in the program?
a) next interrupt of the interrupt vector table
b) immediate next instruction where interrupt is occurred
c) next instruction after the RETI in the memory
Explanation: When the RETI instruction is executed, PC will fetch 2-bytes (address) from top of stack
which is stored when interrupt is occurred. This will return to the place where interrupt is occurred and
starts executing instructions.
284. Which pin of the external hardware is said to exhibit INT0 interrupt?
a) pin no 10
b) pin no 11
c) pin no 12
d) pin no 13
Explanation: INT0 interrupt is caused when pin no 12 in the hardware of the 8051 controller is enabled
with a low leveled pulse.
285. Which bit of the IE register is used to enable TxD/RxD interrupt?

a) IE.D5
b) IE.D2
c) IE.D3
d) IE.D4
Explanation: IE.D4 is used to enable RS interrupt or the serial communication interrupt.
286. Which of the following combination is the best to enable the external hardware interrupt 0 of the IE
register (assuming initially all bits of the IE register are zero)?
a) EX0=1
b) EA=1
c) any of the mentioned
d) EX0=1 & EA=1
Explanation: For executing the EX0 interrupt, the EX0 and EA bits of the IE register should be set. EA is
set to enable all the interrupts and EX0 is set to enable the external hardware interrupt 0 interrupt and
mask the other enabled interrupts.
287. Why normally LJMP instructions are the topmost lines of the ISR?
a) so as to jump to some other location where there is a wider space of memory available to write the codes
b) so as to avoid overwriting of other interrupt instructions
Explanation: There is a small space of memory present in the vector table between two different
interrupts so in order to avoid overwriting of other interrupts we normally jump to other locations where
a wide range of space is available.
288. Which register is used to make the interrupt level or an edge triggered pulse?
a) TCON
b) IE
c) IPR
d) SCON
Explanation: TCON register is used to make any interrupt level or edge triggered.
289. What is the disadvantage of a level triggered pulse?

a) a constant pulse is to be maintained for a greater span of time
b) another interrupt may be generated if the low-level signal is not removed before the ISR is finished
c) it is difficult to produce
d) another interrupt may be caused if the signal is still low before the completion of the last instruction
Explanation: In a level triggered interrupt, if the low signal at interrupt pin must be removed before the
execution of last instruction of the ISR i.e. RETI. If low signal at interrupt pin is not removed before
completing the ISR then it will be generating another interrupt.
290. What is the correct order of priority that is set after a controller gets reset?
a) RI/TI > TF1 > TF0 > INT1 > INT0
b) RI/TI < TF1 < TF0 < INT1 < INT0
c) INT0 > TF0 > INT1 > TF1 > RI/TI
d) INT0 < TF0 < INT1 < TF1 < RI/TI
Explanation: On reset Interrupt Priorities are as INT0 > TF0 > INT1 > TF1 > RI/TI, where ‘>’ is used to
denote highest priority.
TOPIC 10: “LCD Interfacing”.
291. How many rows and columns are present in a 16*2 alphanumeric LCD?
a) rows=2, columns=32
b) rows=16, columns=2
c) rows=16, columns=16
d) rows=2, columns=16
Explanation: 16*2 alphanumeric LCD has 2 rows and 16 columns.
292. How many data lines are there in a 16*2 alphanumeric LCD?
a) 16
b) 8
c) 1
d) 0
Explanation: There are eight data lines from pin no 7 to pin no 14 in an LCD.
293. Which pin of the LCD is used for adjusting its contrast?
a) pin no 1
b) pin no 2
c) pin no 3
d) pin no 4
Explanation: Pin no 3 is used for controlling the contrast of the LCD.
294. For writing commands on an LCD, RS bit is

a) set
b) reset
c) set & reset
Explanation: For writing commands on an LCD, RS pin is reset.
295. Which command of an LCD is used to shift the entire display to the right?
a) 0x1C
b) 0x18
c) 0x05
d) 0x07
Explanation: 0x1C is used to shift the entire display to the right.
296. Which command is used to select the 2 lines and 5*7 matrix of an LCD?
a) 0x01
b) 0x06
c) 0x0e
d) 0x38
Explanation: 0x38 is used to select the 2 lines and 5*7 matrix of an LCD.
297. Which of the following step/s is/are correct for sending data to an LCD?
a) set the R/W bit
b) set the E bit
c) set the RS bit
Explanation: To send data to an LCD, RS pin should be set so that LCD will come to know that it will
receive data which has to display on the screen. R/W pin should be reset as data has to be displayed (i.e.
write to the LCD). High to low pulse must be applied to the E pin when data is supplied to data pins of
the LCD.
298. Which of the following step/s is/are correct to perform reading operation from an LCD?
a) low to high pulse at E pin
b) R/W pin is set high
c) low to high pulse at E pin & R/W pin is set high
Explanation: For reading operations, R/W pin should be made high and added to it, a low to high pulse is
also generated at the E pin.
299. Which instruction is used to select the first row first column of an LCD?
a) 0x08
b) 0x0c
c) 0x80
d) 0xc0
Explanation: 0x80 is used to select the first row first column of an LCD.
300. The RS pin is _________ for an LCD.

a)input
b) output
c) input & output
Explanation: The RS pin is an input pin for an LCD.
Topic11: “Keyboard interfacing”.
301. Which of the following steps detects the key in a 4*4 keyboard matrix about the key that is being pressed?
a) masking of bits
b) ensuring that initially, all keys are open
c) checking that whether the key is actually pressed or not
Explanation: For detecting that whether the key is actually pressed or not, firstly this must be ensured
that initially all the keys are closed. Then we need to mask the bits individually to detect that which key is
pressed. Then we need to check that is the key actually pressed or not, by checking that whether the key
pressed for a time more than 20 micro seconds.
302. What is described by this command: CJNE A,#00001111b, ROW1

a) it masks the bit and then jumps to the label where ROW1 is written
b) it makes the value of the accumulator 0FH and then jumps at the address where ROW1 label is written
c) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is there if
the value becomes equal
d) it compares the value of the accumulator with 0FH and jumps to the location where ROW1 label is
there if the value is not equal
Explanation: This particular command CJNE A,#00001111b, ROW1 compares the value of the accumulator
with OFH and jumps to ROW1 address if the value is not equal.
303. To detect that in which column, the key is placed?

a) we can mask the bits and then check it
b) we can rotate the bits and then check that particular bit which is set or reset(according to the particular
condition)
Explanation: We can mask or we can even rotate the bits to check that particularly in which column is the key
placed.
304. In reading the columns of a matrix, if no key is pressed we should get all in binary notation
a) 0
b) 1
c) F
d) 7
Explanation: If no key is pressed, then all the keys show 1 as they are all connected to power supply.
305. If we need to operate a key of a keyboard in an interrupt mode, then it will generate what kind of interrupt?
a) ES
b) EX0/EX1
c) T0/T1
d) RESET
Explanation: If a key is to operate in an interrupt mode then it will generate an external hardware interrupt.
306. To identify that which key is being pressed, we need to:

a) ground all the pins of the port at a time
b) ground pins of the port one at a time
c) connect all the pins of the port to the main supply at a time
Explanation: To detect that which key is being pressed, we need to ground the pins one by one.
307. Key press detection and Key identification are:

a) the same processes
b) two different works are done in Keyboard Interfacing
d) any of the mentioned
Explanation: They are two different works that are involved in Keyboard Interfacing. One is used for checking
that which key is being actually pressed and the other is used to check that is the key actually pressed or not.
TOPIC 12: ADC, DAC Interfacing
308. Why two pins for ground are available in ADC0804?

a) for controlling the ADCON0 and ADCON1 register of the controller
b) for controlling the analog and the digital pins of the controller
c) for both parts of the chip respectively
d) for isolate analog and digital signal
Explanation: Two grounds are available in ADC0804 to isolate analog signal from digital signal. This isolation
provides accuracy in digital output.
309. What is the function of the WR pin?

a) its active high input used to inform ADC0804 to the end of conversion
b) its active low input used to inform ADC0804 to the end of conversion
c) its active low input used to inform ADC0804 to the start of conversion
d) its active high input used to inform ADC0804 to the start of conversion
Explanation: WR is active low input used to inform the ADC0804 to start the conversion process.
310. State which of the following statements are false?

a) CLK IN pin used for External Clock Input or Internal Clock with external RC element
b) INTR pin tells about the end of the conversion
c) ADC0804 IC is an 8 bit parallel ADC in the family of the ADC0800 series
Explanation: CLK IN pin is used to tell about the conversion time, INTR pin tells about the end of the
conversion and ADC0804 has a resolution of 8 bits only so all three statements are true.
311. While programming the ADC0808/0809 IC what steps are followed?

a) select the analog channel, start the conversion, monitor the conversion, display the digital results
b) select the analog channel, activate the ALE signal (L to H pulse), start the conversion, monitor the
conversion, read the digital results
c) select the analog channel, activate the ALE signal (H to L pulse), start the conversion, monitor the
conversion, read the digital results
d) select the channel, start the conversion, end the conversion
Explanation: While programming the ADC0808/0809 IC firstly we need to select the channel from the A, B, C
pins. Then we need to activate the ALE signal, this is needed to latch the address. Then we start the conversion
from the WR pin. After monitoring the INTR pin we get to know about the end of the conversion. Then we
activate the OE enable to read out data out of the ADC chip.
312. In ADC0808/0809 IC which pin is used to select Step Size?

a) Vref
b) Vin
c) Vref/2 & Vin
Explanation: Step Size is calculated by formula Vref/(2n). As ADC0808/0809 8-bit ADC value of n=8.
Therefore formula becomes Vref/(28) = Vref/256. If Vref = 5V then Step Size will be 5/256 i.e. 19.53mV.
313. What is the difference between ADC0804 and MAX1112?

a) ADC0804 has 8 bits and MAX1112 has 1 bit for data output
b) ADC0804 is used for adc and dac conversions whereas MAX1112 is used for serial data transmissions
c) ADC0804 has 32 bits and MAX1112 has 3 bit for data output
Explanation: ADC0804 is used for parallel ADC and MAX1112 is used for serial ADC.
314. Which of the following statements are true about DAC0808?

a) parallel digital data to analog data conversion
b) it has current as an output
Explanation: DAC0804 is used for parallel data to analog data conversion.
315. 8 input DAC has ________
a) 8 discrete voltage levels
b) 64 discrete voltage levels
c) 124 discrete voltage levels
d) 256 discrete voltage levels
Explanation: For n input DAC has 2^n discrete voltage levels.
316. INTR, WR signal is an input/output signal pin?

a) both are output
b) both are input
c) one is input and the other is output
Explanation: INTR pin tells about the end of the conversion (output) and WR pin tells us to start the
conversion (input).
317. What is the function of the SCLK pin in MAX1112?

a) It is used to bring data in
b) It is used to bring data out and send in the control byte, one at a time
c) It is used to get output clock
d) It is used to get serial output
Explanation: SCLK is used to bring data out and send in the control byte.
TOPIC 13: “Sensor Interfacing”.
318. A thermistor is a __________

a) sensor
b) adc
c) transducer
d) micro controller
Explanation: A thermistor is a device which is used to convert the temperature into electrical signals, so it acts
as a transducer.
319. What is the difference between LM 34 and LM 35 sensors?

a) one is a sensor and the other is a transducer
b) one’s output voltage corresponds to the Fahrenheit temperature and the other corresponds to the
Celsius temperature
c) one is of low precision and the other is of higher precision
d) one requires external calibration and the other doesn’t require it
Explanation: LM 34’s output voltage corresponds to the Fahrenheit temperature and LM 35 corresponds to the
Celsius temperature.
320 . An electronic device which converts physical quantity or energy from one form to another is called
______
a) Sensor
b) Transistor
c) Transducer
d) Thyristor
Explanation: An electronic device that converts physical quantity or energy from one form to another is called
Transducer. Examples: Sensor, Speaker, Microphone, etc.
321. What is signal conditioning?

a) to analyse any signal
b) conversion or modification is referred to as conditioning
c) conversion from analog to digital is signal conditioning
d) conversion from digital to analog is signal conditioning
Explanation: Signal Conditioning is referred to as the conversion of a signal from one form to other, now this
may be from analog to digital conditioning or digital to analog conditioning.
322. What steps have to be followed for interfacing a sensor to a microcontroller 8051?
a) make the appropriate connections with the controller, ADC conversion, analyse the results
b) interface sensor with ADC and ADC with 8051
c) interface sensor with the MAX232, send now to microcontroller, analyse the results
Explanation: For interfacing a sensor with an 8051 microcontroller, we need ADC in between because output
of sensor is analog and microcontroller works on digital signals only. So whatever signal generated by the
sensor is converted into its digital equivalent using ADC and equivalent digital signal is given to the
microcontroller for processing.
323. LM35 has how many pins?

a) 2
b) 1
c) 3
d) 4
Explanation: LM35 has 3 pins.
1.Power( +5 Volts )
2.Output analog voltage
3.Ground( 0 Volts )
324. Why Vref is set of ADC0848 to 2.56 V if analog input is connected to the LM35?
a) to set the step size of the sampled input
b) to set the ground for the chip
c) to provide supply to the chip
Explanation: Vref is used to set the step size of the ADC conversion, if it is selected to 2.56 then the step size
will be selected to 10mV, so for every step increase of the analog voltage an increase of 10 mV will be there.
TOPIC14: “Interfacing with 8255”.
325. The 8255 is a ______ chip.

a) Input/Output
b) Analog to Digital
c) Digital to analog
Explanation: The 8255 is Input/Output (I/O) chip. It has three separate accessible ports. The 8255 chip is used
to expand the I/O ports of microcontrollers.
326 . Which pins of a microcontroller are directly connected with 8255?

a) RD
b) WR
c) D0-D7
Explanation: RD, WR, D0-D7 all are directly connected to the 8051 for telling the chip about the control
signals and also for transferring the data.
327. Find the control word for PA = out, PB = in, PCL = out, PCH = out (Mode0)?
a) 0x02H
b) 0x82H
c) 0x83H
d) 0x03H
Explanation: The value that is being loaded in the control word is 10000010b for PB as an input port and all
others as the output ports being operated in mode0. The hex equivalent of 10000010b → 0x82H.
328. Which pins are used to select the ports and the control register?
a) CS
b) A1
c) A0
Explanation: CS pin is an active low input pin for 8255 and it is used for selecting a chip. A0 and A1 pins are
used for select ports and the control register.
329. What is the value of the control register when RESET button is set to zero?
a) 0x00H
b) 0xFFH
c) 0x11H
d) value remains the same
Explanation: RESET is active-high signal input into the 8255 used to clear the control register. When RESET
is activated (i.e. set to high), all ports are initialized as input mode. Hence the value of the control register
remains the same as it is even when the RESET button is set to zero.
330. Why MOVX instruction is being used to access the ports of the 8255?
a) because 8255 is connecting a microcontroller in memory mapped I/O configuration
b) because 8255 is used to access the external communication
c) because 8255 is used to access the data transfer
d) because 8255 is used to access the interfacing of LCD, motor etc
Explanation: As 8255 is connecting a microcontroller in memory mapped I/O configuration. This means that
memory space used to access 8255 (i.e. 8255 is treated as external memory). MOVX instruction is used to
access external memory locations.
331. What is correct about the BSR mode from below?

a) In BSR mode, only the individual bits of PORT A can be programmed
b) In BSR mode, only the individual bits of PORT B can be programmed
c) In BSR mode, only the individual bits of PORT C can be programmed
Explanation: BSR (Bit Set/Rest) mode is used to program individual bits of PORT C only.
332. How many pins of the 8255 can be used as the I/O ports?
a) 8
b) 16
c) 24
d) 32
Explanation: There are 3 ports available in the 8255 so 24 pins are available for the I/O ports pins.
TOPIC 15: “Interfacing with RTC”.
333. DS12887 is a ____________

a) Timer IC
b) Serial communication IC
c) RTC IC
d) Motor
Explanation: DS12887 is a real time clock that is widely used to provide accurate time and date for many
applications.
334. DS12887 has _____ amount of RAM.

a) 14 bytes
b) 114 bytes
c) 128 bytes
d) 64 bytes
Explanation: DS12887 has 128 bytes of non-volatile RAM.
335. DS12887 has _____ amount of RAM for general purpose applications.
a) 9 bytes
b) 114 bytes
c) 128 bytes
d) 14 bytes
Explanation: DS12887 has 128 bytes of non-volatile RAM. Out of 128 bytes, 14 bytes of RAM for
clock/calendar and control registers, and another 114 bytes of RAM for general purpose data storage.
336. In DS12887, which bits of the Register A are used to turn on the oscillator?
a) D4
b) D5
c) D6
Explanation: In DS12887, D4-D6 bits of register A are used to turn on the oscillator. A specific value of 010 of
D4-D6 is desirable for turning on the oscillator.
337 . In DS12887, which out of the following is correct about the SQW pin?
a) it is an output pin
b) it can provide up to 15 different square waves
c) the frequency of the square wave is set by the register A
d) all of the mentioned are correct
Explanation: In DS12887, SQW pin stands for SQuare Wave. It is an output pin that can provide us with 15
different square waves. The frequency of the square wave is selected by programming register A.
338. In DS12887, what is correct about the UIP bit of the register A?
a) it is a read only bit
b) it is used to know about the result
c) it is used to select the DS12887 datasheet
Explanation: In DS12887, UIP bit of register A stands for Update In Progress. The update-in-progress (UIP)
bit is a status flag i.e. read-only bit.
339. In DS12887, what is the range of RAM addresses which are used to store the values of time, calendar and
alarm data?
a) 00-7FH
b) 00-09H
c) 0EH-7FH
d) 0A-0DH
Explanation: In DS12887, the first ten locations i.e. 00-09H are used to store the values of time, calendar and
alarm data.
340. Is DS12887 has non-volatile RAM?

a) Yes
b) No
c) Can’t be determined
Explanation: Yes, DS12887 has non-volatile RAM.
341. Name the read only registers are present in the DS12887?
a) register A, register B
b) register B, register C
c) register C, register D
d) register D, register A
Explanation: Register C and D are the read only registers in the DS12887 found at memory locations 0C-0DH.
342. In DS12887, when the external source is turned-off, how does DS12887 get power to retain its data?
a) Internal Lithium Battery
b) Internal Lead Battery
c) Additional external Alkaline Battery
d) Additional external Lithium Battery
Explanation: When Vcc falls below 3V or external voltage source is switched-off, internal lithium battery
provides power to DS12887. And this will prevent loss of data.
TOPIC16:“I/O Port Programming and Addressing Modes”.
343. What is the principle on which electromagnetic relays operate?

a) electromagnetic induction
b) motor control
c) switching
Explanation: Electromagnetic relays are the devices that are used for switching of devices like motors, that
operates on the principle of electromagnetic induction.
344. What are DPDT relays?
a) Single pole, single throw
b) Single pole, double throw
c) Double pole, double throw
Explanation: In DPDT relays, there are double pole or two contacts are found namely normally open and
normally closed contacts, so it is called a double pole, double throw relays.
345. Why do we need a ULN2803 in driving a relay?
a) for switching a motor
b) for increasing the current limit in the relays
c) for increasing the power
d) for decreasing the current limit in the relays
Explanation: We need a ULN2803 for driving a relay because more current is generally required for driving a
relay that is generally not provided by a microcontroller, so we need a ULN2803 to increase the current limit.
346 . Why are solid relays advantageous over electromagnetic relays?
a) they need zero voltage circuit
b) they need less current to be energised
c) they need less voltage to be energised
Explanation: Solid relays are advantageous over electromagnetic relays because they are faster as they
consume less current to be energised.
347 . What are optoisolators?
a) it is a driver
b) it is a thing isolated from the entire world
c) it is a device that can be used as an electromagnetic relay without a driver
Explanation: Optoisolators are devices that can be used as an electromagnetic relay without a driver. It usually
consists of a led (transmitter) and a photoresistive receiver.
348 . How can we control the speed of a stepper motor?

a) by controlling its switching rate
b) by controlling its torque
c) by controlling its wave drive 4 step sequence
d) cant be controlled
Explanation: Speed of a stepper motor can be controlled by changing its switching speed or by changing the
length of the time delay loop.
349 . Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch
.
350 . The RPM rating given for the DC motor is for?
a) no-loaded
b) loaded
Explanation: RPM rating given for a DC motor is for a no-loaded condition.
351 . PWM allows the control of a DC motor with the same phase, but with different amplitude phases?
a) true
b) false
Explanation: PWM allows the control of a DC motor with the same amplitude, but with different phases.
352 .How can the direction of the DC motor be changed?

a) by changing the torque
b) by changing the switching speed
c) by changing the polarity of voltages connected to the leads
d) by changing the RPM rating
TOPIC16:“I/O Port Programming and Addressing Modes”.

353. What is the principle on which electromagnetic relays operate?
a) electromagnetic induction
b) motor control
c) switching
Explanation: Electromagnetic relays are the devices that are used for switching of devices like motors, that
operates on the principle of electromagnetic induction.
354. What are DPDT relays?
a) Single pole, single throw
b) Single pole, double throw
c) Double pole, double throw
Explanation: In DPDT relays, there are double pole or two contacts are found namely normally open and
normally closed contacts, so it is called a double pole, double throw relays.
355. Why do we need a ULN2803 in driving a relay?
356. Why are solid relays advantageous over electromagnetic relays?
357. What are optoisolators?
a) it is a driver
358. How can we control the speed of a stepper motor?
359. Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.
360. The RPM rating given for the DC motor is for?
a) no-loaded
b) loaded
361. PWM allows the control of a DC motor with the same phase, but with different amplitude phases?
a) true
b) false
362. How can the direction of the DC motor be changed?
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected
to its leads.
363 .ULN2803 in driving a relay?
364. Why are solid relays advantageous over electromagnetic relays?
365. What are optoisolators?
a) it is a driver
366. How can we control the speed of a stepper motor?
367. Which of the following can be a unit for torque?
a) kg/m2
b) ounce-inch
c) kg-m3
d) g/m
Explanation: Torque is equal to the force applied at a particular distance. So its unit can be ounce-inch.
368. The RPM rating given for the DC motor is for?
a) no-loaded
b) loaded
369. PWM allows the control of a DC motor with the same phase, but with different amplitude phases?
a) true
b) false
370
. How can the direction of the DC motor be changed?
Explanation: The direction of the DC motor can be changed by changing the polarity of the voltages connected
to its leads.
TOPIC 17 :Advanced Virtual RISC Microcontroller Architecture

371. Is the following instruction correct LDI R3,50?
a) Yes
b) No
c) Cant be said
Explanation: If LDI Rd,k is written then the range of Rd varies from R16-R31, as R3 is less than R16 so this
instruction will generate an error.
372.Registers R0-R31 are used for what type of works?
a) they are used for arithmetic and logic instructions
b) they are used for data copy
c) they are used for calculations
Explanation: GPRs are used for implementing arithmetic and logic instructions in the controller. They do the
same work as the accumulator does in the other microcontrollers and microprocessors.
373. The largest value that can be loaded in an 8 bit register is?
a) 11111111H
b) FH
c) FFH
d) 00H
Explanation: The largest value that can be loaded in an 8 bit register is 11111111b or FFH.
374. The total space for the data memory available in the AVR based microcontroller is?
a) FFH
b) FFFH
c) FFFFH
d) FFFFFH
Explanation: The maximum value that can be loaded in the code memory of an AVR based microcontroller is
FFFFH.
375. Which of the following instructions affect the flags of the status register?
a) AND
b) INC
c) OR
Explanation: AND, INC, OR could affect status register flags. All arithmetic and logical instructions affect
status register flags except SER Rd instruction. SER Rd is used to SEt Register i.e. after the execution of this
instruction Rd loaded with FFH value and no flag is affected.
376. What is the difference between the two given instructions?
LDI R16,0x34 and LDI R16,$34
a) One copies the hexadecimal value to R16 and the other copies the decimal value to the R16 register
b) One is for command, other is for data
c) One is for assignment, other is for operations
d) Both the commands are the same
Explanation: Both the above commands are the same. They both are used for assigning the hexadecimal values
to the registers.
377. Which out of the following is not a directive?
a) .EQU
b) .DEVICE
c) .ORG
d) .LDI
Explanation: .EQU, .DEVICE, .ORG all are the directives to the assembler whereas LDI is a command.
378. Is an assembly language a high level language?
a) Yes
b) No
c) Cant be said
Explanation: High Level Languages are the languages that are written in the common english, so that even a
common man can understand it easily like C, C++, whereas assembly language is a middle level language
between the high level and the machine level.
379. A 14 bit program counter can execute a maximum of _________ memory locations?
a) 4K
b) 8K
c) 16K
d) 64K
Explanation: A program counter of an AVR is 14 bit long which means it has 2^14 bytes of memory or 16K
bytes of memory.
380. When AVR wakes up, then the value of PC becomes?
a) 00H
b) 000H
c) 0000H
d) 00000H
Explanation: When an AVR wakes up, then the PC starts at the memory location 00000H.
TOPIC 18 : “Jump, Loop and Call Instructions”.
381. Which of the following is correct about BRNE instruction in avr microcontrollers?
a) it is used to compare two registers
b) it is used to compare two values
c) it is used to check the zero flag
d) it is used to jump to the given mentioned label when the zero flag accounts to 0
Explanation: BRNE label instruction is used to jump to that particular address denoted by label if condition
(Z=0) is true or satisfied. If the condition is not satisfied then it will execute the next immediate instruction.
382. How many times is this loop going to get executed?
LDI R20, 10
now: LDI R21, 70
DEC R21
BRNE now
OUT PORTB, R20
a) 10
b) 70
c) 700
Explanation: As the R21 register is loaded with 70, so to make it zero it needs to be decremented 70 times then
only the OUT instruction will be executed so this loop repeats 70 times.
383. Which of the below mentioned are not the conditional jumps?
a) BRLO
b) BRMI
c) BRVC
Explanation: BRLO is used to branch if C=1, BRMI is used when N=1 and BRVC are used when V=0, so all
are the conditional jumps.
384. What is the relation between the target and the relative address?
a) target address= PC address + relative address
b) target address= relation address*2
c) relative address= PC address + target address
Explanation: Target address can be calculated by calculating the sum of the address of the program counter and
the relative address.
385. In the JMP instruction, how many bits are there for determining the target address?
a) 16
b) 32
c) 22
d) 10
Explanation: In the JMP instruction of 4 bytes space, 22 bits are there for determining the target address and
the other 10 are for the op code verification.
386. Which of the following statements are correct?
a) relative address of RJMP instruction varies from 000-fffH
b) target address of JMP instruction varies from 000000-3fffffH
c) IJMP instruction jumps to that address that points to by the Z register
Explanation: The relative address of the RJMP instruction varies from 000-fffH. The target address of the JMP
instruction varies from 000000-3fffffH. IJMP instruction is used to jump at that particular address pointed to by
the Z register. So all are the correct statements.
387. Which of the following is used to represent the last RAM address?
a) MEM
b) LASTRAM
c) RAMEND
Explanation: RAMEND instruction is used to represent the last RAM address. By loading RAMEND to the SP
register, the stack pointer represents the last RAM address.
388. Which of the following statements are correct about the RCALL instruction?
a) it is a 2 byte instruction
b) it is a 4 byte instruction
c) it is a 16 byte instruction
Explanation: RCALL instruction is used to go to the target address in the memory from -2048 to 2047.
389. On power on SP points to the address?
a) ffffH
b) fffH
c) 00h
Explanation: On power on SP register points to the 00H address.
390. Which of the following statements is true?
a) CALL instruction is used to transfer control anywhere in the 4M memory space
b) PUSH instruction is used to take out the value from the stack into some register
c) POP instruction is used to jump to any location
d) RCALL is a 4 byte instruction
Explanation: CALL instruction is used to transfer control anywhere in the 4M memory space available in the
AVR.
TOPIC 19 :“I/O Port Programming and Addressing Modes”.
391. In AVR, which registers are there for the I/O programming of ports?
a) PORT
b) PIN
c) DDR
Explanation: For I/O programming of the ports in AVR microcontrollers, there are basically three main
registers. They are PORT, PIN, DDR, so all of the mentioned is the right option.
392. The data will not go from the port registers to the pin unless:
a) DDR register of that port is set to 0

b) PORT register of that port is set to 1
c) DDR register of that port is set to 1
d) PORT register of that port is set to 0
Explanation: The data will not go from the port registers to the pin unless the DDR register of that port is set to
1 because by doing this we make that port an output port after which data can be taken from the PORT registers
to the pin.
393. On reset DDR registers of all ports are set to:
a) 0
b) 1
d) 0 & 1
Explanation: On reset, the DDR registers of all the ports are set to 0 which means that the by default all ports
are set as input ports.
394. Which of the following statements are correct?
a) PIN register of a port is used to bring data into CPU from pins
b) PORT register is used to send data out to pins
c) DDR register is used to control the direction of a port
Explanation: There are three registers that are related to a port. They are PIN, PORT, DDR. PIN register is
used to bring data into CPU from pins, PORT register is used to send data to pins and DDR register is used to
control the direction of the data transfer. So all are the right options.
395. All series of AVR has 8 pins in all of their ports?
a) true
b) false
d) can’t be determined
Explanation: Atmega8 series has 7 pins in its PORTC.
396. Which of the following is not a single bit instruction in AVR?
a) SBI
b) PORT
c) CBI
Explanation: PORT is not a single bit instruction in an AVR microcontroller. It is a byte oriented instruction
used to take the data out of the CPU to the pins.
397. Which of the following is correct about the SBIS instruction?
a) it is used to the monitor the status of the HIGH for the single bit of a port
b) it is a byte oriented instruction
c) It is a 4 byte instruction
Explanation: SBIS is a bit oriented 2 byte instruction that is used to monitor the status of a single bit of a port.
398. Instruction CBI PORTB,1 means
a) clearing the PORTB register
b) clearing the first bit of the PORTB register
c) setting the PORTB register
d) setting the first bit of the PORTB register
Explanation: CBI PORTB, 1 means to clear the first bit of the PORTB register. It is a bit oriented instruction.
399. Which of the following instruction can be used to toggle a bit of the PORT?
a) SBI
b) CBI
c) SBI & CBI
Explanation: If SBI and CBI are used together, then they can be used to toggle a bit of a port successfully.
400. What is the main function of the SBIC instruction?
a) it is used to clear a particular bit of a port
b) it is used to jump unconditionally
c) it is used to skip the instruction if a particular bit of a port is zero
Explanation: SBIC is used to skip the instruction when a particular bit of a port is set to zero.
III .Digital Electronics
401. Any signed negative binary number is recognised by its ________

a) MSB
b) LSB
c) Byte
d) Nibble
402. The parameter through which 16 distinct values can be represented is known as ________
a) Bit
b) Byte
c) Word
d) Nibble
403. If the decimal number is a fraction then its binary equivalent is obtained by ________ the number
continuously by 2.
a) Dividing
b) Multiplying
c) Adding
d) Subtracting
404. The decimal equivalent of the binary number (1011.011)2 is ________

a) (11.375)10
b) (10.123)10
c) (11.175)10
d) (9.23)10
405. An important drawback of binary system is ________

a) It requires very large string of 1’s and 0’s to represent a decimal number
b) It requires sparingly small string of 1’s and 0’s to represent a decimal number
c) It requires large string of 1’s and small string of 0’s to represent a decimal number
d) It requires small string of 1’s and large string of 0’s to represent a decimal number
406. The decimal equivalent of the octal number (645)8 is ______

a) (450)10
b) (451)10
c) (421)10
d) (501)10
407. The largest two digit hexadecimal number is ________

a) (FE)16
b) (FD)16
c) (FF)16
d) (EF)16
408. Representation of hexadecimal number (6DE)H in decimal:

a) 6 * 162 + 13 * 161 + 14 * 160
b) 6 * 162 + 12 * 161 + 13 * 160
c) 6 * 162 + 11 * 161 + 14 * 160
d) 6 * 162 + 14 * 161 + 15 * 160
409. The quantity of double word is ________

a) 16 bits
b) 32 bits
c) 4 bits
d) 8 bits
410. If the number of bits in the sum exceeds the number of bits in each added numbers, it results in _________
a) Successor
b) Overflow
c) Underflow
d) Predecessor
411. An overflow is a _________

a) Hardware problem
b) Software problem
c) User input problem
d) Input Output Error
412. An overflow occurs in _________

a) MSD position
b) LSD position
c) Middle position
d) Signed Bit
413. Logic circuitry is used to detect _________

a) Underflow
b) MSD
c) Overflow
d) LSD
414. 1’s complement can be easily obtained by using _________
a) Comparator
b) Inverter
c) Adder
d) Subtractor
415. The advantage of 2’s complement system is that _________

a) Only one arithmetic operation is required
b) Two arithmetic operations are required
c) No arithmetic operations are required
d) Different Arithmetic operations are required
416. The 1’s complements requires _________

a) One operation
b) Two operations
c) Three operations
d) Combined Operations
417. Which one is used for logical manipulations?

a) 2’s complement
b) 9’s complement
c) 1’s complement
d) 10’s complement
418. For arithmetic operations only _________

a) 1’s complement is used
b) 2’s complement
c) 10’s complement
d) 9’s complement
419. The addition of +19 and +43 results as _________ in 2’s complement system.
a) 11001010
b) 101011010
c) 00101010
d) 0111110
420. Binary coded decimal is a combination of __________

a) Two binary digits
b) Three binary digits
c) Four binary digits
d) Five binary digits
421. The decimal number 10 is represented in its BCD form as __________

a) 10100000
b) 01010111
c) 00010000
d) 00101011
422. Add the two BCD numbers: 1001 + 0100 = ?

a) 10101111
b) 01010000
c) 00010011
d) 00101011
423. Carry out BCD subtraction for (68) – (61) using 10’s complement method.
a) 00000111
b) 01110000
c) 100000111
d) 011111000
424. Code is a symbolic representation of __________ information.

a) Continuous
b) Discrete
c) Analog
d) Both continuous and discrete
425. When numbers, letters or words are represented by a special group of symbols, this process is called
__________
a) Decoding
b) Encoding
c) Digitizing
d) Inverting
426. A three digit decimal number requires ________ for representation in the conventional BCD format.
a) 3 bits
b) 6 bits
c) 12 bits
d) 24 bits
427. How many bits would be required to encode decimal numbers 0 to 9999 in straight binary codes?
a) 12
b) 14
c) 16
d) 18
428. The excess-3 code for 597 is given by __________

a) 100011001010
b) 100010100111
c) 010110010111
d) 010110101101
429. The decimal equivalent of the excess-3 number 110010100011.01110101 is _____________

a) 970.42
b) 1253.75
c) 861.75
d) 1132.87
430. In boolean algebra, the OR operation is performed by which properties?

a) Associative properties
b) Commutative properties
c) Distributive properties
d) All of the Mentioned
431. The expression for Absorption law is given by _________
a) A + AB = A
b) A + AB = B
c) AB + AA’ = A
d) A + B = B + A
432. According to boolean law: A + 1 = ?

a) 1
b) A
c) 0
d) A’
433. The involution of A is equal to _________

a) A
b) A’
c) 1
d) 0
434. A(A + B) = ?
a) AB
b) 1
c) (1 + AB)
d) A
435. DeMorgan’s theorem states that _________

a) (AB)’ = A’ + B’
b) (A + B)’ = A’ * B
c) A’ + B’ = A’B’
d) (AB)’ = A’ + B
436. (A + B)(A’ * B’) = ?

a) 1
b) 0
c) AB
d) AB’
437. Complement of the expression A’B + CD’ is _________

a) (A’ + B)(C’ + D)
b) (A + B’)(C’ + D)
c) (A’ + B)(C’ + D)
d) (A + B’)(C + D’)
438. Simplify Y = AB’ + (A’ + B)C.

a) AB’ + C
b) AB + AC
c) A’B + AC’
d) AB + A
439. The boolean function A + BC is a reduced form of ____________

a) AB + BC
b) (A + B)(A + C)
c) A’B + AB’C
d) (A + C)B
440. The logical sum of two or more logical product terms is called __________
a) SOP
b) POS
c) OR operation
d) NAND operation
441. The expression Y=AB+BC+AC shows the _________ operation.

a) EX-OR
b) SOP
c) POS
d) NOR
442. The expression Y=(A+B)(B+C)(C+A) shows the _________ operation.

a) AND
b) POS
c) SOP
d) NAND
443. A product term containing all K variables of the function in either complemented or uncomplemented form
is called a __________
a) Minterm
b) Maxterm
c) Midterm
d) ∑ term
444. According to the property of minterm, how many combination will have value equal to 1 for K input
variables?
a) 0
b) 1
c) 2
d) 3
445. The canonical sum of product form of the function y(A,B) = A + B is __________
a) AB + BB + A’A
b) AB + AB’ + A’B
c) BA + BA’ + A’B’
d) AB’ + A’B + A’B’
446. A variable on its own or in its complemented form is known as a __________

a) Product Term
b) Literal
c) Sum Term
d) Word
447. Maxterm is the sum of __________ of the corresponding Minterm with its literal complemented.
a) Terms
b) Words
c) Numbers
d) Nibble
448. Canonical form is a unique way of representing ____________
a) SOP
b) Minterm
c) Boolean Expressions
d) POS
449. There are _____________ Minterms for 3 variables (a, b, c).

a) 0
b) 2
c) 8
d) 1
450. _____________ expressions can be implemented using either (1) 2-level AND-OR logic circuits or (2) 2-
level NAND logic circuits.
a) POS
b) Literals
c) SOP
d) POS
451. A Karnaugh map (K-map) is an abstract form of ____________ diagram organized as a matrix of squares.
a) Venn Diagram
b) Cycle Diagram
c) Block diagram
d) Triangular Diagram
452. There are ______ cells in a 4-variable K-map.

a) 12
b) 16
c) 18
d) 8
453. The K-map based Boolean reduction is based on the following Unifying Theorem: A + A’ = 1.
a) Impact
b) Non Impact
c) Force
d) Complementarity
454. Each product term of a group, w’.x.y’ and w.y, represents the ____________in that group.
a) Input
b) POS
c) Sum-of-Minterms
d) Sum of Maxterms
455. The prime implicant which has at least one element that is not present in any other implicant is known as
___________
a) Essential Prime Implicant
b) Implicant
c) Complement
d) Prime Complement
456. Product-of-Sums expressions can be implemented using ___________

a) 2-level OR-AND logic circuits
b) 2-level NOR logic circuits
c) 2-level XOR logic circuits
d) Both 2-level OR-AND and NOR logic circuits
457. Each group of adjacent Minterms (group size in powers of twos) corresponds to a possible product term of
the given ___________
a) Function
b) Value
c) Set
d) Word
458. Don’t care conditions can be used for simplifying Boolean expressions in ___________
a) Registers
b) Terms
c) K-maps
d) Latches
459. It should be kept in mind that don’t care terms should be used along with the terms that are present in
___________
a) Minterms
b) Expressions
c) K-Map
d) Latches
460. Using the transformation method you can realize any POS realization of OR-AND with only.
a) XOR
b) NAND
c) AND
d) NOR
461. There are many situations in logic design in which simplification of logic expression is possible in terms of
XOR and _________________ operations.
a) X-NOR
b) XOR
c) NOR
d) NAND
462. These logic gates are widely used in _______________ design and therefore are available in IC form.
a) Sampling
b) Digital
c) Analog
d) Systems
463. In case of XOR/XNOR simplification we have to look for the following _______________
a) Diagonal Adjacencies
b) Offset Adjacencies
c) Straight Adjacencies
d) Both diagonal and offset adjencies
464. Entries known as _______________ mapping.

a) Diagonal
b) Straight
c) K
d) Boolean
465. The output of an EX-NOR gate is 1. Which input combination is correct?

a) A = 1, B = 0
b) A = 0, B = 1
c) A = 0, B = 0
d) A = 0, B’ = 1
466. In which of the following gates the output is 1 if and only if at least one input is 1?
a) AND
b) NOR
c) NAND
d) OR
467. The time required for a gate or inverter to change its state is called __________
a) Rise time
b) Decay time
c) Propagation time
d) Charging time
468. What is the minimum number of two input NAND gates used to perform the function of two input OR
gates?
a) One
b) Two
c) Three
d) Four
469. Odd parity of word can be conveniently tested by ___________

a) OR gate
b) AND gate
c) NAND gate
d) XOR gate
470. The number of full and half adders are required to add 16-bit number is __________
a) 8 half adders, 8 full adders
b) 1 half adders, 15 full adders
c) 16 half adders, 0 full adders
d) 4 half adders, 12 full adders
471. Which of the following will give the sum of full adders as output?
a) Three point major circuit
b) Three bit parity checker
c) Three bit comparator
d) Three bit counter
472. Which of the following gate is known as coincidence detector?

a) AND gate
b) OR gate
c) NOR gate
d) NAND gate
473. An OR gate can be imagined as ____________

a) Switches connected in series
b) Switches connected in parallel
c) MOS transistor connected in series
d) BJT transistor connected in series
474. How many full adders are required to construct an m-bit parallel adder?
a) m/2
b) m
c) m-1
d) m+1
475. The following switching functions are to be implemented using a decoder:

f1 = ∑m(1, 2, 4, 8, 10, 14) f2 = ∑m(2, 5, 9, 11) f3 = ∑m(2, 4, 5, 6, 7)
The minimum configuration of decoder will be __________
a) 2 to 4 line
b) 3 to 8 line
c) 4 to 16 line
d) 5 to 32 line
476. How many AND gates are required to realize Y = CD + EF + G?

a) 4
b) 5
c) 3
d) 2
477. The NOR gate output will be high if the two inputs are __________
a) 00
b) 01
c) 10
d) 11
478. How many two-input AND and OR gates are required to realize Y = CD+EF+G?
a) 2, 2
b) 2, 3
c) 3, 3
d) 3, 2
479. A universal logic gate is one which can be used to generate any logic function. Which of the following is a
universal logic gate?
a) OR
b) AND
c) XOR
d) NAND
480. A full adder logic circuit will have __________

a) Two inputs and one output
b) Three inputs and three outputs
c) Two inputs and two outputs
d) Three inputs and two outputs
481. How many two input AND gates and two input OR gates are required to realize Y = BD + CE + AB?
a) 3, 2
b) 4, 2
c) 1, 1
d) 2, 3
482. Which of following are known as universal gates?

a) NAND & NOR
b) AND & OR
c) XOR & OR
d) EX-NOR & XOR
483. The gates required to build a half adder are __________

a) EX-OR gate and NOR gate
b) EX-OR gate and OR gate
c) EX-OR gate and AND gate
d) EX-NOR gate and AND gate
484. A single transistor can be used to build which of the following digital logic gates?
a) AND gates
b) OR gates
c) NOT gates
d) NAND gates
485. How many truth table entries are necessary for a four-input circuit?
a) 4
b) 8
c) 12
d) 16
486. Which input values will cause an AND logic gate to produce a HIGH output?
a) At least one input is HIGH
b) At least one input is LOW
c) All inputs are HIGH
d) All inputs are LOW
487. Exclusive-OR (XOR) logic gates can be constructed from what other logic gates?
a) OR gates only
b) AND gates and NOT gates
c) AND gates, OR gates, and NOT gates
d) OR gates and NOT gates
488. The basic logic gate whose output is the complement of the input is the ___________
a) OR gate
b) AND gate
c) INVERTER gate
d) XOR gate
489. The AND function can be used to ___________ and the OR function can be used to _____________
a) Enable, disable
b) Disable, enable
c) Synchronize, energize
d) Detect, invert
490. The dependency notation “>=1” inside a block stands for which operation?
a) OR
b) XOR
c) AND
d) XNOR
491. If we use an AND gate to inhibit a signal from passing one of the inputs must be ___________
a) LOW
b) HIGH
c) Inverted
d) Floating
492. Logic gate circuits contain predictable gate functions that open theirs ____________
a) Outputs
b) Inputs
c) Pre-state
d) Impedance state
493. SSI refers to ___________

a) Small Scale Integration
B) Short Scale Integration
c) Small Set Integration
d) Short Set Integration
494. Small Scale Integration(SSI) refers to ICs with __________ gates on the same chip.
a) Fewer than 10
b) Greater than 10
c) Equal to 10
d) Greater than 50
495. MSI means ___________

a) Merged Scale Integration
b) Main Scale Integration
c) Medium Scale Integration
d) Main Set Integration
496. MSI includes _______ gates per chip.

a) 12 to 100
b) 13 to 50
c) greater than 10
d) greater than 100
497. LSI means ________ and refers to ________ gates per chip.
a) Long Scale Integration, more than 10 upto 10000
b) Large Scale Integration, more than 100 upto 5000
c) Large Short Integration, less than 10 and greater than 5000
d) Long Short Integration, more than 10 upto 10000
498. Integrated circuits are classified as ___________

a) Large, Small and Medium
b) Very Large, Small and Linear
c) Linear and Digital
d) Non-Linear and Digital
499. The full form of DIP is ___________

a) Dual-in-Long Package
b) Dual-in-Line Package
c) Double Integrated Package
d) Double-in-Line Package
500. LCC refers to ___________

a) Longest Chip Carrier
b) Leadless Chip Carrier
c) Leaded Chip Carrier
d) Large Chip Carrier
501. PGA refers to ____________

a) Plastic Grid Array
b) Pin Grid Array
c) Pin Greater Array
d) Plastic Greater Array
502. MOS families includes __________

a) PMOS and NMOS
b) CMOS and NMOS
c) PMOS, NMOS and CMOS
d) EMOS, NMOS and PMOS
503. CMOS refers to __________

a) Continuous Metal Oxide Semiconductor
b) Complementary Metal Oxide Semiconductor
c) Centred Metal Oxide Semiconductor
d) Concrete Metal Oxide Semiconductor
504. Propagation delay is defined as __________
a) the time taken for the output of a gate to change after the inputs have changed
b) the time taken for the input of a gate to change after the outputs have changed
c) the time taken for the input of a gate to change after the intermediates have changed
d) the time taken for the output of a gate to change after the intermediates have changed
505. Propagation delay times can be divided as __________

a) t(PLH) and t(LPH)
b) t(LPH) and t(PHL)
c) t(PLH) and t(PHL)
d) t(HPL) and t(LPH)
506. Power Dissipation in DIC is expressed in __________

a) Watts or kilowatts
b) Milliwatts or nanowatts
c) DB
d) Mdb
507. The maximum noise voltage that may appear at the input of a logic gate without changing the logical state
of its output is termed as __________
a) Noise Margin
b) Noise Immunity
c) White Noise
d) Signal to Noise Ratio
508. All input of NOR as low produces result as __________

a) Low
b) Mid
c) High
d) Floating
509. In RTL NOR gate, the output is at logic 1 only when all the inputs are at __________
a) logic 0
b) logic 1
c) +10V
d) Floating
510. Resistor–transistor logic (RTL) is a class of digital circuits built using _______ as the input network and
_______ as switching devices.
a) Resistors, bipolar junction transistors (BJTs)
b) Bipolar junction transistors (BJTs), Resistors
c) Capacitors, resistors
d) Resistors, capacitors
511. The limitations of the one transistor RTL NOR gate are overcome by __________
a) Two-transistor RTL implementation
b) Three-transistor RTL implementation
c) Multi-transistor RTL implementation
d) Four-transistor RTL implementation
512. TTL circuits with “totem-pole” output stage minimize __________

a) The power dissipation in RTL
b) The time consumption in RTL
c) The speed of transferring rate in RTL
d) Propagation delay in RTL
513. The minimum number of transistors can be used by 2 input AND gate is __________
a) 2
b) 3
c) 4
d) 5
514. Diode–transistor logic (DTL) is the direct ancestor of _____________

a) Register-transistor logic
b) Transistor–transistor logic
c) High threshold logic
d) Emitter Coupled Logic
515. In DTL logic gating function is performed by ___________

a) Diode
b) Transistor
c) Inductor
d) Capacitor
516. In DTL amplifying function is performed by ___________

a) Diode
b) Transistor
c) Inductor
d) Capacitor
517. How many stages a DTL consist of?

a) 2
b) 3
c) 4
d) 5
518. The full form of CTDL is ___________

a) Complemented transistor diode logic
b) Complemented transistor direct logic
c) Complementary transistor diode logic
d) Complementary transistor direct logic
519. Transistor–transistor logic (TTL) is a class of digital circuits built from ____________
a) JFET only
b) Bipolar junction transistors (BJT)
c) Resistors
d) Bipolar junction transistors (BJT) and resistors
520. TTL is called transistor–transistor logic because both the logic gating function and the amplifying function
are performed by ____________
a) Resistors
b) Bipolar junction transistors
c) One transistor
d) Resistors and transistors respectively
521. The full form of TCTL is ____________
a) Transistor-coupled transistor logic
b) Transistor-capacitor transistor logic
c) Transistor-complemented transistor logic
d) Transistor-complementary transistor logic
522. The full form of ECL is __________

a) Emitter-collector logic
b) Emitter-complementary logic
c) Emitter-coupled logic
d) Emitter-cored logic
523. Which logic is the fastest of all the logic families?

a) TTL
b) ECL
c) HTL
d) DTL
524. The full form of MOS is ___________

a) Metal oxide semiconductor
b) Metal oxygen semiconductor
c) Metallic oxide semiconductor
d) Metallic oxygen semiconductor
525. What are the types of MOSFET devices available?

a) P-type enhancement type MOSFET
b) N-type enhancement type MOSFET
c) Depletion type MOSFET
526. Which insulating layer used in the fabrication of MOSFET?

a) Aluminium oxide
b) Silicon Nitride
c) Silicon dioxide
d) Aluminium Nitrate
527. Which of the following plays an important role in improving device performance of MOSFET?
a) Dielectric constant
b) Threshold voltage
c) Power supply voltage
d) Gate to drain voltage
528. The full form of CMOS is ____________

a) Capacitive metal oxide semiconductor
b) Capacitive metallic oxide semiconductor
c) Complementary metal oxide semiconductor
d) Complemented metal oxide semiconductor
529. Two important characteristics of CMOS devices are ____________

a) High noise immunity
b) Low static power consumption
c) High resistivity
d) Both high noise immunity and low static power consumption
530. CMOS behaves as a/an ____________

a) Adder
b) Subtractor
c) Inverter
d) Comparator
531. CMOS logic dissipates _______ power than NMOS logic circuits.
a) More
b) Less
c) Equal
d) Very High
532. Semiconductors are made of ____________

a) Ge and Si
b) Si and Pb
c) Ge and Pb
d) Pb and Au
533. The basic building blocks of the arithmetic unit in a digital computers are __________
a) Subtractors
b) Adders
c) Multiplexer
d) Comparator
534. A digital system consists of _____ types of circuits.

a) 2
b) 3
c) 4
d) 5
535. In a combinational circuit, the output at any time depends only on the _______ at that time.
a) Voltage
b) Intermediate values
c) Input values
d) Clock pulses
536. In a sequential circuit, the output at any time depends only on the input values at that time.
a) Past output values
b) Intermediate values
c) Both past output and present input
d) Present input values
537. All logic operations can be obtained by means of __________

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
538. The design of an ALU is based on __________

a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
539. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____
result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
540. The flag bits in an ALU is defined as ___________

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
541. In parts of the processor, adders are used to calculate ____________

a) Addresses
b) Table indices
c) Increment and decrement operators
542. Total number of inputs in a half adder is __________

a) 2
b) 3
c) 4
d) 1
543. In which operation carry is obtained?

a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
544. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
545. If A and B are the inputs of a half adder, the carry is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
546. Half-adders have a major limitation in that they cannot __________

a) Accept a carry bit from a present stage
b) Accept a carry bit from a next stage
c) Accept a carry bit from a previous stage
d) Accept a carry bit from the following stages
547. The difference between half adder and full adder is __________
a) Half adder has two inputs while full adder has four inputs
b) Half adder has one output while full adder has two outputs
c) Half adder has two inputs while full adder has three inputs
548. If A, B and C are the inputs of a full adder then the sum is given by __________
a) A AND B AND C
b) A OR B AND C
c) A XOR B XOR C
d) A OR B OR C
549. If A, B and C are the inputs of a full adder then the carry is given by __________
a) A AND B OR (A OR B) AND C
b) A OR B OR (A AND B) C
c) (A AND B) OR (A AND B)C
d) A XOR B XOR (A XOR B) AND C
550. How many AND, OR and EXOR gates are required for the configuration of full adder?
a) 1, 2, 2
b) 2, 1, 2
c) 3, 1, 2
d) 4, 0, 1
551. Half subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 5 bits
552. For subtracting 1 from 0, we use to take a _______ from neighbouring bits.
a) Carry
b) Borrow
c) Input
d) Output
553. How many outputs are required for the implementation of a subtractor?
a) 1
b) 2
c) 3
d) 4
554. Let the input of a subtractor is A and B then what the output will be if A = B?
a) 0
b) 1
c) A
d) B
555. Let A and B is the input of a subtractor then the output will be ___________
a) A XOR B
b) A AND B
c) A OR B
d) A EXNOR B
556. Let A and B is the input of a subtractor then the borrow will be ___________
a) A AND B’
b) A’ AND B
c) A OR B
d) A AND B
557. What does minuend and subtrahend denotes in a subtractor?

a) Their corresponding bits of input
b) Its outputs
c) Its inputs
d) Borrow bits
558. Full subtractor is used to perform subtraction of ___________

a) 2 bits
b) 3 bits
c) 4 bits
d) 8 bits
559. The full subtractor can be implemented using ___________

a) Two XOR and an OR gates
b) Two half subtractors and an OR gate
c) Two multiplexers and an AND gate
d) Two comparators and an AND gate
560. The output of a subtractor is given by (if A, B and X are the inputs).
a) A AND B XOR X
b) A XOR B XOR X
c) A OR B NOR X
d) A NOR B XOR X
561. The output of a full subtractor is same as ____________

a) Half adder
b) Full adder
c) Half subtractor
d) Decoder
562. All logic operations can be obtained by means of ____________

a) AND and NAND operations
b) OR and NOR operations
c) OR and NOT operations
d) NAND and NOR operations
564. The design of an ALU is based on ____________

a) Sequential logic
b) Combinational logic
c) Multiplexing
d) De-Multiplexing
565. If the two numbers are unsigned, the bit conditions of interest are the ______ carry and a possible _____
result.
a) Input, zero
b) Output, one
c) Input, one
d) Output, zero
566. If the two numbers include a sign bit in the highest order position, the bit conditions of interest are the sign
of the result, a zero indication and ___________
a) An underflow condition
b) A neutral condition
c) An overflow condition
d) One indication
567. The flag bits in an ALU is defined as ____________

a) The total number of registers
b) The status bit conditions
c) The total number of control lines
568. Which statement below best describes a Karnaugh map?

a) It is simply a rearranged truth table
b) The Karnaugh map eliminates the need for using NAND and NOR gates
c) Variable complements can be eliminated by using Karnaugh maps
d) A Karnaugh map can be used to replace Boolean rules
569. Which of the examples below expresses the commutative law of multiplication?
a) A + B = B + A
b) A • B = B + A
c) A • (B • C) = (A • B) • C
d) A • B = B • A
570. The Boolean expression Y = (AB)’ is logically equivalent to what single gate?
a) NAND
b) NOR
c) AND
d) OR
571. The observation that a bubbled input OR gate is interchangeable with a bubbled output AND gate is
referred to as:
a) A Karnaugh map
b) DeMorgan’s second theorem
c) The commutative law of addition
d) The associative law of multiplication
572. The systematic reduction of logic circuits is accomplished by:

a) Symbolic reduction
b) TTL logic
c) Using Boolean algebra
d) Using a truth table
573. Each “1” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
574. Each “0” entry in a K-map square represents:

a) A HIGH for each input truth table condition that produces a HIGH output
b) A HIGH output on the truth table for all LOW input combinations
c) A LOW output for all possible HIGH input conditions
d) A DON’T CARE condition for all possible input truth table combinations
575. Which of the following statements accurately represents the two BEST methods of logic circuit
simplification?
a) Actual circuit trial and error evaluation and waveform analysis
b) Karnaugh mapping and circuit waveform analysis
c) Boolean algebra and Karnaugh mapping
d) Boolean algebra and actual circuit trial and error evaluation
576. Looping on a K-map always results in the elimination of __________

a) Variables within the loop that appear only in their complemented form
b) Variables that remain unchanged within the loop
c) Variables within the loop that appear in both complemented and uncomplemented form
d) Variables within the loop that appear only in their uncomplemented form
577. Which of the following expressions is in the sum-of-products form?

a) (A + B)(C + D)
b) (A * B)(C * D)
c) A* B *(CD)
d) A * B + C * D
578. Which of the following is an important feature of the sum-of-products form of expressions?
a) All logic circuits are reduced to nothing more than simple AND and OR operations
b) The delay times are greatly reduced over other forms
c) No signal must pass through more than two gates, not including inverters
d) The maximum number of gates that any signal must pass through is reduced by a factor of two
579. Which of the following expressions is in the product-of-sums form?
a) (A + B)(C + D)
b) (AB)(CD)
c) AB(CD)
d) AB + CD
580. Controlled inverter is also known as _____________

a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate
582. Why XOR gate is called an inverter?

a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) It behaves like a AND gate
583. Controlled buffers can be useful __________

a) To control the circuit’s output into the bus
b) In comparison of component’s output with its input
c) In increasing the output from its low input
584. What is the first thing you will need if you are going to use a macro-function?
a) A complicated design project
b) An experienced design engineer
c) Good documentation
d) Experience in HDL
585. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
586. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
587. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
588. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
589. The selector inputs to an arithmetic/logic unit (ALU) determine the __________
a) Selection of the IC
b) Arithmetic or logic function
c) Data word selection
d) Clock frequency to be used
590. Controlled inverter is also known as ____________

a) Controlled buffer
b) NOT gate
c) Both controlled buffer and NOT gate
d) Controlled gate.
592. Why XOR gate is called an inverter?
a) Because of the same input
b) Because of the same output
c) It behaves like a NOT gate
d) It behaves like a AND gate
593. The binary subtraction of 0 – 0 = ?

a) Difference = 0, borrow = 0
b) Difference = 1, borrow = 0
c) Difference = 1, borrow = 1
d) Difference = 0, borrow = 1
594. How many basic binary subtraction operations are possible?

a) 1
b) 4
c) 3
d) 2
594. What are the two types of basic adder circuits?

a) Sum and carry
b) Half-adder and full-adder
c) Asynchronous and synchronous
d) One and two’s-complement
595. Which of the following is correct for full adders?

a) Full adders have the capability of directly adding decimal numbers
b) Full adders are used to make half adders
c) Full adders are limited to two inputs since there are only two binary digits
d) In a parallel full adder, the first stage may be a half adder
596. The inverter can be produced with how many NAND gates?
a) 2
b) 1
c) 3
d) 4
597. How many NOT gates are required to implement the Boolean expression: X = AB’C + A’BC?
a) 2
b) 3
c) 4
d) 5
598. What are carry generate combinations?

a) If all the input are same then a carry is generated
b) If all of the output are independent of the inputs
c) If all of the input are dependent on the output
d) If all of the output are dependent on the input
599. In serial addition, the addition is carried out __________

a) 3 bit per second
b) Byte by byte
c) Bit by bit
d) All bits at the same time
600. How many shift registers are used in a 4 bit serial adder?
a) 4
b) 3
c) 2
d) 5
IV.COMPUTER ORGANIZATION & ARCHITECTURE

601. The ______ format is usually used to store data.
a) BCD
b) Decimal
c) Hexadecimal
d) Octal
602. The 8-bit encoding format used to store data in a computer is ______
a) ASCII
b) EBCDIC
c) ANCI
d) USCII
603. A source program is usually in _______

a) Assembly language
b) Machine level language
c) High-level language
d) Natural language
604. Which memory device is generally made of semiconductors?

a) RAM
b) Hard-disk
c) Floppy disk
d) Cd disk
605. The small extremely fast, RAM’s are called as _______

a) Cache
b) Heaps
c) Accumulators
d) Stacks
606. The ALU makes use of _______ to store the intermediate results.
a) Accumulators
b) Registers
c) Heap
d) Stack
607. The control unit controls other units by generating ___________

a) Control signals
b) Timing signals
c) Transfer signals
d) Command Signals
608. ______ are numbers and encoded characters, generally used as operands.
a) Input
b) Data
c) Information
d) Stored Values
609. The Input devices can send information to the processor.

a) When the SIN status flag is set
b) When the data arrives regardless of the SIN flag
c) Neither of the cases
d) Either of the cases
610. ______ bus structure is usually used to connect I/O devices.

a) Single bus
b) Multiple bus
c) Star bus
d) Rambus
611. The I/O interface required to connect the I/O device to the bus consists of ______
a) Address decoder and registers
b) Control circuits
c) Address decoder, registers and Control circuits
d) Only Control circuits
612. To reduce the memory access time we generally make use of ______
a) Heaps
b) Higher capacity RAM’s
c) SDRAM’s
d) Cache’s
613. ______ is generally used to increase the apparent size of physical memory.
a) Secondary memory
b) Virtual memory
c) Hard-disk
d) Disks
614. MFC stands for ___________

a) Memory Format Caches
b) Memory Function Complete
c) Memory Find Command
d) Mass Format Command
615. The time delay between two successive initiations of memory operation _______
a) Memory access time
b) Memory search time
c) Memory cycle time
d) Instruction delay
616. The decoded instruction is stored in ______

a) IR
b) PC
c) Registers
d) MDR
617. The instruction -> Add LOCA, R0 does _______

a) Adds the value of LOCA to R0 and stores in the temp register
b) Adds the value of R0 to the address of LOCA
c) Adds the values of both LOCA and R0 and stores it in R0
d) Adds the value of LOCA with a value in accumulator and stores it in R0
618. Which registers can interact with the secondary storage?

a) MAR
b) PC
c) IR
d) R0
619. During the execution of a program which gets initialized first?
a) MDR
b) IR
c) PC
d) MAR
620. Which of the register/s of the processor is/are connected to Memory Bus?
a) PC
b) MAR
c) IR
d) Both PC and MAR
621. ISP stands for _________

a) Instruction Set Processor
b) Information Standard Processing
c) Interchange Standard Protocol
d) Interrupt Service Procedure
622. The internal components of the processor are connected by _______

a) Processor intra-connectivity circuitry
b) Processor bus
c) Memory bus
d) Rambus
623. ______ is used to choose between incrementing the PC or performing ALU operations.
a) Conditional codes
b) Multiplexer
c) Control unit
624. The registers, ALU and the interconnection between them are collectively called as _____
a) process route
b) information trail
c) information path
d) data path
625. _______ is used to store data in registers.

a) D flip flop
b) JK flip flop
c) RS flip flop
626. The main virtue for using single Bus structure is ____________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
627. ______ are used to overcome the difference in data transfer speeds of various devices.
a) Speed enhancing circuitory
b) Bridge circuits
c) Multiple Buses
d) Buffer registers
628. To extend the connectivity of the processor bus we use ________

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
629. IBM developed a bus standard for their line of computers ‘PC AT’ called _____
a) IB bus
b) M-bus
c) ISA
630. The bus used to connect the monitor to the CPU is ______
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
631. ANSI stands for __________

a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
632. _____ register Connected to the Processor bus is a single-way transfer capable.
a) PC
b) IR
c) Temp
d) Z
633. In multiple Bus organisation, the registers are collectively placed and referred as ______
a) Set registers
b) Register file
c) Register Block
d) Map registers
634. The main advantage of multiple bus organisation over a single bus is _____
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
635. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Hard disk and Processor
d) CD/DVD drives and Processor
636. During the execution of the instructions, a copy of the instructions is placed in the ______
a) Register
b) RAM
c) System heap
d) Cache
637. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can
execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the
execution of the same instruction which processor is faster?
a) A
b) B
c) Both take the same time
d) Insufficient information
638. A processor performing fetch or decoding of different instruction during the execution of another
instruction is called ______
a) Super-scaling
b) Pipe-lining
c) Parallel Computation
639. For a given FINITE number of instructions to be executed, which architecture of the processor
provides for a faster execution?
a) ISA
b) ANSA
c) Super-scalar
640. The clock rate of the processor can be improved by _________

a) Improving the IC technology of the logic circuits
b) Reducing the amount of processing done in one step
c) By using the overclocking method
641. An optimizing Compiler does _________

a) Better compilation of the given piece of code
b) Takes advantage of the type of processor and reduces its process time
c) Does better memory management
642. The ultimate goal of a compiler is to ________

a) Reduce the clock cycles for a programming task
b) Reduce the size of the object code
c) Be versatile
d) Be able to detect even the smallest of errors
643. SPEC stands for _______

a) Standard Performance Evaluation Code
b) System Processing Enhancing Code
c) System Performance Evaluation Corporation
d) Standard Processing Enhancement Corporation
644. As of 2000, the reference system to find the performance of a system is _____
a) Ultra SPARC 10
b) SUN SPARC
c) SUN II
645. When Performing a looping operation, the instruction gets stored in the ______
a) Registers
b) Cache
c) System Heap
d) System stack
646. The average number of steps taken to execute the set of instructions can be made to be less than one by
following _______
a) ISA
b) Pipe-lining
c) Super-scaling
d) Sequential
647. If a processor clock is rated as 1250 million cycles per second, then its clock period is ________
a) 1.9 * 10-10 sec
b) 1.6 * 10-9 sec
c) 1.25 * 10-10 sec
d) 8 * 10-10 sec
648. If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is
(Where S is a term of the Basic performance equation)?
a) 3
b) ~2
c) ~1
d) 6
649. CISC stands for _______
a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
650. As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
a) Intel Atom SParc 300Mhz
b) Ultra SPARC -IIi 300MHZ
c) Amd Neutrino series
d) ASUS A series 450 Mhz
651. The instruction, Add #45, R1 does _______
1. Adds the value of 45 to the address of R1 and stores 45 in that address
2. Adds 45 to the value of R1 and stores it in R1
3. Finds the memory location 45 and adds that content to that of R1
4. None of the mentioned
2. In the case of, Zero-address instruction method the operands are stored in _____
1. Registers
2. Accumulators
3. Push down stack
4. Cache
3. Add #45, when this instruction is executed the following happen/s _______
1. The processor raises an error and requests for one more operand
2. The value stored in memory location 45 is retrieved and one more operand is requested
3. The value 45 gets added to the value on the stack and is pushed onto the stack
4. The addressing mode which makes use of in-direction pointers is ______

1. Indirect addressing mode
2. Index addressing mode
3. Relative addressing mode
4. Offset addressing mode
5. In the following indexed addressing mode instruction, MOV 5(R1), LOC the effective address is
______
1. EA = 5+R1
2. EA = R1
3. EA = [R1]
4. EA = 5+[R1]
6. The addressing mode/s, which uses the PC instead of a general-purpose register is ______
1. Indexed with offset
2. Relative
3. Direct
4. Both Indexed with offset and direct
7. When we use auto increment or auto decrements, which of the following is/are true?
1. In both, the address is used to retrieve the operand and then the address gets altered
2. In auto increment, the operand is retrieved first and then the address altered
3. Both of them can be used on general purpose registers as well as memory locations
1. 1, 2, 3
2. 2
3. 1, 3
4. 2, 3
8. The addressing mode, where you directly specify the operand value is _______
1. Immediate
2. Direct
3. Definite
4. Relative
9. The effective address of the following instruction is MUL 5(R1,R2).

1. 5+R1+R2
2. 5+(R1*R2)
3. 5+[R1]+[R2]
4. 5*([R1]+[R2])
10. _____ addressing mode is most suitable to change the normal sequence ofexecution of instructions.
1. Relative
2. Indirect
3. Index with Offset
4. Immediate
11. Which method/s of representation of numbers occupies a large amount of memory than others?
1. Sign-magnitude
2. 1’s complement
3. 2’s complement
4. 1’s & 2’s compliment
12. Which representation is most efficient to perform arithmetic operations on the numbers?
1. Sign-magnitude
2. 1’s complement
3. 2’S complement
13. Which method of representation has two representations for ‘0’?

1. Sign-magnitude
2. 1’s complement
3. 2’s complement
14. When we perform subtraction on -7 and 1 the answer in 2’s complement form is _________
1. 1010
2. 1110
3. 0110
4. 1000
15. When we perform subtraction on -7 and -5 the answer in 2’s complement form is ________
1. 11110
2. 1110
3. 1010
4. 0010
16. When we subtract -3 from 2 , the answer in 2’s complement form is _________
1. 0001
2. 1101
3. 0101
4. 1001
17. The processor keeps track of the results of its operations using flags called ________
1. Conditional code flags
2. Test output flags
3. Type flags
18. The register used to store the flags is called as _________

1. Flag register
2. Status register
3. Test register
4. Log register
19. The Flag ‘V’ is set to 1 indicates that _____________

1. The operation is valid
2. The operation is validated
3. The operation has resulted in an overflow
20. In some pipelined systems, a different instruction is used to add to numbers which can affect the
flags upon execution. That instruction is _______
1. AddSetCC
2. AddCC
3. Add++
4. SumSetCC
21. The most efficient method followed by computers to multiply two unsigned numbers is _______
1. Booth algorithm
2. Bit pair recording of multipliers
3. Restoring algorithm
4. Non restoring algorithm
22. For the addition of large integers, most of the systems make use of ______
1. Fast adders
2. Full adders
3. Carry look-ahead adders
23. In a normal n-bit adder, to find out if an overflow as occurred we make use of ________
1. And gate
2. Nand gate
3. Nor gate
4. Xor gate
24. In the implementation of a Multiplier circuit in the system we make use of _______
1. Counter
2. Flip flop
3. Shift register
4. Push down stack
25. When 1101 is used to divide 100010010 the remainder is ______

1. 101
2. 11
3. 0
4. 1
26. The smallest entity of memory is called _______

1. Cell
2. Block
3. Instance
4. Unit
27. The collection of the above mentioned entities where data is stored is called ______
1. Block
2. Set
3. Word
4. Byte
28. An 24 bit address generates an address space of ______ locations.

1. 1024
2. 4096
3. 248
4. 16,777,216
29. If a system is 64 bit machine, then the length of each word will be _______
1. 4 bytes
2. 8 bytes
3. 16 bytes
4. 12 bytes
30. The type of memory assignment used in Intel processors is _____
1. Little Endian
2. Big Endian
3. Medium Endian
31. When using the Big Endian assignment to store a number, the sign bit of the number is stored in
_____
1. The higher order byte of the word
2. The lower order byte of the word
3. Can’t say
32. To get the physical address from the logical address generated by CPU we use ____________
1. MAR
2. MMU
3. Overlays
4. TLB
33. _____ method is used to map logical addresses of variable length onto physical memory.
1. Paging
2. Overlays
3. Segmentation
4. Paging with segmentation
34. During the transfer of data between the processor and memory we use ______
1. Cache
2. TLB
3. Buffers
4. Registers
35. Physical memory is divided into sets of finite size called as ______
1. Frames
2. Pages
3. Blocks
4. Vectors
36. Add #%01011101,R1 , when this instruction is executed then ______
1. The binary addition between the operands takes place

2. The Numerical value represented by the binary value is added to the value of R1
3. The addition doesn’t take place, whereas this is similar to a MOV instruction
37. If we want to perform memory or arithmetic operations on data in Hexa-decimal mode then we use
_________ symbol before the operand.
1. ~
2. !
3. $
4. *
38. When generating physical addresses from a logical address the offset is stored in __________
1. Translation look-aside buffer
2. Relocation register
3. Page table
4. Shift register
39. The technique used to store programs larger than the memory is ____________
1. Overlays
2. Extension registers
3. Buffers
4. Both Extension registers and Buffers
40. The unit which acts as an intermediate agent between memory and backing store to reduce process
time is ___________
1. TLB’s
2. Registers
3. Page tables
4. Cache
41. Does the Load instruction do the following operation/s?

1. Loads the contents of a disc onto a memory location
2. Loads the contents of a location onto the accumulators
3. Load the contents of the PCB onto the register
42. Complete the following analogy:- Registers are to RAM’s as Cache’s are to ___________
1. System stacks
2. Overlays
3. Page Table
4. TLB
43. The BOOT sector files of the system are stored in ___________
1. Harddisk
2. ROM
3. RAM
4. Fast solid state chips in the motherboard
44. The transfer of large chunks of data with the involvement of the processor is done by _______
1. DMA controller
2. Arbitrator
3. User system programs
45. Which of the following techniques used to effectively utilize main memory?
1. Address binding
2. Dynamic linking
3. Dynamic loading
4. Both Dynamic linking and loading
46. RTN stands for ___________

1. Register Transfer Notation
2. Register Transmission Notation
3. Regular Transmission Notation
4. Regular Transfer Notation
47. The instruction, Add Loc,R1 in RTN is _______
1. AddSetCC Loc+R1
2. R1=Loc+R1
3. Not possible to write in RTN
4. R1<-[Loc]+[R1]
48. Can you perform an addition on three operands simultaneously in ALN using Add instruction?
1. Yes
2. Not possible using Add, we’ve to use AddSetCC
3. Not permitted
49. The instruction, Add R1,R2,R3 in RTN is _______

1. R3=R1+R2+R3
2. R3<-[R1]+[R2]+[R3]
3. R3=[R1]+[R2]
4. R3<-[R1]+[R2]
50. In a system, which has 32 registers the register id is __________ long.

1. 16 bit
2. 8 bits
3. 5 bits
4. 6 bits
51. The two phases of executing an instruction are __________

1. Instruction decoding and storage
2. Instruction fetch and instruction execution
3. Instruction execution and storage
4. Instruction fetch and Instruction processing
52. The Instruction fetch phase ends with _________

1. Placing the data from the address in MAR into MDR
2. Placing the address of the data into MAR
3. Completing the execution of the data and placing its storage address into MAR
4. Decoding the data in MDR and placing it in IR
53. While using the iterative construct (Branching) in execution _____________ instruction is used to
check the condition.
1. TestAndSet
2. Branch
3. TestCondn
54. When using Branching, the usual sequencing of the PC is altered. A new instruction is loaded which
is called as ______
1. Branch target
2. Loop target
3. Forward target
4. Jump instruction
55. The condition flag Z is set to 1 to indicate _______

1. The operation has resulted in an error
2. The operation requires an interrupt call
3. The result is zero
4. There is no empty register available
56. __________ converts the programs written in assembly language into machine instructions
1. Machine compiler
2. Interpreter
3. Assembler
4. Converter
57. The instructions like MOV or ADD are called as ______

1. OP-Code
2. Operators
3. Commands
58. The alternate way of writing the instruction, ADD #5,R1 is ______
1. ADD [5],[R1];
2. ADDI 5,R1;
3. ADDIME 5,[R1];
4. There is no other way
59. Instructions which won’t appear in the object program are called as _____
1. Redundant instructions
2. Exceptions
3. Comments
4. Assembler Directives
60. The assembler directive EQU, when used in the instruction: Sum EQU 200 does ________
1. Finds the first occurrence of Sum and assigns value 200 to it
2. Replaces every occurrence of Sum with 200
3. Re-assigns the address of Sum by adding 200 to its original address
4. Assigns 200 bytes of memory starting the location of Sum
61. The purpose of the ORIGIN directive is __________

1. To indicate the starting position in memory, where the program block is to be stored
2. To indicate the starting of the computation code
3. To indicate the purpose of the code
4. To list the locations of all the registers used
62. The directive used to perform initialization before the execution of the code is ______
1. Reserve
2. Store
3. Dataword
4. EQU
63. _____ directive is used to specify and assign the memory required for the block of code.
1. Allocate
2. Assign
3. Set
4. Reserve
64. _____ directive specifies the end of execution of a program.

1. End
2. Return
3. Stop
4. Terminate
65. The last statement of the source program should be _______

1. Stop
2. Return
3. OP
4. End
66. When dealing with the branching code the assembler ___________
1. Replaces the target with its address
2. Does not replace until the test condition is satisfied
3. Finds the Branch offset and replaces the Branch target with it
4. Replaces the target with the value specified by the DATAWORD directive
67. The assembler stores all the names and their corresponding values in ______
1. Special purpose Register
2. Symbol Table
3. Value map Set
68. The assembler stores the object code in ______

1. Main memory
2. Cache
3. RAM
4. Magnetic disk
69. The utility program used to bring the object code into memory for execution is ______
1. Loader
2. Fetcher
3. Extractor
4. Linker
70. To overcome the problems of the assembler in dealing with branching code we use _____
1. Interpreter
2. Debugger
3. Op-Assembler
4. Two-pass assembler
71. The return address of the Sub-routine is pointed to by _______

1. IR
2. PC
3. MAR
4. Special memory registers
72. The location to return to, from the subroutine is stored in _______
1. TLB
2. PC
3. MAR
4. Link registers
73. What is subroutine nesting?

1. Having multiple subroutines in a program
2. Using a linking nest statement to put many subroutines under the same name
3. Having one routine call the other
74. The order in which the return addresses are generated and used is _________
1. LIFO
2. FIFO
3. Random
4. Highest priority
75. In case of nested subroutines the return addresses are stored in __________
1. System heap
2. Special memory buffers
3. Processor stack
4. Registers
76. The appropriate return addresses are obtained with the help of ____ in case of nested routines.
1. MAR
2. MDR
3. Buffers
4. Stack-pointers
77. When parameters are being passed on to the subroutines they are stored in ________
1. Registers
2. Memory locations
3. Processor stacks
4. All of the mentioned
78. The most efficient way of handling parameter passing is by using ______
1. General purpose registers
2. Stacks
3. Memory locations
79. The most Flexible way of logging the return addresses of the subroutines is by using _______
1. Registers
2. Stacks
3. Memory locations
80. The wrong statement/s regarding interrupts and subroutines among the following is/are ______
i)The sub-routine and interrupts have a return statement
ii) Both of them alter the content of the PC
iii) Both are software oriented
iv) Both can be initiated by the user
1. i, ii and iv
2. ii and iii
3. iv
4. iii and iv
81. The private work space dedicated to a subroutine is called as ________

1. System heap
2. Reserve
3. Stack frame
4. Allocation
82. If the subroutine exceeds the private space allocated to it then the values are pushed onto _________
1. Stack
2. System heap
3. Reserve Space
4. Stack frame
83. ______ pointer is used to point to parameters passed or local parameters of the subroutine.
1. Stack pointer
2. Frame pointer
3. Parameter register
4. Log register
84. The reserved memory or private space of the subroutine gets deallocated when _______
1. The stop instruction is executed by the routine
2. The pointer reaches the end of the space
3. When the routine’s return statement is executed
85. The private space gets allocated to each subroutine when _________
1. The first statement of the routine is executed
2. When the context switch takes place
3. When the routine gets called
4. When the Allocate instruction is executed
86. _____ the most suitable data structure used to store the return addresses in the case of nested
subroutines.
1. Heap
2. Stack
3. Queue
4. List
87. In the case of nested subroutines, the stack top is always _________
1. The saved contents of the called sub routine
2. The saved contents of the calling sub routine
3. The return addresses of the called sub routine
88. The stack frame for each subroutine is present in ______
1. Main memory
2. System Heap
3. Processor Stack
89. The data structure suitable for scheduling processes is _______

1. List
2. Heap
3. Queue
4. Stack
90. The sub-routine service procedure is similar to that of the interrupt service routine in ________
1. Method of context switch
2. Returning
3. Process execution
4. Method of context switch & Process execution
91. In memory-mapped I/O ____________

1. The I/O devices and the memory share the same address space
2. The I/O devices have a separate address space
3. The memory and I/O devices have an associated address space
4. A part of the memory is specifically set aside for the I/O operation
92. The usual BUS structure used to connect the I/O devices is ___________
1. Star BUS structure
2. Multiple BUS structure
3. Single BUS structure
4. Node to Node BUS structure
93. In intel’s IA-32 architecture there is a separate 16 bit address space for the I/O devices.
1. False
2. True
94. The advantage of I/O mapped devices to memory mapped is ___________

1. The former offers faster transfer of data
2. The devices connected using I/O mapping have a bigger buffer space
3. The devices have to deal with fewer address lines
4. No advantage as such
95. The system is notified of a read or write operation by ___________

1. Appending an extra bit of the address
2. Enabling the read or write bits of the devices
3. Raising an appropriate interrupt signal
4. Sending a special signal along the BUS
96. To overcome the lag in the operating speeds of the I/O device and the processor we use
___________
1. BUffer spaces
2. Status flags
3. Interrupt signals
4. Exceptions
97. The method of accessing the I/O devices by repeatedly checking the status flags is ___________
1. Program-controlled I/O
2. Memory-mapped I/O
3. I/O mapped
98. The method of synchronising the processor with the I/O device in which the device sends a signal
when it is ready is?
1. Exceptions
2. Signal handling
3. Interrupts
4. DMA
99. The method which offers higher speeds of I/O transfers is ___________
1. Interrupts
2. Memory mapping
3. Program-controlled I/O
4. DMA
100. The process wherein the processor constantly checks the status flags is called as ___________
1. Polling
2. Inspection
3. Reviewing
4. Echoing
101. The interrupt-request line is a part of the ___________

1. Data line
2. Control line
3. Address line
102. The return address from the interrupt-service routine is stored on the ___________
1. System heap
2. Processor register
3. Processor stack
4. Memory
103. The signal sent to the device from the processor to the device after receiving an interrupt is
___________
1. Interrupt-acknowledge
2. Return signal
3. Service signal
4. Permission signal
104. When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses
1. i, iv
2. ii, iii and iv
3. iii, iv
4. i, ii
105. The time between the receiver of an interrupt and its service is ______
1. Interrupt delay
2. Interrupt latency
3. Cycle time
4. Switching time
106. Interrupts form an important part of _____ systems.

1. Batch processing
2. Multitasking
3. Real-time processing
4. Multi-user
107. A single Interrupt line can be used to service n different devices.
1. True
2. False
108. ______ type circuits are generally used for interrupt service lines.
i)open-collector
ii) open-drain
iii) XOR
iv) XNOR
1. i, ii
2. ii
3. ii, iii
4. ii, iv
109. The resistor which is attached to the service line is called _____
1. Push-down resistor
2. Pull-up resistor
3. Break down resistor
4. Line resistor
110. An interrupt that can be temporarily ignored is ___________

1. Vectored interrupt
2. Non-maskable interrupt
3. Maskable interrupt
4. High priority interrupt
111. The 8085 microprocessor responds to the presence of an interrupt ___________

1. As soon as the trap pin becomes ‘LOW’
2. By checking the trap pin for ‘high’ status at the end of each instruction fetch
3. By checking the trap pin for ‘high’ status at the end of execution of each instruction
4. By checking the trap pin for ‘high’ status at regular intervals
112. CPU as two modes privileged and non-privileged. In order to change the mode from privileged to
non-privileged.
1. A hardware interrupt is needed
2. A software interrupt is needed
3. Either hardware or software interrupt is needed
4. A non-privileged instruction (which does not generate an interrupt)is needed
113. Which interrupt is unmaskable?

1. RST 5.5
2. RST 7.5
3. TRAP
4. Both RST 5.5 and 7.5
114. From amongst the following given scenarios determine the right one to justify interrupt mode of data
transfer.
i)Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs
1. i and ii
2. ii
3. i, ii and iv
4. iv
115. When dealing with multiple devices interrupts, which mechanism is easy to implement?
1. Polling method
2. Vectored interrupts
3. Interrupt nesting
116. The interrupt servicing mechanism in which the requesting device identifies itself to the processor to
be serviced is ___________
1. Polling
2. Vectored interrupts
3. Interrupt nesting
4. Simultaneous requesting
117. In vectored interrupts, how does the device identify itself to the processor?
1. By sending its device id
2. By sending the machine code for the interrupt service routine
3. By sending the starting address of the service routine
118. The code sent by the device in vectored interrupt is _____ long.
1. upto 16 bits
2. upto 32 bits
3. upto 24 bits
4. 4-8 bits
119. The starting address sent by the device in vectored interrupt is called as __________
1. Location id
2. Interrupt vector
3. Service location
4. Service id
120. The processor indicates to the devices that it is ready to receive interrupts ________
1. By enabling the interrupt request line
2. By enabling the IRQ bits
3. By activating the interrupt acknowledge line
121. We describe a protocol of input device communication below:

I)Each device has a distinct address.
ii) The BUS controller scans each device in a sequence of increasing address value to determine if the entity
wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following.
1. Programmed mode of data transfer
2. DMA
3. Interrupt mode
4. Polling
122. Which one of the following is true with regard to a CPU having a single interrupt request line and
single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices are possible.
1. iii
2. i, iv
3. ii, iii
4. iii, iv
123. Which table handle stores the addresses of the interrupt handling sub-routines?
1. Interrupt-vector table
2. Vector table
3. Symbol link table
124. _________ method is used to establish priority by serially connecting all devices that request an
interrupt.
1. Vectored-interrupting
2. Daisy chain
3. Priority
4. Polling
125. In daisy chaining device 0 will pass the signal only if it has _______
1. Interrupt request
2. No interrupt request
3. Both No interrupt and Interrupt request
126. ______ interrupt method uses register whose bits are set separately by interrupt signal for each
device.
1. Parallel priority interrupt
2. Serial priority interrupt
3. Daisy chaining
127. ______________ register is used for the purpose of controlling the status of each interrupt request in
parallel priority interrupt.
1. Mass
2. Mark
3. Make
4. Mask
128. The added output of the bits of the interrupt register and the mask register is set as an input of
______________
1. Priority decoder
2. Priority encoder
3. Process id encoder
4. Multiplexer
129. Interrupts initiated by an instruction is called as _______

1. Internal
2. External
3. Hardware
4. Software
130. If during the execution of an instruction an exception is raised then __________

1. The instruction is executed and the exception is handled
2. The instruction is halted and the exception is handled
3. The processor completes the execution and saves the data and then handle the exception
131. _____ is/are types of exceptions.

1. Trap
2. Interrupt
3. System calls
132. The program used to find out errors is called __________
1. Debugger
2. Compiler
3. Assembler
4. Scanner
133. The two facilities provided by the debugger is __________

1. Trace points
2. Break points
3. Compile
4. Both Trace and Break points
134. In trace mode of operation is ________

1. The program is interrupted after each detection
2. The program will not be stopped and the errors are sorted out after the complete program is
scanned
3. There is no effect on the program, i.e the program is executed without rectification of errors
4. The program is halted only at specific points
135. What is the operation in Breakpoint mode?

1. The program is interrupted after each detection
2. The program will not be stopped and the errors are sorted out after the complete program is
scanned
3. There is no effect on the program, i.e the program is executed without rectification of errors
4. The program is halted only at specific points
136. What are the different modes of operation of a computer?

1. User and System mode
2. User and Supervisor mode
3. Supervisor and Trace mode
4. Supervisor, User and Trace mode
137. The instructions which can be run only supervisor mode are?
1. Non-privileged instructions
2. System instructions
3. Privileged instructions
4. Exception instructions
138. A privilege exception is raised __________

1. When a process tries to change the mode of the system
2. When a process tries to change the priority level of the other processes
3. When a process tries to access the memory allocated to other users
139. How is a privilege exception dealt with?

1. The program is halted and the system switches into supervisor mode and restarts the
program execution
2. The Program is stopped and removed from the queue
3. The system switches the mode and starts the execution of a new process
4. The system switches mode and runs the debugger
140. The DMA differs from the interrupt mode by __________

1. The involvement of the processor for the operation
2. The method of accessing the I/O devices
3. The amount of data transfer possible
141. The DMA transfers are performed by a control circuit called as __________
1. Device interface
2. DMA controller
3. Data controller
4. Overlooker
142. In DMA transfers, the required signals and addresses are given by the __________
1. Processor
2. Device drivers
3. DMA controllers
4. The program itself
143. After the completion of the DMA transfer, the processor is notified by __________
1. Acknowledge signal
2. Interrupt signal
3. WMFC signal
144. The DMA controller has _______ registers.

1. 4
2. 2
3. 3
4. 1
145. When the R/W bit of the status register of the DMA controller is set to 1.
1. Read operation is performed
2. Write operation is performed
3. Read & Write operation is performed
146. The controller is connected to the ____

1. Processor BUS
2. System BUS
3. External BUS
147. Can a single DMA controller perform operations on two different disks simultaneously?
1. True
2. False
148. The technique whereby the DMA controller steals the access cycles of the processor to operate is
called __________
1. Fast conning
2. Memory Con
3. Cycle stealing
4. Memory stealing
149. The technique where the controller is given complete access to main memory is __________
1. Cycle stealing
2. Memory stealing
3. Memory Con
4. Burst mode
150. The controller uses _____ to help with the transfers when handling network interfaces.
1. Input Buffer storage
2. Signal enhancers
3. Bridge circuits
V. Computer Organization
801. The duration between the read and the mfc signal is ______
a) Access time
b) Latency
c) Delay
d) Cycle time
802. The minimum time delay between two successive memory read operations is ______
a) Cycle time
b) Latency
c) Delay
803. MFC is used to _________

a) Issue a read signal
b) Signal to the device that the memory read operation is complete
c) Signal the processor the memory operation is complete
d) Assign a device to perform the read operation
804. __________ is the bottleneck, when it comes computer performance.

a) Memory access time
b) Memory cycle time
c) Delay
d) Latency
805. The logical addresses generated by the cpu are mapped onto physical memory by ____________
a) Relocation register
b) TLB
c) MMU
806. VLSI stands for ___________

a) Very Large Scale Integration
b) Very Large Stand-alone Integration
c) Volatile Layer System Interface
807. The cells in a row are connected to a common line called ______
a) Work line
b) Word line
c) Length line
d) Principle diagonal
808. The cells in each column are connected to ______

a) Word line
b) Data line
c) Read line
d) Sense/ Write line
809. The word line is driven by the _____

a) Chip select
b) Address decoder
c) Data line
d) Control line
810. A 16 X 8 Organisation of memory cells, can store upto _____

a) 256 bits
b) 1024 bits
c) 512 bits
d) 128 bits
811. A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be
organized into _____
a) 128 X 8
b) 256 X 4
c) 512 X 2
d) 1024 X 1
812. Circuits that can hold their state as long as power is applied is _______
a) Dynamic memory
b) Static memory
c) Register
d) Cache
813. The number of external connections required in 16 X 8 memory organisation is _____

a) 14
b) 19
c) 15
d) 12
814. The advantage of CMOS SRAM over the transistor one’s is _________
a) Low cost
b) High efficiency
c) High durability
d) Low power consumption
815. In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data
lines are there.
a) 10
b) 8
c) 9
d) 12
816. The Reason for the disregarding of the SRAM’s is ________

a) Low Efficiency
b) High power consumption
c) High Cost
817. The disadvantage of DRAM over SRAM is/are _______

a) Lower data storage capacities
b) Higher heat dissipation
c) The cells are not static
818. The reason for the cells to lose their state over time is ________
a) The lower voltage levels
b) Usage of capacitors to store the charge
c) Use of Shift registers
819. The capacitors lose the charge over time due to ________
a) The leakage resistance of the capacitor
b) The small current in the transistor after being turned on
c) The defect of the capacitor
820. _________ circuit is used to restore the capacitor value.

a) Sense amplify
b) Signal amplifier
c) Delta modulator
821. To reduce the number of external connections required, we make use of ______
a) De-multiplexer
b) Multiplexer
c) Encoder
d) Decoder
822. The processor must take into account the delay in accessing the memory location, such memories are
called ______
a) Delay integrated
b) Asynchronous memories
c) Synchronous memories
d) Isochronous memories
823. To get the row address of the required data ______ is enabled.
a) CAS
b) RAS
c) CS
d) Sense/write
824. In order to read multiple bytes of a row at the same time, we make use of ______
a) Latch
b) Shift register
c) Cache
d) Memory extension
825. The block transfer capability of the DRAM is called ________

a) Burst mode
b) Block mode
c) Fast page mode
d) Fast frame mode
826. The difference between DRAM’s and SDRAM’s is/are ________

a) The DRAM’s will not use the master slave relationship in data transfer
b) The SDRAM’s make use of clock
c) The SDRAM’s are more power efficient
827. The difference in the address and data connection between DRAM’s and SDRAM’s is _______
a) The usage of more number of pins in SDRAM’s
b) The requirement of more address lines in SDRAM’s
c) The usage of a buffer in SDRAM’s
828. A _______ is used to restore the contents of the cells.

a) Sense amplifier
b) Refresh counter
c) Restorer
829. The mode register is used to _______

a) Select the row or column data transfer mode
b) Select the mode of operation
c) Select mode of storing the data
830. In a SDRAM each row is refreshed every 64ms.

a) True
b) False
831. The time taken to transfer a word of data to or from the memory is called as ______
a) Access time
b) Cycle time
c) Memory latency
832. In SDRAM’s buffers are used to store data that is read or written.
a) True
b) False
833. The SDRAM performs operation on the _______

a) Rising edge of the clock
b) Falling edge of the clock
c) Middle state of the clock
d) Transition state of the clock
834. DDR SDRAM’s perform faster data transfer by _______

a) Integrating the hardware
b) Transferring on both edges
c) Improving the clock speeds
d) Increasing the bandwidth
835. To improve the data retrieval rate ____________

a) The memory is divided into two banks
b) The hardware is changed
c) The clock frequency is increased
836. The chip can be disabled or cut off from an external connection using ______
a) Chip select
b) LOCK
c) ACPT
d) RESET
837. To organise large memory chips we make use of ______

a) Integrated chips
b) Upgraded hardware
c) Memory modules
838. The less space consideration as lead to the development of ________ (for large memories).
a) SIMM’s
b) DIMS’s
c) SRAM’s
d) Both SIMM’s and DIMS’s
839. The SRAM’s are basically used as ______

a) Registers
b) Caches
c) TLB
d) Buffer
840. The higher order bits of the address are used to _____
a) Specify the row address
b) Specify the column address
c) Input the CS
841. The address lines multiplexing is done using ______

a) MMU
b) Memory controller unit
c) Page table
d) Overlay generator
842. The controller multiplexes the addresses after getting the _____ signal.
a) INTR
b) ACK
c) RESET
d) Request
843. The RAS and CAS signals are provided by the ______
a) Mode register
b) CS
c) Memory controller
844. Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read operation. Then
the refresh overhead of the chip is ______
a) 0.0021
b) 0.0038
c) 0.0064
d) 0.0128
845. When DRAM’s are used to build a complex large memory, then the controller only provides the refresh
counter.
a) True
b) False
846. RAMBUS is better than the other memory chips in terms of ________
a) Efficiency
b) Speed of operation
c) Wider bandwidth
847. The key feature of the RAMBUS tech is ________

a) Greater memory utilisation
b) Efficiency
c) Speed of transfer
848. The increase in operation speed is done by ________________

a) Reducing the reference voltage
b) Increasing the clk frequency
c) Using enhanced hardware
849. The data is transferred over the RAMBUS as _______

a) Packets
b) Blocks
c) Swing voltages
d) Bits
850. The type of signaling used in RAMBUS is ______

a) CLK signaling
b) Differential signaling
c) Integral signaling
851. The special communication used in RAMBUS are _________

a) RAMBUS channel
b) D-link
c) Dial-up
852. The original design of the RAMBUS required for ________ data lines.
a) 4
b) 6
c) 8
d) 9
853. The RAMBUS requires specially designed memory chips similar to _____
a) SRAM
b) SDRAM
c) DRAM
d) DDRRAM
854. A RAMBUS which has 18 data lines is called as _______

a) Extended RAMBUS
b) Direct RAMBUS
c) Multiple RAMBUS
d) Indirect RAMBUS
855. The RDRAM chips assembled into larger memory modules called ______
a) RRIM
b) DIMM
c) SIMM
856. If the transistor gate is closed, then the ROM stores a value of 1.
a) True
b) False
857. PROM stands for __________

a) Programmable Read Only Memory
b) Pre-fed Read Only Memory
c) Pre-required Read Only Memory
d) Programmed Read Only Memory
858. The PROM is more effective than ROM chips in regard to _______
a) Cost
b) Memory management
c) Speed of operation
d) Both Cost and Speed of operation
859. The difference between the EPROM and ROM circuitry is _____
a) The usage of MOSFET’s over transistors
b) The usage of JFET’s over transistors
c) The usage of an extra transistor
860. The ROM chips are mainly used to store _______

a) System files
b) Root directories
c) Boot files
d) Driver files
861. The contents of the EPROM are erased by ________

a) Overcharging the chip
b) Exposing the chip to UV rays
c) Exposing the chip to IR rays
d) Discharging the Chip
862. The disadvantage of the EPROM chip is _______

a) The high cost factor
b) The low efficiency
c) The low speed of operation
d) The need to remove the chip physically to reprogram it
863. EEPROM stands for Electrically Erasable Programmable Read Only Memory.
a) True
b) False
864. The disadvantage of the EEPROM is/are ________

a) The requirement of different voltages to read, write and store information
b) The Latency read operation
c) The inefficient memory mapping schemes used
865. The memory devices which are similar to EEPROM but differ in the cost effectiveness is ______
a) Memory sticks
b) Blue-ray devices
c) Flash memory
d) CMOS
866. The only difference between the EEPROM and flash memory is that the latter doesn’t allow bulk data to
be written.
a) True
b) False
867. The flash memories find application in ______

a) Super computers
b) Mainframe systems
c) Distributed systems
d) Portable devices
868. The memory module obtained by placing a number of flash chips for higher memory storage called as
_______
a) FIMM
b) SIMM
c) Flash card
d) RIMM
869. The flash memory modules designed to replace the functioning of a hard disk is ______
a) RIMM
b) Flash drives
c) FIMM
d) DIMM
870. The reason for the fast operating speeds of the flash drives is ____________
a) The absence of any movable parts
b) The integrated electronic hardware
c) The improved bandwidth connection
871. The standard SRAM chips are costly as _________
a) They use highly advanced micro-electronic devices
b) They house 6 transistor per chip
c) They require specially designed PCB’s
872. The drawback of building a large memory with DRAM is ______________

a) The large cost factor
b) The inefficient memory organisation
c) The Slow speed of operation
873. To overcome the slow operating speeds of the secondary memory we make use of faster flash drives.
a) True
b) False
874. The fastest data access is provided using _______

a) Caches
b) DRAM’s
c) SRAM’s
d) Registers
875. The memory which is used to store the copy of data or instructions stored in larger memories, inside the
CPU is called _______
a) Level 1 cache
b) Level 2 cache
c) Registers
d) TLB
876. The larger memory placed between the primary cache and the memory is called ______
a) Level 1 cache
b) Level 2 cache
c) EEPROM
d) TLB
877. The next level of memory hierarchy after the L2 cache is _______
a) Secondary storage
b) TLB
c) Main memory
d) Register
878. The last on the hierarchy scale of memory devices is ______

a) Main memory
b) Secondary memory
c) TLB
d) Flash drives
879. In the memory hierarchy, as the speed of operation increases the memory size also increases.
a) True
b) False
880. If we use the flash drives instead of the harddisks, then the secondary storage can go above primary
memory in the hierarchy.
a) True
b) False
881. The reason for the implementation of the cache memory is ________
a) To increase the internal memory of the system
b) The difference in speeds of operation of the processor and memory
c) To reduce the memory access and cycle time
882. The effectiveness of the cache memory is based on the property of ________
a) Locality of reference
b) Memory localisation
c) Memory size
883. The temporal aspect of the locality of reference means ________

a) That the recently executed instruction won’t be executed soon
b) That the recently executed instruction is temporarily not referenced
c) That the recently executed instruction will be executed soon again
884. The spatial aspect of the locality of reference means ________

a) That the recently executed instruction is executed again next
b) That the recently executed won’t be executed again
c) That the instruction executed will be executed at a later time
d) That the instruction in close proximity of the instruction executed will be executed in future
885. The correspondence between the main memory blocks and those in the cache is given by _________
a) Hash function
b) Mapping function
c) Locale function
d) Assign function
886. The algorithm to remove and place new contents into the cache is called _______
a) Replacement algorithm
b) Renewal algorithm
c) Updation
887. The write-through procedure is used ________

a) To write onto the memory directly
b) To write and read from memory simultaneously
c) To write directly on the memory and the cache simultaneously
888. The bit used to signify that the cache location is updated is ________
a) Dirty bit
b) Update bit
c) Reference bit
d) Flag bit
889. The copy-back protocol is used ________

a) To copy the contents of the memory onto the cache
b) To update the contents of the memory from the cache
c) To remove the contents of the cache and push it on to the memory
890. The approach where the memory contents are transferred directly to the processor from the memory is
called ______
a) Read-later
b) Read-through
c) Early-start
891. The memory blocks are mapped on to the cache with the help of ______
a) Hash functions
b) Vectors
c) Mapping functions
892. During a write operation if the required block is not present in the cache then ______ occurs.
a) Write latency
b) Write hit
c) Write delay
d) Write miss
893. In ________ protocol the information is directly written into the main memory.
a) Write through
b) Write back
c) Write first
894. The only draw back of using the early start protocol is _______
a) Time delay
b) Complexity of circuit
c) Latency
d) High miss rate
895. The method of mapping the consecutive memory blocks to consecutive cache blocks is called ______
a) Set associative
b) Associative
c) Direct
d) Indirect
896. While using the direct mapping technique, in a 16 bit system the higher order 5 bits are used for ________
a) Tag
b) Block
c) Word
d) Id
897. In direct mapping the presence of the block in memory is checked with the help of block field.
a) True
b) False
898. In associative mapping, in a 16 bit system the tag field has ______ bits.
a) 12
b) 8
c) 9
d) 10
899. The associative mapping is costlier than direct mapping.

a) True
b) False
900. The technique of searching for a block by going through all the tags is ______
a) Linear search
b) Binary search
c) Associative search
901. The set-associative map technique is a combination of the direct and associative technique.
a) True
b) False
902. In set-associative technique, the blocks are grouped into ______ sets.
a) 4
b) 8
c) 12
d) 6
903. A control bit called _________ has to be provided to each block in set-associative.
a) Idol bit
b) Valid bit
c) Reference bit
904. The bit used to indicate whether the block was recently used or not is _______
a) Idol bit
b) Control bit
c) Reference bit
d) Dirty bit
905. Data which is not up-to date is called as _______

a) Spoilt data
b) Stale data
c) Dirty data
906. The main memory is structured into modules each with its own address register called ______
a) ABR
b) TLB
c) PC
d) IR
907. When consecutive memory locations are accessed only one module is accessed at a time.
a) True
b) False
908. In memory interleaving, the lower order bits of the address is used to _____________
a) Get the data
b) Get the address of the module
c) Get the address of the data within the module
909. The number successful accesses to memory stated as a fraction is called as _____
a) Hit rate
b) Miss rate
c) Success rate
d) Access rate
910. The number failed attempts to access memory, stated in the form of a fraction is called as _________
a) Hit rate
b) Miss rate
c) Failure rate
d) Delay rate
911. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one, when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
912. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one
and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
913. If hit rates are well below 0.9, then they’re called as speedy computers.
a) True
b) False
914. The extra time needed to bring the data into memory in case of a miss is called as __________
a) Delay
b) Propagation time
c) Miss penalty
915. The miss penalty can be reduced by improving the mechanisms for data transfer between the different
levels of hierarchy.
a) True
b) False
916. The CPU is also called as ________

a) Processor hub
b) ISP
c) Controller
917. A common strategy for performance is making various functional units operate parallelly.
a) True
b) False
918. The PC gets incremented _____________

a) After the instruction decoding
b) After the IR instruction gets executed
c) After the fetch cycle
919. Which register in the processor is single directional?

a) MAR
b) MDR
c) PC
d) Temp
920. The transparent register/s is/are __________

a) Y
b) Z
c) Temp
921. Which register is connected to the MUX?

a) Y
b) Z
c) R0
d) Temp
922. The registers, ALU and the interconnecting path together are called as ______
a) Control path
b) Flow path
c) Data path
923. The input and output of the registers are governed by __________
a) Transistors
b) Diodes
c) Gates
d) Switches
924. When two or more clock cycles are used to complete data transfer it is called as ________
a) Single phase clocking
b) Multi-phase clocking
c) Edge triggered clocking
925. ________ signal is used to show complete of memory operation.

a) MFC
b) WMFC
c) CFC
926. The completion of the memory operation is indicated using ______ signal.
a) MFC
b) WMFC
c) CFC
927. _________ signal enables the processor to wait for the memory operation to complete.
a) MFC
b) TLB
c) WMFC
d) ALB
928. The small extremely fast, RAM’s all called as ________

a) Cache
b) Heaps
c) Accumulators
d) Stacks
929. The main virtue for using single Bus structure is ________
a) Fast data transfers
b) Cost effective connectivity and speed
c) Cost effective connectivity and ease of attaching peripheral devices
930. To extend the connectivity of the processor bus we use ______

a) PCI bus
b) SCSI bus
c) Controllers
d) Multiple bus
931. The bus used to connect the monitor to the CPU is ____________
a) PCI bus
b) SCSI bus
c) Memory bus
d) Rambus
932. The ISA standard Buses are used to connect ___________

a) RAM and processor
b) GPU and processor
c) Harddisk and Processor
d) CD/DVD drives and Processor
933. ANSI stands for _____________

a) American National Standards Institute
b) American National Standard Interface
c) American Network Standard Interfacing
d) American Network Security Interrupt
934. IBM developed a bus standard for their line of computers ‘PC AT’ called ________
a) IB bus
b) M-bus
c) ISA
935. The general purpose registers are combined into a block called as ______
a) Register bank
b) Register Case
c) Register file
936. In ______ technology, the implementation of the register file is by using an array of memory locations.
a) VLSI
b) ANSI
c) ISA
d) ASCI
937. In a three BUS architecture, how many input and output ports are there?
a) 2 output and 2 input
b) 1 output and 2 input
c) 2 output and 1 input
d) 1 output and 1 input
938. The main advantage of multiple bus organisation over a single bus is __________
a) Reduction in the number of cycles for execution
b) Increase in size of the registers
c) Better Connectivity
939. CISC stands for _________

a) Complete Instruction Sequential Compilation
b) Computer Integrated Sequential Compiler
c) Complex Instruction Set Computer
d) Complex Instruction Sequential Compilation
940. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where
S is term of the Basic performance equation).
a) 3
b) ~2
c) ~1
d) 6
941. In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.
a) MUX
b) DE-MUX
c) En-CDS
942. There exists a separate block consisting of various units to decode an instruction.
a) True
b) False
943. There exists a separate block to increment the PC in multiple BUS organisation.
a) True
b) False
944. ________ are the different types of generating control signals.

a) Micro-programmed
b) Hardwired
c) Micro-instruction
d) Both Micro-programmed and Hardwired
945. The type of control signal is generated based on ________

a) contents of the step counter
b) Contents of IR
c) Contents of condition flags
946. What does the hardwired control generator consist of?

a) Decoder/encoder
b) Condition codes
c) Control step counter
947. What does the end instruction do?

a) It ends the generation of a signal
b) It ends the complete generation process
c) It starts a new instruction fetch cycle and resets the counter
d) It is used to shift the control to the processor
948. The Zin signal to the processor is generated using, Zin = T1+T6 ADD + T4.BR…
a) True
b) False
949. What does the RUN signal do?

a) It causes the termination of a signal
b) It causes a particular signal to perform its operation
c) It causes a particular signal to end
d) It increments the step counter by one
950. The name hardwired came because the sequence of operations carried out is determined by the wiring.
a) True
b) False
951. The benefit of using this approach is ________

a) It is cost effective
b) It is highly efficient
c) It is very reliable
d) It increases the speed of operation
952. The disadvantage/s of the hardwired approach is ________

a) It is less flexible
b) It cannot be used for complex instructions
c) It is costly
d) less flexible & cannot be used for complex instructions
953. The End signal is generated using, End = T7.ADD + T5.BR + (T5.N+ T4.-N).BRN…
a) True
b) False
954. In micro-programmed approach, the signals are generated by ______

a) Machine instructions
b) System programs
c) Utility tools
955. A word whose individual bits represent a control signal is ______

a) Command word
b) Control word
c) Co-ordination word
d) Generation word
956. A sequence of control words corresponding to a control sequence is called _______

a) Micro routine
b) Micro function
c) Micro procedure
957. Individual control words of the micro routine are called as ______
a) Micro task
b) Micro operation
c) Micro instruction
d) Micro command
958. The special memory used to store the micro routines of a computer is ________
a) Control table
b) Control store
c) Control mart
d) Control shop
959. To read the control words sequentially _________ is used.
a) PC
b) IR
c) UPC
960. Every time a new instruction is loaded into IR the output of ________ is loaded into UPC.
a) Starting address generator
b) Loader
c) Linker
d) Clock
961. The case/s where micro-programmed can perform well _______________

a) When it requires to check the condition codes
b) When it has to choose between the two alternatives
c) When it is triggered by an interrupt
962. The signals are grouped such that mutually exclusive signals are put together.
a) True
b) False
963. Highly encoded schemes that use compact codes to specify a small number of functions in each micro
instruction is ________
a) Horizontal organisation
b) Vertical organisation
c) Diagonal organisation
964. The directly mapped cache no replacement algorithm is required.

a) True
b) False
965. The surroundings of the recently accessed block is called as ______

a) Neighborhood
b) Neighbour
c) Locality of reference
966. In set associative and associative mapping there exists less flexibility.
a) True
b) False
967. The algorithm which replaces the block which has not been referenced for a while is called _____
a) LRU
b) ORF
c) Direct
d) Both LRU and ORF
968. In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are
incremented by one when _____ occurs.
a) Delay
b) Miss
c) Hit
d) Delayed hit
969. The LRU provides very bad performance when it comes to _________
a) Blocks being accessed is sequential
b) When the blocks are randomised
c) When the consecutive blocks accessed are in the extremes
970. The algorithm which removes the recently used page first is ________
a) LRU
b) MRU
c) OFM
971. The LRU can be improved by providing a little randomness in the access.
a) True
b) False
972. In LRU, the referenced blocks counter is set to’0′ and that of the previous blocks are incremented by one
and others remain same, in the case of ______
a) Hit
b) Miss
c) Delay
973. The counter that keeps track of how many times a block is most likely used is _______
a) Count
b) Reference counter
c) Use counter
d) Probable counter
974. The key factor/s in commercial success of a computer is/are ________

a) Performance
b) Cost
c) Speed
d) Both Performance and Cost
975. The main objective of the computer system is ________

a) To provide optimal power operation
b) To provide the best performance at low cost
c) To provide speedy operation at low power consumption
976. A common measure of performance is ________

a) Price/performance ratio
b) Performance/price ratio
c) Operation/price ratio
977. The performance depends on ________
a) The speed of execution only
b) The speed of fetch and execution
c) The speed of fetch only
d) The hardware of the system only
978. The main purpose of having memory hierarchy is to ________

a) Reduce access time
b) Provide large capacity
c) Reduce propagation time
d) Reduce access time & Provide large capacity
979. The memory transfers between two variable speed devices are always done at the speed of the faster
device.
a) True
b) False
980. An effective to introduce parallelism in memory access is by _______

a) Memory interleaving
b) TLB
c) Pages
d) Frames
981. The performance of the system is greatly influenced by increasing the level 1 cache.
a) True
b) False
982. Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can
execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the
execution of the same instruction which processor is faster.
a) A
b) B
c) Both take the same time
d) Insufficient information
983. If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where
S is a term of the Basic performance equation).
a) 3
b) ~2
c) ~1
d) 6
984. The physical memory is not as large as the address space spanned by the processor.
a) True
b) False
985. The program is divided into operable parts called as _________

a) Frames
b) Segments
c) Pages
d) Sheets
986. The techniques which move the program blocks to or from the physical memory is called as ______
a) Paging
b) Virtual memory organisation
c) Overlays
d) Framing
987. The binary address issued to data or instructions are called as ______
a) Physical address
b) Location
c) Relocatable address
d) Logical address
988. __________ is used to implement virtual memory organisation.

a) Page table
b) Frame table
c) MMU
989. ______ translates the logical address into a physical address.

a) MMU
b) Translator
c) Compiler
d) Linker
990. The main aim of virtual memory organisation is ________

a) To provide effective memory access
b) To provide better memory transfer
c) To improve the execution of the program
991. The DMA doesn’t make use of the MMU for bulk data transfers.
a) True
b) False
992. The virtual memory basically stores the next segment of data to be executed on the _________
a) Secondary storage
b) Disks
c) RAM
d) ROM
993. The associatively mapped virtual memory makes use of _______

a) TLB
b) Page table
c) Frame table
994. The main reason for the discontinuation of semi conductor based storage devices for providing large
storage space is _________
a) Lack of sufficient resources
b) High cost per bit value
c) Lack of speed of operation
995. The digital information is stored on the hard disk by ____________

a) Applying a suitable electric pulse
b) Applying a suitable magnetic field
c) Applying a suitable nuclear field
d) By using optic waves
996. For the synchronization of the read head, we make use of a _______
a) Framing bit
b) Synchronization bit
c) Clock
d) Dirty bit
997. One of the most widely used schemes of encoding used is _________
a) NRZ-polar
b) RZ-polar
c) Manchester
d) Block encoding
998. The drawback of Manchester encoding is _________

a) The cost of the encoding scheme
b) The speed of encoding the data
c) The Latency offered
d) The low bit storage density provided
999. The read/write heads must be near to disk surfaces for better storage.
a) True
b) False
1000. _____ pushes the heads away from the surface as they rotate at their standard rates.
a) Magnetic tension
b) Electric force
c) Air pressure

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I .

Multiple Choice Questions on Microprocessors

2. A machine language instruction format consists of

Explanation: Machine language instruction format has both the fields.

3. The length of the one-byte instruction is

Explanation: This format is only one byte long.

4. The instruction format ‘register to register’ has a length of

Explanation: This format is 2 bytes long.

5. The R/M field in a machine instruction format specifies

6. In a machine instruction format, S-bit is the

7. The bit which is used by the ‘REP’ instruction is

8. If a W-bit value is ‘1’ then the operand is of

“Addressing Modes of 8086”

11.The instruction, MOV AX, 0005H belongs to the address mode

Explanation: Since immediate data is present in the instruction.

13. The instruction, MOV AX, [2500H] is an example of

Explanation: Since register is used to refer the address.

15. The instruction, MOV AX,[BX] is an example of

17. The addressing mode that is used in unconditional branch instructions is

Explanation: In intersegment mode, the control to be transferred lies in a different segment

19. The instruction, JMP 5000H:2000H; is an example of

“Instruction Set of 8086/8088 – 1”

22. Which of the following is not a data copy/transfer instruction?

Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

24. Which of the following instruction is not valid?

Explanation: The translate(XLAT) instruction is used to find codes.

Explanation: POPF is pop flags to stack.

Explanation: ADD instruction adds the data.

Explanation: The DEC instruction decrements the contents of a specified register/memory

37. The instruction that enables subtraction with borrow is

40. In general, the destination operand of an instruction can be

42. During comparison operation, the result of comparing or subtraction is stored in

44. Which of the following is a mnemonic?

Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.

46. The expansion of DAA is

Explanation: This instruction performs conversion operation.

Explanation: In this conversion, the result has to be only in AL.

50. The Carry flag is undefined after performing the operation

56. NOP instruction introduces

57. Which of the following is not a machine controlled instruction?

“Assembler Directives and Operators”

61. The directive that marks the end of a logical segment is

Explanation: The directive SEGMENT indicates the beginning of the segment.

“Do’s and Don’ts While Using Instructions”

Explanation: Only one memory operand can be specified in one instruction.

69. The instruction that is not possible among the following is

Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.

70. The instruction that is not possible among the following is

Explanation: Both the operands cannot be memory operands.

71. Both the operands source and destination of an instruction cannot be

Explanation: Since destination operand should not be immediate data.

73. The operands of an instruction cannot be

“Programming With An Assembler”

74. The disadvantage of machine level programming is

Explanation: The machine level programming is complicated.

Explanation: All the files should have the extension, .ASM.

78. The listing file is identified by

80. The listing file contains

81. DEBUG.COM facilitates the

82. DEBUG is able to troubleshoot only

83. The Stack follows the sequence

Explanation: The stack follows last-in-first-out sequence.

85. The stack is useful for

86. The Stack is accessed using