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Integrated Circuit (IC) Design Flow

Anand Darji (M.Tech, IITB)
Lecturer, Electronics Engineering Department,
S.V. National Institute of Technology, Surat-7

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Need of IC Design
• ICs consist of miniaturized electronic
components built into an electrical network on a
monolithic semiconductor substrate by
photolithography.

• There are three main advantages of ICs over

discrete circuits:
Cost
Performance.
Size
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Need of IC Design
• Cost is low because the chips, with all their components,
are printed as a unit by photolithography.

• less material is used to construct a circuit as a packaged

IC die than as a discrete circuit.

• Performance is high since the components switch quickly

and consume little power compared to their discrete
counterparts, because the components are small and close
together.

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Introduction to ASIC
• ASIC:Application-Specific Integrated Circuit

• An ASIC is an integrated circuit (IC) customized for a

particular use, rather than intended for general-purpose use.
• For example, a chip designed solely to run a cell phone is
an ASIC.

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ASIC Complexity
• As feature sizes have shrunk and design tools improved
over the years, the maximum complexity and hence
functionality possible in an ASIC has grown from 5,000
gates to over 100 million.

• Modern ASICs often include entire 32-bit processors,

memory blocks including ROM, RAM, EEPROM, Flash
and other large building blocks. Such an ASIC is often
termed a SoC (System-on-a-chip).

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Transistor Counts by Moore’s law

1 Billion
K
1,000,000
Transistors

100,000
Pentium® III
10,000 Pentium® II
Pentium® Pro
1,000 Pentium®
i486
100 i386
80286
10 8086
Source: Intel
1
1975 1980 1985 1990 1995 2000 2005 2010
Projected
Digital Integrated Circuit 2nd Courtesy, Intel
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VLSI Design Cycle

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ASIC Design Flow

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Classification of ASICs
• Full-custom ASIC
• Semi-custom ASIC
Cell-based ASIC
Gate-array-based ASIC
• Programmable ASIC
Programmable Logic Device (PLD)
Field-programmable gate array (FPGA)

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Full Custom ASIC

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Full-Custom ASIC
• Engineers design some or all of the logic cells,
circuits, or layout specifically for one ASIC

Full-custom ICs are the most expensive to manufacture

and to design
Manufacturing lead time (the time it takes just to make
an IC – not including design time) is typically 8 weeks

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Full-Custom ASIC
• When does it make sense?
there are no suitable existing cell libraries available
existing logic cells are not fast enough
logic cells are not small enough
logic cells consume too much power
ASIC is so specialized that some circuits must be
custom designed

• Trends: fewer and fewer full-custom ICs are

being designed (excluding mixed analog/digital
ASICs)

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Full-Custom ASIC Flow

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FULL Custom ASIC Flow

Technology Selection

Design Specification
(W/L Ratio)

Schematic Entry

Schematic Simulation
To Fablab
System Partitioning
Postlayout Error Physical
Design &
Simulation Verification
Floor Planning L
A
Placement Y
O
U
Parasitic Extraction Routing
T

OK OK
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Designing
• Technology Selection
Based on specifications i.e Cost, Speed, Area, Power
requirement, the technology is decided.
Technology will be deciding minimum feature size.

• Circuit Design (W/L Ratio)

As per requirement of Speed, Area, Power W/L ratios
of MOS transistors are designed.
Generally Width of transistors are changed keeping L
unchanged.

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Functional Simulation
• Schematic Entry
In Schematic entry, graphical representation of various components
are selected from Model libraries and placed in the editor window
and are manually connected by the designer.
Mentor Graphics – Design Architect, Cadence – Virtuoso
Schematic Composer, Synopsys – cosmosSE

• Schematic Simulation
process of analyzing the design functionality with through component
model libraries for intended pacifications.
NGSpice, Cadence- Spectre; Synopsys- Hspice; Mentor Graphics-
Eldo.

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Physical Design
• System Partitioning
Analog – Digital
Control Path –Data path

• Layout Design
Converting Circuit to different layers (Process Masks)
for fabrication.
SDL (Schematic Driven Layout) is automatic
Minimum distance between layers is called feature.
Feature is decided by technology used

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Contd…
• Layout
Layout has three steps:
Floorplan : Arrange the blocks of the netlist on the chip.
Placement : Decide the locations of cells in a block.
Routing : Make the connections between cells & blocks.

Synopsys- Astro,
Mentor graphics- Calibre,
Cadence- SOC encounter

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Physical Design Verification

• DRC
Interface between designer and process engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
scalable design rules: lambda parameter
absolute dimensions (micron rules)
Iteratively Modify layout till DRC errors becomes Zero

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Contd…
• LVS (Layout Vs Schematic)
When there is no DRC error go for LVS
LVS is equivalency check between Layout and actual
schematic

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Post Layout Simulation

• Parasitic Extraction (PEX)
Extracts the resistance and capacitance of the
interconnect and generates new net-list
Synopsys-Star, Mentor graphics - xCalibre.

• Post layout Simulation

Verifies functionalities of Extracted net-list during
PEX through circuit simulators
Circuit Simulators :HSpice, Spectre, Eldo.

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Semi-Custom ASIC

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Semi-Custom ASIC
• Unlike full-custom ASIC's, semi-custom ASIC's are
designed with the help some available library components
or active elements to allow a certain degree of
m od if icat ion d u ring t he m an uf act u rin g p roc es s .

• Two Approaches
Standard Cell based
Gated Array Based

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Standard-Cell
• Cell-based IC (CBIC) uses predesigned logic cells known as
Standard cells

• Each standard cell has been already optimized entity through Full-
custom ASIC flow and stored as Library

• Layout is usually automatically Placed and Routed through CAD tool

• Pre-designed standard-cell library reduces design risk and time

• Typical Standard Cell library consists of nand, nor,inverters, buffers,

inverters, registers, decoder, encoders, adders, RAM, ROM etc.

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Characteristics of CELL
• Each cell is designed with a fixed height.
To enable automated placement of the cells, and Routing of
inter-cell connections.
A number of cells can be abutted side-by-side to form rows.

• The power and ground rails typically run parallel to upper

and lower boundaries of cell.
Neighboring cells share a common power and ground bus.
NMOS transistors are located closer to the ground rail while the
PMOS transistors are placed closer to the power rail.

• The input and output pins are located on the upper

and lower boundaries of the cell.

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Layout :Standard-Cell-Based ASIC

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Floor plan : Standard Cell Design

Inside the I/O frame which is reserved for I/O
cells, the chip area contains rows or columns of
standard cells.
Between cell rows are channels for dedicated inter-
cell routing.
Over-the-cell routing is also possible.
The physical design and layout of logic cells
ensure that
When placed into rows, their heights match.
Neighboring cells can be abutted side-by-side,
which provides natural connections for power and
ground lines in each row.

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Semi-Custom ASIC Flow

A) Standard Cell Based ASIC

B) Gate Array Based ASIC

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Standard Cell Based ASIC

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Design Specification
• This is the beginning and most important step towards
designing a chip as the features and functionalities of the
chip are defined.

• The goal is to specify the functional requirements for the

design and define the external interfaces to the related
designs.

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Logic Design and Functional Verification

• Design Starts with Specifications
Text Description or System Specification Languages like C,
System C, System Verilog
• RTL Description
Automated conversion from system specification to RTL possible
Example: Cadence C-to-Silicon Compiler
Most often designer manually converts to Verilog or VHDL
• Verification
Generate test-benches and run simulations to verify functionality
Assertion based verification
Automated test-bench generation
Simulators: NC Verilog and NCvhdl From Cadence, ModelSim
from Mentor Grapics

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RTL Synthesis
• RTL Synthesis
Automated generation of generic gate description from RTL
description
Logic optimization for speed and area
State machine decomposition, datapath optimization, power
optimization
Modern tools integrate global place-and-route capabilities
• Library Mapping
Translates a generic gate level description to a net-list using
a target library

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Functional or Formal verification

• HDL ambiguities can cause the synthesis tool to
produce incorrect net-list
• Rerun functional verification on the gate level net-
list
• Two Methods of Formal verification
Model checking: prove that certain assertions are true
Equivalence checking: compare two design descriptions

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Synthesis Tools

• The most popular tools in the market are:

Design Compiler by Synopsys,
Leonardo spectrum by Mentor Graphics,
Synaptic by Xilinx.

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Static Timing Analysis (STA)

• Check Temporal requirement of design
• Uses intrinsic gate delay information and estimated routing
loads to exhaustively evaluate all timing paths
• Requires timing information for any macro-blocks e.g.
memories
• Will evaluate set-up and hold-time violations
• Special cases need to be flagged using timing constraints
(more later)
• Reports “slack time”
• Re-synthesize the circuit or re-design to improve delay
• Popular tool for STA is Synopsys Primtime

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Test insertion and Power analysis

• Test insertion
Insert various DFT (Design for Test) features
Automatic Test Pattern Generation (ATPG) tools generate test
vectors to perform logic and parametric testing
Tool use is Synopsys Tetramax

• Power Analysis
Power analysis tool predict the power consumption of circuit
Either test vectors or probabilistic activity factors used for estimation

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Standard Cell Place and Route

DEF: Design Exchange Format

ESPF: Extended Standard Parasitic Format
SDF: Standard Delay Format
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Physical Design:
Floor Planning, Placement and Routing
• Manually place major modules in the chip depending on
connections with other modules
• Standard cell rows are defined next and the gates are placed
• Timing driven placement tries to minimize delay on critical
paths
• Routing
Route special nets : Power, Ground
• Clock tree synthesis/ routing
Minimize skew
Insert buffers
Global and detailed routing of signal nets
Popular Tool for Place and Route :
Cadence - SOC encounter

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Placement

SDF : Standard Delay Format

DEF: Design Exchange Format
LEF: Library Exchange Format
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Place and Route

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Verification
• Parasitic Extraction
This step is performed after Routing step
Output file is Extended Standard Parasitic Format (ESPF)
• Static Timing Analysis
• Cross Talk, Vdd Drop Analysis
• Detail power analysis with wire load capacitance
• Final DRC/LVS check
Cadence : Assura, Dracula
Mentor : Calliber
• GDS-II (Graphics Data Stream) file format output for
Foundry

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Write GDS-II
• It was originally developed by Calma for its layout design software,
"Graphic Data System" ("GDS") and "GDS II". Now the format is
owned by Cadence Design Systems.

• GDS II files are usually the final output product of the IC design
cycle and are given to IC foundries for IC fabrication.

• Initially, GDS II was designed as a format used to control integrated

circuit photomask plotting.

• Popular Tools : Cadence- Soc Encounter and Synopsys - Astro.

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Gate-Array-Based ASIC
• Gate array (GA) implementation requires a two-step
manufacturing process:

1. The first phase, which is based on generic (standard) masks,

results in an array of uncommitted transistors on each GA chip.

2. These uncommitted chips can be customized later, which is

completed by defining the metal interconnects between the
transistors of the array.

• Only the top few layers of metal, which define the

interconnection between transistors, are defined by the
designer

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GA Based IC Design Flow

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Channeled Gate Arrays

• Channeled gate
arrays
• leave space between
rows of transistors for
wiring
• Routing is simpler
• Only one Metal layer is
used

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Channel less Gate Arrays

Channel less gate

arrays –
• use rows of unused
transistors for routing.
• Higher Packing density
• Variable Size Cell support
• Universally used

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Structured Gate Arrays

Structured gate
arrays – also
known as embedded
gate arrays. For
instance, embedded
area set aside for
memory

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Performance Analysis of ASIC Design

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Programmable ASIC:PLD

• PLD can be configured or programmed to create a part

customized to a specific application

• No customized mask layers or logic cells

• A matrix of logic macrocells (programmable array logic

followed by flip-flop/latch)

• A single block of programmable interconnect

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PLD Structure

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Programmable Logic Device

I5 I4 I3 I2 I1 I0 Programmable
OR array I3 I2 I1 I0 Programmable
OR array I5 I4 I3 I2 I1 I0 Fixed OR array

Programmable AND array Fixed AND array Programmable AND array

O 3O 2O 1O 0 O3O2O1O0 O 3O 2O 1O 0

PLA PROM PAL

Indicates programmable connection
Indicates fixed connection

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Field-Programmable Gate Array (FPGA)

• None of the mask layers are customized

• A method for programming the basic logic cells and the

interconnect.

• An array of programmable basic logic cells that can

implement combinational and sequential logic

• A matrix of programmable interconnect surrounds the

basic logic cells.

• Programmable I/O cells surround the core

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Field-Programmable Gate Array

(FPGA)

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FPGA vs. CBIC

Easy to Design Difficult to Design

Short Development Time Long Development Time
Low NRE Costs High NRE Costs
Design Size Limited Support Large Designs
Design Complexity Support Complex
Limited Designs
Performance Limited High Performance
High Power Consumption Low Power Consumption
High Per-Unit Cost Low Per-Unit Cost (at
high volume)

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Summary : Design Styles

Design Style
FPGA Gate array Standard Full
cell custom
Cell size Fixed Fixed Fixed Variable
height
Cell type Programm Fixed Variable Variable
able
Cell placement Fixed Fixed In row Variable

Interconnections Programm Variable Variable Variable

able
Design time Very fast Fast Medium Slow

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Comparisons
Design Cost / Quality % Companies
Methods Development involved
Time
Full Custom

Standard Cell
Library Design

ASIC – Standard
Cell Design

RTL-Level Design

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• Reference
CMOS VLSI Design, A Circuits and Systems Perspective,
3rd Edition ve, 3rd Edition, Neil Weste et al. © 2005
Pearson Addison-Wesley
Application Specific Integrated Circuit Design by Smith
Digital Integrated Circuit- A Design Perspective , 3rd
Edition, by Rabaey et al. PHI

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• Questions ???????

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