9. 10. nL 12, Number Systems and Arithmetic Decimal number 15 may be written in binary system as (@ 1110 (@) 1100 () Wak (d) 4001 . Decimal number 74 may be written in bine.) system as (a) 1001019 (©) 1001011 () 1001001 (d) 100011 . Decimal number 21.125 may be written in binary systen: as (@)\You01.001 (© ig101.010 (®) 10100.001 (2) 10100.100 4. Decimal equivalent of binary number 1111.01 is (a) 14.25 (®) 15.25 fe) 15.01 @ 7.35, Decimal equivalent of binary number 0.1011 (a) 0.6875 (b) 6.875 © 0.4876 (@) ~0.6875 Radix of octal number system is (a) 2 ya ©) 8 (d) 10 Decimal equivalent of octal number 57 is (a) 47 (6) 65 (©) 54 @ 50 Octal equivalent of decimal number 49 is (@) 61 () 59 (ec) 47 (d@) 53 Maximum number of binary bits required to represent a digit of octal number is (a) 2 @4 Octal equivalent of decimal (51)jo is (a) (63), () <4 © (67, (a) Ng BCD equivalent of decimal number (85), is (@ 1000-1100 (6) 1000-0101 (©) 1401-1010 (@) 1101-0101 BOD equivalent of decimal number (43) gi (@) 165-911 099-007 (@) ¥.90-08 wOrO5:I0 13. 14. 15. 16. 17. 18. 19. 20. 21. 22, » Binary DIGITAL CIRCUITS Excess-3 code is also known as (a) weighted code (8) eyclie redundancy eode (6) self complementing code {2) algebraic code Waick of the following codes is an unweighted code ? (a) 8421 code (b) Bxcoss-3 cote (c) 2421 code (d) 63210 corte Which of the following codes is a weighted code? (a) Excess-3 code () gray code (6) shift-counter code (a) 5111 code Excess-3 equivalent of decimal number (8) jo (a) 1011, (®) 1101 fe) 110 (a) 1001, The gray code equivalent of binary number (1000001), is (@) 1100001 (b) 1100011 (©) 1000011 (@) 110201 Decimal number (85), is encoded as 1100- 0101 in (a) 8421 code (e) 2421 code (b) 4421 code (a) 2221 code Binary equivalent of gruy code number 101 (a) 101 (b) 110 e) 100 m1 Number of binary bits required to represent a hexadecimal digit is (@) 3 4 Os ia 6 Hexadecimal equivalent of decimal number 1000 is (a) 3E8 ie) 3C¥ (h) 4 ES (d) 3 ET Binary subtraction 1111-111 will yield (a) 1100 (b) 1000 (©) 1001, (@) 1010 addition 100! = 1101 vivi 1 t99 10One’s compliment of 010001 is fa) 101110 () lon fe} O10 (a) 01110 ‘The 2's compliment of binary number 0.01011 (a) 1.10101 (b) 0.10101 (e) 0.10100 (a) 1.10100 . ASCII code is used as an alphabatic code (b) acyclic code (©) a weighted code (@) an alphanumeric code ASC. code is a) ad-bite ie) abit code (b) a Git code (d) none of these Binary divisizn 10010.1011 * 11.01 yields at () 100.11 wu (@) 101.1 Asiv-bit alpha-numeric code is able to code a) 86 characters () 48 characters (c) i characters (d) 128 characters 28. 30, Number 17 in BCD representation is a) woul (o) 001 111 (e) 10 U1 {d) 10001 B1. Cyclic codes are useful in @) arithmetic computation () continuously varying digital signals repre- sentation (©) randomly varying digital representation (d) transferring the information signals 82, BCD equivalent of Gray.code number 1001 1001 1100 () 110 (a) 1101, 33, Hexadecial equivalent of decimal number 6) OF 0101 lent of heradevim: d) 41.836 36. Hexadecimal equivalent of binary number 1000101011001 ie 2359 ter SD (b) 9493 (@) 8DF2 DIGITAL CIRCUITS Binary 1000 when multiplied by binary 1111 results in binary a) 1111112 (©) 1111000 (6) 1111100 (d) 1110000 38, Byte signifies (@) an integrated circuit (6) astring of 2 bits (c} asstring of 4 bits (@) a string of 8 bits 39. 1 k-byte is precisely equal to (a) 1012 bits (c) 1000 bits (b) 1024 bits (a) 1020 bits Hexadecimal number system is (a) an obsolete system no longer in use (b) widely used in analysing and programming microprocessors used in caleukators only none of these id) 41, Hexadecimal system uses digits from (a) 1 to 16 (b) 1t09 ©) 1to6 (d) 0t09 42. Main advantage of hexadecimal number system is (a) case of conversion from hexadecimal to | decimal and vice-versa ease of conversion from hexadecimal to binary and vice-versa case of conversion from hexadecimal to gray code and vice-versa use of number and alphabets oe) © (a) 43, Binary coded decimal (BCD) numbers express each decimal digit as a (a) unit (b) bit (c) byte (@) nibble 44, BCD numbers are useful whenever (a) binary to BOD conversion is desired (b) binary to hexadecimal conversion is desired (c) decimal information is transferred into or out, of digital system (d) none of these st. Bou mony isces ore there mm binary 1011 1003 6110 1110 (at 2 © 3 @4 47. What does 4-k represent ? (a) 4000 (b) 4048 (©) 4182 (a) 4096jeurrs: +h of the following hexadecimal number at prior to F 52B ? () F51B (@) F528 ihich of the following hexadecimal lumbers represents. an odd decimal (by EG id) AA Which of the following hexadecimal umbers represents an even decimal umber ? (®) DS (@) ac (a) NOW gate (¢) EX-OR gate (6) NAND gate (@) AND gate &, A.B.C =D represents a (a) NOR gate () NAND gate f(c) EX-OR gate (d) AND gate E Output of which of the following gates in 1 only if at least one of its inpute is 0? F(@) NOR gate () NAND gate (@) EX-OR gate (dé) AND gate Output of which of the following gates is 0 b only if at least one of its inputs is 1? $(a) NOR gate () NAND gate (©. EX-ORgate (d) AND gate Bi: AB = Y is the Boolean expression for (a) OR gate (b) NOR gate Hi(c) NAND gate (d) EX.OR gate R A+B =Y is the Boolean expression for. (a) AND gate (6) NAND gate f (c) NOR gate (d) EX-OR gate [. Which gate has the output low only when both inputs are high ? E @) AND () NAND (©) OR (@) NOR NOR gate is logically equivalent to (a) an OR gate followed by an AND gate (8) an OR gate followed by a NAND gate (©) an AND gate followed by OR gate (@) an OR gate followed by an inverter 7a 59. ANAND gate is equivalent to (a) an AND gate followed by a OR gate () an AND gate followed by an inverter (c) an inverter followed by OR gate (d) an inverter followed by an AND gate 60. NAND gate is called a universal gate because (a) itis most commonly used (6) all logical functions can be realized by use of NAND gates alone (c) all minimization techniques en be aplicd to it (d) it can realize AND and NOT functions 61. AB + AB =D represents (a) anOR gate (6) an EX.OR gate () aNOR gate (@) a NAND gate Complementary function is represented by (@) NOR gate" (b) NOT gate (©) NAND gate (@) EX-OR gate 63. Boolean expression for three input AND gate @A.B.C=D () A+B+C=D © RBC=D @) A+B+T =D 64. Boolean expression for three input OR gate (@) R+B+T=D ) A+B+C=D @AB.C=D @ABT=D 65. The circuit given below is functionally equivalent to a ie se—_{>—_ (a) OR gate (b) NOR gate (©) AND gate (d) NAND gate 66. The circuit given below is functionally equivalent to " 62, camel = —D (b) NOR gate (d) NAND gate (a) OR gate (c) AND gate 67. The circuit given below is functionally equivalent to (a) EX.OR gate ) inhibit gate (b) comparator eh) NAND gate69, 70. 74. .. The circuit given below is functionally equivalent to (b) NOR gate (d) NAND gate fa) EX-OR gate (c) AND gate Half-adder is also known as ia) ANDeircuit (6) NAND circuit (c) NOReireuit__ (d) EX-OR cireuit Which of the following Boolean algebra rules is correct * (a) Axe by ASA. B=AtB c) At KB sAtB d) M(A+B)=B 5 | Which of the following statements is true ? (a) (A+ B)(A+C) = AC + BC b) (A+ B)(A+C)= AB +C (c) (A+ B)(A+C)=A4 BC (a) (A+ B)(A+C) = AC +B . Which of the following is a universal gate ? (a) AND (b) O} ) EX-OR (@ NAND |. Logic 1 in positive logic system is represented by (a) zero level (b) lower voltage level (c) higher voltage level dd) negative voltage Which of the following statements is true ? (a) A+ ABA (b) A(R+B) =AB ©) AB+ AB =A a) CA+ CRB =CA+CB ‘An AND circuit a) is a memory circuit {S) gives an output when all input signals are present simultaneously (c) isa negative OR cireuit (@) isa linear circuit . The following symbol represents a 2) inverter () buffe schmitt trigger (@) flip-flop 79. @ >— ‘An alternative way of showing a two it NOR gate is An alternative symbol for two input Nj gate is @ —D-ich of the following Boolean algebra fements represents distributive law ? HA+B)+C ‘A.(B40)=(AB) + (A.0) A.(B.0)=(AB).C ABSBA ich of the following Boolean algebra fements represents commutative law ? a) A+ARA ) A+ AB =A+B AsBaBea none of these h of the following is not functionally a nplete set ? a). AND, OR (6) NAND a NOR (d) AND, OR, NOT which of the following gates, the output high if and only if all inputs are high? (@) NOT (®) AND @) XOR In which of the following gates the output is high if and only if at least one input is high? (@) NOT (® AND @ OR (@) NAND Inwhich of the following gates the output is high if and only if at least one input is Tow (a) NOT (e) OR (®) AND (@) NAND In which of the following gates the output is 0 if and only if at least one input is 1? (a) NOT (6) AND (@) NAND ; ‘For which of the following logic gates, the output is complement of the input ? (@) NOT () AND F() OR (a) XOR Let A and B be the inputs to. a NAND gate. Then the output is equal to (@) A+B O AB © x @ AB Let A and B be the inputs to a XOR gate. Then the output is given by G@) A+B (6) AB © XB (@) AB+AB The NAND gate can function as a NOT gate if (a). inputs are connected together () inputs are left open (c) one input is set to 0 (@) one input is set to 1 91. 92, 93, 94, 96. 97. 98, 99, 100. 75. What is the minimum number of two-input NAND gates used to perform the function of two-input OR gate ? (a) one (b) two ©) three (@) four Which of the following gates are added to the inputs of the OR gate to convert it into NAND gate ? (@) NOT () AND (©) OR (d) XOR * Which logic function is produced by adding inverters to the inputs of an AND gates ? (@) NAND (®) NOR (©) XOR. (@) OR Which logic function is produced by adding an inverter to each input and the output of an AND gate ? (a) NAND () NOR fe) OR (a) XOR Which of the following gates is known as “concidence detector”? (@) AND () OR () NOT (@) NAND An AND gate may be visualized as (a) switches connected in series (®) switches connected in parallel (©) MOS transistor connected in series (d) none of these An OR gate may be imagined as (a) switches connected in series (6) switches connected in parallel (©) MOS transistors connected in series (@) none of the above Which of the following gates would have output I when one input is 1 and the other input is 0? (a) OR (®) AND fe) NAND (d) both (a) and (c Which gate is formed by adding an inverter at the output of an OR gate? (a) NOR () XOR (c) EQUIVALENCE (d) NAND What is minimum nuniber of NAND gates needed to perform the logic function A.B ? (a) 1 @) 2 () 3 (4 Which of the following isMbootionatly a complete set ? (a) AND, OR ib) AND,XOR AND, O# New16 — 102. Which of the following is not true # a) 04A=A (6) 1+A=1 AtA=A @) 1.A=1 103. Reduced form of Boolean expression (A + B) \Ae Chis a) AB eM (0) A+B+C er MC i (d) A+ BC Wt Reduced form of Boolean expression ag + AB +ABis @) ari (e) K+B 8 @ A+B 105. Which of the following logic expressions is wrong ? a () 191=0 te (@) 1018 106, Simplified form of Boolean expression (A+B + AB)(A+ C)is ai A+B+C fe) A+ BC (b) AB + BC (ac+B 107. Simplified form of Boolean expression (A+ B+ CAs B+O)(AFB+ Cis (® A+Be (d) AB+T 108. Complement of Boolean expression A(B+O)(E + Dis (a) A+BC+CD ( Avncsé {c) A(B+C)(C+D) _ (d) (C+D) (B+ O)CA 109. Simplified form of Boolean expression (A+ B+ AB)Cis (@) 1 () 0 ec) C (a) Tt 110. The complement of (A + BC + AB) is -) 46) KBC 111. How many bits are required to encode all twenty six letters, ten symbols and ten numerals ? fa} 5 6 fe 7 id) 46 piGrraL cincurY 112, Which table shows the logical state of d digital circuit output for every possitl ‘combination of logical states in the inputs! (a) funetion table (6) truth table () routing table (@) ASC-II table . 113. Clock signals are u sed in sequential lo circuits (a) to tell the time of the day {b) to tell how much time has elapsed since system was turned on (c) to carry serial data signals id) to synchronize events in various parts of system 114. Which table shows the electrical state of digital circuits output for every possil combination of electrical states in t input? (@) function table (©) routing table (b) truth table (@) ASC-I table 115. A comparison between serial and pt ‘adder reveals that serial order (a) is slower (0) is faster (c) operates at the same speed as parallel adi (d) is more complicated 116. The circuit given below isa so—{nat —~ 2 8 {At —in Saputs ° Ss @ (a) full adder (@) full subtractor (©) parity checker (d) none of the above 117. The output D and E in the circuit of @ are (a) D=(A@B).C E=(A@B)@C (b) D=AB+BC+AC E=A@BeC () D=(A@B)EC ASBI+C ©) three (d) any number, 119. A positive AND gate is also a nege (a) NAND gate (6) NOR gate (c) AND gate _(d) OR gatebencurs sn Boolean algebra, the term sum-of- iproducts means () the AND function of several OR functions ; (©) the OR finction of several AND functions (©) the OR function of several OR functions }(@) the AND function of several AND functions The m-bit parallel adder consists of (a) (m + 1) full address () m2 full address () (m= 1) full address (d) m full address j The output of a sequential circuit depends on ;(@) present inputs :(6) past outputs: (©) both present and past inputs (@) past inputs Which of the following is not a sequential E eireuit ? (a) flip-flop @) counter {/ (©) shift register (¢) multiplexer A full adder adds the h' bits of two numbers to the (a) difference of the previous bit, (6) sum of all previous bits (6) carry from (& ~ 1)" bit ‘Tersum of previous bit, The cireuit which constitutes a sequential F* circuit is (a): flip, (6) counter (©) shiftregister (qd) all of these 8. Popular applications of flip-flop are (a) counters 7 (6) shift registers (©) transfer register G@) all of these ‘ (a) AND function of several OR functions (8) OR funetion of several AND functions (c) OR function of several OR functions (@) AND function of several AND functions 128. What is the form of the Boolean expression AB+ BC =¥? (@) product-of:sums (®) sum-of products (©) karnaugh map (@) matrix 129, What is the form of the boolean expression (A+B)(E+D)=x? (a) product-of sums (0) sum-of products (©) karnaugh map (@) matrix a 180. The device which selects one of the several inputs and transmits it to a single output is (a) decoder (6) multiplexer (©) demultiplexer (¢) counter 181. A multiplexer is also known as (a) counter (6) decoder (©) data selector () none of these 182. The circuit used for parallel to serial conversion of data is known as (a) decoder (0) demultiplexer (©) multivibrator (@) multiplexer 183) The dynamic hazard problem occurs in (2) combinational cireuit alone (b) sequential cireuit alone (©) both sequential and combinational circuits (d) none of the above 134, A simple flip-flop is (a) a 2-bit memory (6) a L-bit memory (©) a fourstate device (@) obtained by cross gates ‘oupling of two NAND switching function is symmetric with respect to a set of literals if and only if the function remains unchanged after (@) two of these literals are interchanged (6) any permutation of the literals (©) all the literals are changed in anticlockwise order (@) all the literals are changed in clockwise order 136. A demisltiplexer is used to (@) route.the data from single input to one of many outputs (6) select data from several inputs and route it to single output () perform serial to parallel converion (@) all ofthe above @®. te race hazard prostom oceurs dust (a) faulty design of logic circuits (®) non-redundant form of the circuit (c) time-delay in circuits due to high speed logic (@ all of the above 138. Simplification of function by k-map requires that the function should be in the (a) SOP form (©) POS form (c) canonical mn (@) any of the above 199. An SR flip-flop does not accept the input entry when (a) both inputs zero '6) zero at Rand one at S () zero at Sand one at R (@) hoth inputs at une78 140, The functional difference between SR and JK flip-flop is that {a} JK flip-flop has a feedback path (3) JE Mip-flop does not require an external clock «ok flip-flop is faster than SR flip-flop K flip-flop can accept, both inputs atl 141. Number of flip-flops needed to divide the input frequency by 32 is (a) 2 4 te) 5 @s @ Mos logic gates have no current hogging problem because the gate terminal has (a) low input impedance 'b) zero impedance {c) compensating effect (d) high impedance 143. A flip-flop can store fa) Thitofdata — (b) 2bits of data (@) Sbitsof data (d) 4 bits of data @ sehmut trigger maybe weed to Seti tinge Pecopnaing RNY i a ne id) none of these Jowly varying voltage into square 145. Asynchronous sequential circuits are difficult to design because (a) they use external clock (8) they are more complex (e) they have stability problem (a) they have fast response 146. A master slave Jk flip-flop consists of 1a) a cascade of two SR flip-flops (6) a Jk flip-flop connected in series with a D flip-flop ic) two SR flip-flops connectéd in parallel id) an SR fhip-flop and aT flip-flop 147, The flip-flop free from race-around problem is ia) SR flip-flop bi D P ld) Master slave dk fitp-flop 148. A bit shift register can be made by using number of Jk flip-flops a) 3 @) 4 5 @ 8 Cte factor is not important white selecting a logic technology is ta) cost 2) power dissipation te umber of pins dl) speed of operation frequency to voltage J DIGITAL CIRCUTS, 150. Most of the memory systems have (a) electro-pneumatic properties (0) electrostatic properties (c), magnetic properties (d) all of these 151, Which of the following statements is wrong 7 Asynchronous counter oa (a) has flip-flops that simultaneously (6) is capable of operating’at high frequencies (c) requires more logic elersents (d) has large carry propagation time change stat 152, Which of the following statements is wrong. 2 Carry look ahead adder is used 4 (a) when number of bits is more (b) when only carry is required (c) when time is an important factor (d) to save time lost in propagation of carry 153, The logic which has the highest speed is (@) DIL () RTL () ECL (d) TT, 154, Which of the following logics has high noise! immunity? (a) RTL () TTL () BCL (@) BTL 155. Which ofthe following logic gates dissipate| minimum power ? (@) RTL () TTL (©) MOS (d) ECL Which out of the following logic families is most expensive ? (@) RTL () TTL (@ DTL @ BCL 157. Which out of the following logic families has maximum fan-out-capacity ? (a) RTL (6) EC () MOS {@) CMOS Which out of the following TTL sub-families has maximum speed ? (a) standard TTL () Schottky-clamped TTL (©) high speed TTL. (@) low power TTL 159. The fan out TTL logic gate is about (@) 5 @) 10 (©) 20 (d) 50 160. Switching speed of ECL logic is very high because (a) it uses positive logic (b) it uses negative logic (c) it uses high speed transistors (@) its transistors remain unsaturatedET flip-flop is commonly used as (a) both digital counter and frequency divider (0) a delay switch (©) a digital counter alone E (a) none of these f62. In a flip-flop, ratio of the frequency of the ‘inpist pulse to the frequency of output pulse is @) 12 @1 @2 @3 When an inverter is placed between two E inputs of an S-R flip-flop, the resulting flip- (flop is F(a) Jk flip-flop ®) Dlip-flop (©) TAip-fop (@) Master slave Jk flip-flop For an input pulse train of clock period T, the delay produced by n-stage shift register will be (@) aT © (ne )T () (@-DT @2nT Which of the following conditions must be met to avoid race around problem ? (a) at ar >t, (@) 2t, ———— (a) an adder circuit (®) a subtractor circuit (e) a comparator circuit (d) a parity generator circuit The minimum decimal equivalent of the number 110.0 is (a) 183 (®) 194 fe) 268 (d) 269 (PES5) 4 XOR (CB15),, is equal to (@) (8320),, @ E35), ©) F505 @) (8520),5 ae Ina negative edge triggered J-K flip-flop in order to the output Q state 0, 0 and 1 in the next three seccessive clock pulses, the J-K input states required would be respectively (a) 00, 01 and 10 (®) 00, 01 and 11 (©) 00, 10 and 01 (@) 01,10 and 11 The initial state of MOD-16 down counter is 0110. After 37 clock pulses, the state of. counter will be share bu sitftregusterss shou te the srure, To have the content "OOO" again number of clock pulses required would be switching between cut-off and active regions,Brora. cincurrs 3: Symmetrical equare wave of time period 100 scan be obtained from square wave of time period 10 us by using a (a) divide by - 5 circuit (). divide by - 2 circuit (©). divide by - 5 circuit followed by a divide by Qeireuit ~ @ BCD counter Fit) For a particular type of memory, the access time and the cycle time are respectively 200 ns and 200 ns. The maximum rate at which the data can be accessed is (a) 2.5 x 10% (6) 5 x 10%/s, (©) 2% 10% (d) 1 108s #48, In the negative logic system, (a) the more negative of the two logic levels represents a logic "I" state (6) the more negative of the two logic levels represents a logic "0" state (c) all input and output voltage levels are negative (d) the output is always complement of the intended logic function 40. If the output of a logic gate is "I" when all its inputs are at logic ‘0’, the gate is either (a)'a NAND or a NOR (@) an AND or an EX-NOR (©) an OR ora NAND (@) an EX-OR an EX-NOR £250. For the Karnaugh map shown in the given figure, the minimum Boolean function is x» Lo 1 oo [4 1 or fa ite (ail 7 10 fT T am vy tray te) seeey2 251. 18 dBm is equivalent to (a) 2mW (6) 10 mW (c) 20mW ~ (d) none of these (b) xz #2 +27" (@) v242' +92 252. The voltage gain vérsus frequency curve of ‘an OP-Amp is shown in the given figure. The gain bandwidth product of the op-amp is Vottage| 20 o8 gay 20087 00c0de N. 08 FE Frecueney (a) 200 He (©) 200 kHz ae (b) 200 MHz. (d) 2MHa 218 253. The vg of the op-amp circuit shown in the given figure is wo” [28 a a I ieee lente 8 pos (a) 110, (b) 10», ©) ¥ (a) zero @® A122 v monolithic regulator is adjucted to Obtain o higher output voltage aa shaun thecleen Reure: The wil be () OV (©) 24V ‘The voltage levels of a negative logic system must (a) necessarily be negative (6) be negative or positive (c) necessarily be positive (@) necessarily be 0 Vand -5V 256, The given figure shows a NAND gate with input waveforms A and B 255. The correct output waveform X of the gate is a258, 260. - 7 DicrraL ciRcums) 261. The Boolean expression for the shaded area) in the given Venn diagram is uy 2 (6) zero e (@) AB+BC+CA er X (@) Te - 4 : ° (6) ABC + ABC+ABC 3 The Boolean theorem AB + AC + BC () ABC+ABC + =AB+ A Ceorresponds to » (d) ABC +ABC 262. Match List - I with List - If and select # correct answer by using the codes give below the lists : (a) (44 B) (A +0) (B+O) 2144 B) (0) AB+AC+BC=AB+BC List -1 List - II F Re enon ay Cte (Logic family) (Characteristic AB+ AC+BC (A+B) (A +0) B40 ofthe lone ly (V4 B)-(K +0) (B+ 0) 2 AB+ AC family) |. The circuit shown in the figure is ae ee : consumption B. ECL 2 Highest packing density c. NMOS 8. Least power consumption D. Mos 4. Saturated logic Codes : a ae ABCD ) a subtractor (a) ©) parity generator ee ene d) comparator @14 32 a | | 4128 The output 'F? of the multiplexer circuit ae shown in the figure wild be The minimised logic circuit for the cireuit shown in figures 4 w AB () (d) ABC+ ABC +ABC + auca 269. AI msec pulse can be converted into a 10 ‘msec pulse by using (a) anastable multivibrator (6) amonostable multivibrator . (c) abistable multivibrator (@) aJ-K flip-flop ion for the given K- map ts (X: don’t care) 270. An input frequency of 12 kHz is applied to the J-K flip-flops arrangement shown in the AB given figure. The resulting output frequency cD\ 00011130 marie 00 1a oO 1[x 4 ufafa[x [x wa x [x (@) €B+BD+CD (a) 24 kHa (b) 12 KH () 6kHe, (@) 3 kHz () AB+CB +BC (@ CB +AC+BS 271, Athree-input NAND gate is to be used as an = = inverter. Which one of the following @ CB+ch+cB measures will achieve better results ? 265. In the figure shown X, X, Xq will be I’s (a) The two inputs not used are kept open complement of A, A, Ap if (8) The two inputs not used are connected to ground (0 level) ee — (c) The two inputs not used are connected to logic (1 level) eo x (d) None of these a 272, Which one of the following represents the pe aa coincidence logic ? (@ ¥=0 a ) “ (©) Y= Ko = Ay = Ap (d) Y=Ay=Ay= Ay 266. The microprocessor having refresh logic for dynamic memory is OF (a) 6502 ~ (6) INTEL 8085 (c) Motorola MC 6800 (d) 280 267. In hexadecimal system, 7716 - 3B16 is o equal to (a) 3D16 (b) 6016 (c) 3C16 (d) 7316 268. The register which keps track of the (ad) sequence of instruction execution is (a) memory address register (6) memory buffer register (c) stack pointer (@) program counter718 ~ The output of the gate circuit shown in the given figure is a) (A+ B)(C + D) (6) AB+CD fe) ABCD ) (ASBVICFD) 274. Which one of the following is the dual - form of the Boolean identity AB+ AC=(A+C)(A +B)? AB+ ACs AC+AB ) (A+B) +08 40) =(A+ OK +B) fe) (A+B)(A +) 5 AC + AB d) AB+ AC =AB+ AC+BC BD. The circuit shown in the given figure is a c) shift rogister (d) decade counter Match List - I with List - H and select the correct answer by using the codes given below the lists 276. List -1 List -11 A 45 1 10110100 B. 90 2 1101002 . 180 3. 01011010 D. 2 4 00101101 DIGITAL ciRcUTTS' Codes : ABCD @s 452 4312 43562 @3 421 “4 Atransistor is operated as anon - saturated ‘switch to eliminate (a) storage time (b) turn-off time (c) turn-on time (qd) delay time €7B In the circuit shown in the figure, if R, = R, =1k2, then the value of V, will be” (a) 4.559 8) 25V Fr fe Me ) 1V AL (d) zero 279. The output ¥ of the circuit showren figure is (a) (A+B)C+DE (@) AB+C(D+B) (@) (A+B)C+D+E (d) (AB +0). DE 280. TTL circuits with active pull-up are preferred because of their suitability for fa) wired - And Operation () bus operated system (c) wired logic operation (d) reasonable dissipation and speed of operation 281. Consider the following statements} regarding configurations of TTL devices : 1, The output impedance of totempole transistor is high. 2 Open collector output devices have low switching speed 3. Power consumption of Schottky devices is high j ‘Tri-state ouput devices have high switehi speed Of these statements statements are the correcThe Q output of a J-K FLIP-FLOP is‘. The ‘output does not change when a clock-pulse is applied. The inputs J and K will be respectively (where ‘x’ don’t care state) (@) Oandz (®) xand0 (©) Lando (@) Oand1 A 12-bit ADC is employed to convert an analog voltage of zéro to 10 volts. The resolution of the ADC is (a) 2.44 mV (0) 24.4 mV © 833mV @12v BR) ina 4: bit weighted -resietor D/A converter, the resistor value corresponding to LSB is 16 kQ. The resistor value corresponding to the MSB will be (a) 1kQ (6) 2kQ (ce) 4kQ (d) 16kQ 285. The intérface chip used for data transmission between 8086 and a 16-bit ADC is. (a) 8259 (6) 8255 (c) 8253 d) 8251 286. The circuit shown in the figure below 1 is equivalent to @ @ » 719 @y The Venn diagram representing the Boolean expression A+(A-B)is @ | | @ ® fo Ge) © @ nie Cp ee a fow many mintermséxeluding redundant terms) does the mjrtimal ewitching function flv, we, %, 92) =x + Fz originally have? (a) 16 () 20 (©) 4 (@) 32 289, While obtaining minimal eum of products expression, (a) all don’t cares are ignored (6) all don’t cares are treated as logic ones {c) all don’t cares are treated as logic zeros (d) only such don't cares that aid minimisation are treated as logic ones. 290. The complement of the Boolean expression AB «(BC+ AC) is @ (K+B)+@s OK +O @(A-B)+@BS+ aE) (©) (A+B)-B+ OK +T) @) (A+B). (B+ O(A+0) When two gates with open collector outputs are tied together as shown in the figure, the output obtained will be @ K+B+G+D & © Ke B+ G+ 5 = © (Ka BC+ D) goog, | (d) (A+B)(C+D) Oo—L 292. A full adder can be made out of (@) two half- adders (0) two half- adders and a NOT gate (c} two half- adders and an OR gate id) two half- adders and an AND gate @720 293. The cireuit shown in the figure is functionally equivalent to (b) OR gate (d) NAND gate (c) EX- OR gate 294, The schematic shown in the figure indicates (a) CMOS NOR gate () CMOS NAND gate (c) CMOS AND gate (d) CMOS transmission gate 295. Por the design of a sequential circuit having nine states MINIMUM number of memory elements required is w) 4 c) 5 9 296, A4-bit binary ripple counter uses flip-flops with a propagation delay time of 25 ns each. The maximum possible time required for change of state will be (a) 25 ns () 50n8 (©) Tn (d) 100 ns 97) The OP - AMP circuit shown in the figure is | Icoat = 0a | Ideal sive OPA >——_D+--_—}+-—0, Vie ) a sample/hold cireuit a rectifier/amplifier circuit (c) a peak detector circuit d) an antilog amplifier circuit 299, 300. 301. 302, DIGITAL CIRCUITS 298. The output X of the logic circuit shown in the given figure is (a) A+BC (e) AB () BC (@) AB+E Consider the Karnaugh map given below: co gi 10 of1T [s]e of [tele] erase | elo) ta wfafel ja} The function represented by this map can be simplified to the minimal form as (@) Hie +r, +4 % ® oy @ Hy Ba By 4 2y2qt mF FX pny Ep By +2, %y Hy Hy Ey + Hyp Ey xgeeyey yng +41 Fy Foy Ina digital system, there are three inputs ‘A, Band C. The output should be high when atleast two inputs are high. The Boolean expression for the output is (@) AB+BC+AC (6) ABC +ABC + ABC+ABC (©) ABC +ABC+ ABC (@) AB+BC+AC In digital circuit, Schottky transistors are’ preferred over normal transistors because of their (@) lower propagation delay (®) higher propagation delay (c) lower power dissipation (@) higher power dissipation Consider the following regarding ICs: 1, ECL has the least propagation delay 2, TTL has largest fanout. CMOS has the biggest noise margin. 4. TTL has the lowest power consumption. statements;DIGITAL cir are (a) () Vi IRCUITS land3 Sand4 voltage. Of these statements the correct statements () 2and4 (@) 1 and2 803. For a logic family Xpy = minimum output high leve voltage. Vo, = maximum output low level voltage. Vig = minimum acceptable input high level maximum acceptable input low level voltage. The correct relationship among these ie (@) Vir > Vor > Viz > Vou, (®) Vou> Vin > Vat > Vou, (©) Vin > Vo > Vou > Vi (@) Vou> Vin > Vou> Vi _,804. The input waveform V, and the output waveform V, of a Schmitt NAND are shown in the given figures. 24192 ou i The disty cycle of the output waveform will be 2a 2av| W oa Ye aa 02 (a) 100% (b) 85.5% (c) 72.2% (d) 25% 805. Match List - I with List - If and select the correct answer by using the codes given below the lists: ~ List -1 (Pin terminals) (Applications) A. SID, SOD 1. Wait state B. READY 2. Interrupt ©. TRAP 3. Serial date transfer D. ALE 4. Memory or VO read/write 5. Address latch control Codes: (@) A 3 3 ©) @ 4 4 B 1 1 3 3 Hwa wane 306. The software that transfers the object Program from secondary memory to the main memory is called (a) assember (©) linker (®) loader (d) task builder 807. The output voltage V, with respect to ground of the R-2R ladder network shown in the given figure is (iv we © 3V ®) 2V @av 308. The logic circuit realized by the circuit shown in the given figure will be Co () F=B0e (©) F=AOC BC @ F=Aaec 309. Match List -I (Citeuits) with List - II (Types of integration) and select the correct answer by using the codes given below the lists : List - 1 A. Fulladder B. Magnitude comparator C. Programmable 3. MSI logic array Codes: AB 3 2 3 1 c 1 List-11 ‘4, VLSI 2, SSI122 = 310. Load resistance R, between X and Y in the switch shown in the given figure cannot be replaced by ® te) (a) W 311. The voltage V, of the circuit in the given figure is av ) 31V (@) zero = M0, 1, 2, 3) represents GD The output of the circuit shown in the figure GB) The circuit shown below is 316. 317, DIGITAL CIRCUITS, will be Output (a) delayed pulses (®) square waves (c) triangular waves (d) trapezoidal waves Which one of the following is a correct set of specifications of one side of a 360 K floppy disc? Number Number Number Number of of of of tracks bitslinch sectore bytes! sector (a) 40 40009 512 ) 80 20001856 @ 60 3000 9 512 @ 4 1000 9 256 a a] fox ce a} — (a) 2:1 sealar (b) 4:1 scalar (c) up-down counter (d) none of these The difference between sequential and combinational cireuit is that 9 (a) combinational circuits store bits (®) combinational circuits have memory (c) sequential circuits store bits (d) sequential circuits have memory The product-of-sum expression for given truth table is j xX Y|zZ o oli o 110 tO bie ©) Kr ¥) (d) None of: s estTAL CIRCUITS I8. Which of the following number systems has f two O's ? F(a) Sign plus magnitude (6) 1's complement ; (c) 2's complement » (d) None of these 19. Which of the following flip-flop cannot be converted to D-type (delay) flip-flop ? F(a) S—R fp flop () J—K flip flop (©) Master slave flip-flop @ None of these 120. The characteristic of a flip-flop is (a) The flip-flop is a bistable device with only two stable states (b) The flip-flop has two output signals (c) The outputs are complement of each other. (@) Allof these S21, The expression for shaded area shown below is (@) ABs BC @) ABC+ABC (© ABC+ABC (d) None of these ‘822. Which of the following is a coincidence logic circuit ? 1 @ Ost, DS en (6) 7 @ > re 72 923. The circuit shown in the given figure realizes the function => . —_—P—_ oy ® (a) (A+B+C)(DB) (0) (A+(B+6)(DE) (©) (A+B+0)(DE) (d) (AFB +0)(DE) 324, If two numbers in excess-3 code are added and the result is less than 9, then to get equivalent binary (a) 0011 is subtracted (2) 0011 is added (c) 0110 is subtracted (d) 0110 is added . A7 bi Hemming code (Even parity checker) 0001001 for a BCD digit is known to have errors. The BOD encoded digit is @9 (®) 6 @ 8 @o 826. A is even or Bis true Negative of above statement will be (a) Ais odd or Bis false (b) Ais odd and Bis false (©) Ais even and Bis false (d) Ais even and Bis false 827. The basic memory cell of dynamic RAM consists of (a) a capacitance (8) a transistor (c) a flip-flop (@) a transistor acting as a capacitor 928. PROMs are used to store (a) bulk information (®) sequence information (c) information to be accessed rarely (d) relatively permanent information ey The number of NAND gates required for two dimensional addressing of 256 8 bit ROM using 8 to 1 selectors is (a) 16 (b) 32 (d) 104 @ the negative logic AND gate shoun in the siven figure in equivatent to. positive logic Py Bo____4 AND gate to) NAND gatwo 381. The minimum Boolean for the following cireuit is 7 co es ite | [es fe oe] Led si (a) AB+AC+BC (6) A+BC ©) AeB (@) AsB4C ‘The number of switéhing functions of 3 variables is (a) 8 (b) 64 / fe) 128, (d) 256 SY 888, When signed numbers are used in binary arithmetic, then which one of the following notation would have unique representation for zero? (a) sign - magnitude (b) 1’s complement (c) 2s complement (a) $'s complement . A carry lookahead adder is frequently used for « addition because it (a) is faster (6) is more accurate (c) used fewer gates (d) costs less 335. The logic cirewit given below converts a binary code ¥; 9 ¥5 into 1 Ye te | oer bX x3 (a) Excess - 3 code (©) BCD code (®) Gray code (d) Hamming code 226 What is dual of X+ X¥=X-¥? —————_________ . ne DIGITAL CIRCUITS 337, What is Boolean expression for a gating network that will have ouput 0 only, when LY¥=2LZ=1; X=0,¥=0,2=0; )Y=0,Z=0? (a) X¥Z+ XY¥Z+x¥zZ Be (0). (KY 2),4(X + ¥ +2) 4+K+ ¥ +2) we ©) (K+ ¥ +Z)+ K+ V+ D(X +Y4+D dy) XYZ+XvZ+ KZ x 2B) The number of Boolean functions which can be generated with four variables is (@4 @ 16 (c) 256 (@) 65,536 339, A Darlington pair is used for (a) low distortion (b) high frequency range (©) high power gain - @) high current gain 340, An ideal power supply.has (@) zero internal resistance (®) very large input resistance (c) very small output resistance (@) very large output resistance 341, Which one of the following can be used to change data from spatial code to temporal code ? (a) Shift registers (®) Counters (©) AD converters (d) Combinational circuits 842, If the memory chip size is 256 * 1 bits, then the number of chips required to make up 1k (1024) bytes of memory is (@) 32 “24 @ 12 @s 343. For a six bit ladder D/A converter which digital input of 101001, the analog value is| (assume 0 = 0 Vand 1 =+ 10 V) q (a) 0.423 (0) 0.552 (e) 0.641 (d) 0.923 S44, An n-bit ADC using Vp as reference Sreniation i anity of~ TAL CIRCUITS The D to A conversion technique is (a) Successive approximation (b) Weighted resistor technique (€) Dual slope technique H: (@) Single slope technique HG) A full-adder can be implemented ‘ith half. E adders AND OF gates. A 4-bit parallel full ‘adder without any initial carry requiree (c) Shalf-adders, 4-OR gates (@) Shalfadders, 3-OR gates "(© Thalf-adders, 4-OR gates (@) Thalf-adders, 3-OR gates ich one of the following will give the sum of full-adder as output ? (q) Three input majority circuit, (6) Three bit parity checker (©) Three bit comparator @ Three bit counter »! ey B48. Which one of the following is equivalent to AND - OR realization ? (q) NAND - NOR realization (&) NOR- NOR realization (©) NOR-NAND realization (@ NAND - NAND realization The greatest negative number which can be stored in computer that has 8-bit work length and uses 2's complement arithmetic is (a) ~ 256 (b) - 255 (© - 128 @ ~127 $850. A retriggerable monshot is one which (a) can be triggered only once (6) has two quasi-stable states (@) cannot be triggered until full pulse has been outputted (@) iscapable of being triggered while the output, isbeing generated‘ (851. A 4-line-to-I-line multiplexer shown in Fig (@) (the same as per IEEE convention is shown in Fig (b) is fed with three logic inputs A, B and C as shown. The output of the multiplexer will be es) +), , xe 0+ oa | Sit M4 Nee—| Lr cp} Fig. ca (@) ym (01,2. ©) Em (0, 3,5 © ») Ww" 352. The output fix, y) of the multiplexer shown in Fig (a) (the’ same IEEE convention is shown in Fig (b) resulting from the input logical values is 353, 354. Fig. (a) (a) an EXOR gate (&) a NOR gate (c) an AND gate (d) a NAND gate Fig.) Which of the following statements are correct ? 1. Aflip-flopis used to store 1-bit of information, 2. Race-around condition occurs in a J-K flip flop to store 2-bits of information 3. Meater-siave configuration is used in flip- flops to store 2-bits of information. 4, Atransparent latch consists of a D-type flip- flop. Select the correct answer using the codes given below : (@) 1,2and3 (®) 1,3and4 (©) 1,2and4 (@) 2,3and4 A divide-by.78 counter can be realized by using (a) 6 nos of mod-13 counters (b) 13 nos of mod-6 counters (©) one mod-13 counter followed by one mod-6 counters (d) 13 nos of mod-18 counters . In a sequential corced, the outputs at any instant of time depend (a) only on the inputs present at that instant of time (®) on past output as well as present inputs (c) only on the past inputs (a) only on the past outputs In a 4-bit weighted-resistor DIA converter, the resistor value corresponding to LSB is 32 hQ. The resistor value corresponding to MSB will be (a) 32kQ. wer 8kQ d ib) 16 Ke 4k 4 10-bit DIA converter provides an analog culput which has a maxinism value of 0.23 volts, The resolution és Ie mV + (6) mV 15 mV ai 25 1a7.26 7 359, The following switching functions are to be implemented using a decoder. f, = Sm, 2, 8, 10, 14) fy = 3m (2, 5, 9, 1) fy = 2m (2, 4, 5, 6, 7) The minimum configuration of the decoder should be (a) 2to-d line (b) 3+to-8 line (e) 40-16 line (d) 5-to-92 line 360. Flash ADC is (a) a serial ADC ) a parallel ADC (c) partiy serial and partly parallel (d) successive approximation ADC. 361. A bit synchronous counter uses flip-flops with propagation delay time of 15 ns each. The maximum possible time required for change of state will be (a) 15 ns (®) 80ns (o) 45 ns (a) 60ns . The block diagram shown in the given figure represents (a) modulo-3 ripple counter ) modulo-6 ripple counter (c) modulo-7 ripple counter synchronous counter () modulo: 363, If the input and signals of a block box are as given in the following figures, then the black box is alan DIGITAL ciRcUITS 4 364. A combinational circuit is one in which the 4 output depends on the (@) input combination at that time (0) input combination and the previous output. (c) input combination at that time and the, previous input combination ‘ (d) present outputand the previous output 365. The output (X) waveform’ for the given combination circuit for the inputs at A and B (waveform shown in the figure) will be @ tome Lome] [roms ®) Ssms_ Sm tS ~ 4s, 5 te Noms 10m 10mg sf sf |s I] fe) @ 3 3 tsms_lproL_tsens_fos|_5me 366, The open collector ofthe gates are connected together as shown in the given figure. The logic expresson for ¥ will beHAL CIRCUITS ae) hich one ofthe following circuits converts 370. The circuit shown in the given figure is ‘an RS Flip Flop to T Flip Flop ? A (a) an adder circuit (b) a subtractor cireuit (c) a comparator circuit (d) a parity generator circuit 871. The Boolean function represented by the following circuit is EHO a —| out (a) A[F+(B+0).(D-B)) (®) A[P+(B +0): DE] (©) A+(F. (BC +DE), @ A-([F.(B+0)+(D-B) the lists 368. Consider the following truth table : List List-11 A B Cc »D (Mernories) (Particular characteristic) o 0 o 4 ace GS A. StaticPL 1. Erasable nna memory programmable o 1 1 Oo B. CCD memory 2, Ultra high 10 0 42 speed I e 2 2 C. ECLmemory 3, Stores large . BOL men 8, Stores large 1 1 aso volume of date 1 1 1 0 D. GAL memory 4. Does not need The corresponding Boolean function ‘Fis refreshing (@) A+B+C (@) K+Bec 5. Non - volatile K OE Codes ABCD ’s complement of a given 3 or more bit © binary number of non-zero magnitude is same as the original number if all bits bya Bay except the (a) MSB are zeros (b) LSB are zeros (©) MSBare ones (d) LSB are ones128 S74, 376. . Given A 1, B= 1, Q,=0und P, = I. When the clock input (CK) fs applied, then ae LT ty Cpe (a 4420 0 ya coP el pfaaeeiereg OQ..:2bP ad peer \ncserran Vora sequential cireuit are (a) fh must have at least six gates, ui It must have some feedback. ley Us output should depend on some past value, lu!) Both (6) and (e) above. |. Which one of the circuits given below converts a JKFIF to a TFIF ? Coe =} o —e The sets of gates which are best suited for parity checking and parity generation are {a) AND, OR, NOT gates (b) X-OR-NOR gates (c) NAND gates (a) NOR gates The output of a logic gate is 1 when all its inputs are at logic 0. The gate is either (a) a NAND or an EX-OR (®) an OR or an EX-OR (©) an AND or an EX-OR \d) 2 NOR or an EX-NOR 378. S 380, 381. DIGITAL CIRCUITS The circuit shown in the given figure is a Rs whe yo voy Ly) ° Feet! BR Rs Va=(M(0)) (a) positive logic OR circuit (b) negative logic OR circuit (@) positive logic NAND circuit (d) negative logic NAND circuit The logic function performed by the cireuit given in the figure is X, X,: inputs Yq: output (a) Yo=-XX, (6) Yy= X +X (©) Yo= X,Xp @) Yo= X,-X i If the various logic families are in the ascending order of their fan- capabilities, the sequence will be (a) TTL, ECL, IIL, COMS (®) ECL, TTL, IIL, CMOS (¢) MIL, TTL, ECL, COMS (@) TTL, ECL, CMOS, ITL The circuit shown in the figure given is equivalent to ste aeBarra. cincurrs Ni: The simplified Boolean expression from the Karnaugh map given in the figure below is wet [e 8 ft @ AC+AD+anc () KB + AD + ABC () AC+ACD+ABD-BCD 1,@) AB + OD + AD — The logic circuit shown in the given figure can be minimized to a @ x pe o —D)— o =— ® , 84. Consider the Analog to Digital converters given below : = 1, Successive Approximation ADC 2. Dual Ramp ADC 3. Counter method ADC 4, Simultaneous ADC The correct sequence of the ascending order in terms of conversion times of these ADC's is (a) 3,2,4,1 © 23,1,4 (6) 2,3,4,1 4d) 3,2,1,4 885. A 4-bit D/A converter gives an output voltage 0f 4.5 V for an input code of 1001. The output voltage for an input code of 0110 is (a) 15V (b) 20 (©) 30V (@) 45 In successive-approximation A/D converter, offeet voltage equal to 4 LSB is added to the DiA converter’s output, to (a) improve the speed of operation (0) reduce the maximum quantization error (0) tneconsestiee! 887. Consider the following statements : 729 In order to inerease the bandwidth of tuned amplifiers, one can use . 1. tuned circuit with inductance having high Q factor. 2, double - tuned amplifier with two tuned circuits coupled by mutual inductance. . staggered tuned amplifiers in which different tuned circuits which are cascades are tuned to slightly different frequencies Of these statements, the correct statement(s) islare (a) Lonly (©) 2and3 (®) Land2 (d) 1,2and3 G65) Consider the following statements A differential amplifier is used at the input stage of an operational amplifier IL, Differential amplifiers have vory high CMRR Of these statements (a) both I and II are true and Il is the correct, explanation of I (®) both I and IT are true but IT is not the ONLY explanation of I (c) Tis true but Il is false (d) Tis false but IT is true 389. Which one of the foilowing logic function is implemented by the gates when their open collector type outputs are tied together as shown in the given figure ? 2—l>—_ (@) f2AB+C4D (b) f= AB +(G4D) (©) f= AB+(C+D) @ f= RBSCHD 390. The cireuit shown in the following figure realises the function soy PD )(A + B)C+ DE ) (A+ B)C+D+E (c) AB+C+DE (@) AB+C(D+E) po7.30 391. For the circuit shown in the yiven figure, the frequency of the output Q will be twice the input frequency half the input clock frequency .e as the input clock frequency .wof the propagation delay of the EF 397. The input pulses to the different stages of ihe counter shown in the following figure must be of ® 398. a) constant frequency and constant width 'b: constant frequency but variable width ) variable frequency but constant width dd) variabel frequency as well as variable width 393. State transition table and state transition diagrams from part of design steps is the case of ia) Combinational cireuits (®) Amplifier cireuits (c) Delay cireuits (d) Sequential circuits. |. A DIA converter has 5 V full scale output voltage and an accuracy of + 0.2 %. The maximum error for any output voltage will be (a) 510V. fe) 20mV) (b) 10 mV (a) 25 mV 895. The circuit of a gate in the resistor transistor logic (RTL) family shown in the given figure is alan’ AND gate NAND gate (®) OR gat (d) NOR gate |. Consider the following statements : 400. abl A rang counter consisting of five will have (a) 5 states (b) 10 states pigrraL c1ncurTs ‘The decoding error of the counter can bef avoided by (a) increasing propagation delay of Aip-flopy used in the counter using very fast logic gates le) using the strobe signal (@) reducing the propagation delay of fitpeflof unsed in the counter ‘The flag which is not used for branching in a microprocessor is (a) Carry flag (b) Auxiliary carry flag fe) Overflow flag (@) Parity flag Which one of the following can be used as} parallel to series converter ? (a) Decoder (b) Digital counter (c) Multiplexer (d) Demultiplexer A multiplexer 1, Selects one of the several inputs ang transmits it to a single output 7 2. Routes the data from a single input to one off many outputs 1 oe 3. Convets parallel data into serial data 4, Is a combinational cireuit (a) 1,2and 4 () 1,8and4 (®) 2,3and4 @) 1,2and3 Consider the following statements : 4 Race around condition occurs in a JK flip flop when both inputs are one. (d) infinite states} 32 states,Bi cincurs erystal oscillator is frequency used in ‘digital circuits for timing purpose because fof its (@) low cost E (8) high frequoney stability (©) simple circaity | (d) ability to set the frequency at the desired value BS. The output ¥ for the logic circuit shown in E the given figure is (a) AB () AB ) A+B (d) A+B |. The thermal run-away in a CE transistor amplifier can be prevented by biasing the transistor in such a manner that (@) Vop> “ec © Vop< ‘ec © Vog= “82 Gd) Vog=0 105. The figure of merit of a logic family is FP given by (@) gain «bandwidth + (®) propagation delay time = power dissipation (©) fan-out x propagation delay time (@) noise margin x power dissipation 16. The full-adder is defined by an adder circuit an adder circuit ~ (a) having two inputs used to add two binary digits. It produces their sum and carry as input, (®) havig three inputs used to add two binary digits plus a carry. It produces their sum and carry as outputs (©) used in the least significant position when adding two binary digits with no enrry-in to consider. It produces their sum and carry as outputs, (d) having two inputs and two outputs rat 407. The half-adder circuit in the given figure has inputs AB = 11. The logic level of P and Q outputs will be as (a) P=Oand ()-P=0and (c) P= land (@) P=1and 408. The circuit shown in the given figure eee (a) is an oscillating circuit and its output is a square wave (®) is one whose output ramains stable in "I state (¢) is one whose output ramains stable in “0 state (d) gives a single pulse of 3 times propagation delay 409. RAM *(@) is a non-volatile memory whereas ROM isa volatile memory. () is a'volatile memory whereas ROM is non: volatile memory. (©) and ROM are volatile memories but in ROM data is not lost when power is switched off. (d) and ROM are non-volatile memories but in RAM data is lost when power is switched off. GB Dtatch List - I (Memory elements) with Li ist - II (Properties) and select the correct answer using the codes given below the lists : List -1 A.Somiconductor 1, B. Ferrite core 2 memory C. Magnetic tape memory Codes : List - 1 Destructive read out Combinational logic Volatile rewegau. 412, au, Ey complement of (2BED jag i8 (a) E304 (@) D403 te) D402 (@) 6.403 The number of digit I present in the binary representation of Bx DID 47x64 45 x84 98 (a) 8 : 9 fe) 10 ww In an assembler, which one of the following is required for variable numes in symbol table ? ta) Addresses (b) Values isters (d) Storage Which one of the following is equivalent to the Boolean expression AB + BC + CA? (a) AB+BC+CA (6) ¢ () BB+ B+O+ Gra) (@) (A+B) B¥O) (C+A) . Given Boolean theorem AB + AC +BC= AB + AC. Which one of the following identities is true? (a) (A+B) (B +0) (B+C)=(A+B)- (A +0) b) AB+ KC+BC#AB+BC () AB+ AC+BC =(A+B)-(A +C). (B40) ) (A+B)-(K +0) (B40) #AB+ AC ) AND gate [c) NAND gate 416, 8 418, 419. DIGITAL CIRCUITS ‘The transistor in the circuit of the given figure is operating (a) in the cut-off region (6) in the active region {c) in the saturation region (d) either in the active or the saturation region Which of the following regions of operation mainly responsible for heating of the, transistor under switching operation ? 1. Saturation region. 2 Cut - off region. 3. Transition from saturation to cut- off. 4, Transition from cut - off to saturation. Select the correct answer using the codes, given below: (a) Land (©) 8and4 () 2ands (d) Land 4 The operation x ®} represents (@) x-y 0) B+ © a+ @) 3-5 The term AB + AC + BG reduce to (a) AB+CA. () AC+BC () AC+BC @) AB+ BC The control logic for a binary multiplier i specified by a state diagram. The staf diagram has four states and two inputs, implement it by the sequence register decoder method. (a) two flip-flops and 2 « 4 decoders are ne (®) four flip-flops and 2 x 4 decoders are ne (c) two flip-flops and 8 x 9 decoders are ne (q) four flip-flops and 3 * 9 decoders are nee1.(6) 11.(6) 21.(a) 31.(6) 41.(@) 51.(6) 61. (6) 71. (¢) 81. (c) 91.(c) 101. (a) F111. (6) 121. (d) 131. (c) 141. (c) 161. (d) 161. (a) 171. (c) 181. (d) 191. (c) 201. (d) 211. (0) 221. (d) 281.(d) 241. (d) 251.0), 261. (a) 271. (0) 2a) 12. (c) 2256) 82, (6) 42.(6) 52. (a) 62.(6) 72.(d) 82.(a) 92, (a) 102. (d) 112. (6) 122. (c) 192. (d) 142. (c) 152, (b) 162. (c) 172. (6) 182.(d) 192. (0) 202. (a) 212. (a) 222. (a) 232. (c) 242.(d) 252. (b) 262. (c) 272. (b) 3.(a) 18. (¢) 23. (c) 38. (6) 48. (d) 53. (6) 63. (a) 78.(c) 83. (6) 93. (6) 108. (d) 1138. (¢) 123. (d) 133. (c) 143. (d) 153. (c) “163, (6) 173. (b) 183. (6) 193. (b) 208. (6) 213. (b) 223. (d) 283. (c) 243. (6) 253, (d) 263. (b) 273. (6) 4.(b) 14. (6) 24,(a) 34. (a) 44.(c) 54.(a) 64. (6) 74.(a) 84. (c) 94. (c) 104. (a) 114. (a) 124. (c) 134. (6) 144, (c) 154. (d) 164. (6) 174. (0) 184.(6) 194. (6) 204.) 214. (c) 224. (¢) 234. (a) 244.(d) 254. (a) 264. (d) 274,‘ 25. (a) 385. (b) 45. (a) 5B.(c) 65. (c) 75. (b) 85.(d) 96. (a) 105. (c) 115. (a) 125. (d) 136. (6) 145. (c) 158. (c) 166. (4) 175. (a) 185. (c) 195. (a) 205, (d) 215. (0) 225, (b) 238. (d) 245. (b) 255. (6) 265. (6) 275, 16. (a) 26.(d) 36. (a) 46. (b) 56. (c) 66. (a) 76. (c) 86. (c) 96. (a) 106. (c) 116. (a) 126.(d) 136. (a) 146, ) 156. (a) 166. (a) 176. (d) 186.(¢) 196. (d) 206. (a) 216. (a) 226. (a) 236. (d) 246. (c) 256. (c) 266. (d) Ta) 17. (a) 27.(e) a7. (0) 47.(@) 57. (6) 67. (b) Te) 87.(a) 97.(0) 107. (6) 117. (6) 127. (a) 137. (e) 147.(d) 157. (d) 167. (c) 177. (c) 187. (6) 197, (b) 207. (a) 217.(a) 227. (e) 287.(a) 247.(d) 257. (b) 267. (c) 18.(6) 19.(6) 28.(d) 29. (c) 88.(d) 39.6) 48.(0) 49.(0) 58d) 59.06) 68.(2) 69.12) 78.(c) 79.(b) 88.(b) 89. 98.(d) 99. (a) 108.(a) 109. (d) 118.() 119, (a) 128.(b) 129,(a) 138. (a) 139.) 148.(4) 149. (c) 158. (5) 159. (b) 168.(d) 169, (c) 178,(6) 179,(a) 188.(a) 189.(¢) 198.(d) 199, 208.(a) 209. (i) 218.(6) 219.(b) 228.(d) 229.c) 238.(c) 299. (b) 248.(c) 249. (a 258. (2) 259. id 268. (d) 10. (a) 20. (6) 30. (b) 40. (a) 50. (cd) 60. (b) 70. (0) 80. (6) 90. (a) 100. (6) 110, (a) 120. (6) 130. (6) 140. (d) 150. (c 160. (a 170. (6) 180. (6) 190. (@) 200. (61 210, 220, (a) 230.(a) 240. 250. (d) 260. (d) 270.1) 0,288. (a) 303. (b) 813. (b) 823.(d) 333. (0) 343, (b) 361.(b) 352.(e) 353. (c) 361. (a) 362(c) 363. (a 378, (a) 383. (d) BOL) B92 4d) BOB. Cd) 401.(a) 402.(5) 4083.16) AIL fe) 412.0) 418. (€) 284.(0) 294, (4) 804. (c} 314. (0) 824. (c) 334, (a) 344. (a) 364. ( 874, id, 984. (¢) 394. (b) 404. (6) 414.(0) 285. (6) 295. (6) 305. (6) 315.(b) 825. (a) 885. (6) 345.(b) 355. (6) 365. (c) 985. (c) 395. (8) 405. (6) 415.(0) 286, 296.(d) 306. (5) 316.(d) 826. (6) 336.() 346. (6) 356. (d) 366. (a) 376, (6) 886. (d) 896. (a) 406. (b) 416. (0) 307.(a) 317.40) 327.(d) 387. (0) 347.(a) 57. (d) 367. (6) 377.(d) 387, (c) 397. (6) 407. (6) 417.(d) 288. (c) 298. (c) 308. (c) 318. (b) 328. (d) 338. (b) 348. (d) 358. (a) 368. (d) 378. 388. (a) 398. (c) 408. (a) 418.(c) DigiTaL cincurTS: 289. (cd) 299. (c) 809. (6) 319.(d) 829. (b) 839.(d) 849. (c) 859. (c) 369. (a) 389, 399. (c) 409. (6) 419.(c) 290. (a) 800. (6) 310. (d) 320. (d) 3380. (d) 340. (a) 350. (d) 360. (6) 370. (c) 3880. (0) 390. (a) 400. (a) 410. (a) 420. (a)