8-3-1 Interrupt System Based on a Single 82594 _— ee The 8259A is contained in a 28-pin dual-in-line package that requies only a+ supply voltage. Its organization is show! along with its connections supply voltag: toa maximum mode system. Its pins (other than the supply voltage and ground pins) are defined as follows: D7-D0—For r_ communicating with the CPU over the data bus. ( On a few systems bus drivers may be needed, but on other systems direct connections can be used INT—To s¢hd interrupt request signals to-the-CPU. INTA—To ri receive interrupt acknowledge signals from the CPU. The 82594. assumes that ait acknowledgment consists of two negative pulsessThus making it compatible with 8086/8088 systems. ‘D—To oLIRR desister ora priority level on the data bus is place 20 n the bus depends on the state of the &259A and is di Scanned wth CamScannera 390 System Bus Structure Ona i | : Poe an acala] [Sere Pore [eee] | rN ro >. CSE Geo Figure 8:17 Organization ofthe 82594 programmable intecrupt conte. _ | eave SiR To signa the $259 that it isto accept data from the data hes the data to set the bits in the command wordS)How the received distributed is discussed later. sant) | SFor indicating that the 8259A is being accessed )TS pit 8 Se | Wo the address bys through the decoder lop compares the NBN, ' bits ofthe adres ofthe #259A with the gress currently 0” bus. Input to this pin can be combined with Sd 4o give the TeAdY ME ot € A0—For indicating which port of the 8259A is being accessed) ™ ‘must be reserved in the 1/O address space for cach 8259 | | | ; | stem Tf the \ ‘Scanned wih ComScanner‘ec.63_Interupt Priory Management 331 OF ecg iteap equss rom UO interac referred to as saves, her 259A CASD-—To ent «pata slave devi) Theis untons con SPIER For one of two purposes ihe a an input © deeemine wheter, The R2S9A isto be a master (SPIEN = 1) or asa slave (SPIEN = 0) arn an output toisable the data bus transceivers when data are being eatery from the $259A to the CPU. Whether the SPIEN pin is used as an input or output depends on the buffer mode discussed below. ) Foran 8085 the two adresses associted with an 82598 are normally eons seat, andthe Aline i conneied tothe AO pin, but becuse thee are Soy Eiht data pins om the 82S9A and the 886 always inputs the interop pointe ha the lover 8 bits of its I6bit data bus, all data anfers fo and fave he Son must be made over the lower byte ofthe bus. The east way to goats the a wansfers wil use the lover hal of the buss to connect the Al fae we AO ead ise tho consecutive even adresses, withthe fst Beng dibe by f, Hones to simplify the following discussion, the second ares wl be refened foe he od ares for both cases ‘The contol portion ofthe 82594 contains several programmable bis tha canbe viewed as being contained in seven f-bit registers, These egoters ee cna iat two groups, with one group containing the nation sonmacd sont Ne) tnd the otber group contains the operation command words (OCW. ie we, faizaon command word are normally se by an iaitaieton outing when he computer sytem first brought up and remain constant thoughout ie opeeon By contrast, the operation command words ate used to dynamically contel the Procsing of itezups Create ands asec making lop) piony esoher nd ISR pe tc ching aod Gomratng he sree eee ine IRR Tatches the incoming requests and, m Soajjicion priority resoher, allows unmasked requests with sufficient Priory 0 put a 1 on the INT pin. The Bory rescuer loi determines te pitts othe requests nthe ad 'BRisfor holding the request curently being procecey glee bitin the IRR ict to it's eompared with he coresponding mask bitin he IMR. the mas biti, the request pase on to he lore ea tf iti 1, the request blocked: When an iteruptrearen& toe oe he gly fe8olver its priority is examined and, if according to the current state of oti esolver he interrapt is tobe sen othe CPU. the INT tne kee (Assuming that the IF flag in the CPU is 1, the CPU will enter its interrupt Seavence ate $a the completion ofthe current instruction and return two negative pulses te ENTA line) Upon the arrival ofthe firs pulse the IRR latches are d Mainsines ERR Will ignore further signals on the IR7-IRO lines Wi can UMtil the end of the seeond INTA pulse, Also, t eared rt’ SPP Fopriate ISR bit to be set and the corresponding IRR bit to be "Sth The second INTA pulse eauses the current contents of ICW2 to be placed ‘Scanned wih ComScanner332 yt Bus Stee ' on D7-DO, and the CPU uses this byte asthe interTups PE 1 te automa g Gr iterrpe (EON) bit in ICWA i 1, atthe ond OF second INTA pike. TSR bit that was set by the first INTA pulse is Oo ; otherwise, the ISR hy EOI) command is sent to Oc)" not cleared until the proper end of interrupt ( cot ords ae normal ae et nation coma al Asn aes th nt ey on and contain. hc an initializing routine when the system i 07 rte held constant throughout the systems operation. i f2s94 has an eves tate a ae A it andthe ina a (OO abe omen C7 aR et ation coy aie forthe emaning TCWS 1 Jriitons of the bits in ICWL are (pits 7-S—-Not used in an 503618088 system. only in an 8080 or BIBS sien a 1 ies te etd bein COD opal Ba 4 Avagenich abo use te oven adress (AO = OF oo aetermanes wheter ie cage trigered mode (TIM * Oar a en eoue (LIM ~ 1) tobe ised The edge raced the levee ype ised when the covesponding ISR ae ey Not sein an S808 system, only in an BOBO o TS ssen ae a ctndiates whether of not the &259A is cascaded wi te a See gen only one S259A fs inthe interrupt system oer cays set to 1 if an ICW4 sto be output to during the iiiatin are ot an R688 system this bit mast aways be set (01 beams Bit in [CWS must beset to 1) pin 7-3 of ICW2 are hed from bits 7-3 of the second byte output by the Ct aa the initialization of the 8259A, and bits 2-0 are set according 1 the vt crit MGctupt request, e-.. fequest on TR6 would cause them to be se 01M TCWS is significant only in systems including more than one 8259A and is uh wont SNGL = 0 This cat i cussed in Set. $3 TCW4 is output 0 LACE CCW) i to: oer, the contents of 1CW4 is cleared. The bis i# (Bits 7-5—always set to 0. Bi SMI ef the pecially nated mode used. This mole ad in stems having more than one 82394 and is seus ew | BQ@UP BUF = indicates thatthe SPEN is to be used as an out | Saheb the sytem’ 4286 ansesvers while the CPU input from 2 toate eae a a Suan baat ings ual ony one 82594, should be ape tothe SPN Di. SoA MaE is LS ianored if BUF = 0. Fora system having forthe ab bit should be Is otherwise, it should be I for the mate Bie 1 AOD ABO! = eared at the 1. then the ISR e the ond ie aa gethe ISR Dit that caused the in he second INTA pulse ‘Scanned wih ComScannerre sees tenet Pot ent - Bit 0 (HPM)—HPM = 1 indicates the 259A is in an 8086/8088 syste | ae eeria orsnSeyten) 8 SSR Ti ‘A typical program sequence for setting the contents of the ICWs, whic asumes thatthe even address of the 8259A is 0080, is fs, whieh, MOV ALtoH OUT soHLAL MOV ALTON our otitaL Mov ALDH our tiAL “The fist two instructions cause the requests to be edge triggered, denote that only one §259A is used, and inform the 8259A that an ICW4 will be output. The next two instructions cause the 5 most significant bits of the interrupt type to be set 10 (0011, ICW3 is not output to because SNGL = 1; therefore, the last two instruc- tions set ICW4 to OD, which informs the 8259A that the special fully nested mode isnot to be used, the SP/EN is used to disable transceivers, the 8259A is a master, EOI commands must be used to clear the ISR bit, and the 8259A is part of an 80868088 system. ‘There are three OCWs. The command word OCWI is used for masking interrupt requests; when the mask bit corresponding to an interrupt request is 1 then the request is blocked, OCW2 and OCW3 are for controlling the mode of the 8259A and receiving EOI commands. A byte is output to OCWI by using the ‘odd address associated with the 8259 and bytes are output to OCW2 and OCWS by using the even addresses, OCW? is distinguished from OCW3 by the contents of bit 3 of the data byte. If bit 3 is 0. the byte is put in OCW2, and it itis 1, itis put in OCW3. Both OCW2 and OCW3 are distinguished from ICW1. which also uses the even address, by the contents of bit 4 of the data. If bit + is 0, then the byte is put on OCW2 or OCW3 according to bit 3. There is no ambiguity in ICW2. ICW3, ICW4, and OCWI all using the odd address because the initialization words must always follow ICW1 as dictated by the initialization sequence, and an output to OCW! cannot occur in the middle of this sequence. Referring back to Fig. 8-17, bits L2-LU of OCW? are for designating an 1 level, bit 5 is for giving EOI commands, and bits 6 and 7 are for controlling the JR levels. Recall that when the AEOI bit in ICW4 is 1, the ISR bit, whi by the interrupt request, is reset automatically at the end of the second pulse, but if AEO! = 0, then the ISR bit must be explicitly cleared by an EOL ‘command, which consists of sending an OCW2 with bit 5 equal to 1, When an EOL command is given the meanings of the four possible combinations of bit 7, the R (rotate) bit, and bit 6, the SL. (set level) bit, are’ Ast 0 0 ra ply od © 1 Shpoctcalyctoars tho IS tt cated by LL, $0 Rata roy eo tata devi ater bing sored nas th lowest pay ot ry un position ypc by L2-LO's west ‘Scanned wih CamScanner934 System Bus Structure Chang ‘The bits in OCW? are only temporarily retained ty pee ina the actions specified by them are carried out. This statement i POTTS Important yi regard to the EOI bit. Let us now extn, these po steater deh ing with the normal priority mode (0). bepinning with the normal Pee the gest pity. one an TRI sth RO ns fist INTA pulse arrives the priority resoha bigest pro a8 eTS Gronty toe ke allows only the unmasked reques! Oe naainae cast significant bits of ICW2. wl cro Because the 3 least signiticrry sinter address. are determined by which 1sR Peer determines the IIE eee tech ISR bith bi is set, the adress of the inter ca with the device connected tothe highs, priority TR pins begun first and eee if ISRn is set, the priority resolver wil n ‘Under the normal priority mode ee i tthe pry reser w ia recoaize amy requests om IRI TYG oquent, ifthe IF flag in the CPU hs Tegues om R chity than the one being processed may Cee a requeats having higher priority than te one PSE Pe reer tne current interrupt routine to be interrupted WH Tae sing cates ane Hep wating, The Yower-pronity requests a Bracers SS Prt priorities as the higher-priorty ISR bits are cleare : ort ally cleared at the end of the second bit corresponding to an interrupt is automatically atthe end of hese FAT pole, When AEOL = 0 the ISR must be cleared by the interup setting bit $ of OCW2. by setting Ste ofthe normal priority mode, suppose that initially AEOI ; and all ISR and IMR bits are clear. Also suppose that, as shown in FE qeguests cccur simultaneously on IR2 and IR4, then a request arrives Heo fasta request arrives at TR3, and that these are the only requests. Firsts Sr be set and the interrupt routine associated with IR2 will start executing: ¢© routine resets the IF flag to 1 and when the IR1 request is made, ISR1 Wl fi, hand the IRI routine will be executed in its entirety. While it is executing "OT eset the IF bit to 1 and send the necessary command to clear ISI. Pr", return 10 the IR2 routine, ISR2 is cleared. Then ISR4 is set and its TOUT, ‘begun. While this routine is executing IR3 is made. It is acknowledged 2554p IF is reset to 1, and ISR3 is set. Then the 1R3 routine is initiated. BefOre ge routine is completed it should clear ISR3 and set IF, The return is made | IRS routine, which should clear ISR4 before returning to the IR2 rou R2 routine, having already cleared the ISR2 bit, would simply TET ine interrupted program. (Note tha if IF is not reset to 1 within the inteFTUP" 0" ne further interrupts will not be processed until the routine is completed: 'S" IRET instruction is encountered.) Although a 1 sent to bis urn 10 0 f OCW2 normally caus re bghesep bit Gs the ls ISR it toe set) to be eared any ISR bie Pik re by sending an OCM2 with he Be Scand EO bit se 1 OL ‘Scanned wih ComScanner« ¢ i 4 y 4 4 4 4 ee. 03 Inter Prorty Management a8 aad 182 routine 183 aves 183 routine sro ed en) ‘saa ee tee net_D nay Liner Figure 818 Actions taken inthe normat ‘operating mode when a typical sequence of intr- ‘aps occurs, the number of the bit to be cleared in L2-LO. If ortooors is sent to OCW2, then ISR3 will be cleared, In addition to the normal priority mode discussed above, OCW2 the priority by assigning bottom priority to any one of the IR levels, I the other priorities will follow as if the normal ordering had been ‘nstance, if the lowest priority is given to IR4, then the order of priori IRS, IR6, 1R7, IRO, IR1, 1R2, IR3, IRS Ge~ IRS is rotated into the top-priority position). A rotation by one can be Qbisined by letting the combination for the R and SL. bits be 10. I the R sad St, Bi combination is 11 then the IR level with the lowest priority is the one spoctied byL210- IF IRS currently has top priority and can rotate In this case tated. For ties will be: To100000 ‘sent to OCW2, then the new priority ordering would be JRG, IR7, ARO, IRL, 1R2, TRI, IRA, IRS but if yiteoore ‘Scanned wih CamScanner336 is sent, the new ordering woul! 1R3, ‘The R and SL bits R= Land SL = Oeause anton tums off this action so that wand EOL = 0 result im the | TOL command being sent: TET ‘no action. sent to O requests are Pr the priority order ESMM ~ Land S} ccan be made. If SMM bit will have n0 & “The P (polling) assumes that the CPU is not aee¥ aeiprerrapt requests in the TR Signal would cause the apPFOpriah had been receive form ignored. M = 0. pra, IRS, TRO. als suromati jowest priori in ye ESMM (enabl Tm CWS the ESM TE the prionty me a switch back 10 the PAO? h the ESMM bit equ fect and the special mas ‘itis used t0 place the 82: Md, and would return to the Al eE_ ene be 0, TRI, RZ FOI = 0. In th fo nave signi is case rotations when = f,andR = SL=9 atin donot tke pee «AL» etn designated ty 12 without being ation, R = Oand SL = I.citses mic maining mode) and SMM (special mak Jos discussed above. I a bytes eto 1, then unmasked interrupt processor's IF it is 1) and Pipyte to OCW in which ity ordering of interrupts Je special mask ‘and SMM are se! ided that the wr te 0 is sent to OCW3. then the sk mode will not change. 359A in polling mode. This mode (UF = 0) and it is necessary fx bit is 1 the next RD ist as if INTA signal byte of the ro be polled. When the P fe bit in the ISR to be set jus LL register in the CPU where 1 = 1 indicates that an interrupt is P IR level of the highest-priority int dering is TR3, IR4. IRS, there are unmasked interrupts on (where 0080 is the even ai (where 0080 is the even address of the 8259A) is executed, then Wi, and Wo give terrupt. For example. 1. the priority °F TRG, IR7. IRO, IRI, TR2 TR4 and IRA, and the instruction IN ALSOH hen P he conter " teenth e , oF ontents of IRR or ISR can be read into the aves ‘Hat the time th mureanie ne the IN instruction is ¢9 s 259A, ep. for the wud He caval ya be read 05 G10 oa stconlgmea esas would ing © NA , H the contents of IMR to AL ™ ‘Scanned wih CamScannerer eee se » Asa final note regarding the internal workings of the 8259A, let us examine 83-2 Interrupt System Based on Multiple 8259As ‘A multiple 8259A interrupt system i diagrammed in Fig. 819. In this figure data busdrivers are not shown, bu they could be inserted as shown in Fig. 89. Although the SPIEN pin on the master 8259A is connected tothe data bus transceivers (a0 is applied to the SP/EN pins of the slaves. Only one slave is shown, but up to seven ‘more slaves could be similarly connected into the system permitting up to 64 dist interrupt request lines. When designing the address decodes Jose, exch 8259 must be given its own address pai inthe UO address space. he diversi in the CAS2-CASO lines may oF may not be needed, depending on the prox of the aster to the slave {ny multiple 82594 system the slaves must be inialzed as well asthe mi ‘The master would be intaized in the same way a5 indicated above except SNGL would be set t0 0 and ICW3 would need to be filed. A 1 would be put ach ICW3 bit for which the corresponding TR bit is connected t0 a slave sad ‘ould be put in the remaining bits, The SENM bit may he act tol to aeuvane ‘pecial fully nested mode. The SNGL bit should also he st to O when iit the slaves, Thus, an ICWS wil be roquited foreach slave, but fora soe ‘asa diferent meaning. Fora slave, ICWS has the forn © [ele] o [we] wi] wo IMhete the 3 least significant bits provide the slave with anid [The identification number given to the skive should be the san the master request line to which its INT pin is counected, When a slave puts 1 om its INT pin this signal is sent t0 the appropriate TR Pin on the master. Assuming that the IMR and puioity vesolver do met block this Signal, i is to the CPU through the INT pin on t ster, Whew the CPU ‘elurns the INTA signal the master will H only set the appropriate ISK bit and ‘Scanned wih ComScanner-_ sgec.-4 Bus Standards Beal clear the corresponding IRR bit, it will also check the corresponding bit in ICW3 fo determine whether or not the interrupt came from a slave. If so, the master will place the number of the IR level on the CAS2-CASO lines if not it will put the Prptents of ICW2 on the data bus and no signals will be applied to the CAS2— CASO lines. The INTA signal is also received by all of the slaves, but only that Slave whose ID matches the number sent to it by the master over the CAS2-CASO Iines will accept the signal. In the selected slave the appropriate ISR bit will be fet, the corresponding IRR bit will be cleared, and its ICW2 will be put on the Gata bus. Because ICW2 contains the interrupt type, it is important that unique ‘combinations be put in the master and slave ICW2s during the initialization process. EOI commands are required for both the master and the slave if their AEOI bits are 0 Except for the response to the INTA signal discussed above, the actions taken by all 8259 devices in the system are the same. Also, their modes are controlled and their registers are read in the same way. There is one exception, however. If the SFNM bit in the ICW4 of the master is initialized to 1, the master will enter the special fully nested mode. This mode is ordinarily used with the normal priority mode and AEOI = 0. In this case, the master will allow unmasked requests of sufficient priority to be passed on to the INT pin even if the corresponding ISR bitis already 1. This means that if @ higher-priority request arrives at a slave while one or more of the slave's requests is being processed, the new request will be allowed to send its INT signal through the master. When using the special fully nested mode, two EOI commands may need to be sent by the'interrupt routine. First, a nonspecific EOI command would be sent to the slave that caused the interrupt and then the slave's ISR would be tested. If and only if the ISR contains all Os would a nonspecific EOI command be sent to the master. Therefore, assuming that slave 1 is connected to IR1 and slave 2 is connected to IR2 of a master, they are the only slaves, and the highest priority in all three 8259As is assigned to IRO, the fully nested order of priorities would be: Highest priority Master: IRO Slave 1: IRO, IRL, IR2, IR3, IR4, IRS, IR6, 1R7 Slave 2: IRO, IRI, 1R2, 1R3, TR4, IRS, IR6, 1R7 Master: 13, IR4, IRS, IR6, 1R7 Lowest priority 1, be used to block out some of ‘The masks in the master and slaves may, of cours the requests. > Scanned wth CamScanner