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58448-Article Text-103943-1-10-20100825 PDF
58448-Article Text-103943-1-10-20100825 PDF
ABSTRACT
Five (5) kVA power inverter was designed and simulated base on two topologies; Boost converter
and Half-bridge inverter topology. A 555 timer IC was used as the control at fixed frequencies of 25
kHz and 50 Hz for the two stages. The results of the simulation were obtained. The graphs for both
stages were plotted and the results show a significant increase in the voltage and duty cycle. The
wave form of the output gives a square wave form.
Keywords: Power inverter, Simulation, Topology, Converter
Vi
PWM &
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Bajopas Vol. 2 Number 1 June, 2009
The output to the input voltage gain of the inverter is given by (Simon and Oliva, 2005).
2.0
and 2.1
2.2
2.3 a
or 2.3 b
However, with 555-timer IC’s an inexpensive regulated SMPS is constructed, feedback and pulse width
modulation were shown in Figure 2.0. If the desired inverter frequency and the voltage are known, the power
consumed by the switching on and off of the converter can be estimated by the following equation
(http://supertex.com/pdf/app.note/AN-36.pdf, 2008).
2.4
7 ZFB
D
L 3
RFB
1 VCC 4 Vout
RST OUT
2
RC
DIS Qsw
6
Battery 5 THR
Selection of a converter frequency is very important, losses. Conversely, lower frequencies can reduce
since many applications require certain frequencies for switching losses but require large inductors. Converter
EMI reasons. Higher switching frequencies allow the in the range of 20 kHz-100 kHz are generally suitable.
use of smaller inductors but lead to high switching Duty cycle is calculated as follows.
2.6
The equation above yield duty cycles greater than 100%. For the inductor rating, peak inductor current can be
approximated using the following equation
2.7
Select Qsw and D voltage, peak repetitive current, and average forward
For switching transistor Qsw, the most important current and reverse recovery time. Since peak inductor
parameters are break down voltage, on resistance, current also flows through the switch and the diode, it
peak current, and power dissipation. For the diode, may be used to rate these components as well.
the important parameters are reverse break down
2.8
Maximum average current will occur at minimum input voltage
2.9
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Bajopas Vol. 2 Number 1 June, 2009
Average power dissipation in the switch can be estimated from the following equation.
3.0
Where
Output capacitance Cout stores high voltage energy must largely dependent on the desired ripple voltage
and also reduces EMI by restricting high frequency on Vout. Generally, ripple (as a fraction of output
current paths to stop short loops. The value of Cout voltage) of about 10% is adequate.
3.2
types
Select Timing Components , The ratio sets the maximum possible duty
Timing components , determine cycle, while , together determine
nominal converter frequency and maximum duty cycle. nominal output frequency. Maximum duty cycle can
Selection of these components is an iterative process. also be calculated using the following equation.
3.3
The ratio must be greater than for proper operation of the 555 timer. If less, timing capacitor
voltage will be unable to discharge to and output of the 555 will remain low. Nominal converter
frequency can be calculated using the following equation.
3.4
3.7
and
If is too low, it will prevent timing capacitor voltage from rising to as required for nominal
operation of the 555, resulting in switch staying on and the current rising to destructive levels. To prevent
this from occurring, the ratio of must always be greater than two.
3.8
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Bajopas Vol. 2 Number 1 June, 2009
is turned off to close before the other switch, to start
Power Inverter stage design conducting. The advantage of H-bridge inverter
However, in this part H-bridge inverter topology was topology has lower number of switches and simple
adopted. The half bridge inverter in the simplest form control (Emadi and Stoyan, 1992). The differential
is shown is Figure 3.0 H-bridge inverter topology has equation for the current from t =0 to t =T 2
lower number of switches and simple
control.(http://Guru/PEInverter/Half- governing the current and voltage flows of half-bridge
bridge/pdf/inv.pdf, 2006). The duration of the dead inverter may be written as
band should be large enough to allow the switch that
di(t )
L + Ri(t ) = Vs 3.9
dt
Its general solution is of the form
Vs
i (t ) = + Ae − t τ 4.0
R
L
Where τ , the time constant for R-L load, is τ = , Applying the initial condition, that is
R
i(0) = I min = −I max when t = 0 , we get A = − Vs − I max .
R
Hence, the expression for the current in the circuit during t = 0 and t = T 2 is
i (t ) =
Vs
R
( )
1 − e −t τ − I max e −t τ 4.1
The current attains its maximum value at t = T 2 and is obtained from (4.1) as
I max =
Vs
R
(
1 − e −T 2τ
)− I max e − T 2τ
Rearranging the term we get
2τ
Vs ⎛ 1 − e −T ⎞
I max = ⎜⎜ −T 2τ
⎟⎟ 4.2
R ⎝1 + e ⎠
Hence the current in the circuit during t = 0 and t = T 2 is
− T 2τ
V ⎛1 − e ⎞ −t τ
i (t ) =
Vs
( )
1 − e − t τ − s ⎜⎜
R ⎝ 1 + e −T 2τ
⎟⎟ e 4.3
R ⎠
Figure 3.0 (i) Half-bridge inverter with dual supply, and (ii) single supply
MATERIALS AND METHODS the above equations. The design topology which was
Two methods were employed for the inverter designed adopted is shown in Fig.4 with two stages; boost
and simulation; the computer simulation with NI converter and half-bridge inverter, and their controls.
Multisim 10. Software and the circuit analysis using
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Bajopas Vol. 2 Number 1 June, 2009
1st Stage 2nd Stage
Control Control
(555-timer IC) (555-timer IC)
Feedbac
Figure 4.0 DC-AC Inverter circuit design
RESULTS:
Based on the simulation and the equations above the results were plotted using origin 50 with the following
graphs:
Buck Converter
Boost Converter
Buck-Boost Converter
10
Vout/Vin
4
Duty cycle(%)
Figure 5.0 Graph of commonly converters compared analytically with equation 2.0 which shows the boost
converter has high gain.
Boost Converter
18
16
14
Vout/Vin 12
10
Duty Cycle
Figure 6.0 Graph of the gain to the duty cycle from the simulation result
B
1.0
0.8
)
le
0.6
y
tycc
0.4
u
(d
D
0.2
0.0
1 2 3 4 5 6 7 8 9 10
RC/RD ratio
Figure 7.0 Graph of maximum duty cycle with ratio of timing resistors
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Bajopas Vol. 2 Number 1 June, 2009
However, the nominal converter frequency was ratio of 3.4 with equation 10; the RC value was 40.5kΩ
chosen to be 25 kHz which gave an inductor of 500μH which indicated RD is 11.9kΩ. For maximum regulation,
and inductor peak current IL(pk) using equations (2.6) RFB should be greater than 81.0kΩ since RC was
and (2.7) with design power level of 700mW. 40.5kΩ then RFB is slightly greater than 81.0kΩ which
Maximum duty is 70% at 6.0volt correspond to RC/RD approximately 90.0kΩ
RC/RD=3
RC/RD=4
RC/RD=5
RC/RD=6
70 RC/RD=7
RC/RD=8
RC/RD=9
60 RC/RD=10
50
Freqency(kHz)
40
30
20
10
0
0 20 40 60 80 100 120 140 160 180
RC kohms
RC/RD=3
RC/RD=4
RC/RD=5
RC/RD=6
RC/RD=7
200 RC/RD=8
RC/RD=9
180 RC/RD=10
160
140
V (volt)
120
BIAS
100
80
60
40
20
2 3 4 5 6
RFB/RC
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Bajopas Vol. 2 Number 1 June, 2009
XSC1
Ext T ri g
+
_
A B
+ _ + _
ZFB
02BZ2.2
7
D
L 3
500uH
RFB BAV21 Vout
1 RC 90kΩ 8
VCC
41kΩ 2 Qsw
RST OUT
DIS VN10LF
6
6-12v Cin 7uF 5 THR
4.7uF
TRI Cout
CON 0
0 RD 12kΩ 555
0 GND
CT 1nF
0 0
0
ZFB
24
02BZ2.2
27
D
22 L
500uH
RFB BAV21 Vout
RC 90kΩ VCC
41kΩ 23 Qsw
RST OUT
26 DIS VN10LF
XSC1
6-12v Cin 7uF 25 THR
4.7uF
TRI
0 Cout Ext T ri g
+
CON
0
0 RD 12kΩ 555
_
0 GND A
_
B
_
+ +
CT 1nF
0 0
U7
LM7812CT
19 VREG LINE 21
20
VOLTAGE
COMMON 17
R6 U5A
0 1 14 7
28
Q3
7kΩ T1
3 2 8
4
U2A 0 16
R3 ~1PR 11 MCT6
3 5 IRFP250
1J 1Q
9 0
42kΩ 8 1 1CLK 7408N
U2C
50% TS_POWER_25_TO_1
Ke y=A 2 6 18
1 1K ~1Q 10
R1
24kΩ
4 RST
8
VCC
OUT
U1
3
4
10kΩ
R4
6
U3A
74HC113D_4V
7408N 12
R7
3 13 U5B 6 Q2
TS25T1 power
2
7
2
DIS
THR
TRI
100kΩ
Key=A
R5
50%
7
5 7
U4
7kΩ
4
MCT6
5 15
IRFP250
Transformer
5
R2
5
0
C2
CON
0
10kΩ 1
330nF GND
6
1
0 LM555CM 0 0 2
3554AM
0
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Bajopas Vol. 2 Number 1 June, 2009
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