MODELS 6407 AND 6409 RF ANALYZER |. OPERATION AND MAINTENANCE MANUAL Demian) len mee [eneron [J Xx) Ac ar INTENSITY GRATICULE. «MENU. MENU CONTROL —-ONOFF—«UPIDOWN SELECT Figure 8-96. All Subsidiary Control Panel Block Diagram Figure 8-97. All PCB Parts Locator Diagram a-110 6407/6409 OMMMANUAL CHANGES MANUAL: ‘Title: 6400 Operation end Maintenance Manual, Models 6407 and 6408 RF Analyzer Part Number: 10410-00009 Rev, Ltr/Date: = and F CHANGE PACKET Part Number: 10900-00079 SERIAL NUMBERS AFFECTED: 835001 and up INSTRUCTIONS 1. Make all manua} changes. Manual changes ere listed in numerical order by page number. 2, Replacement pages are provided for all manual changes. The black bar or bers in the margins of the replacement page show the area in which the changes were made. CHANGE 1, February 1991 L Page 7-2 Replace with enclosed page 7-1 and 7-2, Changed: February 1991. 2. Page 7-6 thru 7-10 Replace with enclosed pages 7-6 thru 7-10, Changed: February 1991. 8. Page 8-102 Replace with enclosed pages 8-101 and 8-102, Changed: February 1991. PCOs: K108, K223, and 19705 6400 OMM C184.11 All Control Panel PCB ‘The All Subsidiary Control Panel PCB contains the switches for MENU SE- LECT, MENU UP/DOWN, and GRATICULE ON/OFF. The video intensity control is also mounted on this PCB, The All block and parts locator diagrams are shown in Figures &§96 and 8-97 respec- tively, The All schematic is shown with the Al schematic in Figure 8-28 a. Switches. The All PCB switch- es—-MENU SELECT, MENU UP/DOWN, and GRATICULE ON/OFF--are con- nected into the control panel matrix via Connector Pl. Figure 8-95 shows the All switch matrix lines. which allows $2 to operate as two normal, double pole, single throw buttons. Intensity Control. The intensity control varies the video level to the monitor, This control, located in the video signal path, has less than 5V of signal, The intensity potentiometer consists of RI and R2. Resistor R2 ensures that the display cannot be turned all the way down. Consequently, it is impossible to have a completely blank screen, ‘The intensity control connection to the Al0 Motherboard is through Connector SI. The pin numbers and connections are shown below. The GRATICULE ON/OFF is operated by ‘switeh ly the MENU UE/DOWN commu tn by switch S2; and, MENU SELECT by oo aoe switch 3. Suitch so tu a conver. een fee Risin ome eaayaneiee tani Re |G ee throw! rocker Suitek,” Diodes CR black | Video return to CRT. thee ORG provide ‘rignal” seutiogs eo eee si tokanas) ig OR | ' : | te ea a = hie ' ' ut xt Figure 6-95. Switch Matrix Lines 6407/6409 OMM 8-109MANUAL ERRATA MANUAL: Title: Models 6607 and 6409 RF Analyzer Operation and Maintenance Manuel (OMM) Part Number: 10410-00008 . Rev, LtriDate: F ERRATA PACKET Part Number: 10901-00066 INSTRUCTIONS Cut out this errata change and paste or tape over the corresponding paragraph in the OMM. ERRATA 1, June 1981 1. Pages 1-2 2. Replace paragraph titled, “Option 5, Graphics Printer, ” with the cut-out text on the following page. 6407/6409 OMIMFigure 8-94. A10 Motherboard Schematic 3h sors oss ae e108 6407/6409 OwM6407/6409 OMM Paste this over the existing paragraph on page 1-2. — Cut along dashed lines — Option 5, Graphics Printer. RF Analyzer is sup- plied with a Model 2225C Inkjet Printer, along with ‘an interface eable, inkjet cartridge, and 50 sheets of fan-fold printer paper. Changed: June 1991owas LOAD DATA, DECODER Us : re wT a sT8 ACK RCVD, RESET FF | PRESET ACK FF USA cuR Busy PE Mux SELECT _ > RESET t 3 PS} $d SECS }$ A a$pmpa$}jmpa RR A Figure 8-92. Printer Circuit Block Diagram 8-107OPERATION AND MAINTENANCE MANUAL MODELS 6407 AND 6409 RF ANALYZER 160 JARVIS OF WILTRON | MORGAN HLL CA 95057280 TEL, (08) 778.2000. TELEX 285227 WICTRON MH FX 408-778-0099 30810-00009, REVISION: F PRINTED: NOVEMBER 199 ‘COPYRIGHT 1985 WILTRON COMPANYoD OE po Pas EI a Figure 8-93. Al0 PCB Parts Locator DiagramWARRANTY All WILTRON products are warranted against defects in materials and workman- ship for one year from the date of shipment, except for YIG oscillators which are warranted for two years. WILTRON’s obligation covers repairing or re- placing products which prove to be defective during the warranty period. Buy- ers shall prepay transportation charges for equipment returned to WILTRON for warranty repairs. Obligation is limited to the original purchaser. WILTRON is not liable for consequental damages. LIMITATIONS OF WARRANTY The foregoing warranty does not apply to WILTRON connectors that have failed due to normal wear. Also, the warranty does not apply to defects resulting from improper or inadequate maintenance by the Buyer, unauthorized modification or misuse, or operation outside of the environmental specifications of the product. No other warranty is expressed or implied, and the remedies provided herein are the Buyer's sole and exclusive remedies.(cl The Y output clears the Acknowledge flip-flop (ACK FF), A3, so that it is ready to respond to the printer's acknowledging signal (ECK) that the data has been received. (2) The ¥3 output enables the status” latch (Ul) to read the four printer status lines: ACK, BUSY, PE, and SELECT. (e) The Y, output presets the RESET flip flop, U3, for an inactive, logic-high output. () The ¥5 output clears the RESET flip flop for an ac- tive-state, logic-low output. This output sets the RESET output line to its active-low state. The RESET line resets the printer. operation of U¢ is as fol- (a) Select_output_Yo. This! output is selected when the six input lines have the logic states shown below: ()A0-A2: low (1/0 ports 58H) (2) Aa: high @) PSB: low (4) TOSELS: low Approximately 1 uS after having been selected, the PSE line returns to its inactive HIGH state and deselects the Yq output This output then goes HIGH and clocks the data through lateh U2. (®] Select output ¥;. Same as ia] above, except the A0-52 logic status is: 6407/6409 OMM, te) (a) fe) (i () AO: high (2) al: low (3) At low (1/0 port: 59H). The Yy output provides the 1 US active low strobe pulse (PSE) to the printer. Select output Y. Same as la) above, excep! the AQ-A2 logic status is: (1) a0: low (2) Al: high 3) A2: Tow (1/0 port: SAH). The Y, output clears the Acknowledge FF. Select output Y3. Same as fa) above, except the A0-A2 logic status is: a (2) @) (1/0 ports The Y3 output enables the status latch, Ul. Select output Yy. Same as Ta) above, except the A0-A2 logic status is: a low (2) low @) high (I/O port: The Yq output presets the RESET FF, U3B. Select output Ys. Same as (a) above, except the A0-A2 logic status is: (1) AO: high @) AL: low (3) 2: (1/0 port: 5D). The Ys output clears the RESET FF, U3B.Section I 1 ut 6407/6409 TABLE OF CONTENTS. GENERAL INFORMATION 1-1 Scope of Manual ...sseseeeeee : 1-2 Introduction ..... 1-3 Identification Number. 1-4 Description of 6400 System. 1-5 Options -sseseeeee 1-6 Accessories « . 1-7 Specifications « 1-8 Replacement Diode for SWR Autotester and RF Detector.......- 1-9 Precautions For Use of SWR Autotester and RF Detector «++... INSTALLATION 2-1 Introduction 600 2-2 Initial Inspection ...- pucdED 2-3. Preparation for Use.. 2-4 GPIB Setup and Installation .. 24.1 Interface Connector +..++ 24.2 Cable Length Restrictions. 24.3 GPIB Interconnections 24.4 GPIB Address og 2-45 Data Delimiting (CR-CR/LF 2-5 Preparation for Storage and/or Shipment 2-5.1 Preparation for Storage -...+ 2-5.2 Preparation for Shipment LOCAL (FRONT PANEL) OPERATION 3-1 3-2 3-3 om Introduction see. Control Panel Controls .++++ 3-2.1 CRT Display.+ 2 SYSTEM FUNCTIONS Keys 3 NETWORK ANALYZER Keys and Indicators «+++ 4 DATA ENTRY Keys and Knob... 5 6 7 HARD COPY Keys « SOURCE Keys and Indicators « GPIB Key and Indicator Rear Panel Connectors. pyoerey eggs hadFigure 8-91. Tick Signal Squaring Circuit b. Circuits ft 2 8-106 Line Tick Circuit. The line tick is a synchronization pulse that stabilizes the display on the CRT. This pulse comes from the A9 PCE and goes to the A7 PCB via the AO and Aé PCBs. The line tick circuit is shown in Figure 8-91. The line tick is squared by Ql. A logic level signal is fed to the base of Ql through R2. The signal reappears at the col lector of Ql inverted, squared off, and at the same TTL logic level. Capacitors C1 and C2 prevent any fast edges that might inter- fere with the timing opertion. Printer Control Circuit. This circuit controls the several operations needed to print data. The operations are: (a) Holding the data until the printer is ready to accept it. (b) Reading the printer's acy knowledging signal that the data has been accepted. (c) Reading any status signals from the printer; such as, printer busy, printer out of paper, printer selected. la) Reseting the printer to its Power ON default settings. The printer circuit consists of ICs Ul thru U3 and associated components. A simplified schematic is shown in Figure 8-92, and the schematic is shown in Figure 8-94. Refer to the simplified schematic for the following discussion. The controlling chip in this circuit is decoder U4. The output lines on this IC generate logic signals that perform the following sequential actions: (a) The Yq output clocks the data through latch U2 and out to the printer. (b) The ¥, output_ sends a Strobe pulse (STE) to the printer that tells it valid data is on the line. 6407/6409 OMMSection HI v vr TABLE OF CONTENTS (Continued) Continued 3-4 365 3-6 Measurements With RF Analyzer « 3-41 Transmission and Return Loss Measurements 34.2 Absolute-Power Measurement «++ 3-43 Alternate Sweep Measurement Operational Checkout « Error Messages-+++ REMOTE (GPIB) OPERATION 41 42 43 44 45 4-6 Introduction sssseseeee a1 Description of the IEEE~£88 Bus (GPIB) 2 4d 4-2.1 Data Bus Description : +41 42.2 Management Bus Description seseeeee Es +41 42.3 Data Byte Transfer (Handshake) Bus Description .ssseeee 4-2 GPIB Operation seesseee 42 Command Codes, Descriptions « + 43 Bus Messages, Analyzer Response To « 43 Alphabetical Index to RF Analyzer Command Codes sessesseeees 4-3 PERFORMANCE VERIFICATION Sel Introduction 5-2 Recommended Test Equipment - : 5-1 5-3. Test Records.. poopcgscnocnacca 5-1 5-4 CW Frequency Accuracy Test sesseeceseeesseeseeeeeeeeeeeeeeees Sol 5-5 Output Power Flatness Test ssee+ @cg09Ge53600030 “3 5-6 Signal Path Accuracy seessececeeeeeeeneeees 5-6 5-1 Residual FM Test seseeee 5-8 Source Output Signal Test . CALIBRATION 6-1 Introduction «. o1 6-2 Recommended Test Equipment.. 6-1 6-3 Adjustments Following PCB Replacement +s+eeseeeee sees Oo 6407/6409 OMM8 Connector P& Connector PS is 9. Connector P9. Connector P9 is the central processor unit (A6) the Graphic Display Processor PCB edge connector, (A7) PCB edge connector. Table 8-23, Connector PS Table 8-24. Connector P9 (Circuit side (Component side (Circuit side] (Component side of the PCB) of the PCB) of the PCB) ofthe PCB) Pin] Signal | Pin Pin] sicnat | Pin] Signal No. | Ident. Now| téent, | Now |__tdent. A a| po 1 B B | oz 2 c c | ps 3 D d| ve 4 E z | 3D 5 F F | ao 6 iH H nfo 7 I a] ne 8 K K| ave 9] — L L ale 10 _ M mM] n/c n N Nn] nye 12 P P| ave B R R| sv |v s s | ov 15 | ov T T nfo 16 ca 0 ul ale vf = v vale iS w w] tosrg fis | = x x] n/e 20 | = ¥ y| ave a] - z z| vscrn | 22 | vscrn AA nt aa] compvip | 23 | vscrn BB n/c n/c BB VSYNT 24 VSCRN: ce | nye SYNC cc] vscrn | 25 | vipzo pp | n/c -15V pp] async | 2% | vscrn rE | PLLCONT 215V ze | ajc male FF | RESET TICK rF{ veow | 2 | = 6407/6409 OMM 8-105TABLE OF CONTENTS (Continued) Section Page VI Continued 6-4 Ad Sweeper PCB Adjustments . 6-4.1 Main Tuning Coil Calibration .. 64.2 FM Coil Calibration. 6-43 FM Coil Sweep Width .. 6-44 ALC Power Calibration ... 6-5 A3 Signal Channel Calibration « 1 Range Change Error at -20 dBm 65.2 Overall Gain Calibration ... 66 CRT Set Up .. VII PARTS LISTS 7-1 Introduction «0... TH 7-2, Parts—Ordering Information col 7-3. Exchange Program. TH 7-4 Abbreviations . TH 7-5 Replaceable Parts vee. TH VIII SERVICE 8-1 Introduction 8-2 General Information. ee 8-2.1 PCB Exchange Program. 8-2.2 Recommended Test Equipment . 82.3 Preventive Maintenance 8-24 Static Handling Procedures « 82.5 Soldering... 8-3 Service Instructions . 84 Microwave Components « 84.1 SWR Autotesters 84.2 RF Detectors. 8-4.3 Diode Replacement 84.4 Diode Replacement for Detector 84.5 Connector Cleaning . 6407/6409 OMM iiiConnector _P. interfaces th thi Connector P4 e printer. Table 8-18. Connector P4 Centronics Connector Pin | Signal Pin | Signal Ni Iden N Ident. ee 1 | 3B 19 | ov 2 Do 20 | ov 3 DI 21 | ov 4 D2 22 | ov 5 D3 23 | ov 6 | Da 24 | ov 7 Ds 25 | ov 8 Dé 26 | ov on | pa 27, | ov 10 | ACK 28 | ov ret BUSY 29 | ov 12 Pap ouT| 30 | ov 13 SEL 31 | INIT 14 = 32 | n/c 15 - 33 | ov 16 ov 34 | n/c 17 ov 35 | n/c 18 36 | ne Table 8-19. Connector P4 Motherboard Pin | Signal Pin | Signal No. | Ident. Now| Ident. 1 STE is | ov 2 ov 19 | ACK 3 DO 20 | ov 4 ov 21 (| BUSY 5 D1 22 | ov 6 ov 23. | PAP OUT 7 D2 24 | ov 8 ov 25 | SEL 9 D3 26 | INIT 10 ov 27 | ale iL D4 28 | ale 12 ov 29 | n/c B Ds 30 | ov 14 ov 31 | ov 15 Dé 32 | n/c 16 ov 33. | ov Lo D7 34 | ne Connector PS, Connector PS Brings power from A9 to the other PCBs, the ribbon bus, and the CRT. PS also carries the line tick signal. The A4 PCB however, receives power to Ad, P6 from A9, P2. Table 8-20. Connector PS Signal Ident. +12 Monitor Supply OV return PIN 1 -15V Ribbon Bus supply OV return for PINs 3 and 5 +15V Ribbon Bus supply Line tick signal OV return for PIN & +5V supply to all logic Connector PG. P6 makes the connection between the intensity control potentiometer on All to ALO. Table 8-21. Connector Pé Pin Signal Ident. ideo Ground Return from the Control Panel Send to the Control Panel Unallocated Table 8-22. Connector P7 Video Monitor Connector P?. Connector P7 carries power plus video and synchronization signals to the crt. Pin No. Signal Ident. HSYNC Screen VIDEO Screen INSYNC +12 Volt Supply 8-104 6407/6409 OMMTABLE OF CONTENTS (Continued) Section Page VIII Continued 8-5 Gaining Access to PCBS eeseeeeseee 8-6 Troubleshooting Flow Charts - 8-7 PCB Circuit Descriptions... 87.1 Overall Comments... 8-7.2 Al Control Panel 8-7.3 A3 Signal Channel. 8-7.4 Ad Sweeper Board « 8-7.5 RF Deck eeeseeee ppaccoO 8-7.6 A Central Processor Unit. 8-7.7 A7 Graphics Display Processor « 8-7.8 AS GPIB.. 8-7.9 A9 Power Supply 8-7.10 10 Motherboard ..... 8-7.11 All Auxiliary Control Panel . iv 6407/6409 OMM8-7.10 A10 Motherboard PCB The A10 Motherboard provides _ the medium for connecting the digital PCBs to each other, to the rest of the as- semblies, and to the outside world. Tables 8-15 thru 823 contain each different connector's pin numbers and the associated signal identification. The two circuits on this PCB are the tick signal squaring circuit and the hard copy circuit. The tick signal squaring circuit is shown in Figure 8-91. The printer circuit is shown in Figure 8-92. The parts locator diagram and schematic are shown in Figures 8-93 and 8-94, a. Connectors 1. Connector Pl, Connector PI goes to the ribbon bus that connects the Aé CPU PCB to the A3 Signal Channel, Al control panel, and Ad Sweeper PCBs. Marker information is derived from the A4 PCB, Power required by the Al control panel and the A3 signal channel PCBs is also carried over this bus. 2, Connector P2. The A8 GPIB option communicates and receives power through connector P2. A high frequency clock line runs through this ribbon cable. To minimize distortion, this clock line is sandwiched between two ground wires. 3. Connector P3. Connector P3 takes the composite video to the rear panel BNC connector. 6407/6409 OMM Table 815. Connector Pl Pin | Signal Pin | Signal No._| Iden. No, fNo_f ident Not Aten 1 | ne lege) De 2 | ave 1 | D3 3 | -isv 20 =| pe 4 | ov Bt | Gy palo; 5 | B08 | 22 DO 6 | oy, Pa EAT digital 7 | sstistt 24 a6 8 | INT isp leas 9 | mrt 26 «| Ad 10 | INTE 27 re un | awry ze | az 12 | n/c 29 | a 13. | PSB a || 20 14 | Tom 31 | TosEry 15 | vz 32 | TOSEE? 16 | D6 33 | TOSECe 17 | ps 34 | toserd Table 8-16. Connector P2 Signal] Pin Iden No. Do n | az DI ieee |g D2 3 «| RD D3 14 | TOsEry Dé 1s | WR Ds 16 | sv Dé | INT D7 1s | ov AO 19 | cLK al 20 | ov Table 8-17. Connector P3 Fin Signal No. Ident. 1 Composite Video Output 2 Video Ground 8-103SECTION I GENERAL INFORMATION 1-1 Scope of Manual... 1-2 Introduction .... 1-3 Identification Number... Description of 6400 System... Options « Accessories sesseeee 1-7 Specifications .. 1-8 Replacement Diode for SWR Autotester and RF Detector.. 1-9 Precautions For Use of SWR Autotester and RF Detector... 6407/6409 OMM ContentsREFERANCE AZ a snaeas VOLTAGE, SELECTOR z ! ; ; ia 5 ser elas eo ‘Te : ee Le ov aww cel bn wo! “< ag efits fom A Toe lez “svat 95 your “ 444 1300/1 20v02h SLO BLOW boow/2ubveue Ske ow os _ chee r> 5 va dan car $5 sev al Figure 8-90. A9 Power Supply Schematic 8-102, 6407/6409 OMM100-240V CONTROL PANEL. ONOFF SWITCH pails eal +12 LINE TRIGGER, 4 +15V @ 250 mA “BV @ 250 mA 4, US +#18V @ 640 mA ABV @ 640 mA Us, u7 425 VOLTAGE av Vv sev “5V 15V sev fev 425 CURRENT 14 34a S20mA 250mA 250m coma, coma 20mA WATTAGE 15w 20w 10W Figure 8-88. A9 Power Supply Block Diagram 8-101General InformationLoe HB | Fae ~ a @i ome ee Figure 8-89. A9 PCB Parts Locator Diagramwopeusojuy jeseuesTable &14. Power Supply Outputs TYPICAL MAXIMUM REGULATOR | DC VOLTAGE | DC_CURRENT | DC CURRENT | USED MAINLY BY vl +12 Velts ’ Video monitor U2 +5 Volts : All logic v3 -18 Volts YIG tuning v4 +15 Volts Signal Channel vs 5 Volts Signal Channel U6 +18 Volts Sweeper Board U7 -18 Volts Sweeper Board v8 425 Volts Switched Attenuator All of the supply rails follow the Be same pattern. The +/-I5V and the ac +/-18V rails, however, have addi- pseeosar | tional diodes across their outputs to macnn hie protect them from reverse biasing. vector The +25V rail is regulated by a 15V ee monolithic regulator, U8, that has ee its reference-ground terminal biased cw nina to +10V by CRI6. This biasing is feet RST through R9. [ea ae |. PSU_ON/OFF LED Indicator. The J aeainsnesiee power supply ON/OFF indicator is provided by a resistor and LED 5 indicator across the output of the Figure 8-87. Regulated Outputs SHV rail. These components are located on the component side of the PCB. Rectified voltage from CR18 charges reservoir capacitor Cl. A safety discharge path for this circuit is Line Trigger. The line trigger is a provided by resistor RI, The mono- Togic level signal output that is Hithic regulator, Ul, produces the derived from the ac line. It is used required output voltage of +12V. This by the A6 microprocessor PCE to regulator is protected from the perform real time events and tim- cutput line by hold-up diode CR9. ings. The trigger output is formed Final decoupling for the regulator by CR24, RIL iz, C26 and C2. is provided by capacitors C2 and 3. 6407/6409 OMMSECTION! GENERAL INFORMATION 1-1 SCOPE OF THE MANUAL This manual provides general, installation, and operation information for the Models 6407 and 6409 RF Analyzer (Figure 1-1). 1-2 INTRODUCTION Section I provides information about the equipment identification number, perfor- mance specifications, and options. 1-3 IDENTIFICATION NUMBER All WILTRON instruments are assigned six-digit ID number, such as "505001. This number appears on a decal affixed to the rear panel. Please use this identifica~ tion number in any future correspondence with WILTRON Customer Service about this instrument. Figure 1-1. 6407/6409 OMM 1-4 DESCRIPTION OF 6400 SYSTEM The 6407 and 6409 RF Analyzers are com- plete measurement systems for testing RF components and systems. Each consists of an RF analyzer, with its own built-in scalar network analyzer and sweep-fre- quency source, an external RF detector, and an SWR Autotester. The RF detector is used to measure transmission loss and absolute power, and the SWR Autotester is used to measure return loss. 1-5 OPTIONS ‘The following options are available: Option 1, Rack Mount. A kit is available containing mounting brackets and chassis track slides. The track slides have a 90-degree tilt capability. Model 6409 RF Analyzer and 2225C Ink Jet Printer 1-1Guest @ 2 & oe o or ° El =| el & 1 c= ill 07/6409 OMM. Figure 8-85. A8 PCB Parts Locator Diagram 8-7.9 A9 Power Supply PCB The A9 PCB provides eight regulated voltages. These voltages are shown in Table &14, The block diagram, parts locator diagram, and schematic are shown in Figures 8-88, 8-89, and 8-90 respectively. a, General. The input to the A9 PCB is provided by the line voltage selector module on the rear panel. This module contains a line fuse and a line filter, and allows the use of either of four international line voltages: 100, 120, 220, and 240 Vac. Two cable harnesses come from the input module, one goes to the front panel mounted line ON/OFF switch, and the other goes to the toroidal transformer mounted on the Al0 motherboard. Another cable harness takes the secondary ac voltages from the transformer to input connector P3 of the A9 power supply PCB as shown on the schematic (Fig- ure 8-90). The power supply is a multi-rail, linear unit that provides the out- puts shown in Table 814. The regulated outputs from A9 go to the A10 motherboard through con~ nector Pl and to the A4 sweeper board through connector P2 as shown in Figure 8-87. Each regulator circuit employs a three-pin, monolithic regulator (UI thru U8) that has internal over- current and over-temperature protec tion. To allow for more efficient cooling, the 5 volt regulator, U2, has 2 703 case and is mounted on a separate heatsink along with its bridge rectifier. All the other regulators use the 70220 case and are mounted on an aluminum heat- sink that is bolted along one edge of the PCB. 8-100 be Polyswitch. The polyswitches (RTI thru RTT) are temperature dependent resistors used as solid state fuses. Polyswitches (except at the +5V circuit) are used to ensure that the regulated outputs are short-circuit Protected in case of an equipment failure. They also ensure. that failure of the power supply does not cause damage to other circuits within the instrument. A discus sion follows. When the maximum current rating of the polyswitch is exceeded, inter- nal heating causes it to increase in resistance very rapidly by several orders of magnitude. The resultant low current/nigh voltage condition of the device causes only a small amount of power to be dissipated by the polyswitch. This small power level Keeps the device in a high impedance state, which results in only a very small amount of power being dissipated by the failure that caused the condition. The polyswitch is reset by switch- ing the line power OFF for a ap- proximately ten minutes to allow the device to cool. Regulator Circuits. The linear Fegulator circuits provide required supply voltages to the instrument. Table 8-14 shows these voltages plus typical and maximum current rat- ings. Since all the regulator cir- cuits are very similar, only one is fully described. Major differences in the other sections, however, are detailed below. The 12 Volt supply for the video monitor is derived from the 15 volt RMS winding on the transformer and is taken to bridge rectifier CRIS through polyswitch RT2. 6407/6409 OMMOption 2, 70 dB Step Attenuator, 10 dB Steps. RF Analyzer comes supplied with a control-panel- or GPIB-programmable 10 4B step attenuator having a 70 dB range. Option 3, GPIB Interface. RF Analyzer is equipped to operate on the IEEE-488 Inter~ face Bus. With Option 3 installed, all control-panel keys, except line POWER, are bus-programmable. Option 3 may be installed in the field. Option 4, 75-Ohm RF Output (6407 only). RF Analyzer comes supplied with an RF OUTPUT connector having an impedance of 78 ohms. Option 5, Graphics Printer. RF Ana- lyzer is supplied with a Model 2225C Inkjet Printer, 2225-1 Interface Cable one 2225-2 Inkjet Cartridge, and 500 sheets of 2225-3 Fan Fold Printer Paper. Option 6, Protective Cover. RF Ana- lyzer comes with a protective cover for the control (front) panel. 1-6 ACCESSORIES The following accessories are available for the 6407 and 6409 RF Analyzers: Extender Cables: Extender Cables are used to make remote measurements and are placed between the SWR Autotester or detector and the analyzer. Cables cause no degradation in performance. For lengths and models numbers of available cables, see below. Model Length 800-109 7.6 meters (25 ft) 800-110, 15.2 meters (50 ft) 800-111 30.4 meters (100 ft) 800-112 61 meters (200 ft) GPIB. Cables: GPIB (IEEE-488) cables are used to interconnect instruments on GPIB. See listing of available cables below. Model Length 2100-5, 0.5 meter (1.6 ft) 2100-1 1 meter (3.3 ft) 2100-2 2 meters (6.6 ft) 2100-4 4 meters (13.2 f0) Le RF Limiters: RF limiters are used to protect 6400 detectors against damage from: @ DC Voltage--blocks up to 50 volts © AG Voltage~filters 60 hertz and below signals up to 100 volts and impulse currents up to 500 milliamp- ¢ RF Power--protects for up to 4 watts from 1 to 1500 megahertz. See listing of available RF limiters below. Impedance Model. Connectors (Obms) 1850 BNC Male & Female 50 1N50 N Male & Female 50 1875 BNC Male & Female 75 1N75 N Male & Female 75 1-7 SPECIFICATIONS Specifications for the 6407 and 6409 RF Analyzers and the 6400 SWR Autotesters and RF Detectors are provided in Table 1-1 on page 1-4. 1-8 REPLACEMENT DIODE FOR SWR AUTOTESTER AND RF DETECTOR Field replacement of the detector diode is possible with both the 6400-71 Series RF Detectors and the 6400-6 Series SWR Autotesters. For the SWR Autotester, the WILTRON part number of the diode is 10-9. For the detector, it is 10-21. 1-9 PRECAUTIONS FOR USE OF SWR AUTOTESTER AND RF DETECTOR The 6400-Series SWR Autotesters and RF Detectors (RF components) are high- quality, precision laboratory instruments and should receive the same care and respect afforded other such instruments. Complying with the following precautionary notes will guarantee longer component life and less equipment downtime due to con- nector failure. Also, such compliance will ensure that RF component failures are not due to misuse or abuse—two failure causes not covered under the WILTRON warranty. 6407/6409 OMM& ane BEoPRE RR OR ebkl: ‘ag a 2 x al 7 bh. Tag § a [uterus [ise notes Mot UseD PERS eS EC > 0 pmo Ty veers uses xc. Figure 8-86. A8 GPIB Schematic 8-99a. Beware of Destructive Pin Depth on Mating Connectors. Measure the pin depth (Figure 1-2) of the connector that mates with the RF component before mating. Based on RF compo- nents returned for repair, destructive pin depth on mating connectors is the major cause of failure in the field. When an RF component connector is mated with a connector having a de- structive pin depth, damage will likely occur to the RF component connector. (A destructive pin depth has a center pin that is too long in respect to the connector's reference plane.) Table 1-2. RF Component Pin-Depth Tolerance test port | Pin opm |] amc Gauce* connector Tree | qmiis) READING eS tomate 207 -0.000 | 349 -0.000 +0008 +0,003 N-fenale 207 #94000 seme as -0,003 | pin deotn smc Is Maury Microwave Corp. - Reading N-Connector Pin Depth The center pin on an RF component connector has a precision tolerance measured in mils (1/1000 inch). Whereas, connectors on test devices that mate with RF components may not be precision types, and their pins may not have the proper depth. Com sequently, they must be measured be fore mating to ensure suitability. When gauging pin depth, if the test device connector measures out of tolerance (Table 1-2) in the "+" region (Figure 1-3) the center pin is too long. Mating under this condition will probably dam- age the RF component connector. On the other hand, if the test device con- hector measures out of tolerance in the "=" region, the center pin is too short. A mating, while not causing any dam- age, will now result in a poor connec~ tion and a consequent degradation in performance. 6407/6409 OMM Figure 1-3. MMC Pin Depth Gauge Avoid Over-Torguing Connectors. Over- Yorquing connectors is destructive; it may damage the connector center pin. Finger-tight is usually sufficient, espe- cially on type N connectors. NEVER USE PLIERS TO TIGHTEN CONNEC- TORS c. Do Not Disturb Teflon Tuning Washers on Connector Center Pins. The center Conductor on most RF component con- nectors contains a small teflon tuning washer located near the point of mat- ing (interface). This washer pensates for minor impedance disconti- 13seanstvens a i in Te =] t fel = | a. 8-98 Figure 8-84, The 6400 bus address, which has been set using switch SI, is read when the instrument is turned on. If the address is changed while the instru- ment is operating, the RETURN TO LOCAL button must be pressed to allow the new address to be loaded. Buffering. The remaining sections of U8 perform buffering functions: 1. USE buffers and inverts the interrupt output of Ul to drive the TNT; line. 2. USD buffers the incoming clock signal. e A8 GPIP Block Diagram Since the transmit/receive control line from controller Ul is used by more than one TTL load, the signal is buffered, and inverted where necessary, by USA and B. Interrupts, Once U1 has been in- itialized it needs no regular atten- tion. If a bus transaction takes place that concerns the 6400, Ul exerts an TNT) interrupt. The CPU then responds by interrogating U1 to establish the cause of the inter- rupt before taking appropriate ac- tion. 6407/6409 OMMnuities at the interface. The washer's location is critical to the RF compo nent's performance, DO NOT DISTURB. 4. Avoid Mechanical Shock. RF compo- nents are designed to withstand years of normal bench handling. However, do not drop or otherwise roughly treat vices, and like other such devices, they require careful handling. e. Keep Connectors Clean. The pre- cise geometry that makes possible the RF component's high perform- ance can be easily disturbed by dirt and other contamination adhering to connector interfaces. When not in them. They are laboratory-quality de~ use, keep the connectors covered. Table 1-1. Specifications Source Number of Typical Data Points Smoothing Sweep Time Frequency Range: 6407: 1 to 1000 MHz 101 orF <100 ms 6409: 10 to 2000 MHz 201 OFF <250 ms Frequency Resolution: 10 kHz 401 oFF <400 ms Frequency Accuracy: +100 kHz 301 MIN <350 ms, Frequency Drift: 201 MIN <350 ms With Time: <100 kH2/hour 401 MIN ame ahs 2lP* 05. w vere fe “y ae ED BR af a ; L oe tee e fig eles - vaneo muse joes oo |e mee | Les ¥ SR vig pe as 2 HR, tse 2 13 | 00 PY a 2 e oe} = oe = [te TD Ve Teaae ea ay i t aS —SPARES __ ‘ ve Teas] os + es uN oN on a ele] Joa "D&, “DE, «Dag | Bio. | yl 78S Bt 8 Sen UNLESS OTHERWISE SPECIFIED. |, 2 os 2 AesSTMs ORE Dom. acres we IN he (=) a obe oS De ® : eee ua wR “ae tithes Bes Figure 8-82. A? GDP Schematic 6407/6409wonelersuya a |£ COMPOSITE VIDEO (REAR PANEL) 7 : e [ow : : DEO TOCRT 7 : e a EDGE : i i Usb : CONNECTOR | eer : e REGISTER i : i 2 AS INTERFACE. sss see eee CRT INTERFACE si ER ed u12, 14, Uaza DECODER and ‘DRIVER. ur GRAPHICS DISPLAY. PROCESSOR, ure, u17 MEMORY ‘ADDRESS BUS 2 43, U3a Us, US Usa, U7a, UB, . vco TIMING 10. U1T, Us2b : CONTROL SEQUENCE | MULTIPLEXERS : SQUARER GENERATOR | and DRIVERS sso WADRO-MADAT VIDEO MIXER 13, U4, 01-04 geo 18, U20, Ut9, U21, U30, U31, U32, U33 MEMORY PLANE 0 22, U24, U23, U2, 1US4, U35, U36, U37 MEMORY PLANE 1 RASICAS/OE seen 26, U2, U27, U38, U39, Udo, MEMORY PLA LOGIC, TIMING, and MEMORY INTERFACE ssn eg u2a, at NE 2 Figure 8-80. AT GDP Block Diagram 8-9325 6407/6409 OMM SECTION Il INSTALLATION Introduction Initial Inspection sssseceeseeeeeeeeseeeees Preparation for USC ..ssssesseeeeeaeeeseesneteeeees GPIB Setup and Installation «. 2-4.1 Interface Connector «- 2-4.2 Cable Length Restrictions. 24.3 GPIB Interconnections «.+++0++ 2.4.4 GPIB Address « . 2-4.5 Data Delimiting (CR-CR/LF Switch). Preparation for Storage and/or Shipment 2-5.1 Preparation for Storage 25.2 Preparation for Shipment Contentsea JOUTTUTUUT a * © TOU WTO AT PCB Parts Locator Diagram Figure 8-81.We al Wez Figure 8-79. Decoding Address Lines and Enable Lines Since these lines are not valid at all times, they are latched by U12 (Figure 8-79), along with the conrol line ALE from Ul. These decoded lines provide four lines (only three of which are used) corresponding to each of the four blocks of memory covered by Alé and Al?. By further gating these signals with the DBIN (U1, pin 2) signal, sepa- rate enable signals can be provided for the bi-directional bus drivers, U20 and 21 (WEVDBIN) of the video memory planes. Similarly, the WE 6407/6409 OMM, lines are also derived for the memory ICs; in this case it is necessary to introduce a small delay using R15 and Cl to allow for the turn-around time of the bi-direc~ tional buffers. This delay action ensures that the buffers have turned around to drive data to the memories and that the data bas settled before the Write Enable line is pulsed on the memo- ries. The separate WE lines are driven by U424 through anti-ringing resistors R19 thru R21.SECTION II INSTALLATION 2-1 INTRODUCTION This section provides information on initial inspection, preparation for use, and General Purpose Interface Bus (GPIB) interconnections. It also includes reship- ment and storage information. 22 INITIAL INSPECTION Inspect the shipping container for damage. If the container or cushioning material is damaged, retain until the contents of the shipment have been checked against the Packing list and the instrument has been checked for mechanical and electrical operation. If the analyzer is damaged mechanically, notify your local sales representative or WILTRON Customer Service. If either the shipping container is damaged or the cushioning material shows signs of stress, notify the carrier as well as WILTRON. Keep the shipping materials for the car- rier's inspection. 2-3 PREPARATION FOR USE Preparation for use consists of checking that the line voltage module on the rear panel is set for the correct line voltage. This module can be configured for any of four international, nominal line voltages: 100, 120, 220, or 240 Vac. Before leaving the factory, each analyzer is preset, and fused for the line voltage present in the customer's area. If the actual line voltage is different from that shown on the module, the module can be changed to a different voltage using the procedure in Figure 2-1. 6407/6409 OMM 24 GPIB SETUP AND INTERCONNECTION The analyzer provides automated microwave measurements via the GPIB. The following paragraphs provide information about interface connections, cable requirements, and the addressing of the RF analyzer. 24.1 Interface Connector Interface between the analyzer and other devices on the GPIB is via a 24-wire interface cable. This cable uses connector shells having two connector faces. These double-faced connectors allow for the parallel connection of two or more cables to a single device. Figure 2-2 shows the pin assignments for the Type 57 GPIB connector installed on the rear panel. 24.2 Cable Length Restrictions ‘The GPIB system can accommodate up to 15 instruments at any one time. To achieve design performance on the bus, proper timing and voltage level relation~ ships must be maintained. If either the cable length between separate instruments or the accumulated cable length between all instruments is too long, the data and control lines cannot be driven properly and the system may fail to perform. Cable length restrictions are as follows: No more than 15 instruments may be installed on the bus. 2 Total accumulative cable length in meters may not exceed two times the number of bus instruments or 20 meters~whichever is less.Table 13, Memory Timing Signals Signal Location ‘Action UI8-U19, pin 7 Clocks out data at pixel rate. U18-U19, pin 15 Loads 16 bits to shift reg (U18, v19) 19, pin 13 Video (plane 0) data out U20-U21, pin 1 Determines read or write from/to memory ICs U30-U33. 020-U21, pin 19 Controls tri-state of buffers, pre~ vents data conflict. 030-033, pin 4 Low allows data write to memory. 30-U33, pin 5 Latches in part of address. 30-033, pin 16 Latches in other part of address. U30-U33, pin 1 Controls output of memory to bus VDO0-VDO15. Prevents conflict. a Figure 8-78. Logic Timing 8-92. 6407/6409 OMMTo change the line voltage from that shown on the Line Voltage Selector Module, proceed as follows: a. Remove the power cord from the line voltage module. b. Insert the blade of a small screwdriver into the slot at the top-center of the module, and pry ‘open the cover. c. Remove the voltage selector drum by pulling straight out. d. Rotate the drum so that the desired line voltage marking faces out, then reinstall the drum. Fuse Sizes, Ratings, and Part Numbers i IseaT SCREWDRIVER HERE TO OPEN FUSE cavity Remove the fuse cartridge from the right-hand fuseholder- The fuse cartridge is identified with a white arrow and is located beneath the voltage selector drum. Check that the proper fuse is installed (see table, below). correct fuse, if replace the fuse Change to the necessary, and cartridge. Close the cover, and ensure that the desired line voltage value is displayed through the opening in the cover. Reinstall the line cord. Line Fuse Fuse Wiltron PIN- | Wiltron PIN- [votese [ee | rating | ‘ste | “rune | eta | 100 Vac Japan 2A, antisurge BAG 631-52 533-221 | 240 Vac UK 1A, antisurge | 5x 20mm l Figure 2-1. Changing the Line Voltage 6407/6409 OMMMAoRO MADR? Figure 8-77, Timing for the latching of U15 and the switching of Ul6 and UI? is generated in the timing section (paragraph 8-7.7e). The whole address is latched into the memory chips (U30-U33 for plane 0) using the Row Address Strobe (RAS) (pin 5 on each memory IC) and Column Address Strobe (CAS) (pin 16 on each memory IC) both of which are generated by the timing logic. The data of the memory location addresses, if in a READ cycle, is presented to the internal. ‘bus VDO0-VDO15 when the IC is enabled by the output enable (OE) control line (pin 1 on all memory ICs). If in a WRITE cycle, as in the update of display memory, the GDP chip (U1) ensures that data is available om these lines that pass through U20 and U2l. For display cycles, the data is clocked into the shift registers U18 and U19 by the LOAD signal, LD (pin 15 of U18 and U19). Video memory planes 1 and 2 operate similarly. Memory plane 1 contains the A channel trace and trace identifiers plane 2 contains the B channel 6407/6409 OMM Formation of Memory Address Bus trace and trace identifier; and plane 0 contains all other information including graticule, markers, and alphanumerics. The memory timing signals are shown in Table 8-13. Logic Timing. Timing sequences (Figure 8-78) are provided by a se- quence generator formed by US and U9. US counts the pixel clock from U3A, pin 2. U9 takes the address latch enable line ALE (U1, pin 6, inverted by USD) as a serial input, and clocks the signal through the IC at pixel rate so that ALE is at the phase shifted outputs of QA and QC (pins 15 and 13), Timing signals KAS, TAS, and_the multiplexer select | signal, KOW- BDRSEL, are generated by gating KLE and the phase shifted ALE with U10. The KAS and CAS signals are then driven by U42B through the anti-ringing resistors R17 and R18 to the memory ICs, The UE signal is derived in a similar way using vl. To access the three memory planes, the Alé and Al7 address lines from Ul (pins 38 and 39) must be decoded. 8-91ope coneron CHASSIS GROUND ‘TVPES7 mcoRIBeON CONNECTOR TAOPrENX PRY S850 Figure 2-2. GPIB Connector Panel 24.3 GPIB Interconnection The only interconnection required for GPIB operation is between the analyzer and the controler. This interconnection is via a special GPIB cable. The WILTRON Part number for such a cable is 2100-5, -1, -2, or -4 (0.5, 1, 2, or 4 meters in length). 24.4 GPIB Address The analyzer leaves the factory preset to address 5. If a different address is desired, the ADDRESS switches on the GPIB connector panel (Figure 2-2) provide for selecting any address number between 0 and 31, Figure 2-3 shows how to select an address number. 6407/6409 OMM Figure 2-3. Address SelectionTSence nuw vo on Lok TOLINE FREGUENCY ‘TMNG T9 eS ronesy PRocess| Figure 8-73. Phase-lock Loop Circuitry BN a wnt. —%o <| ri oe veryecron vids, Figure 8-74. GDP Syncronization Pulses Figure 8-76. CRT Driver Board Lo + contre P oMnoes ssc, |rompiron Figure 8-75, 8-90 GDP Interface to Monitor 6407/6409 OMM24.5 Data Delimiting Data is delimited on the GPIB by either the carriage return (CR) ASCI character or both the carriage return and line feed (CR/LF) ASCII characters. The 6400 software accomodates either character automatically. 25 PREPARATION FOR STORAGE ‘AND/OR SHIPMENT Paragraphs 2-5.1 and 2-5.2 give instructions for preparing the analyzer for storage or shipment. 2-5.1 Preparation for Storage Preparing the analyzer for storage consists of cleaning the unit, packing the inside with moisture-absorbing dessicant crystals, and storing the unit in a temperature environment that is maintained between ~40 and +70 degrees centigrade. 2-5.2 Preparation for Shipment To provide maximum protection against damage in transit, the analyzer should be repackaged in the original shipping container. If this container is no longer available and the analyzer is being returned to WILTRON for repair, advise WILTRON Customer Service; they will send a new shipping container free of charge. In the event neither of these two options is possible, instructions for packaging and shipment are given below. 24 Use _a Suitable Container. Obtain a corrugated cardboard carton with a 275-pound test strength. This carton should have inside dimensions of no less than six inches larger than the instrument dimensions to allow for cushioning. Protect the Instrument. Surround the instrument with polyethylene sheeting to protect the finish. Cushion the Instrument. Cushion the instrument on all sides by tightly packing dunnage or urethane foam between the carton and the instrument. Provide at least three inches of dunnage on all sides. Seal the carton by tape or an Seal the Container. using either shipping industrial stapler. Address the Container, If the instru- ment is being returned to WILTRON for service, mark the WILTRON ad- dress and your return address on the carton in one or more prominent loca~ tions. For international customers, use the address of your local representative (see Table 2-1). For U.S.A. customers, use the WILTRON address shown be~ low: WILTRON Company ATTN: Customer Service 490 Jarvis Drive Morgan Hill, CA 95037-2809 6407/6409 OMMThe other interface requirement is to the phase lock circuitry on A6. This circuitry compares the frame rate generated by the GDP with the line frequency (Figure 8-72), and provides a voltage to tune the clock for the GDP. This tuning voltage enters the board (Figure 8-73) through R40, the test jumper, and R38, C39, and L1 to the varicap, CR4. “In the absence of a tuning signal, the test jumper enables the oscillator to run at approximately the correct frequency. Verne Figure 8-72, Phase-lock Loop Circuitry: Ab to AT Those components preceding the varicap provide loop stability by filtering extraneous noise from the tuning signal. The clock signal is squared and buffered to the rest of the board by U43 and U3A. This signal is used to set the pixel clock. After dividing down, it also sets the main GDP clock (2 x Worn ¢. GDP _Interface_to the CRT. The GDP produces the synchronization pulses HSYNC and VSYNC (Figure 8-74). These pulses are buffered (VSYNC is also inverted) by U8B and UI3B before going to the CRT driver PCB. 6407/6409 OMM Three planes of video are combined and mixed with a synchronized blanking signal (Figure 875). The blanking from Ul is synchronized to the actual clocking of the video data. This compensates for logic delays which could cause spurious display data to appear at the screen edges. This synchronization is per- formed by combining the blanking signal from Ul with the enable signal, which loads the video shift registers, at U6B, This combined signal is then gated with the three video signals by U13, and mixed at various video levels with R6 thru RM, CRI thru CR3, and R22, This mixed video is further ampli- fied by Q1 and Q2, which is biased by R29 thru R30. The signal is then buffered by Q4 before going to the CRT section (edge connector pin 25), The signal is further mixed with composite synchronization signals through U4 to provide composite video by Q3, R31 thru R33, and C13, which goes to the edge connector pin K, The ground is also taken to the surrounding edge connector pins. Figure 8-76 shows the signal flow to the CRT via the monitor driver board. The CRT and its associated PCB are not field reparable. Memory Access. All memory access is performed over the 16-bit bus ADO thru ADI5, Memory is read into Ul, processed, and sent back over the same bus. This bus contains both data and address information. Information flows from Ul (address information on ADO-AD15) to U15 (Figure 8-77), which latches in the high order addresses (AD8-AD15). The addresses are multiplexed by U16 and UIT to form the memory address bus MADRO-MADR7. Resistors R12, R2, R3, R13, RS, Rid, R38, and R39 prevent this high speed, multi- plexed, address bus from ringing. 8-89Table InEECMouca sn tees eioran fenelee (usr erv0, Feepre aes Foca ates eo Fete ozs ES omian Sans ‘lcs aeLcrex Teper 554200 Elven Sune, Da Teton 207138 6407/6409 OMM 2-1, WILTRON Company International Sales Representatives ‘Teoptone: 358) 5281 Fc sae ee ee Foren (Ghocheae Steen tae See eae csermay Saigate sinermonsenvces Pr. Tavestatsowortw Srauelsemnenes 10 Srestne Sateen od, Jateesoonant er Posto Tem ice Acai ELETROMUCEONICA SA Pesan de Root 2146 ns eer aes eee ue Saensonetan Ma Bg. F, Minos Yio Seca Be meen re =e Peet’ Tnpone tone? Faoapraaeie ‘cox rina) Toes tae new ZEALAND SEMRGAS cccrowe ‘cor: exo A ncLEON Aine Noweowet sameeren See Remesenracones Eivzoheres ira Stare 2758 =a ELSerrOMIeCQUPUENT Maawerma co. Po Serr, pay, 1481 pare (rere ERGAPONE exccrrowes Steneenneleaats Puevecrnonics 9 onan Srey 208 Foxit 706 807 Tetons Facey saree a2) ‘Sason Soca) MiEeavoxa Teter Teva ore npr Tecate Gh8125 Zatncrg fuecscestese Facey se ‘ab Tema 1 ee ea Eten ineer Saat! Saecasvaen ase Jawestsoag Bsmt sp 2-5/2-687.7 AT Graphic Display Processor (cP) The GDP generates video timing, reading and writing from the three memory planes, memory refresh, and the contin- ual process of reading out each line of information for display purposes. The A7 block diagram is shown in Fig- ure 8-80. The parts locator diagram and schematic are shown in Figures 8-81 and 8-82. Unless otherwise directed, refer to the block diagram (Figure 8-80) for the following circuit descriptions. a. General. There are three memory Planes on A7. Each plane is capable of providing 512 by 512 pixels (or other equivalent format). Since each memory plane needs to be lé-bits wide for the GDP, each memory plane consists of four memory chips, with each chip containing 16k x 4 of memory. The memory chips are comprised of U30 through val. All access to the AT? PCB and memory is through ports. The CPU (A6), however, cannot access the GDP memory directly. The reading and writing process on AT occurs only as instructed by the controlling microprocessor, Ul. The clock for the GDP is controlled by the phase-lock circuitry from A6. The clock is generated on A7 by a voltage tuned oscillator, with the video frame rate being returned to A6 for comparison and locking to the mains frequency. With this procedure, the display update is synchronized to ensure a stable display. 8-88 The video and timing signals are further processed to provide a com- posite video output (for external monitors), and a mixed video signal and timing signals for the 6400 CRT. GDP Interface to AG. The Ul GDP TC performs all timing, update, and accesses to video memory functions necessary to form a graphic display. The CPU informs’ the GDP of types of graphic commands and coordi- nates. The GDP then carries out those commands. The interface between A6 and AT (Figure 6-71) is through two ports: one Write port for commands and one Write port for parameters. In order to examine the status of the GDP at any time, one of the ports can also be read. The port to be accessed is determined by AO. AO is read if RD is LOW, and written to if WE is LOW. This information is mapped into the microprocessor's port map by U2, which gates the read and write lines with the port block--in this case, the port block is TOSELg which makes ports 60H to 6FH provide access to the GDP. Figure 871, CPU Access to GDP 6407/6409 OMMFigure 8-70. A6 CPU Schematic (Continued) 8-87Front Panel Operationme aes A B c Oo os, Ecioce ss rare ve 3 F GS + AS Stone SEE] me l & | | 4 & | Figure £70. Ab CPU Schematic 6407/6409 OMM Changed: August 1990uonesedo faued jossTO AB GPIB OPTION (IF INSTALLED) DECODING U7, U8 AIS ANS: g, 28 ‘COMPARATOR ails) ur u22, U23 IcLock cinourt MIcRO- INTERRUPT — Ut2A BUFFER PROCESSOR PRIORITY WNTOINT? ENCODER/BUFFER uz4, utc & D WAIT-STATE, BUFFERS ua, UN x1 15 Miz ue OSCILLATOR EPROMS U13, U14, U15, UI, U19, U20 POWER.ON RESET R1,C1, CRE BATTERY BACKUP, CIRCUIT 21, 01-04, Uza, O5 PHASE LOCK LOOP. CIRCUITRY 2s, U26, U3 LINE TICK FROM A7 AND A10 TO VTO ON AT Figure 8-68, A6 CPU Block Diagram 8-853-1 32 33 34 365 SECTION Ill LOCAL (FRONT PANEL) OPERATION Introduction « Control Panel Controls «++ 3-21 CRT Displa 2 SYSTEM FUNCTIONS Keys ae 3 NETWORK ANALYZER Keys and Indicators « 4 DATA ENTRY Keys and Knob. 5 6 HARD COPY Keys . 6 SOURCE Keys and Indicators wseeseee 3-27 GPIB Key and Indicator «++ co 3 Rear Panel Connectorsesseeeeeee Goccoga 3 Measurements With RF Analyzer s+.s+ on 3-12 34.1 Transmission and Return Loss Measurements ++. 3-12 34.2 Absolute-Power Measurement. 3+16 3-43. Alternate Sweep Measurement. 3-16 Operational Checkout .sseeee 3-16 Error Messages+s+++ 3-24 6407/6409 OMM ContentsUiMAnannninamoanonnnonnnonanh Figure 8-69. A6 PCB Parts Locator Diagramstrument on and off. hen Pressed to ON, it initiates fbn instrument seit test, Duwossirr: rsjests tne tne Qerriene overt: turns se Drew w/.00n seitens dover JSELECT: Implements the so Tected menu option, when its use Ts Indicated by ‘Instruce ‘Hons on the CRT. JA Connector: Provides input for Channel Ay De meter, Proves trout Dee ower: terme tne 6 ‘output is unleveled. re arrur commoctor: Provides JSOURCE Keys and Indicators: Control AF source functions: Refer. to paragraph 3-2.6 for Geral led key descriptions. @uro corr Keys: inistares a erie steer and Key Key Oe Enter numerical deta. Refer fo paragraph 3-2.4 for de- Falled key descriptions. omen OOF: Turns ne in~ (GIMEVELED: Lights wien the ame ereezes te sate, shin cen then be manipulated (1) by ageing or “changing Limit for marker values or (2) by changing offset or resolution Values. Inicetor Is II while ‘the deta ere frozen, which occurs when the HOLD. ot START PRINT “keys are ac: vated, @rervere panurzen Keys and @svsren ewcrins cays Seve ]ORT: Displays Channel A and B traces, network analyzer fond RF souree parameters, and Control and cel oration henus, Refer to" parsgresh 3-2,1" for a detatied descrip Fon, Figure 3-1. Model 6409 RF Analyzer Front Panel Controls 6407/6409 OMMTo set the U3B control latch, the microprocessor writes a data byte to port 40H, with data bit DO set to 1. This enables the U3A interrupt latch, To reset the U3B control latch, the microprocessor writes a data byte to port 40H with data bit DO set to 0. This disables the U3A interrupt latch and resets the INT) line to its inactive state. On initial power ON, Ri4 and C4 perform a hardware reset to the U3B control latch. h. Phase Lock Loop Circuitry. This circuitry, in conjunction with other circuitry on the A7 PCB, controls the frequency of the voltage-con- trolled oscillator (VCO) A7U3. The phase-lock loop (PLL) circuit con- sists of U25A, U25B, U26C, U2? and associated circuitry. The two J-K flip flops U25A and U25B (Figure 8-67) are used as a phase/frequency comparator. The comparison is between the VSYNC signal form the Graphics Display Processor on A? and the line fre- quency (provided by the tick signal). The signal at the junction of RIT and R18 is a mixture of the two Q outputs of the comparator. When the VSYNT signal is in phase with the tick signal, the pulse train at this junction has a mean value of 2V. This value is half way between TTLI and TTLO. The output of U27 stabi- lizes as the integrator R19 and C27 smooths the signal to its mean value. If the inputs are out of phase, the voltages vary in such a way as to cause the output of U27 to move in a direction that will ultimately bring the two input signals back in phase. Links, Three links are provided in the circuit. Links 1 and 2 are hard-wired and no longer used. Link 3 allows isolation of the battery when the Aé PCB is in long term storage. The current drawn from the battery during standby mode is, typically, less than 100uA, aw. meso? “ Figure 8-67. Phase-Lock Loop (PLL) Circuit 6407/6409 OMMSECTION Ill LOCAL (CONTROL PANEL) OPERATION 3-1 INTRODUCTION This section describes the operation of the Models 6407 and 6409 RF Analyzer using the control panel controls. It describes the controls and rear panel connectors; how to make transmission, return loss, power, and alternating sweep fneasurements; and’ how to check that the instrument is operating properly. 3-2 CONTROL PANEL CONTROLS Operation of the control panel controls is described in Figure 3-1 and in paragraphs 3-21 thru 3+ 3-21 CRT Display (Figure 3-2) The CRT displays the measurement traces and the present settings for the NETWORK ANALYZER and frequency SOURCE con- trols: a. CRT Screen: Displays (1) either the respective outputs of channels A and B on traces A and B, (2) the Channel A signal alternating between traces A and Bor (3) the Channel A signal on trace A alternating with the Channel B sig- nal on trace B. See Figure 3-19 on page 3-11 for a description of the alternating sweep mode. b. NETWORK ANALYZER Settings: The two lines labeled “A” and "B" across the top of the screen display the type of measurement selected and the offset and vertical resolution values set for traces A and/or B. c+ SOURCE Mode Selection: The source mode is displayed in the box in the top-right side of the screen. This box displays "SWEEP" when a normal sweep has been selected, "ALTERNATE SWEEP (A) (or A,B)" when an alternat- NETWORK ANALYZER—ol 2! ZrstEtESIOY SETTINGS ae Hig Litt ———— UNE } ‘TRACE A IDENTIFICATION” i AND REFERENCE LINE \ Low uM UNE source sermnas——ef Siti, Hg SE Trace 8 IDENTIFICATION I h. eed EES, | source move G—wessace Anca Figure 3-2. CRT Display 341Figure 8-66. Line Interrupt Circuit turns on. The CMOS STDEY line is pulled LOW, inhibiting the RAMs and turning off Q2 and Q3. This action turns Q1 off, isolating the RAM chips from the main 5V supply rail. Standby current, at a reduced voltage, is then supplied to the RAMs from the battery. Resis- tors R4, R5, Ré, Ril, and R12 provide biasing for the transis- tors in this section. Line Interrupt. The line interrupt Circuit enables the microprocessor to schedule operations with refer- ence to a real time stimulus, or tick signal. This squarewave tick is obtained from one of the secondary windings on the power supply trans- former. The line interrupt circuit 8-84 consists of U3A, U3B, U6aA, and associated components. A simplified schematic is shown in Figure 8-66. The two major components of this circuit are the interrupt latch, U3A, and the control latch, U3B. When the U3B control latch is set (Q output HIGH), any rising edge of the tick signal sets U3B to its active state. The TNTp is then held LOW. The circuit will remain in this stable state, with the inter- rupt active (regardless of what happens at the tick input), until the microprocessor clears the condition. The clearing is done by resetting the U3B control latch to both clear and disable the interrupt, then setting it again to re-enable the latch. The latch is now ready for the next rising edge of the tick signal. 6407/6409 OMMing sweep has been selected, "RF OFF" when the RF output has been turned off, or "HOLD" when the instrument is in the HOLD mode. [el al) a. SOURCE Frequency and _Power_and Horizontal Resolution (GRATICULE) ~ Settings: The three Tines along the | Figure 3-3. SYSTEM FUNCTIONS Keys bottom of the screen display the () source start/stop frequencies, The SYSTEM FUNCTIONS keys are describ- (2) alternate sweep start/stop fre- ed below. (3) BF power setting and horizontal @ SAVE/RECALL Key: Displays a mena resolution (GRATICULE) of the (Figure 3-4) that lets the operator displayed traces. SAVE the current control panel setting or RECALL any of nine stored front In the normal-sweep mode, the horizon- panel setups. The MENU rocker switch tal resolution and intelligent-graticule (Figure 3-1) is used to make the selec divisions are automatically chosen for tion. Should this key be pressed and optimum display of the selected fre~ then not wanted, the DATA ENTRY Gheney sweep width. CLEAR (Figure 3-10) key can be used to cancel the key action. In either of the two alternate-sweep modes, the graticule is fixed at 10 vertical and 10 horizontal divisions. b. SELF TEST Key: Initiates a self test of the analyzer. If the analyzer func- 3-22 SYSTEM FUNCTIONS Keys tions properly, the screen displays "ALL (Figure 3-3) TESTS PASSED." If the self test re- Description Nossage Descript ton ENTER MEMORY | Enter 9 number on The SAVE/RECALL | Selecting RECALL allows: ae NUMBER keypad. recall of any of #h0 (29) nine stored setups, using © Menu 2 = Recalt umber entered via the key= pad. See Menu 2. Message Deseripti save Selecting SAVE store & number for the contro! pane! save use 4 rien | setup to be assiqnes vie me ress! sexect | keypac. Ses Manu 3. ENTER WEMORY | Enter a nusber on the om weyeod. Meow 1 “te % Meow 3 ~ Se Figure 3-4. SAVE/RECALL Key Menus 32 6407/6409 OMMFigure 8-64. Microprocessor Control Circuit aoe 6407/6409 OMM Figure 8-65. RAM Control Circuitveals a problem, the screen displays a failure message instead. Also at the end of the self test the screen displays the GPIB address, if Option 3 is fitted. c. RESET Key: Displays a menu (Figure 3-5) that lets the operator use the MENU SELECT key (Figure 31) to restore the factory-selected control panel settings. The settings for the 6409 and 6407 (in parenthesis) are shown below. Channel A: TRANSMISSION Channa! A: OFFSET: 0,0 03 Channel A: RESOLUTION: 10 a8/Division Channs! 8: Channel 8: Channel 8: RESOLUTION: 10 oB/Division Source Mode: Norma | SwEEP START Frequency: 10 Hz (1 siz) STOP Frequency: 2000 Miz (1000 MH) POWER LeveL: 10 d8m SMQOTHING: OFF FREQUENCY DATA POINTS: 201 32.3 NETWORK ANALYZER Keys and Indicator (Figure 3-6) The NETWORK ANALYZER keys and indi- cator described below are the same for both channels A and B. Generally, should cone of these keys be pressed and then not wanted, the DATA ENTRY CLEAR (Figure 3-10) Key can be used to cancel the key action. ECT] Press the MENU SELECT key to r To RESTORE | store the factory selected con Deraucts | trol pene! se*singse 163 the OATA ENTRY CLEAR key to return to the measurement nooo cALieRaTioN | Col iorarion gate is not attected DATA 15 NOT | By The RESET key, AFFECTED Figure 3-5. RESET Key Menu a. DISPLAY ON/OFF Key and_ Indicator: Key turns its associated trace and 6407/6409 OMM NETWORK ANALYZER. Do of TF in OO ww oeo Cera FO Oo wel) a ie Figure 3-6. NETWORK ANALYZER Keys and Indicator limits/reference line on or off. The associated indicator is lit when the trace is on. MENU Key: Displays a menu (Figure 3-7) that lets the operator select the measurement type, set test limits, or move the reference line. AUTOSCALE Key: Sets the associated trace at optimum offset and resolution values for viewing the measured data. OFFSET/RESOLUTION Key: Displays a menu (Figure 3-8) that lets the opera~ tor select OFFSET or RESOLUTION. CALIBRATION Key: Displays a series of instructions (Figure 3-9) that guide the operator through a calibration cycle. UNCAL Indicator: Lights when either measurement trace is uncalibrated. BEGIN Indicator: Lights at the begin- ning of a calibration cycle and remains lit until the cycle is completed. SMOOTHING Key and Indicators: Key provides two levels of filtering, MIN and MAX, that improve the display at low-signal levels. OFF indicator is lit when no smoothing (low-level filtering) is supplied. 33Table 8-12. Port Block Description Port Block Name Used On Signal Channel Signal Channel Control Panel (not used) CPU (Tick) GPIB/Centronics GDP (not used) 8-82 lines INT) to INT] is LOW. These lines are encoded’ in priority by U23, with TNT having the highest priority. Three bits from U22, together with the enable line from U23 (pin 15), are buffered onto the data bus when enabled by the inter- rupt-acknowledge line (TNTA) from Ul. This forces the microprocessor to perform a special routine for the active interrupt. Battery Backup. The battery backup circuit saves the contents of the RAMs when the primary power source fails. This circuitry is divided into two sections: LP con- trol and RAM control. 1. UP Control. This section stops the uP from making any further memory accesses when a power failure is detected on the 5V rail. It consists of micropower comparator U28, transistor Q5, and associated components (Figure 8-64). Micropower comparator U28 senses a threshold voltage that is set by resistor chain R24, R29, R25, and R26. Normally, when the supply voltage is above the threshold level, transistor QS is turned off and the RESET input of U2 is held to a logic HIGH by RI and Cl. When the supply voltage falls below the threshold value, Q5 turns on, discharging Cl’ and pulling ESET to logic LOW, thus inhibiting the RIN pin on U2. R28 provides current limit- ing and R27 provides sufficient base drive current to that Q5 turns on properly. RAM Control. This section, upon detecting a power failure, supplies an inhibit signal and a reduced, battery-supplied vol tage to the RAMs. It consists of microcomparator U21, transistors Ql thru Q¢ and’ associated components (Figure 8-65). Micropower comparator, U21, senses a threshold voltage set by resistor chain R7, R30, R8, and R9. Normally, when the supply is above the threshold voltage, transistor Q4 is turned off. The TMOS STDBY line is HIGH, enabling the RAMs, and turning on Q2 and Q3. These two transistors then turn on transistor Ql, which connects the main 5V supply rail to the RAM chips, and trickle charges the battery through R13. When below the the supply voltage falls threshold value, Q4 6407/6409 OMMMessage, CHANNEL (A or 8) set MEASUREMENT TYPE Description Selecting SET SUREMENT TYPE displays Menu 2, which offers measurement choices. Messoae, Deserip! CHANNEL (A or 8) TRINSMISSION | Measure transmission loss RETURN LOSS Measure return loss. POKER dBm Measure absolute powers CAL DATA Display the calibration dete A presestly stored in memory. use 4 THew Press SELECT Mon 2 Message, Description hanna (A or By Selecting eltnor HIGH LIMIT for LOW LIMIT displays 3 Gashed horizontal Tine Selecting SET TEST Limits ————» Hic Limit | thor may be used to delineate 34 ser Gisplays Meny 3, whleh OFF or wx 68 | 9 68 value beyond which the test Limits | provides tor setting limit easurenent is unacceptable. Vines. Ether or both limits can 0s Low timit | selected, and their values set Selecting SET REFERENCE LINE OFF ar xxx 08 | can be set to 199.9 08 REFERENCE LINE | cisplays Menu 4, which sing the DATA-ENTRY keypad al lews for moving the refer To TuRN or rotary knob, In 0,1 38 ence lines Limi7s onsorr | Increments. use THEN PRESS ENTER’ ress 'sevect i Use the DATA ENTRY ENTER key Menu use 4 Ten [to turn timits off end one ress "scvect Monu 5 Message Description ‘CHANNEL (A or 8) | Use the DATA ENTRY rotary knob fo reset the REFERENCE REFERENCE LINE igure 3-2) to an- LINE: other graticuie lines The Feterence line is the point USE KN08. Shout which the trace ex TO AL pends vertically with gif SI T1ON ferent resolution values; it can be set to any gravicule Tine, Press DaTh ENTRY Hew CLERR 70 return to the press cuemr | neasurenent mode, Menu 4 Figure 3-7. Channel A/B MENU Menus 6407/6409 OMMTable &-11. Aé Memory Map Block Address ue ‘Memory ‘Type 0000H-IFFFH 13 2764 EPROM 2000H-3FFFH ul4 2764 8K EPROM 4000H-SFFFH v5 2764 8K EPROM 6000H-7FFFH vUl6 2764 8K EPROM 8000H-9FFFH vir 6264LP 8K CMOS RAM A0O0H-BFFFH UIs 6264LP 8K CMOS RAM (C000H-DFFFH vis 2764 8K EPROM EQ00H-FFFFH 020 2764 8K EPROM (personality) lines to a preset value correspond- the buffers.) When the buffer is not ing to a one byte instruction for enabled, the external data bus Ul. This makes the microprocessor contents are not defined. free run through all the address space so that address lines can be The low order address lines are checked and verified. buffered to the rest of the instru- ment by Ull, which allows further The Aé Memory Map is shown in decoding of the port blocks. These Table 8-11. Access to the lines are also valid during a port memory chips is standard design. access, but are undefined at other Each chip has a separate block times. select line that is provided by U5. US decodes lines Aj3 through Ayg Port block decoding is accomplished from Ul into & blocks of memory. by U7, which provides eight lines, TOSETg through TOSEL;. The port The output enable of each of the block description is shown in Ta- memory chips is controlled by the ble 8-12. READ line (RD) from Ul. The two RAM chips, U17 and U8, also use a All port block select lines are separate supply line and chip select active LOW. The sweeper control to allow the battery backup function board (A4) decodes its own port to save the contents of the RAMs in selects in the range 80H to BFH. case of failure of the primary power The signals required to do this are source. buffered by U8 and comprise 10/M (In/Out/Memory), WR (Write), PSB 4. Buffering. The data bus is buffered (Port Strobe) and ED (Read). These to the rest of the instrument by lines are LOW to indicate Memory U9, a bidirectional buffer. The access, Write, Port Strobe, and Read direction of drive is controlled by respectively. The PSB line is RD or the buffered Ul RD line, and is WR gated with IO/M and is LOW enabled only during port accesses. during any port access. These lines This buffering ensures no bus con- are active for periods of less that flict on the A6 PCB, since all ports 1S at a time. are external to this board and no memory exists off the board. (The e. Interrupts. There are cight inter- tick control port, discussed later, is part of the board, but is external to 6407/6409 OMM rupts supported by the AG PCB. An interrupt is generated if any one of 8-81Message, Description CHANNEL (A or 8) | Selecting OFFSET provides for using the keypad or rotary knob to set the value of the reference Tine (Figure 3-2). Values tron 0,0 d8 40°259,9 8, in incre= hments of 0.1 dB, are possible, Selecting RESOLUTION provides for using the keypad or rotary knob to set the display vertices! resolution, Values tron 0,1 40 10d, in increnents of Ort RESOLUTION , s 4B, are possible wien using the keypad. The rotary knob si lows ej ustments in Gore oat [tree syend|5|caivalees 1 JENU rocker switen to make selection use + Use MENU rocker 5 . Figure 3-8. OFFSET/RESOLUTION Key Menu Calibration Is the process whereby losses inherent in 2 transmission or return toss meesurenent system ere meesured, stored in internal sonory, end later subtracted so that the results. isp layed ere those of the test device, minus residual losses. Pressing the CALIERATION key. initiates. the following sequonce ot menus when the Channel A trace hos bean selected to display transmission loss ‘or gain end the Channel 8 trace return loss, Inportent: Set output power forthe desired fevel Before beginning the calibration sequenc Hossag Description CALIBRATION Places the network analyzer section in the caiibration mode. one PRESS SELECT Press the WENU SELECT key (Figure 3-1) to display the first 0 BEGIN calibration menu. CALIBRATION PRESS CLEAR Press the DATA ENTRY CLEAR Key to return to the network analyzer To RETURN To section to the measurenent mode laet exited, At inis pointy the MEASUREMENT eslitration data nas not been sitected, oD ‘TRANSMISSION Connect the RF Input port on the SkR Autotester to the AF OUTPUT CALIBRATION. port on the sweep generator. Connsct the RF detector between connector A and the Test Port on the SHR Autotesters A sore DETECTOR To Woon only transmission loss TS being measured and the SHR TEST PORT Autorester Is not being used, the Test port called out in ‘the menu lz the port fo which the test device connectss. In most"eases, It will be the RF OUTPUT port on the analysers PRESS SELECT WHEN READY Press the MENU SELECT key to store the residue! losses Inherent in both the getector and the connection, CALIBRATION Key Menus (Page 1 of 2) 6407/6409 OMM 3658-7.6 AG Microprocessor PCB The A6 microprocessor PCB is the central processing unit (CPU) for the 6400. This section describes the A6 PCB's memory processing functions as well as other functions performed on the A6 board, including: 1. An interrupt interface, which pro- vides support for eight prioritized interrupts. The first stage of the phase-locked loop, which controls the clock for the graphic display processor (GDP) on the AT PCB. Figures 8-68, 8-69, and 8-70 show the Aé block diagram, parts locator diagram, and schematic, respectively. Unless otherwise directed, refer to the block diagram for the following discussion. a, General, The Aé PCB contains the instrument's microprocessor and program memory, including the personality PROM and non-volatile memory. The latter is sustained by a battery backup circuit. The board memory occupies the addresses 0000H to FFFFH (64k) in 8k blocks. Higher addresses are not decoded and over- lay the first 64k. For example, an attempt to access address 10000H will actually access address 0000H. A troubleshooting function is pro- vided to isolate the microprocessor from all memory so that data lines can be analyzed. A lé-pin DIL test header can force the data bus to contain a one byte instruction at all times. This frees the micropro- cessor from memory contents and addressing integrity. All instrument PCBs interface to the microprocessor through ports. To minimize hardware on each board, block decoding of the ports is per- formed on the Aé PCB. Eight In/Out select lines (TOSELg thru TOSEL;) are sent out from A6. Each line pulses LOW when data is provided or expected from a port in the range of that line. Not all of these ports are used. 8-80 Clock. The microprocessor, Ul, runs at a frequency determined by crystal Xl. This crystal forms a simple oscillator with U2, The output of the circuit is the crystal frequency divided by three. The Power-on Reset is formed by Rl, CR4, and Cl and has a time constant of one second. CR4 pro- vides a rapid discharge path for Cl, ensuring that a reset occurs in the event of brief power losses. The clock shape and time period can be measured at TPI. The clock is buffered for external use by U12A. This output appears at P8, pin M. This clock output is used by the AS GPIB board, if the GPIB option is installed. Because of the long interface length to some PCBs, one wait-state is provided for all port accesses (to external boards) by U24 and U10C and D. This extra clock cycle, or wait-state, slower exchange of control compensates for the signals and data, One clock cycle is in- serted in the read or write line when the In/Out/Memory (10/M) signal is HIGH, as it is for port activity. The low order thru Ag, are the data ‘lines. Address and Memory. address lines, Ag multiplexed with These lines are separated by U4, which latches in the address lines using the Address Latch Enable (ALE) lines on Ul (pin 25). The address lines are buffered to the rest of the board through U4, and to the rest of the instrument through ul. The unseparated data bus, ADg thru AD), is taken directly to all the EPROMs and RAM, U13 thru U20, through the 16 pin DIL test header. In normal use, the test header connects across the eight data lines. For test purposes, a header can be installed that pulls the data 6407/6409 OMMMessage TURN LOSS CALIBRATION ‘STEP 1 ‘CONNECT sw AUTOTESTER 70 CHANNEL 2 CONNECT OPEN 0 TEST PORT PRESS SELECT Connect the SW Autorester to connector Connect the end of the Model 22N Gpen/Short Iabelee OPEN" to" the Test Porton the SuR Autotester, Press the MENU SEI oT key to store the measurement results. WHEN READY RETURN LOSS. CALIBRATION STEP 2 REMOVE OPEN Reverse ends on the Mose! 22N Onen/Short. ‘NO CONNECT SHORT Press the NENU SELECT key to store en average value of the open ang To Test Port short masuranants, Interns! software hes averaged the losses mecsured then the open was installed with those measured when The shor? was. (n= PRESS SELECT Stalled, WHEN READY ‘CALIBRATION. ‘COMPLETED The calibration cycle is now complete, The losses Inherent in the SHR Auto tester, Type Noto-N Adapter, ond RF detector hove been measured end stored. connect In all tuture nensurenents of test devices et this level of output power, Test DEVICE these losses will be subtracted trom measured losses; consequently, 7he results displayed will bs those of the test device minus resicualss PRESS SELECT WHEN READY 3-6 Figure 3-9. CALIBRATION Key Menus (Page 2 of 2) 6407/6409 OMMc. Filter, The filter prevents YIG- produced harmonics from mixing with the local oscillator of the down converter. 4. Down Converter and Marker Pack. The down converter produces the correct 6400 operating frequency and the marker pack generates the harmonic comb used to correct swept output frequency. Also contained in the down conver- ter is a PIN modulator that pro- vides power leveling for the RF output, The PIN modulator is a current-contro} led variable attenua~ tor. A simplified schematic of the PIN modulator is shown in Fig- ure 8-62. Attenuator. If fitted, this option provides up to 70 dB of attenuation for the RF output. The drive cur- rent for the attenuator is supplied by a cable from the Ad sweep PCB. A simplified attenuator diagram is shown in Figure 8-63. Re output 1] mao common Noo Bus HD) we meu Figure 8-62. PIN Modulator in Down Converter ATTENUATOR DRIVERS FROM Ad SWEEPER —_———, c 7 our 208 20 dB 106B 2068 [ATTENUATOR SECTIONS Figure 863, Attenuator Option 6407/6409 OMM 879DATA ENTRY fe) «4 o «OO OomAmaw mAmomap Figure 3-10. DATA ENTRY Keys and Knob 3-24 DATA ENTRY Keys and Knob (Figure 3-10) The DATA ENTRY keys and knob are described below. a. Knob: Alters measurement values. b. Keypad: Enters measurement values. c. ENTER Key: Terminates data entries made from the keypad and provides on/off control for limits (paragraph 3-2.3b) and markers (paragraph 3-2.6e). a. CLEAR Key: Clears an entered value, if pressed before the ENTRY key. This key can also be used to clear a dis- played menu. 32.5 HARD COPY Keys (Figure 3-11) The HARD COPY keys are described be~ low. on Figure 3-11. HARD COPY Keys 6407/6409 OMM. a. MENU Key: Displays a menu (Figure 3-12) that lets the operator select between printing either the graphic display or a tabulation of the measured values. b. START PRINT Key: Freezes the dis played data and starts printing it. The type of printout then obtained, graphic or tabulated, is based on the last MENU key menu selection. c. STOP PRINT Key: Stops printing the data immediately. Messoge Description ARO coPY we print onsen | Selecting PRINT GRAPH prints the on-screen graphic when the MEM SELECT key 1s pressed. tanuar: | Selecting one of the tabulor 26 Points | options srints out a dare rab- 51 POINTS | ulation et either 26, 51, 101, 101 points | 201 or 401 trequency points. 201 POINTS 401 Points MARKERS ONLY] Selecting MARKERS ONLY prints dete only at the marker tre~ quencies. Figure 3-15 shows samples ot har use 4 tien | pressing SELECT starts the ress’ sevecrl printings Figure 3-12. HARD COPY Menu 3-2.6 SOURCE Keys and Indicators (Figure 3-14) The SOURCE keys and indicators are de- seribed below. Should one of these keys be pressed and then not wanted, the DATA ENTRY CLEAR (Figure 3-10) key can be used to cancel the key action. 378-7.5 RF Components Deck The RF deck contains the components necessary to generate sweep- and CW- frequency RF signals. The overall RF deck block diagram is shown in Fig- a. Oscillator. The YIG oscillator generates swept or CW RF signals. Isolator. The isolator prevents reflected RF energy from returning to the YIG and causing frequency tre 8:60. The BF deck interfaces to the pulling. Mt Sweeper PCB. as shown in. Figs ure 8-61. Dc Converter Attenuator : own Conver oat _ Fer eatstorPek ——eptone 1 1 ron a! 1 ' x 1» «138m 1 ' L a irs ae (0-31486 (6409) ~ (C-31465 (6407) Figure 6-60. RF Components Deck Ml & | Ef, gl E IE g ner «| Gea FIT ELE eT fig pels sae Gew fucox ones) vont a) ssusuemy psa rea] Loe ses wit ev pal entries Figure 8-61. RF Deck/Ad PCB Interface 8-78 6407/6409 OMMwar arensrea DO RERM OR AETC: iiiiiiil ened eueeeeuaee 6407/6409 OMM Option Printout TABULAR” ‘MARKERS. ONLY" Opt ion Printout Option Printout Figure 3-13. Hard-Copy Printouts (Samples) "PRINT GRAPH 3-82. FREQUENCY WIDTH Key! Displays ounce menu that allows frequency entry oe So (Figure 3-16). Oe e. MARKERS Key: Displays a menu that ee Mowe You teventer he, frequency at smn woffa Sich “the “marker aplaye (Figure Oo x0 3-17). {. FREQUENCY DATA POINTS Key and ae mn Indicators: Key selects 101, 201, oF a 4 Or voltage steps for the digital-aweep ramp. Tae highest number provides the Seer nest frequeney-sweep resolution a. FREQUENCY START Key: Displays a nv Key ' sen that E19) That allows for selecting nor, gu . mal or an alternating sweep mode. > FREQUENCY STOP Ker Diplays @ 4. powER LEVEL Key: Opens the out- aaa jutcpowsr parameter ant allows ‘the . BATA ENTRY. Reyped or rotary knob . to be sael to enter a acw power level ¢- FREQUENGY CENTER Key: Displays © TP Shan “yue he ENTER fey vo ter (Figure 3-16) quency 2 minate the power-level entry. Messoge Description Figure 3-15, FREQUENCY START o STOP Key Menu sesane beseraticn iz | key, thet parsrotar Is open for frequency moditication; the WIOTH parameter can be accessed using the MENU r WIDTH key, the WIOTH parameter is open and the with the rocker switchs The frequency is entered vie the DATA ENTRY keypad or A warning mossage displays it the width entry is too wide. ER parameter can be eccossed ENTER WIDTH «If the menu is 2 result of pressing the Figure 3-16. FREQUENCY CENTER or WIDTH Key Menu 6407/6409 OMM. 3-9o 1 2 | 3 | 4 | 5 6 z 8 9 ecole oe cone es v NOTE: LOCATED ON HEATSIN bey con (ow season Figure 8-59, Ad Sweeper Schematic (Continued) H 6407/6409 OMM‘Messege Description MARKERS MENU wiz onann | 1. Select one of the MI-ME parareters as the active marker, using the MENU rocker 2: anna switch end SELECT key, The active marker, the one currently highlighted, is MB: nana ‘open tor frequency entry or nadification, The power at this point on the A ma: nanan trace, 8 trace, or both, appears In the READOUT (Mx) sree. M5 TO Me 2, Enter a trequency trom the Keypad or change the frequency using the keypad or OUT (x) rotary kaob. Ar nanen ¢8 nnnnn o& | 3, Select M5 TO MB to display © listing tor morkers MS to MB. SELECT FOR ALL MARKERS: or Pressing the MENU SELECT key repeatedly toggles el! of the ¢isplayed markers on and setect FoR | oft, except for the active marker. Pressing SELECT also toggles the "ALL MARKERS" READOUT ONLY | oF "READOUT ONLY" menu entries. PRESS ENTER | Pressing the DISPLAY ENTRY ENTER Key turas the active marker off and ony FOR ON/OFF ALL MI=MB parameters that have been assigned frequencies are cisplayed on the screen as dashed= Vertical lines (Figure 3-18), The active marker, the one currentiy highlighted, nas e caret symbol (V) at Hts tops Figure 3-17. SOURCE MARKERS Key Menus [ACTIVE MARKER CARAT 4s SRE SPST C8 <——___maner Lt Figure 3-18. Frequency Marker Screen Display 3-10 6407/6409 OMMFigure 8-59. A4 Sweeper Schematic 6407/6409 OMM 8-75Mossan Description SOURCE MENU | NORWAL is the single, or non-alternating mode, ALTERNATE Is the slternating sweep nod. ser sweze tee | Selecting NOWAL displays "SWEEP" in the box st the top-right and "START" or YOENTERM end "STOP" or *WIDTAY In the. frequency line under the CRT graticle, Use ‘the FREQUENCY START, STOP or CENTER, WIOTH keys to change The displayed valves. eA Selecting ALTERNATE Input A eisplays "ALTERNATE SWEEP AM" on the CRT and applies the rain and alternate sweeps to Input A. The main swoon displays on Trace Ay vie Chennel A, and te alternate sveep on Trace B, via Channel 6, The sweep linits of acremuare | norm ewoese are shown on the ORT. Use the FREQUENCY START/STOP or CENTER/¥IOTH Input A | Kays Cas appropriate) to change the limits of the elternate sveep. Selecting ALTERNATE Inout A ond B displays YALTERNATE SHEEP A, 8” on tho OT auremvare | ond epplies the main end alternate sweeps to both channels, The Channel A output nout h, 8 | ie associated with the mein sweep and the Channel B ovtovt with the alternate seeep, The main veep displays on trace A und the alternate sveep on trace 8. The use 4 rie | sveop linits for both swooos ere shown on the CRT, Use the FREQUENCY START/STOP or PRESS setect | CENTER/WIDTH keys (as appropriate) 70 change the limits of the alternate sweep. Figure 3-19. SOURCE MENU Key Menu 3-2.7 GPIB Indicator and Key = (Figure 3-21 : om STATUS REMOTE Indicator: Lights when in the eT me Wha ites TALK: @ Associated indicator tights whan pogeee acedcempe Tay nice e LISTEN: © analyzer is respectively talking, 3-21) displays inthe MENU area of the SRO: © listening, generating an SRO, or screen igure 3-2), LOCAL Is In the local lockout or remote LOCKOUT: © node. RETURN TO LOCAL Key: eee (1) If pressed while in the GPIB mode, the analyzer returns to the Figure 3-21. GPIB Status Display local’ mode. This occurs unless the local lockout (LLO) message has been programmed, in which — description case the key causes no action. ‘essoge Sessription (It pressed while inthe local GPIB sant is the Fisten address sunber mode, the analyzer's address ADDRESS set using the rear pane! ADOF displays in the MENU area of the a ee panel HOORESS screen (Figure 3-22). 2 Figure 3-22. GPIB Address Display ew ut 3:3. REAR PANEL CONNECTORS ° oO The rear panel contains multipin GPIB and Printer connectors, the GPIB address Figure 3-20. GPIB Indicator and Key 6407/6409 OMM 31saa Baa = 68 ‘€ Figure 8-58. A4 PCB Parts Locator Diagram 6407/6409 OMMLINE VOLTAGE MODULE: See Figure 2-1, page 22 EXTERNAL CRT OUTPUT Provides composite video to ‘monitor having a type P39 medium-persistence display. ® Video Bandwidth: =25 MHz @ Line Rate: =17 kHz Standard Composite Video Interface Voltage Figure 3-23. Rear Panel Connectors switches, a composite-video BNC connect- or, and the line voltage module. The line voltage module and GPIB connector and address switches are described in Section I; the printer and composite-video connec- tors are described in Figure 3-23. 3-4 MEASUREMENTS WITH THE RF ANALYZER The 6407 and 6409 RF Analyzers can be used to make transmission loss or gain, return loss, absolute power, or alternating sweep measurements. 3-4.1 Transmission and Return Loss Measurements How to make a transmission and return loss measurement is described in Table 3-1; a test setup is shown in Figure 3-24. 3-12 GPIB PANEL:‘See Figure 2-2, page 2-3 PARALLEL PRINTER INTERFACE. Provides standard "Centronic type" parallel interface with WILTRON Option 5 Graphics Printer. SWITCH SETTINGS. Move seLect aay cenmmomesinrenrace f tt WILTRON PRINTER ADAPTER, 'SWR RUTOTESTER berécror device Ed shor “Connect Wnen Directed By Calibration Menu Figure 3-24. Test Setup for Transmission and Return Loss 6407/6409 OMMIe Pees |= — ta See | ae po us 19, ju4us.ue,|_s, cw FLTER yap esse one BER cas itt yspo ‘LOGIC, FoR OAc owreren > ‘bus sof vee fe bs bus Figure 8-56. A4 Sweeper Block Diagram: Digital Circuitry, Decoding, YIG = out tomar Pack »—1 ssweer i —_——— [rey oe] nce] S08 v0 ewpenaune ay t Figure 655. Marker Output to Ad i eet T Figure 8-57. Ad Sweeper Block Diagram: ALC Circuitry 6407/6409 OMM 73Table 3-1. Making Transmission and Return Loss Measurements 1, Connect test equipment per Figure 3-24, except do not connect the test de- vice; turn the printer on. 2. Press POWER on the analyzer to on. At the conclusion of the built-in self test, the screen displays "ALL TESTS PASSED," and the CRT resembles that shown below. Control settings may be different from those shown, which are the RESET control settings (6409). The instrument comes on line with the same control settings it had when last turned off. Ensure that both channels are on and that Channel A is set for TRANSMISSION and Channel B for RETURN LOSS. Screen Display with Factory Selected Control Settings 3. Press the NETWORK ANALYZER CALIBRATION key and follow the directions given in the calibration-cycle sequence of menus. If necessary, refer to Figure 3-9 for an explanation of the menus. After finishing the calibration, connect the test device and RF detector as shown in Figure 3-24. ‘Transmission Loss Measurement 4, Measure the transmission loss, as follows: a. Press the Channel B DISPLAY ON/OFF key to off. 6407/6409 OMM.‘pence F Far Votage Tracing Out [Ee vay 8-72 Figure 8-54. Tracking Output The Temperature Correction and Slope Adjust Circuitry (Figure 8-54) is made up of the U40 quad op amp. Temperature correction is achieved by producing a small voltage that varies linearly with variations in temperature. This voltage is further amplified and split into hot and cold separators by the temperature compensation circuitry. This correction voltage is then summed with the slope control voltage and fed into the Slope and Temperature Correction DAC, U38. The magnitude of the output of U38 is dependent upon the power level requirement of the instrument. Finally the signal is fed through R113 to the summing point at the Level Amp, U42. The slope is ad- Temperature Correction and Slope Adjust Circuit/Ramp Voltage justed by R13. trimming potentiometer Two sections of quad FET switch U45 are used to switch between a 0 to +10 dBm power range of the ALC and a greater than +10 dBm range. Each range requires its own slope and ALC control voltages. The final section of circuitry is the Ramp Voltage Tracking output (Figure 8-54), U4, pin 1. This circuit provides a ramp output to the Marker Pack (A5) to maintain marker width as the power level is varied. The output of the marker pack is fed to the sweeper board through P7. It is then latched and buffered for output to the bus by U52 and US3 (Figure 8-55). 6407/6409 OMMTable 3-1. Making Transmission and Return Loss Measurements (Continued) b. Press the Channel A AUTOSCALE key. This gives an optimum vertical display of the test data. Read the transmission loss by interpolating the displayed graphic as described below, or read it directly using the markers and readout function as described in step 6 In the example shown below, the test device is a 500 MHz low pass filter. “TRANSMISSION LOSS F——-——.TRANS MISSION LOSS ABOUT O48, Taace a peje tf Lites \ Sods \restetey ‘ABOUT 500 Miz By interpolating the display, we see that the pass band begins to drop at about 500 MHz, and that the skirt bottoms out at about 750 MHz. The transmission loss is about 0 dB in the pass band and 66 dB at the bottom of the skirt. 6. To use the MARKERS functions to read the results of the above measurement directly, proceed as follows: 3-14 Press the SOURCE MARKERS key. A menu displays with the M1 marker highlighted. Use the DATA ENTRY keypad to enter 500 MHz for the M1 marker, then use the rotary knob to position the marker at the end of the passband. The frequency at this point displays opposite "Ml." For the above example, instead of being about 500 MHz, it is shown to be exactly 498.91 MHz. 640 al 6409 OMM