2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

Very Low-Cost CMOS Audio Amplifier for

1-V Portable Applications
Cristiano Azzolini  , Antonio Ricciardi  , Andrea Boni 
 Silis srl, Parma, Italy  Dip. Ingegneria dell’Informazione, University of Parma, Italy
e-mail: cristiano.azzolini@silis.it, andrea.boni@unipr.it

Abstract— The design of a very low-cost full-analog audio ampli-
fier IC for hearing aid devices is presented. The overall circuit con-
sumes 460-μA from a 1.3-V battery supply (excluded loudspeaker,
without signal) but the hearing aid is able to operate with a depleted
battery down to 1-V. The nominal THD of the circuit is lower than
1-% at 10-mW output power whereas the input referred equivalent
noise voltage is 3.2-μVRM S .
An effective analog offset cancellation circuit ensures a low quiescent
power consumption in case of strong process mismatch.
The silicon area is as low as 1.5-mm2 in a 0.35-μm CMOS process.
Index Terms— Low-voltage amplifier, class AB amplifiers, CMOS
audio amplifiers, low-cost hearing aid, offset cancellation circuit.
I. I NTRODUCTION
Analog circuits oriented to portable applications usually repre-
sent challenging designs since they are subjected to hard power
constraints: such systems are supplied by low-voltage battery, i.e.
1.5-V, and their current consumption defines the battery life time
and, ultimately, the customer satisfaction.
Portable audio systems adds to these constraints further per-
formances whose lack is also immediately perceived by the
user/customer, e.g. low total harmonic distortion coefficient
(THD) and noise level.
The present paper describes the design of an amplifier IC for
medical hearing aid: the circuit receives a low level signal (i.e.
μV-mV range) from the external microphone, it amplifies the
audio signal and finally it drives a miniaturised loudspeaker.
The primary intention of this design was the IC’s ultra low cost:
indeed the target technology is a conventional 0.35-μm CMOS
available at low cost. Silicon area constraints were also stringent.
Unfortunately the MOS thresholds of the process are much higher
than the minimum supply, i.e. 1.1-V (max VT H,n +| VT H,p |=1.6-
V): the high threshold-to-supply voltages ratio is very trou-
blesome for analog hearing aids. On the other hand digital
hearing aid integrating A/D, EEPROM/RAM, DSP and D/A are
much larger than analog counterparts: [1] reports an area of 12-
mm2 with respect to the proposed analog system requiring just
1.5-mm2. Moreover digital hearing instruments also embedding
firmware/software are further expensive.
In the last years, many expensive digital hearing aids have been
designed leaving apart analog approach: this work presents a
small, cheap, full-analog hearing instrument competitive to large
digital systems in terms of audio performances. The proposed
design also overcomes previous analog systems [2] in terms of
power consumption; noise performances with respect to some
digital hearing aids have also been improved, [7].
The remainder of the paper is organised as follows: Sect. II
introduces the system architecture, Sect. III illustrates design
issues regarding the preamplifier and Sect. IV discusses about
the power amplifier. The effectiveness of the solutions proposed
are proofed by simulations in Sect. V and final conclusions are
drawn in Sect. VI.
II. S YSTEM A RCHITECTURE
The simplified scheme of the low-voltage full analog hearing
aid proposed here is shown in Fig. 1. The audio signal provided
by the microphone is AC coupled to a preamplifier (A1) whose
gain is adjusted by the external gain control trimmer: the preamp’s
gain range swings from 6-dB to 40-dB.
The amplified signal is then carried off chip where a tone control
filter allows to emphasise the audio frequency spectrum on the
basis of the patient hearing loss.
Finally a power amplifier drives a differential loudspeaker whose
central tap is connected to the battery supply, Fig. 1. In this
design, its equivalent load impedance is as low as 70-Ω posing
serious current requirements to the output stage of A2. The power
amplifier gain is internally set to 40-dB, leading to 80-dB of
maximum hearing-aid gain.
Since an audio signal with frequency fS delivered to the differen-
tial loudspeaker produces a voltage fluctuation on the battery line
with frequency 2fS , particular care has to be taken in order to
avoid feedback through the microphone and preamplifier power
lines. For this reason both the microphone and the preamplifier
are supplied by a regulated voltage: the critical battery feedback
takes advantage of the improved power supply rejection (PSR) of
the system. The battery feedback is stable if both the regulator
and the preamp maintain a very high PSR on a frequency range
which doubles the hearing aid audio spectrum. The 6.8-μF on
board capacitor filtering the regulated voltage also suppresses the
battery feedback.
In Fig. 1, the raw battery voltage supplies the power amplifier
(Sect. IV) whereas a linear low drop-out voltage regulator (LDO)
provides a stable 0.93-V line for microphone and preamplifier
supply. The LDO reference voltage is generated by a 0.725-V
bandgap reference (BG) operating down to 1-V and 1-% accuracy.
III. P REAMPLIFIER
The simplified schematic of the preamplifier is shown in Fig. 2:
the op-amp is composed by a PMOS level shifter M P 9 − M P 10
followed by a folded cascode, M P 0 ÷ M P 3/M N 1 ÷ M N 4, a
second inverting gain stage (M N 6 − M P 5) and the output stage,
(M N 7 − M P 6). Devices M N 5 − M P 4 deliver the signal to
the second gain stage and they bias the output stage in class
AB operation: indeed, if the voltage at node A increases, M P 6
is turned off and VOUT falls: as a consequence the voltage in
B rises and the reversed current mirror M N 5 − M N 6 forces

978-1-4244-1577-9/08/$25.00 ©2008 IEEE -1-

Authorized licensed use limited to: Corporacion Universitaria de la Costa. Downloaded on August 16,2020 at 20:37:40 UTC from IEEE Xplore. Restrictions apply.
2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era

BATTERY
REGULATOR
22n
LDO BG
PREAMP 70−Ω
MIC 100n 6.8n 22n
A1
EXT. GAIN A2
CONTROL
22n
2.2u
RT EXTERNAL POWERAMP
RG TONE LOUDSPEAKER
CONTROL

Fig. 1. All-analog hearing aid highlighting the designed amplifier: external components are shown.

IA =IB . distortion, output swing and current consumption contrasts with

On the contrary, if the voltage at node A decreases, node B
also drops turning off M N 7; moreover when B decreases IB
is no more mirrored and node A directly drives the output PMOS
M P 6. The output stage quiescent current is determined by:
   
W W
L
MP 6 L open drain stage has a voltage gain which barely reach 1÷2-dB,
IQ = IB    MN 5
W W
L MP 4 L MN 6
where the aspect ratio of M N 5, M N 6, M P 4 and M P 6 are
involved; in this design IQ = 25 − μA.
The frequency compensation is achieved by means of a Miller
network with nulling resistor [3]: referring to Fig. 2, CM =12.5-pF,
RM =10-kΩ. The amplifier is supplied with a regulated voltage of
0.93-V hence operation in weak inversion region is mandatory.
Tab. I collects the main typical performances of the preamp com-
pared with the same results from previous literature works. The
comparison highlights the excellent performances of the proposed
amplifier, especially in terms of DC-gain (greater than 95-dB
in worst case condition), bandwidth and power consumption: as
shown, the amplifier consumes 100-μW, more than halved with
respect to the solution proposed in [4] designed with the same
foundry process. The power consumption is mainly determined
by hearing aid noise requirements.
It is worth notice that the preamplifer of Fig. 2 is able to drive
resistive load as low as 3-kΩ with a THD lower than 1.5-% with
a rail-to-rail output signal (fIN =1-kHz, VOUT =450-mV).
IV. P OWER A MPLIFIER
In the present design the loudspeaker is driven by the power
amplifier shown in Fig. 3. The system specifications on harmonic
the circuit constraints arising from the near 1-V supply voltage.
The central tap loudspeaker suggests to design an open drain
power amplifier, Fig. 3, arising the need for a precise quiescent
current control on the output devices, i.e. IQ . Since the input
impedance of the loudspeaker can be as low as 70-Ω, the last
(1) unless the output devices M O1−M O2 are biased with very large
quiescent currents; power constraint due to the limited battery life
time contrasts with such solution. Therefore the open drain output
stage gain is left quite small leaving the gain requirements to the
previous stages.
In order to significantly damp the harmonic distortion of the
power amplifier (in the range of few percentage points), three
gain stages have been set above the output devices. Indeed, the
total distortion is reduced by the loop gain as follows:
T HD ≈ (A · β)−2 (2)
where A is the opamp gain (typical DC gain above 100-dB) and
β the feedback factor, i.e. 1/100 in this design.
The 0.35-μm technology adopted for a near 1-V power supply
does not allow to stack more than 3 devices: the voltage headroom
is critical for worst-case process variations where the voltage
threshold voltages can reach VT H,n =0.7-V, VT H,p =0.9-V. For
this reason, three gain stages have been chosen taking advantage
of the improved gain provided by the fully differential architec-
ture. More complex architectures, i.e. cascode, require a voltage
headroom which is not available thus increasing the harmonic
distortion of the feedback amplifier.
PMOS source followers M F 1 − M F 2 pull up the input voltage
offset cancellation loop
BOFFSET AOFFSET
LPF
1

Vreg 1st stg. 2nd stg.

VB_OFF
3rd stg. output stage
MP5 VDD
R1 R2 MP0 MP1
VB2 VB VB VB
MP4 MP1 MP2
MP6
Cm X2 Y2 X3 Y3
X1 Y1 OUTN OUTP
A IQ IQ IQ / K
IA IB
Rm Vout
MP3 MP2 MN1 MN2 MN3 MN4 MN5 MN6 1:K
MN1 MN2
0.1uF MO1 MO2 MO3

Vin− Vin+ B INP INN

CM REF
MP9 MP10 MN3 MN4 MN5 MN6 MN7 3kΩ
MF1 MN7 MN8 MF2 MN9 MN10 MN11
MN0 ACMFB
VB1

Fig. 3. Power amplifier schematic including CMFB loops and offset cancellation
Fig. 2. Proposed preamplifier operating in weak inversion region. (nested Miller compensation not shown).

-2-

Authorized licensed use limited to: Corporacion Universitaria de la Costa. Downloaded on August 16,2020 at 20:37:40 UTC from IEEE Xplore. Restrictions apply.
2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era
TABLE I
P REAMPLIFIER P ERFORMANCE AND C OMPARISON
supply tech. DC-gain [dB] GBW [MHz] PM [◦ ] Load Power consumption [μW] THD [%] EIN1[μV] PSRR+4[dB]
[4] 2 0.35-μm 117 1.75 59 C=500-pF 240 - - -
[3] ±1 0.8-μm ≥100 1.8 51 R=25-kΩ 406 - - 98
This 0.93 0.35-μm 107 2.95 61 R=3-kΩ 100 0.0152 2.2 77
work 0.93
1 Equiv. input noise, 0.2÷5 kHz 2 @ fIN =1-kHz, VOU T,peak =50-mV 3 @ fIN =1-kHz, VOU T,peak =400-mV 4 @ 1-kHz

in order to drive the main differential pair M N 1 − M N 2 with a
suitable DC level.
The first two gain stages employ triode-connection CMFB,
M N 7 − M N 8 and M N 9 − M N 10, featuring zero power
consumption and a negligible silicon area. The common mode
voltage is set by choosing a proper aspect ratio for the tail devices,
e.g. let VON be the MOS overdrive voltage, at the first stage
output:
VCM,1 = VT H,MN 7 + VON ≥ 2VON (3)
hence the first stage MOS are saturated for sure. The sec-
ond differential couple is also saturated by setting VCM,1 ≥
VT H,MN 3 + 2VON . It is important to notice that the adopted
local CMFB loop senses the common mode voltage as long as
both devices M N 7−M N 8 works in the same operating region so
the aforementioned considerations hold if the differential voltage
swing at the output of the controlled stage is not high enough to
turn off M N 7 or M N 8.
As a consequence, the third stage employs a conventional CMFB,
Fig. 3: the auxiliary opamp compares the sensed common mode
with a reference voltage generated by a scaled replica of the open
drain output stage: this technique permits to control the quiescent
current on the output branches, IQ . Hence, the same circuit acts as
a CMFB and output current control, saving thus power and silicon
area. The common mode is sensed by 400-kΩ high-resistive poly
resistors: since the output level at nodes X3-Y3 is 500-mV in
typical conditions (M O1 − M O2 are biased in weak inversion
region) neither NMOS nor PMOS source followers can be used
in order to extract the common mode for near 1-V supply. In the
case a high-resistive poly mask is not available, analogous results
are achievable by means of MOS devices biased as resistors.
The amplifier has a frequency compensation composed by nested
Miller RC networks not shown in Fig. 3 for clarity purpose:
CM1 =1.6-pF/RM1 =60-kΩ form the external path between nodes
X1−Y 1 and X3−Y 3, CM2 =1.6-pF forms the nested path (nodes
X1-X2).
The target output power to be delivered to the loudspeaker poses
the amplifier’s output devices size: i.e. for a maximum output
power above 15-mW (70-Ω load, THD le 2%), the aspect ratio
of M O1 − M O2 is 3000/0.5 μm/μm.
The amplifier is responsible for the harmonic distortion of the
currents. The nominal current IQ =150-uA may rise up to 1.2-mA
in case of strong device mismatch. It should be reminded here
that the output devices of the amplifier exhibit a large aspect ratio
hence the offset voltage is ascribed to the first stages.
Conventional offset cancellation techniques adopt switched-
capacitor auto-zeroing solution [5] or digital calibration [6]:
in this full-analog approach an alternative solution has been
developed.
The continuous time offset cancellation circuit is shown in Fig.
3: the internal output voltage at nodes X3-Y3 is measured by the
auxiliary amplifier AOF F SET and then low-pass filtered (LPF)
in order to extract the DC component. A unity gain buffer,
BOF F SET , drives differentially the branch currents of the power
amplifier’s first stage until the output referred offset is balanced.
The correction is limited by the auxiliary loop finite gain error.
Since the audio signal must not perturb the current sources
M P 1 ÷ M P 2, the offset cancellation loop requests a very low
frequency LPF, i.e below 20-Hz: on the basis of cost analysis,
an external 1-μF capacitor has been preferred to on-chip large
active filters. The output resistance of AOF F SET acts as high-
value resistor for the low frequency LPF.
The advantages of the offset cancellation circuit are shown in
Fig. 4: the quiescent current consumption on the output stage
(IMO1 + IMO2 ) is collected for a 100 runs Montecarlo mismatch
simulation without and with the offset cancellation circuit. With-
out offset cancellation histogram shows some occurrences with
current consumption as high as 1.2-mA, more than two times the
hearing aid current budget.
By activating the cancellation circuit the consumption does not
exceed 200-μA, thus proofing excellent correction capabilities.
With the introduction of the cancellation circuit the harmonic
distortion is not affected and the quiescent current consumption of
the overall hearing aid is 460-μA (excluded loudspeaker biasing),
800-μA including loudspeaker.
V. S IMULATION R ESULTS
The complete hearing aid has been simulated at top-level
achieving the results discussed in this section.
Montecarlo occurrences

20
overall hearing aid therefore THD performances are illustrated
With offset cancellation loop
by Spectre system-level simulations in Fig. 6. 15

10
A. Offset Cancellation No offset cancellation loop
Device mismatch has a very different impact on preamp and 5
power amplifier: in the former case, the mismatch induced offset
0
has a minimal effect since the preamplifier loop has a unitary DC 0.15 0.30 0.45 0.60 0.75 0.90 1.05 1.20 1.35
Output stage quiescent current [mA]
feedback factor, Fig. 1. On the contrary, the mismatch effect on
the power amplifier produces an output offset at nodes X3 and Fig. 4. Power amplifier output stage current consumption over 100 Montecarlo
Y3, Fig. 3, leading to a very high error on the quiescent output runs without and with offset cancellation.

-3-

Authorized licensed use limited to: Corporacion Universitaria de la Costa. Downloaded on August 16,2020 at 20:37:40 UTC from IEEE Xplore. Restrictions apply.
2008 International Conference on Design & Technology of Integrated Systems in Nanoscale Era
100 20

RG=1 - RT=1 10
80
RG=1 - RT=45k
60
RG=10k - RT=1
Gain [dB]

Pout [mW]
40 1
RG=10k - RT=45k

20

0
0.1

-20

-40
0.01
10 100 1k 10 k 100 k 1M 0 0.2 0.4 0.6 0.8 1

frequency [Hz] THD [%]

Fig. 5. Hearing aid transfer function highlighting gain trimming (RG) and tone Fig. 7. Output power with respect to THD: both effects of cross-over and peak
control (RT). distortion are visible.

TABLE II
5 5 H EARING A ID P ERFORMANCE S UMMARY

WORST (Vdd=1.1-V, T=0C, slow process)

Battery range 1.1-1.6-V
Current consumption (@ 1.3-V, no signal, min. volume)
Preamp 110-μA
THD [%]

1 1
Power Amplifier core 160-μA
TYP (Vdd=1.3-V, T=27C, typ process) Bandgap+LDO 170-μA
0.5 0.5
Overall IC 460-μA
Loudspeaker bias 340-μA
IC power consumption 600-μW
BEST (Vdd=1.6-V, T=60C, fast process) Loudspeaker power consumption 440-μW
Bandwidth 0.2÷10-kHz
0 0.2 0.4 0.6 0.8 1 1.2 1.35
Input referred noise (0.2÷10-kHz) 3.2-μV
Vout [V]
Load impedance ≥ 70-Ω
Output power (load 70-Ω) @ 1% THD 15-mW
Fig. 6. Total harmonic distortion (typ-best-worst case) for different signal output THD @ 1-kHz (RLOAD =70-Ω)
levels. THD is reported on log axis. VOU T =10-mV 0.4 %
VOU T =1.5-V 1%
Max Signal-to-Noise ratio (200÷10-kHz) 59-dB
Bandgap reference accuracy 1%
The overall transfer function of the hearing aid is shown in Fig. LDO (0.93-V) line regulation 1.72 %
5: the gain trimmer sets the gain from 50 to 82-dB whereas the Temperature operating range -10◦ ÷60◦ C
lower cut-off frequency is adjustable in the range 0.8÷9-kHz. Die area incl. bond pads (0.35-μm CMOS) 1.5-mm2
The critical performance of the hearing aid is the total harmonic
distortion (THD): Fig. 6 reports the THD with respect to output
peak amplitude. Three curves represents the extreme PVT1 corner can sweep from 1.6-V down to 1.1-V.
conditions: typical (supply 1.3-V, T=27◦, typ. process), best case The design has been focused on a ultra low-cost approach
(supply 1.6-V, T=60◦ , fast process) and worst case (supply 1.1- demonstrating the possibilities of a small full-analog chip: the
V, T=0◦ , slow process). It is worth notice that simulations were power consumption is lower than previous analog solutions [2]
performed with battery including a 2-Ω internal resistance: the and some performances have been largely improved even with
effect is a further reduction in the available supply and a critical respect to digital hearing aids, i.e. input referred noise voltage,
battery feedback loop through LDO. [7], and die area, [1].
THD in Fig. 6 highlights the effect of cross-over distortion of
the power amplifier, effective on very low signals. With depleted R EFERENCES
battery, supply 1.1-V, peak distortion due to amplifier saturation [1] D. George Gata et al., ”A 1.1-V 270-μA Mixed-Signal Hearing Aid Chip”,
is also visible. For a certain THD target, Fig. 7 reports the IEEE J. of Solid-State Circuits, vol. 37, Dec. 2002.
[2] A.B.Bhattacharyya et al., ”A Micropower Analog Hearing Aid on Low
maximum output power delivered to the 70-Ω loudspeaker with Voltage CMOS Digital Process”, Proc. of 9th Intern. Conf. on VLSI Design,
the requested distortion. It can be observed that some THD value Jan. 1996.
are caused by both small and large output signals due to cross- [3] K.N. Leung and P.K.T. Mok, ”Nested Miller Compensation in Low-Power
CMOS Design”, IEEE Trans. on Circ. and Syst. II, vol. 48, Apr. 2001.
over and peak distortion respectively. Finally Tab. II summarises [4] A.D. Grasso et al., ”Active Reversed Miller Compensation for Three-Stage
the hearing aid main performances. Amplifiers”, Proc. of Intern. Symp. on Circuits and Systems, May 2006.
[5] C. C. Enz and G. C. Temes, ”Circuit Technique for Reducing the Effect
of Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and
VI. C ONCLUSIONS Chopper Stabilization”, Proc. of IEEE, vol. 84, Nov. 1996
[6] C.Azzolini et al. ,”Design of a 2-GS/s 8-b Self-Calibrating ADC in 0.18μm
The paper describes the design of a very cheap low-voltage CMOS technology”, Proc. of Intern. Symp. on Circuits and Systems, May
hearing aid in 0.35-μm CMOS employing building blocks also 2005.
[7] F. Serra-Graells et al., ”A True-1-V 300μW CMOS-Subthreshold Log-
suitable for general audio portable applications; battery supply Domain Hearing-Aid-On-Chip”, IEEE J. of Solid-State Circuits, vol. 39,
Aug. 2004.
1 Process-Voltage-Temperature variation.

-4-

Authorized licensed use limited to: Corporacion Universitaria de la Costa. Downloaded on August 16,2020 at 20:37:40 UTC from IEEE Xplore. Restrictions apply.