library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use IEEE.std_logic_unsigned.all;

use IEEE.std_logic_arith.all;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating

-- any Xilinx primitives in this code.

--library UNISIM;

--use UNISIM.VComponents.all;

entity UNO is

Port ( clk_in : in STD_LOGIC;

col : in STD_LOGIC_VECTOR (2 downto 0);

clk_out : out STD_LOGIC);

end UNO;

architecture Behavioral of UNO is

signal divisor : integer range 0 to 1000000 :=0;

signal duty : integer:=0;

begin

Divisor50Hz : process(clk_in)
begin

if rising_edge(clk_in) then

divisor <= divisor + 1;

end if;

end process Divisor50Hz;

posicion: process(col)

begin

if col="000" then

duty <= 25000;

end if;

if col="010" then

duty <= 37500;

end if;

if col="001" then

duty <= 50000;

end if;

end process;

process (duty,divisor)

begin

if divisor<duty then

clk_out<='1';
 else

clk_out<='0';

end if;

end process;

end Behavioral;

PINES

NET "clk_in" LOC = P56;

NET "col(0)" LOC = P17;

NET "col(1)" LOC = P15;

NET "col(2)" LOC = P12;

NET "clk_out" LOC = P24;