---Jordi Espinosa;

-- Daniel Sotelo

---- file principal donde se llama a clocks_crono y Display_decoder7seg

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity cronometro is
Port( boton1: in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
anode : out STD_LOGIC_VECTOR(3 downto 0); ---- variable de
salida selecion de display 3 bits
cathode : out STD_LOGIC_VECTOR(7 downto 0)); ---- variable de
salida para encender los led del display de 7 segmentos
end cronometro;

architecture Behavioral of cronometro is

component clocks_crono ---componet para el los reloj

Port(CLK : in STD_LOGIC;
clock_100 : out STD_LOGIC;
clock_centi : out STD_LOGIC);
end component;

component Display_decoder7seg ---- componet para el

display
Port( boton1 : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
clock_100 : in STD_LOGIC;
clock_centi : in STD_LOGIC;
anode : out STD_LOGIC_VECTOR(3 downto 0);
cathode : out STD_LOGIC_VECTOR(7 downto 0));
end component;

signal clk1, clk2 : STD_LOGIC; ----- señales de bus

de reloj

begin

comp0 : clocks_crono port map (CLK => CLK, clock_100 => clk1, clock_centi => clk2);
------ declaracion de port map que se utilizan en los componet
comp1 : Display_decoder7seg port map (CLK => CLK, clock_100 => clk1, clock_centi =>
clk2, boton1 => boton1,
RST => RST, anode => anode, cathode => cathode); --button => button

end Behavioral;