AIR UNIVERSITY

Due Date
Registration ID Department of Electrical & Computer Engineering
ASSIGNMENT #2-BEE-VII-B (CLO-3) 30th October, 2020
FPGA Based Design (EE-324)
Instructor: Engr.Muhammad Ali Raza

1. Add the following two numbers using conditional sum addition techniques:
1001 1101
1101 1011

2. Multiply a 5 bit signed multiplicand ‘a’ with a 5 bit unsigned multiplier

‘b’ by applying a sign extension elimination technique.

a = 11011
b = 10111