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Lecture 19
• Cory Ellinger,
VLSI Design Automation,
Independent Research Project,
GMU, 2005.
Introduction
Introduction
• Technological Advances
– 19th Century - Steel
– 20th Century – Silicon
Design Inception
RTL Design
Place + Route
Physical Verification
Design Complete
RTL Design
Design Function Digital Tool
Cadence NC Verilog
RTL Design
Mentor Graphis ModelSim
Lint Checking
Cadence Hal
(users digression)
FPGA Verification
Xilinx ISE
(users disgression)
Code Coverage
Cadence ICT
(users disgression)
Cadence NC Verilog
Testbench Developement
Mentor Graphics ModelSim
Agilent ADS
System Interface Simulation
Synthesis Matlab
RTL RTL
Synopsys DC
Synthesis Macro Generation Artisan
Cadence RC
Cadence NC Verilog
Gate-Level Simulation
Mentor Graphics Modelsim
Synthesis Synthesis
Floorplan
Macro Placement
/ Std Cell
Placement
Cadence Encounter
Placement-Based
Optimization
RC Extraction
Cadence Fire
&Ice QX
Verification
Verification
Physical Verification
Design Function Digital Tool
GDSII Preparation/
Simulation Preparation Cadence DFII Cadence DFII
Schematic Preparation
Layout / Chip Finishing Back Annotated Simulation Cadence Virtuoso Cadence NC Verilog
DRC
ERC
Synopsys Nanosim
Top-Level Simulation
Cadence AMS Designer
• Pre-designed collection of
logic functions
– OR, AND, XOR, etc
• Cells in a timing-critical path are placed close together to reduce routing related
delays (Timing Driven)
• Floorplan of design:
– Core area defined with large macros placed
– Periphery area defined with I/O macros placed
– Power and Ground Grid (Rings and Straps) established
• Utilization:
– The percentage of the core that is used by placed standard cells and
macros
– Goal of 100%, typically 80-85%
I/O Placement and Chip Package
Requirements
• Some Bond Wire
requirements:
– No Crossing
– Minimum Spacing
– Maximum Angle
– Maximum Length
Guidelines for a Good Floorplan
• Purpose of Grid is to
take the VDD and
VSS received from
the I/O area and
distribute it over the
core area
• Blockages can also
be added in the
floorplan to prohibit
standards cells from
being placed in those
areas
Timing Driven Placement
Design Flow – Timing Driven Placement
• Astro™ optimizes, places, and
routes the logic gates to meet
all timing constraints
• Timing Driven
Placement places
critical path cells close
together to reduce net
RC
• Prior to routing, RC
are based on Virtual
Routes
• Astro™ can interpret gated clocks and can build clock trees
“through” the logic to the registers
Effects of CTS
• Several (Hundreds/Thousands)
of clock buffers added to the
design
Verification
Formal Verification
• 65nm/45nm Concerns
– Leakage power of transistors could reach the level of the dynamic
power of the design
– Wiring delays outweighing gate delays (130nm and beyond)
– Cross coupling capacitance could begin to dominate over the
capacitance of the wire itself