8284A/8284A-1 Clock Generator and Driver for 8086, 8088 Processors DISTINCTIVE CHARACTERISTICS ‘© Generates the System Clock forthe 8086, 2088 Proces- © Generates systom reset output from Schmit tigger sors: SMH, 8MHz with B294A; TOMHz with €284A-1/ input ‘¢ Uses a crystal or @ TTL signal for frequency source Capable of clock synchyonization with other 6284As (© Provides local READY and Mutsbus® READY eynchroni- zation GENERAL DESCRIPTION “The 82844 is single chip clock generetor/crver for the trolled oscilator, @ dvide-by-three counter, completo (8086, 8088 processors. The chip contains a cystalcon- MULTIBUS* "Ready" synchronization and reset log. BLOCK DIAGRAM Lveaze/weaze ro, =, ae RELATED AMD PRODUCTS Part No. Description “Ama086 | 16-5 Microprocessor 1208 _| Bus Controler "WOLTUS we aginnd Seon ot Cap Baigen =e mangas 000 Inseo Cete: Ape 9678284A/82840-1 DiPs CONNECTION DIAGRAMS ‘Top View Note: Pin 1 Is marked for orientation ‘cooodar2 9.000ORDERING INFORMATION Commodity Products [AMO commodity products are avaiaba in several packages and operating ranges, The order number (Vaid Combination) i formed bya combination of a. Temperature Range », Package Type ©. Device Number 4. Speed Option 4 SPEED oprIOn Blank For ste & ste Apolcabons ‘nppcatons alld Combinations Valid Combinations list configurations planned to be ad Comtinanons “seported in volume for this doves. Conmut halal AMD W.0F ean ‘sales office to contirm availabilty of specific valid 0.0.P Cu ‘combinations, to check on nowy reloased valid combinations, aoe ‘and to oblain additonal deta on AMD's standard miltary 286A 18 ‘ade products, “Miltary temperature range products are NPL (Non- Compliant Products List) or Nov-MIL-STO-B89C Compliant products ony. 201 b-vreze/vreze,8284A/8284A-1 PIN DESCRIPTION Pin No. [Name | V0 | Description 37 [BER | 1 | Bes Ero Tw FEW sigalo undo sunt ho Bo Roy age! ROY, a ROva, REN, vakans ROT, we ens FEN; Valdas POY is pon te wototncr acon to Mut aster Sin Shasos you wee Bh Slonls Both sori we bed LOW fh non waa Sytoma” re], 1 eu Rent, Thane srt re casos Yona devc ead on he waa Ba Tal Wa walle 6 Gla as boon Rove fecavod. DY; and Ars wo ated by AEN and KER roopecbvy. = [ASWRE—| 1 Rony Syotranous Souct. The ASTI sral efnes he ayncvonzaon modo oe READY ge When FEVRC iEggee tripe rose fs provid puled HON hae a on lage of REASY Syackenaabon on SLOW, thro we wo sagen of READY Syrehentaon, = IREAGY | “0 Foay, READY athe snehvorand ROY sali Arto guareniond RGU fo re proce aa boo mat ‘he READY gna chars. 716 fie] 1 ont These are the np pi or The tached cya Tho Bal Fequeny 3 nes ha deed wotowe Go eaona. 7 re 7 | Freaveny 758) S96G. Wan 7s Srepped HIGH CLK ie gonraed Wom he EF eu When senped LOW, a PIE thous no ponte tock tbe pened Oe Sree 7 ca TT EiemalFequeney. Used in conncten wt « HIGH agnel on FC CLK = gered Fon he Rp haan Sppmung ons pn Tho vox ‘aga! n'saguare vane 2 Woes te toquony oe Sete’ CL OAD = [GK] “S| Process Cock CU te cock apt vad bythe process: and al dorces whch areciy-corect to te processor lca ts bacung Bool trvon ships a ober MOS evens) area HOH oft 97 ce = MN Frovced on tha aio ve MOS Sevens, he cut hequany f CLR w 73a he Syston EF mA Reengy tee aay oy. z FO |_| Parte ck, Th ral isa TL avel porphor! dock Srl whoos ou Weaueray 172 Wal of LK na aa son au onde [05> |S [Oset Output Ti soa TL rl ott of trl GoGo FOO Ws Wainy weal oat | fe oye 7 THES] oot i Tis one sand 19 gopwato« RESET. The S200A proven a SG Wigpr pt 80a an RC Somecton can Be sed eaaSish ths owerup Tose ot proper eaten, 73 RESET [0 [ Reset Tis sali ved to ros he 6068 amily poner. 7 fesync | 1 Gosk Setvonon Te spall degrod alow mdse B2tAe tbo sncionaedio rowGe Goma Fal ge Fagan Gv HGH wi zt teres counters wh COYNC pos LOW the counts wil esa Sart SINE owas to be enalysyrcrniaod to EFL When ved wih be sal ncaaioe COVNG sho be Noa se to pound DETAILED DESCRIPTION Lock ouTPUTS OSCILLATOR The CLK output is a 39% duy cycle MOS clock civer ‘The oscilator ccc of the 284A is dosigned primary fr use with a fundamontal modo, series resonant crystal from which the operating frequency is derived ‘The crystal frequency should be solacted at threo times the requiced CPU clock. X1 and Xe are the two crystal input crystal connections, The output of the oscilator is buffered and brought out on OSC so that other system timing signals can be rived from tis stable, crysta-contralled source, Two 5102 series resistors aro optional for systoms which have a Voc ramp time greater than (or equal to) V/ms and/or inbaront board capacitance betwoen X1 or Xe exceeding 10pF. This capacttance valve should not include the B284A's pin capacitance. By imiing the stray capacitance to less than {0pF on X1 oF Xe, the deviation from the desired fundamental frequency Is minimized. CLOCK GENERATOR “The clock gonerator consists ofa synchronous cvide-by-throe counter with a special clear input that inhibits the counting This cloar input, (CSYNO), allows tho output clock to be synchronized with an extornal event (such as anothor 8284A, lock). is necessary to synchronize the CSYNC input to the EFI clock external 10 the 8284A (see Figure 1). This is ‘accomplished with two Schotty fip-lops. The counter output I 33% duty oyelo clock at one-third the input requency. ‘The F/6 input is a stapping pin that solocts other the EFI Input or he erystal osclator as the clock forthe +3 counter. the EFI input is selected as the clock source, the oscilatr section can be used independently for another clock source. Output is taken from OSC. designed to dive the 8086 or 8088 processors direct. POLK is @ TTL level peripheral ciock signal whose output frequency is Ye that of CLK. PCLK has a 50% duty cycle. RESET LoGic Reset logic forthe 82044 is provided by a Schmit rigger input (FES) and a synchronizing fipstop to gonerate tho reset tiring The reset signals synctronized to the fang odge of CLK. A simple RC network can be used to provide power-on reset by uilng this function of the 8284A. READY SYNCHRONIZATION “Two READY inputs (ROY, RDY2) are proved to accommo- dato two Mult-Mastor system busses. Each input has. o ‘qualer (REN and AENe, rospectvoly). The AEN signals validate their rospoctve ROY signals. a Mul: Master systom is not being used the AEN pin should be tied LOW. ‘To assure RDY sotup and hold timas are met, synchronization is roqued for all asynchronous active going edges of ether FADY input. Inactive-going edges of ROY (in normally ready ‘systoms) do not require synchronization, but must satisy AD ‘sotup and hold as\a mater of propor systom design ‘Tho twe modes of ROY synchronization operation are datined by the ASYNG input When ASYNC is LOW, two stages of synchronization are provided for active RDY input signals. Positve-going asyn ‘chronous RY inputs wil fst be synchrorizod to Mipflop one al the tsing edge of CLK and then syncrronized 10 ip-lop ‘wo at the next feling edge of CLK: after which time the READY output will go active (HIGH), Nogatvo-going asynchro:‘hous ROY inputs wil be eynctvonized deco fip top wot the fling 2dgo of CLK, ator which time the READY output will 99 inacine. This mode of operation is intonded for use by Asynchronous, (normally not ready), devices in the system Which cannot be guaranteed by design to moot the requirod DY setup fiming trivcx. on each bus eye \Whon ASYNG is high o left open, the first READY flip opis bypassed inthe READY synchronization logic. ADY inputs aro ‘synchronized by Tip.iop two on the Ting edge of CLK botore they aro prosented to the processor. This modo is avaiable for synchronous devices that can be guaranteed to meet the Fequited ROY 80tup time. ZFBYNE can be changed on every bus cycle to select the ‘2ppropriate mode ot synchronization for each device in the system Figure 1. CSYNC Synchronization = sume CLOCK HIGH AND LOW TIME (USING X1, X2) Ry = Ro=5100. CLOCK HIGH AND LOW TIME (USING EFI) vpeze/yPaze Ms 9.0804 9284a/e2 READY TO CLOCK (USING X;, X2) Yee TOR res cs (SeENOTE N sop 4, ewl poe mate 55 (SEENOTE 2) 2 Paso Ganertor POY, ose Tigger Fie yg Re ER, HH sone Fy =Ae=510 READY TO CLOCK (USING EFI) Notes: 4. Ci = 1009 2 = 30pF Fuse LOAD) GENERATION ‘en err ca] (SEE NOTE 1) oe a a, co ee oe mm, oa eo =ABSOLUTE MAXIMUM RATINGS. Storage Temperature 69°C 10 + 100°C ‘Ambiont Tampecature with Powers ‘Applied (COML, At) 0°C to +70"0 (WL) sonnnnnsnnrnnnnnnnnnns= 88°C 10 +1256 [Al Output and Supply Voltages ~0.8V to +7.0V All Input Voltage. "1.0 to +55V Power Dissipation Ww Siresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent device felure. Functionality at or above those limits is not implied. Exposure to absolute ‘maximum ratings for extended periods may atect device relat. OPERATING RANGES commer yo) Boney Temperature 0° to +70°~ Supply Vortage VA78V 10 +525 itary (M) Devices Tempers... 55°C to +125 ‘Supply Vottage +45V 10 +55V Operating ranges define those limits between which the functionality and parameters of the device are guaranteed DC CHARACTERISTICS over operating ranges unioss otherwise specified Parana Deeaipton Tea Conaione | we [ wer] vane Fa on coro ET eS oa =a ie ‘Other Inputs Vr = 045¥_ 05 ma ate re Ge vaiee 3 in Other puis Va = S.25V_ 3 wn Ye et Fr ea Sa Tae [Be By Car fom eran var [a Ts et ae a = Roar pt Ve ts ae eon Low vote ak a aH Vag GK ar a von Cther Ovioas: =m 2a vos Teast REF he i BT oz = Note 1. This specication is provided for reference ony. 2.006 L-veaze/maze8284A/824A-1 ‘SWITCHING TESTING CIRCUIT SWITCHING TESTING CIRCUIT (CL S0pF for READY (CLK, READY) (CLK, READY) “Teo00870 "Too006s0 OL = 100pF for CLK GL = 100pF ‘SWITCHING TESTING WAVEFORM input, output) wrocre7e AC testing inputs are dtiven at 2.4V for 8 logic "1" and O48V for a loge "O" Timing measurements are made at 1.5V for both a logic "1" and "0! TIMING REQUIREMENTS: SWITCHING CHARACTERISTICS over operating ranges uniess otherwise specitiod Parameters Desorption "Test Conditions in Typ [wax [Unite] Tene aral Freqarey HGH Tine [im — son 2 rm as Exel Fresverey LOW Tine 79% = FOR 7 3 tees Fr Peed ic tow 1 ee teense 7 CoML At 5 SIAL Feeney 7 a cre OY ROYs Aaive Soup To CO ERE = HGH = re Teiver ROY ROVe Acie Seip Yo GOK SYNE = LOW 6 is or ROY ROY, ahs Set t 5 = eae DY, ROVe Ho to GK . = tae STE sown 1 CLK Oo fm ‘oar TSWRE Wats OK a fn Tanvmig | AEN, REN soup w ROY, ROVE a I Tease TEN; KEN Hod v0 Gk t 0 = [ive GING Set 0 EF a = tom. (SYNC Hts EF — Ss foe Sane Waa rear = es FEE Soup 16 OK Tie % mI ‘eu TES roi to CUE cor = = ‘unt inp Fie Tne Fre 05 BT ae te Theat Fal Tine From 2 08 ee 2.096TIMING RESPONSES Pramas Been Tes conaion wane [oe [ue a Te eo = a tone CLK HIGH Tene MO ae we aoe 2 ve tar (CAK LOW Time poe ee 2 cnet (CLK Rio or Fat Tine 10V w a5v x osc alia aa freee a o ee [Peet ee = a —— te ce TST = vex | Ret Act CX uo Now 9 a weg 6 z Tex a ay as ‘Ss —— fei re a Safe tw ats ee CT 3 te eo —| fe een a 7 =e SS | Sit Ts to em aaa ToT =e oo nooo aa Freon ets Ca ae . Seup and hold necessary ony 12 gran recog at next clock E Xaptos ony to Ts and Tw sis 4 ppc ery 10 72 ston, SWITCHING WAVEFORMS CLOCKS AND RESET SIGNALS Note: All timing requirements are made at 1.5 vols, unless otherwise noted, 3087 b-wraze/wreze8284A/8284A-1