The Figure 1.

5 shows the pin connection to validate the truth table of 74LS00 Double 2-Input NAND
Gate.

(a) (b)
Figure 1.5: a) Pin configuration for 74LS00 gate IC. b) Connection of pins in breadboard.

The Figure 1.6 shows the pin connection to validate the truth table of 74LS02 Double 2-Input NOR
Gate.

(a) (b)

Figure 1.6 : a) Pin configuration for 74LS02 gate IC. b) Connection of pins in breadboard.
The Figure 1.7 shows the pin connection to validate the truth table of 74LS04 1-Input NOT Gate.

(a) (b)
Figure 1.7 : a) Pin configuration for 74LS04 gate IC. b) Connection of pins in breadboard.

The Figure 1.8 shows the pin connection to validate the truth table of 74LS08 Double 2-Input
NAND Gate.

(a) (b)
Figure 1.8 : a) Pin configuration for 74LS08 gate IC. b) Connection of pins in breadboard.
The Figure 1.9 shows the pin connection to validate the truth table of 74LS32 Double 2-Input OR
Gate.

(a) (b)
Figure 1.9 : a) Pin configuration for 74LS32 gate IC. b) Connection of pins in breadboard.

The Figure 2 shows the pin connection to validate the truth table of 74LS86 Double 2-Input XOR
Gate.

(a) (b)

Figure 2 : a) Pin configuration for 74LS86 gate IC. b) Connection of pins in breadboard.
C)

Figure2.2: Digital circuit in software.

D)

A E B F X
0 0 0 0 1
0 0 0 1 0
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 0
1 1 1 0 1
1 1 1 1 1

Table 2: truth table for digital circuit.