Chapter 7 ■ Number Theory for FPGAs

Listing 7-12.  Binary Bit String

b"1011010", b"1111_0000"

Listing 7-13.  Octal(8) Bit String

o"132", o"360"

Listing 7-14.  Hexagonal(16) Bit String

x"5A", x"F0"

7.1.4.4 Numbers
Numbers include real and integer numbers. In the IEEE library numeric_std package, numbers can be
decimal numbers, negative “-,” you can use exponential notation “E,” and you can even use underscores “_”
to make the number easier to read.
Integer number range: -2,147,483,647 to 2,147,483,647
Real number range: -1.0E38 to + 1.0E38
Following are some examples:

3.14
0.7E8
123_456

7.1.4.5 Base
Sometimes it is more convenient or easier to read when a base other than 10 is used when representing a
number. Here are a couple of examples. The first one is 90 and second one is 240 in decimal.

BASE 2: 2#1011010#
BASE 8: 8#132#
BASE 16: 16#5A#

BASE 2: 2#1111_0000#
BASE 8: 8#360#
BASE 16: 16#F0#

7.1.4.6 Physical
This is a special word in VHDL which represents time, current, and voltage. In FPGA design, we only use
time. Following is an example of 200 Nano seconds.

200 ns

You will see and use a lot of time words in a test bench. (In Chapter 4, in the section “The Test Bench,”
we defined the SYS_CLK to toggle every 10 ns) It is a very useful way to generate a clock in test bench. Keep
in mind that it is an abstraction and will only work in simulation. As such it can appear in your test bench file
but not in your design file. We will talk more about how to create clocks in Chapter 10.

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7.2 Grammar in VHDL
VHDL is a strongly typed language. This means that you need to type more (compared with Verilog, which is
another HDL language). VHDL is always checking the types of objects to ensure consistency and prevent you
from mixing incompatible data types or performing actions that don’t make sense. It is needed in hardware
design because most of the time hardware needs to be the exact type and size to work. It is like needing to
use the correct type and size of screw driver to remove a screw. This section will only cover the most useful
grammar, and you will see more of VHDL grammar throughout the next couple of chapters.

7.2.1 Statements in VHDL
Every VHDL statement is terminated with a semicolon. It is quite similar to other computer languages.
VHDL statements are easy to create, but what the statement means (and what it ultimately does) is up to
you. The semicolons only help you do half of the job.

7.2.2 How to Comment
VHDL only has line comments and doesn't support block comment in VHDL-93. You need to put a double
hyphen (--) in front of the comments and rest of the line will be commented out (Listing 7-15).

Listing 7-15.  VHDL Comment Example

regular_coffee <= coffee and cream and sugar ; -- Here is the comment of how to make a coffee
-- You can start your comment in the beginning of the line

7.2.3 <= and := sign

You will see <= and := in VHDL. They mean totally different things. Let’s talk about <= first. It is used to
assign a value to an object. Remember it is ended by semicolon (Listing 7-16).

Listing 7-16.  VHDL Object Assignment Example (Signal and Variable)

signal_assignment <= value_for_the_signal ; -- You will use this for signal assignment
variable_assignment := value_for_the_variable ; -- You will use this for variable assignment

In the example, we have <= and :=. We are not suggesting you interchange them. The <= sign is used to
assign signals and the := is used to assign variables.

7.2.4 Begin and End

Every time you start with begin remember to finish the section with end. In the earlier examples
(Figures 7-2, 7-3, Listings 7-6, 7-7), you can see that all the begin statements are paired with an end.

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7.2.5 Coding Your VHDL with Style

Coding with a convention style can increase readability. If all of your code uses the same style, you will save
time hunting for bugs or when you try to reuse code you wrote earlier. A good coding style (guideline) also
helps you to avoid certain constructs that often causing bugs. We won’t cover all the guidelines here but we
would recommend you go to the following link to download a copy for yourself and have a browse through.
1.
Do not start writing any VHDL code until you completely understand the
specifications.
2.
Use only IEEE libraries: std_logic_1164 and numeric_std. Do not use the
commonly used Synposys’ libraries std_logic_arith, std_logic_(un)signed,
numeric_bit, or any other none IEEE library.
3.
Comment the general functionality of each section/subsection.
4.
The comments written in the code must include valuable and significant
information. Avoid unnecessary or trivial comments.
5.
Keep the signal names consistent throughout the hierarchy of the design.
6.
Write just one statement per line of code, even when doing component
instantiation.
7.
If possible use lowercase letters for all the code.
8.
For synthesizable code do not use ‘after’ to imply delay: sum <= a + b after 3 ns;
The ‘after’ must only be used in test bench.

■■Note This is a good example that you could follow: https://wiki.electroniciens.cnrs.fr/images/

VHDL_Coding_eng.pdf.

7.3 Summary
After this chapter you should understand the basic elements in VHDL (signal, variable, and constant) and
how to name them (identifiers). You should not use any reserved words for the name of your identifiers. A lot
of the reserved words (keywords) will be used in the next chapter. Remember to have enough comment in
your code to provide a good description, but don’t comment every trivial thing.
In Chapter 8 we are going to employ these basic rules to build some useful designs.

■■Tip  Alt + Shift in Notepad ++ for block edit is very useful in VHDL coding 

“God made the integers, all the rest is the work of man.”
—Leopold Kronecker

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CHAPTER 8

Telling the Truth: Boolean Algebra

and Truth Tables

In this chapter, we will show you how to use the basic elements (signals) to create combinational logic in
VHDL (VHSIC (very high speed integrated circuit) Hardware Description Language). We’ll also cover two
IEEE (Institute of Electrical and Electronics Engineers) libraries, namely, std_logic_1164 and numeric_std
which provide features for more than just Boolean logic in your FPGA (field-programmable gateway array)
design. By the end of this chapter you will know how to create a 4-bit adder using two different approaches
and then you’ll use ModelSim to simulate the 4-bit adder.

8.1 Boolean Algebra
Boolean algebra is like designing switches for turning light bulbs on and off. Figure 8-1 shows a design that
uses two switches to control the doorbell. If we would like to ring the bell when either one of the switches is
connected (high), then we need an OR gate.

Figure 8-1.  Boolean algebra example 1—doorbell

In Boolean algebra, we use the following equation to describe what is happening in the doorbell design:
Bell Ring = Switch 1 + Switch 2
The plus (+) sign in Boolean algebra is logical OR. There are two more basic operation signs in Boolean
algebra. They are  which is AND and ~ which is NOT. Boolean algebra only has two possible outputs, logical
high/true (1) or logical low/false (0) inputs and outputs.
Let’s look at one more example. We would like the output (Result) set to high when all inputs (A, B, and
C) are low (Figure 8-2). The Boolean algebra equation will be like the following:
Result = ~A  ~B  ~C

© Aiken Pang and Peter Membrey 2017 137

A. Pang and P. Membrey, Beginning FPGA: Programming Metal, DOI 10.1007/978-1-4302-6248-0_8
Chapter 8 ■ Telling the Truth: Boolean Algebra and Truth Tables

Figure 8-2.  Boolean algebra example 2 in logic gate

It is very easy to create the logic gates from the Boolean algebra equation. It is like a direct map to the OR,
AND, and NOT gates. This gate-level implementation can be easily written in VHDL, as shown in Listing 8-1.

Listing 8-1.  Boolean Algebra Example 2 in VHDL Code

library ieee; -- All of the deisgn need ieee library
use ieee.std_logic_1164.all; -- Using std_logic_1164 package

entity boolean_algebra_example2 is
port (
A: in std_logic;
B: in std_logic;
C: in std_logic;
Result: out std_logic
);
end boolean_algebra_example2;

architecture behavioral of boolean_algebra_example2 is

-- Declarations, such as type declarations, constant declarations, signal declarations etc
signal temp : std_logic;

begin -- architecture behavioral of boolean_algebra_example2

temp <= NOT A AND NOT B ;

Result <= NOT C AND temp;

end behavioral;

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