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February 2008
MM74HC132
Quad 2-Input NAND Schmitt Trigger
Features General Description
■ Typical propagation delay: 12ns The MM74HC132 utilizes advanced silicon-gate CMOS
■ Wide power supply range: 2V–6V technology to achieve the low power dissipation and
■ Low quiescent current: 20µA maximum (74HC Series)
high noise immunity of standard CMOS, as well as the
capability to drive 10 LS-TTL loads.
■ Low input current: 1µA maximum
■ Fanout of 10 LS-TTL loads The 74HC logic family is functionally and pinout compat-
ible with the standard 74LS logic family. All inputs are
■ Typical hysteresis voltage: 0.9V at VCC = 4.5V
protected from damage due to static discharge by inter-
nal diode clamps to VCC and ground.
Ordering Information
Package
Order Number Number Package Description
MM74HC132M M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
MM74HC132SJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MM74HC132MTC MTC14 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
MM74HC132N N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Top View
Notes:
1. Unless otherwise specified all voltages are referenced to ground.
2. Power Dissipation temperature derating — plastic “N” package: –12mW/°C from 65°C to 85°C.
Guaranteed
Symbol Parameter Conditions Typ. Limit Units
tPHL, tPLH Maximum Propagation Delay 12 20 ns
AC Electrical Characteristics
VCC = 2.0V to 6.0V, CL = 50pF, tr = tf = 6ns (unless otherwise specified)
TA = –40°C TA = –55°C
TA = 25°C to 85°C to 125°C
Symbol Parameter VCC (V) Conditions Typ. Guaranteed Limits Units
tPHL, tPLH Maximum 2.0 63 125 158 186 ns
Propagation Delay 4.5 13 25 32 37
6.0 11 21 27 32
tTLH, tTHL Maximum Output 2.0 30 75 95 110 ns
Rise and Fall Time 4.5 8 15 19 22
6.0 7 13 16 19
CPD Power Dissipation (per gate) 130 pF
Capacitance(4)
CIN Maximum Input 5 10 10 pF
Capacitance
Note:
4. CPD determines the no load dynamic power consumption, PD = CPD VCC2 f + ICC VCC, and the no load dynamic
current consumption, IS = CPD VCC f + ICC .
7.62
14 8
B
5.60
6.00 4.00
3.80
0.90
SEATING PLANE
0.50
(1.04)
DETAIL A
SCALE: 20:1
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
1.65
0.45 6.10
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
19.56
18.80
14 8
6.60
6.09
1 7
0.38 MIN
3.81 0.58
3.17 0.35 8.82
2.54
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions,
specifically the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/
* EZSWITCH™ and FlashWriter® are trademarks of System General Corporation, used under license by Fairchild Semiconductor.
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.