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  • 1768 Cpu Iop: Bb1343 - Iop - R00.Schdoc

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    FernandoAdrián
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    The document shows a diagram of connections between various components on a circuit board. There are multiple CPU, IOP, USB, and key connections as well as connections for an LCD display, LED lights, and various input and output pins connected to chips and ports. Power is supplied through a VBUS connection and an ISP chip is used for programming.

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    BLK

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    The document shows a diagram of connections between various components on a circuit board. There are multiple CPU, IOP, USB, and key connections as well as connections for an LCD display, LED lights, and various input and output pins connected to chips and ports. Power is supplied through a VBUS connection and an ISP chip is used for programming.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    20 views1 page

    1768 Cpu Iop: Bb1343 - Iop - R00.Schdoc

    Uploaded by

    FernandoAdrián
    The document shows a diagram of connections between various components on a circuit board. There are multiple CPU, IOP, USB, and key connections as well as connections for an LCD display, LED lights, and various input and output pins connected to chips and ports. Power is supplied through a VBUS connection and an ISP chip is used for programming.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    of 1

    1 2 3 4 5 6 7 8

    A A

    1768 CPU IOP


    RST TxD0 TXD1
    RST RST TxD0 TxD0 TXD1
    ISP_176X_X4 RXD0 RXD1
    ISP_176X_X4 ISP_176X_X4 RXD0 RXD0 RXD1
    ISP TXD0_1343
    ISP ISP TXD0_1343
    USB_DM RST RXD0_1343
    USB_DM USB_DM RST RXD0_1343
    USB_DP
    USB_DP USB_DP
    VBUS_176X
    VBUS_176X VBUS_176X
    USB_C_176X
    USB_C_176X USB_C_176X
    TMS/SWDIO
    TMS/SWDIO
    KEY_X1 TCK/SWDCLK BB1343_IOP_R00.SchDoc
    KEY_X1 KEY_X1 TCK/SWDCLK
    KEY_X2 TDO/SWO
    KEY_X2 KEY_X2 TDO/SWO PWR
    KEY_X3 TDI
    KEY_X3 KEY_X3 TDI
    KEY_Y1
    KEY_Y1 KEY_Y1
    KEY_Y2 USB_DP
    KEY_Y2 KEY_Y2 USB_DP
    KEY_Y3 USB_DM
    KEY_Y3 KEY_Y3 USB_DM
    KEY_Y4 VBUS
    KEY_Y4 KEY_Y4 VBUS VBUS
    LCD_D7
    LCD_D7 LCD_D7
    LCD_D6
    LCD_D6 LCD_D6
    LCD_D5 BB1343_PWR_R00.SchDoc
    LCD_D5 LCD_D5
    LCD_D4
    LCD_D4 LCD_D4 PER
    LCD_EN
    LCD_EN LCD_EN
    LCD_RS ISP_1343 ADC_IN
    LCD_RS LCD_RS ISP_1343 ISP_1343 ADC_IN
    LED_0 KEY_X1 SCK
    B LED_0 LED_0 KEY_X1 SCK B
    LED_1 KEY_X2 SSEL
    LED_1 LED_1 KEY_X2 SSEL
    LED_2 KEY_X3 MOSI
    LED_2 LED_2 KEY_X3 MOSI
    LED_3 ISP_176X_X4 MISO
    LED_3 LED_3 ISP_176X_X4 MISO
    LED_4 KEY_Y1
    LED_4 LED_4 KEY_Y1
    LED_6 KEY_Y2 SDA
    LED_6 LED_6 KEY_Y2 SDA
    LED_7 KEY_Y3 SCL
    LED_7 LED_7 KEY_Y3 SCL
    ISP_1343 KEY_Y4
    ISP_1343 KEY_Y4
    LED_0
    LED_0
    TXD0_176X LCD_D4 LED_1
    TXD0_176X TXD0_176X LCD_D4 LED_1
    RXD0_176X LCD_D5 LED_2
    RXD0_176X RXD0_176X LCD_D5 LED_2
    TXD1 LCD_D6 LED_3
    TXD1 TXD1 LCD_D6 LED_3
    RXD1 LCD_D7 LED_4
    RXD1 RXD1 LCD_D7 LED_4
    TXD0_1343 LCD_EN LED_6
    TXD0_1343 TXD0_1343 LCD_EN LED_6
    RXD0_1343 LCD_RS LED_7
    RXD0_1343 RXD0_1343 LCD_RS LED_7
    TMS/SWDIO SSEL
    TMS/SWDIO SSEL SSEL
    TCK/SWDCLK SCK BB1343_PER_R00. SchDoc
    TCK/SWDCLK SCK SCK
    TDO/SWO MISO
    TDO/SWO MISO MISO
    TDI MOSI
    TDI MOSI MOSI

    EXT_SW
    EXT_SW
    EXT_SW
    LAN
    ADC_IN TXP
    ADC_IN ADC_IN TXP TXP
    RXP
    RXP RXP
    SCL TXN
    SCL SCL TXN TXN
    SDA RXN
    SDA SDA RXN RXN

    C P1.0_TXD0 BB1343_CPU_R00.SchDoc C
    P1.0_TXD0 P1.0_TXD0
    P1.9_RXD0
    P1.9_RXD0 P1.9_RXD0
    P1.1_TXD1
    P1.1_TXD1 P1.1_TXD1
    P1.10_RXD1
    P1.10_RXD1 P1.10_RXD1
    P1.14_RXER
    P1.14_RXER P1.14_RXER
    P1.8_CRS
    P1.8_CRS P1.8_CRS
    P1.16_MDC
    P1.16_MDC P1.16_MDC
    P1.4_TXEN
    P1.4_TXEN P1.4_TXEN
    P1.17_MDIO
    P1.17_MDIO P1.17_MDIO
    P1.15_REFCLK
    P1.15_REFCLK P1.15_REFCLK
    RSTOUTN
    RSTOUTN RSTOUTN

    BB1343_1768_R00.SchDoc BB1343_LAN_R00.SchDoc

    D D

    Title
    BB1343_BLK_R00.SchDoc
    Size Number Revision
    A3 00
    Date: 24/06/2011 Sheet of
    File: F:\BB1343_BLK_R00.SchDoc Drawn By: R2M ingenieria
    1 2 3 4 5 6 7 8

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