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    16 views56 pages

    Chap 08 - MPI - Avtar Singh

    Uploaded by

    Muhammad Hamza

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    © All Rights Reserved
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    of 56
    088 and 8086 Pin the guration and Their Memory and Input/Output interfaces 4 INTRODUCTION tots point in the book, iew. We have covered the Foran in assembly langu view. This 1S not true of ‘2 8 begin examining Sapte, we Cover the 8088; Ext. The chapters that “SP ineludes the foto We have studied the 8088 and 8086 microprocessors from a software poi cir software architecture, instruction set, how to write, exc ad age, and found that the 8088 and 8086 were identical fom tesa f the hardware architectures of the 8088 and 8086 a i ite the 8088 and 8086 microcomputer from the hardware pot of view: i 8086's signal interfaces, memory interfaces, iaealeea ieesrentts follow cover other hardware and interfucing aspect wing topics: 81 8088 ang 8086 12. Minimum Mode and Maximum-Mode Systems 8 inimum-Mode Interface Signals 854 pe™™-Mode Interface Signals 86 qtttical Characteristics : lock Microprocessors stem Clo, hh The 808% ang 4 Bogg 316 . | can Tl ary Address Space | oro rizaion of the MCmery Ad | gs Hardware Organiza | sg. Address Bus Sta is C a 8.10 Memory sontral Sigal i 811 Read and Write Bus Cye i 2 Memory terface CHEUNS S12 Men Ie 8.13 Programmable 1 pat Output S14 Types of Inpat 8 © jemaed Input Outpt terface ata Transfers 8.16 Input Outpat Di 8.17 Input‘Output Inst S18 Input Output Bus Cycles iructions A 8.1 8088 AND 8086 MICROPROCESSORS se sos, announced in 1978, was the first 16-bit microprocessor introduced by Ing Nahe ofthe 8086 family, the 8088 microprocessor, followed iin 1979. The gngy pss = vessor, the 8086, The difference between these two dey. ware compatible with its predec he e : seshoanecrchitectre, Just like the 8086, the 8088 is internally a 16-bit MPU. However, ena ‘8086 has a 16-bit data bus, and the 8088 has an 8-bit data bus. This is the key hardware itferens & devices have the ability to address up to | Mbyte of memory via their 20-bit address buses they can address up to 64K of byte-wide input/output ports, "The S088 and 8086 are both manufactured using high-performance metal-oxide Semin, | (HMOS) technology, and the circuitry on their chips is equivalent to approximately 29,000 x. They’ are housed in a 40-pin dual in-line package. This package can be mounted into a soa s soldered to the circuit board or have its leads inserted through holes in the board and solder signals pinned out to each lead are shown in Figs. 8-1 (a) and (b), respectively. Many of their pits, | multiple functions. For example, in the pin layout diagram of the 8088, we see that address bus ia, | through A; and data bus lines Dp through D, are multiplexed. For this reason, these leads are live ADp through AD,,. By multiplexed we mean that the same physical pin carries an address bit atc and the data bit at another time. - devices — oO _ ——_—_ At what pin location on the 8088's package is address bit Aj, output? With what other sigs!s! EXAMPLE 8.1 | | multiplexed? What function does this pin serve on the 8086? | | Solution Looking at Fig. #-M(a), we find that the si signal Ay, is 38 and st? multiplexed with signal S,. ignal Ay, is located at pin 38 on the 80 . igure 8-1(b) shows us that pin 38 serves the same functions oa A 8.2 MINIMUM-MODE AND. MAXIMUM-MODE SYSTEMS. The 8088 and 8086 microprocessors ean be conti mum mode or the maximum mode. eet configured to work in either of two modes: The minimum mode is selected by applying 37 sors onan _ aie) Wow aaiaT, wm son OR 7 "Gy ay oR bi mm (280) AE tase) (as) @ r Fire 8-1.) Pin layout of the 8088 mi S'S seoprocessor. (Reprinted with pemmission of Intel Corporation, © 1979) ) th pera s0F (Reprinted with permission of Intel Corporation, ©1981) (6) Pin layout “NM input lead, Minimum mode 8088/8086 systems are typically smaller and contain a single =coprocessor. Connecting MN/MX to logic 0 selects the maximum mode of operation. This ‘aiques the 8088/8086 system for use in larger systems and with multiple processors. This mode- ‘lection feature lets the 8088 or 8086 better meet the needs of a wide variety of system *pirements, Pending on the mode of operation selected, the assignments for a number of the pins ame "S80 package are changed. As Fig. 8-1(a) shows, the pin functions of the 8088 specifi ‘tleses pertain to a maximum-mode system. ee The signals of the 808g microprocessor common to both modes of ere Gr os Daly and those unique to maximum mode, are listed in Figs. peer the signal RD is in comme, find the name, function, and type for each signal. For example eo devices en the pe Tt functions as a read control output and is used to: ign Hhevsignas Bok! rust fou a a ® system bus is set up to read in data. Moreover, mi von It abe 5 ‘ i -mode sy 1g acknowledge (HLDA) are produced only in the minimum RgE wp for Maximum mode, they are replaced by the request/gra sed RQGT, ’ The 0085 q 318 aNd gy Me, "% ———— (Common sign Name Function Type Data enable AO | Aienlanates | Wavecioond = oe Bstate S50 ‘Status tine nisas | Adsentus ouput satate Ait | Addessech ety Adsresustans output WA | interstate state, — Minimum/maximum, Input (b) ede contal Read conta output datate 7 watontecostat — | nue Reet oN Oa ‘Wait state control Input Function ‘System reset, Input Rat Request/grant bus ‘Nonmaskable Input access control Interptrequest TR —_ | usprortyleck TR Interrupt request Input control a eee ima 5-8 | suseysestaus Ve | asy opt 251.050 | struction queve GND Ground status f Figure &2_ (a Signals common to bth minimum and maximum modes. (b) Unique minimus ‘maximam-mode signals EXAMPLE 8.2 a . ” ot Which pins provide different signal functions in the minimum-mode 8088 and minimut 8046? Solution Comparing the pin layouts ofthe 8088 and 8086 in Fig, 8-1, we find the following: 1. Pins 2 through 8 on the 8088 are address Hines A, through A, but on the 8086 they a address/data lines AD,, through AD, 2, Pin 28 on the 8088 is the ion figurati in Confit 319 so? NALS Vogal wove INTERFACE SIG “ 7 elected, the 8088 oF 8086 itself eration is 5 Provides all the contol signal cn and VO interfaces, Figures §-Na) and (hy show Gee diagrams i the meri of the ROSS and 8OR6, respectively rn aeg the follo my int headdress data bus In an BOSS-based microcomputer system, thes lines fit lok at pus, they are used to carry address information to the memory bee A a tr slong and consists of signal lines A, through Ay. OF these, A, Tepresent Theale: Po EA 20-bit address gives the 8088 a 1 Mbyte memory address space Hina. sp and Ay eneny Ays are usesLashen accessing VO, This gives the 8084 sp independent 10 =) abs es 94 Kbytes in length ; = Fe hus lines Dg through D, are actually multiplexed with address lines Ao through A,, iiecet sins reason they are denoted as ADp through AD,. Data line D. se ye LSB. When acting 2s a data bus, yaar Dy is the MSB in the byte they carry read/write data for memo, {See0 deviees, and interrupt-type codes from an interrupt control po fr 10 dev 1, input output ler. ve the 8086 has 16 data bus. “king at Fig. 8-3(b), we see that soilexed with address Tines Ap through Aj, and are there cost Power supply Ve GND Adressdatabus inte To AoA AWS /55 im biempt viene TS [> tears vat ae rae |—_. 5 08 a we ee | tt ‘controls | va HOLD os | bec oy |__, 7 | |_» wa | Vee = | -—— | Mode — | << tao | ee MN ak lock @ rane S088 MPU Figure 8-3 (a) Block disgram of the minim Le —_— TH G000 and igs 320 \ Aressidota tus AS » ——| K : w \ nn, nm -—)] wrt gl wn —— }—__» Ate co} wwe | eg, = (MPU = $i 0 Ween [> ort com ce oa -——> tretist 4a, 7 -———> ia e -——> dN Mos ag . |\-+—— rtany a Clock oy Figure 8-3. (b) Block diagram ofthe minimum-mode 8086 MPU, Status Signals The four most signifi maltiplened, but in this 16 Of both the 8088 and 8086 res the same time that data are trans These status bits are output. ls. Bits S, and Sy together fora 25 Address Status ‘Atermate(relative tothe ES segment) Stack elative tothe 5 segment) Code/None (relative ‘ment ora detauit Data Wve to the DS segment) ‘With permission of Intel Corporation, © 1979) fe 10 the CS seg of zero) uration pin conti 324 rovided to support the memory and /O interfaces of nen the bus carries a valid address, which die n o8 a8d HORE, no Sch as WI ction data estos St eit data are on the bus, ad when o put real data on i eee ce bus werch enable (ALE) is a pulse to logic 1 that signals external cing. Ae es = OnE so MPU woe ages Wocalbus FOIGT, ROT, control fa) os Figure 8-8 (a) 8088 maximum-mode system configuration, “ned. In tum, the 8288 makes its [ORC output switch to logic 0. On the other hand, if the code ‘Soutput by the 8088, it is signaling that no bus activity is to take place: the 8, mand | Signals, 8 produces no _gy oer control outputs Produced by the 8288 consist of DEN, DT/R, and ALE, These these oo Povide the same fu bus ¢ ictions as those describe ni Figure 8-5(b) shows that ‘ontre i ibed for the minimum mode: teu : a rei Seal cts to the 8086 in the same way as the 8088, and it also produces the same als, oe command te “yan code §. ity is taking place? Which Need by a 28 Sq equals 101, what type of bus acti the 8288? 324 e, us code 101 identifies a read Fig, 8-7, we see that bus status ¢¢ nt sd mem ete tHe utut of te ths controtfer to be switched (0 Topic 0 OY ig . ° eh ey, Lock Signal To implement a multi ‘8086. This signal is meant processors from using the bus. This wor signal is eompatible with the Maultius, a multiprocessor environment. Solution processor systema signal called ek (LOCK) is provideg to be output (logic 0) whenever the processor wants to | OM the bie ld be the case when a shared resource is neotk Out he ‘an industry standard for interfacing mmicroprocaa ie SO itn |» moe TE |—» jamie [> lone > TOWC > ROWE AE nk [> McerPoEN x —>] reset —>l el NE wwie wer, wer, as 1 oer, a » Figure 8-5 (6 ) 8086 maxima ‘mmum-mode system conf configuration. figuration 325 vy oso" con U an “ — HF] sinus, oh c] vecooes AMO i SIGNAL Genie ‘ATOR LL |-}—- ori -] CONTROL Pa wou |] Sstcrat’ | —=]}-—= 088 Soa" |} cen: |-=] > cero aton |_| ate 4 cho (a) a wa apnmete 888 apm wit misono il Copan 19) abe at oS on ll Corporation, © 1979) queue Status Signals Two ber signals produced by the 8088 and 8086, in the maximums | at nai fs >| canoer | ate nan |/+———»| 8088 ni Figure 8-19 Maximum-mode 8088 memory interface. Figure 8-20 shows the relationship between the bus status codes and the types o produced, Also shown inthis chat are the names of the corresponding command signal thay at the outputs of the 8288, For instance, the input code 8,8), equal to 100 indicates that ap ime fetch bus cycle isto tke place. Since the instruction fetch is a memory rea, the 828 makes read command (MRDC) output switch to logic 0. oo Another bus command provided forthe memory subsystem is S,8 Sp equal to 110. This a memory write cycle and it causes both the memory write command (MWTC) and advanced write command (AMWC) outputs to switch to the 0 logic level. The other control outputs produced by the 8288 are DEN, DT/R, and ALE. These signals pts same functions as those produced by the corresponding pins on the 8088 in the minimum syem mb The two status signals, QS, and QS,, form an instruction queue code. This code tells te ex circuitry what type of information was removed from the queue during the previous clock ce F 8-8 shows the four different queue statuses. For instance, QS,QS, = 01 indicates thatthe fis Status Inputs > CPU Cy 8288 Command afs]s 0 | 0 | © | Interrupt acknowledge | iNTA © | 0] 1 | Read 10 port ORC ©} 1 | 0} writev0 port owe, ATOWe ott | na None 1 [0 [0 | tastruction etch RDS 1] 0} 1] Read memory RDC Ut | 0] write memory SWC, ANE tT TT tase ‘None of Figure 20 Memory bs cyl sats codes produced in maximum made, (Reprinted with persion of | The next byte OF the instruction thar due to a transfer ot rant red, as A ene fer Of contro} atic cue Ope on cole ifno au Status code 00 is outp alizatiy pone Sila TACK) signal as shown in the interface, can f ne n airy lock Ch 7 nt Pe used ay an “ me ised 10 Fock other processors OfF the syste n bus during 4M MPU to a bus J memory in a multiprocessor system. The READY, of common wis at globe ps ch as gloha ved to int inter. os evi pct ay 2 ee) a on i cen ts memory interface, the BI oe pm the SOBO 8 5 control signals we just described for the 8OR8-bas the maximum-mode 8086 microcomputer. Howe 2. The BHE performs n enable input to the hig ‘ed microcomputer g ver, there is one addi 4p AND WRITE BUS CYCLES ithe ciion we introduced the status and control signals tinue by studying the sequence in which they occur ociated with the memory inter- uring the read and write bus teed cycle fgee $21 shows the memory interface signals of a minimum-mode 8088 system. Here thei seis ilistrated relative to the four time states T,, T>, Ts, and T, of the 8088's bus cycle. Let us nts that occur as data or instructions are read from memory. " The wad bus cycle begins with state T,. During this period, the 8088 outputs the 20-bit address of zen0ty location to be accessed on its multiplexed address/data bus ADs through AD., A, through \ camutiplexed lines A,¢/S, through A, 9/S,, Note that at the same time a pulse is also produced at ~The walling edge or the high level of this pulse should be used to latch the address in extemal ‘sowe see that at the start of T,, signals IO/M and DT/R are set to the 0 logic level. This indicates in the memory subsystem that a memory cycle is in progress and that the 8088 is going to 4 from the bus. Status SSO is also output at this time. Note that all three of these signals are sel at these logic levels throughout all four periods of the bus cycle. 2ecianng with state T,, status bits S, through S, are output on the upper four adress bus nes «| uth Aig. Remember that bits S, and S, identify to external circuitry which sesrieh! A coy al eeerate the address just output, This status information is maintained tens Pt Tagg ett ofthe address output on address bus lines A through Ays Cae ghz ae cefq {Te On the other hand, address/data bus lines ADg through ADy a= Pu Lain per Big ; ™ Period T,, RD is switched to logic 0. This indicat “enema BSS. DEN is switched to logic 0 to enable extern J Onto the microprocessor’s data bus. “ea gan tthe waveforms, input data are read by the SONS Svitigis se 13 And maintain it until after the processor ie J | (Mra yy’ that the 8088 switches RD to the inaetive I fot "fgg inactive logi during T, to disable | tom logic level late during Ts ' ly to the processor. The read cycle ' Ipsystern that 4 read ‘es to the memory sut the data to move al circuitry tallow g Ty. Them ing Ty on. 8088 oa dopa the rea yo termite palo a The 338 Owe tab oy 530 --/ Figure $21 Minimum-mode memory cad bus eyeleof the BOSS. (Reprinted with permission of Intel Co, {A timing diagram for the 8086's memory read eyele is given in Fig, 8-22(a), Compara: ‘Waveforms to those of the 8088 in Fig. 8-21, we find just four differenc BHE is output alo address during T,; the data read by the 8086 during T; can be carried over all 16 data bus li which replaces 10/ is switched to logic 1 at the beginning OFT, and is held at this level forte of the bus cycle; and the SSO status signal is not produced. Figure 8-22(b) shows a read cycle of 8-bit data ina maximum-mode 8086-based system. These waveforms are similar to those gi Comparing these ginning of the bus cycle. This s by the 8288 to produce o i EMR information ‘ls ALE, MRDC, DT/R, and DEN. Write Cycle ‘ ist sven Be 8-23) illustrates the write buy cvele tims ima me. gi foraread cycle in Fig 21 Loounastn write a {s oupat and latched with the T ALE pulse. This is idemtica fF ation «rn conti i038 339 woop fromseennes ee (ee pooness oR a . el “wt avs conouien ourrurs o sc ion ot or 6. Reprint Tete ‘ Fe BORG. (REPT ET Tap meme Mode memory read bus cycle ofthe 80 Fesion of 1 " it mi 7 Tead bus eyele ofthe 8086. (Reprinted with Pe! 31 — coef creat = jet] fb) Mauman-mode memory write bus cycle of the HO, (Reprinted with permission of Intel € ‘orperation. ©1779) sserface diagram for a maximum-mode 4086-based microcomputer system, Here d that ss includes the 8288 bus controller, address bus | latches and an address, decoder, data bus 1 The 04% microcomputer is simpler in that ~4oes not require bank write control lo; se its address space is organized as a single bank de signals S>, 5), and S,, which are putputs of troller. Here they are decoded to produce tl te data transfers over the bus. Figure 8-20 ‘at relate to the memory interface. For example, the code $.5,5, = 101 the bys ae MEMOrY read bus cycle is in Progress. This code makes the MEDC command cl gen logic switch to logic 0. Note in Fig. 8-24 that MRDC i applied to the ban " nee US look at how ns PS the status codes th; “tS that a dat teak the address bus is latched, buffered, and decoded Looking The hatched lines A, through Ay, are latched along with control signal BHE in " ' as PCE Notice e's HES Ayn, through Ajo, are decoded to produce chip enable o pas Cs Le at the 8288 bus controller produces the address latch enable (ALE ee Signaling nied 80 the CLK. input of the latches and stores the bits oft a reed PAL thro the Adress bus latches. The address latch devices butler ane ae ent through, Ave. and CE, through CE, are applied directly to the med aaa he menO™ €¥eles, the MADE Output of the bus contol logic enables the bots oe "ak read Subsystem onto data bus lines Da through Dy. During read ons ‘eh. This get?! logic determines whether the data are rea! fom one ofthe depends on whether a byte- or word-data transfer is taking pls banks the two memory ae over the BS The 8088, and Bog6 ity hee, 342 ‘ Adross | — acoder |__ ___n} ada 1 : bus A Badan “R-eak— tah a. we |-— pe cK lie Bonk vite || contro if >| “oaie —+| i i coe AE | | | . are Me j< Bus. Lo} Bank ogi SL-— [-— Preonteoter read [|-———> 75, tad |g, 8288 NROC| >| control : : ee >| “osie li, DTIR_DEN| | | | oR eM — See | nti iD) ae, | ranscever buler Ready Figure 8-24 Memory interface block diagram. Similarly during write bus cycles, the MWTC ‘output of the bus control logic enables bytes of from the data bus D, through D, ; to be written into the memory. The bank write control logic detemizs to which memory bank the data are written, Note in Fig. 8-24 that in the bank write control logic the latched bank high enable signal BREL and address line Ap, ate gated with the memory write command signal MWTC to produce as! ‘write enable signal for each bank. These signals are denoted as WR,, and WR, For example, if2¥°% of data isto be writen to memory over data bus lines Dp through D; both WR, and WR, ares to their active 0 logic level. Similarly the memory read control logic uses MRDC. Aq. and BHEL® generate RD, and RD,, signals for bank read control . The bus transceivers control the direction of data transfer between the MPU and ne subsystem, In Fig, 8-24, we se that the operation of the transceivers is controlled by the DTR aM? ‘outputs of the bus controller. DEN is applied to the EN input of the transceivers and enables i peration This happens during all read and write bus eyes, TT/R selects the direction of 0 through the devices, Note that itis supplied to the DIR input of the data bus transceivers. ‘When cycle is in progress. DT/R is set to 0 und data are passed from the memory subsystem t0 the the other hand, when a write eyele i taking ph 7 a vel g place. DUR is swite i ta ar the MPU tothe memory subsystem nn DT Ris swuched to logic | and — pin comiguraion 86 a 4) & ft 09 | » | | Inputs z | TE Enatoc 0 ie 4 \ H L " hy ae ; Ra ee © Operation eo OF a0 octal D-type latch, (b) Circuit iggeain of the i r i on ofthe 74F373. (Courtesy of Texas nsrunen's nee q The 8088 an, 1 8086 6 Mi 344 on Address Bus Latches and Buffers . eof an octal latch device that can be used to imple, | agp 372 is an example ofan octal fate Impleme The 744 terface circuit, A block diagram of this device js Shon own i Tay s0s6's memory int jon of the cuitry is shown Saal in Fig, 8-250), Note tht i accepts eight np yg E42 + rtpek (Cut isa Togc 1 the outputs ofthe D-type flip-flops oll te jy 4 Fo their corresponding inputs. When C is switched t0 logic 0, the curren, Intched. The latched information in the flip-ops is not output i op theonah $0 unless the outputecontrol (OC) input of the buffers that follow the latches i benga s teat tewie I, the outputs are inthe high-impedance state. Figure 8-25(c) summarizes th logic g 59 Th the S086 microcomputer system, the 20 address lines (ADg-AD ys, Aig-A,,) ange cnable signal BHE are normally latched in the address bus latch. The circuit configuratic the by $-26 can be used to latch these signals. Fixing OC at the 0 logic level permanently enable show, puts Ag, through A jo, and BHTEL. Moreover, the address information is latched at the ous 7 signal from the bus controller returns to logic 0—that is, when the CLK input of all dey ioe applied Datype Mip-fops are i thea 1S Swi 1 logic 0. In general, itis important to minimize the propagation delay of the address signal through the bus interface circuit. The switching property of the 74F373 latches that eae aa for the circuit of Fig. 8-26 is called enable-to-output propagation delay and has a maximuy mts By selecting fast latches—that is, latches with a shorter propagation delay time—a ao Rin anes a ne: Latched address tus AOHADs Mey TOGA 12 Thea ‘Address latch fox 1007 peda iL ‘Address latch (ctk a 2099 [2) pone oC Figure 8-26 Address latch circuit, & 5 m3 Figure 8-27 Bank write conto logic. sts coe ies preserved fr the aseess time ofthe memory dies Ih doer sre 1Cs cn e used. These latches also provide burn forthe 86's aie Ce sof etch can sink maximum of 24 mA, sankWrite and Bank Read Control Logic Tie memory of the 8086 microcomputer is organized in upper and lower banks It requis ssexz wile and read control signals for the two banks. The logic circuit in Fig. -27 shows bow the ‘rie contol signals, WRy for the upper bank and WR, for the lower bank can be generated fms =scoaole signals WRTC, the address bus latch signals Ay, and BHEL. Two OR gates ae used fnkipupose, Senlarto the bank write control logic circuit, the bank read control logic circuit canbe dsined ‘ret RD, the read for the upper bank of memory, and 'RD,, the read for the lower bank. Figure 8-23 “ses sch a circuit. Note that the circuit uses the MRDC signal from the bus controller. Figure $28 Bank rodeo! al 346 The 8088 ang MO Mig, a Data Bus Transceivers cceawr block of the bus interface eirenit an be jp “Figure 8 29(a) shows a block diagean of this ees ie The data tat bus transe ICs. Pigun : jut output lines are called Ay thn is Sob) ee soo that the G input is used 0 enable the buffer tor ope, leMenteg ©. Non Win ough Ag and By through By Lookine meth AU the gS ci 08. On i in rg 2 tomat elocta the direction a the nee level atthe diteetion (DIR) input selects the direction in which Hata ate tana _ eth hy “he a no Le A ~———>| Le? A + pa >araas A+ tS <—— a — L a < | CS eee eee (a) ” “ED (G (19) — @ P U9 at tT] 8) % Li) 4, a 7) ar e (16) ©) Fe os a 9 a) AS (9) Ba Ps 55 f ) (AB ~ AB) Figure 8-2 i 8-37 (a) Basic PLA architecture. (b) Implementing the logic function F fed teir compl x le = = ion of oe A and B. Programmable connections in the AND amay Pet "Dany are Rei to be combined to form a product term. The product term om (0 fixed inputs of the OR array. The output ‘of the OR gate produces 2 rdeety function, Fi n yop ieuit ion Finally, the inverter complements this function. “OR. ‘ig. 8-37(b) shows how the function F=(AB+? means that the £28" Nome TN ng me f oeanees that thas ben Blown o form am oP eo Rand B 4 and B and produces the product term “agtisnotin produce the product term AB. The bottom ing, '°t 18 use. Gates like this that are not to be active that an X marked into the AND array circuit. For this tease" ‘AB. The second AND #4 [AND gate is should have al tke ofth ost widely welt 7 rae! wen news the circuit structure that is oe eee e837) in two ways. Firs the vaverter has 8 POE ut op jit the logic function from the outPU second, the bu PUIS to the AND array. This new utp! ‘configu tion Pe i The 8088 and 8086 Mig, "Oto, 354 Ona, eur ENABLE FEEDBACK (b) Figure #-38 (a) Typical PLA architecture, Courtesy of Texas Insiruments Incorporated) (b) PLA with output atch (Co ‘of Texas Instruments Incorporated) programmed to work asa standard ouput, standard input, ot logic-controlled input/output. Fors jenly if the upper AND gate, which is the control gate for the output buffer, is set up to perman. the inverter, and the fuse links for its inputs that are fed back from the outputs are all blown oF hes output functions as a standard output PLAs are also available in which the outputs are latched with registers. Figure 8-38(0) circuit for this type of device. Here we see that the output of the OR gate is applied to the Dis?" aclocked D-type flip-flop. In this way, the logic level produced by the AND-OR array is not pee at the output until a pulse is first applied at the CLOCK input. Furthermore, the feedback inpet duced from the complemented output of the flip-flop, not the output of the inverter. This

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