JVC SARA RX-554RBKe RX-554RBKeE U.K. Continental Europe East Europe ~ North Europe liRemote lll @BRD'S FON Contents Safety Precautions AD Adjustment Procedures -—- = 216 Instruction Book 1-4~27 Block Diagrams - 217 Description of Major ICs ~ 24 Schematic Diagrams 2-19 Internal Connection of Display ------- 2-13 Printed Circuit Boards - 2:24~27 Disassembly Procedures --- 2-14 Parts List 31~13 COPYRIGHT © 1998 VICTOR COMPANY OF JAPAN, LTD. No.20673 Mar. 1998Description of major ICs 9MN173222JABN1(IC401):System Control Micon RX554RBK 4.Trminal Layout 2.Key Matrix WO ee RETO] Pome AOL REY OT 1 [SURROUND | PRESET SEX] TONED | — SETTING S402 sea S404 40s FEY oa F | SouRee Toaust | — BE, | —aeore 408 S407 ss S408 Revers] suo | cosa [Asie [Yona er aT S| Eon | TamERS/iNFO| Pry seLecr [DISPLAY WODE 3.Pin Function ae sus esi, Seo Pin No.|_Synbol_|vo| Function R|_Synbol_|vo) Function 1 IN1___| 1 [JOG VOLUME control s2[ CE | 0| Chip enable to 1C121 2 IN2__[1 [JOG VOLUME control 53] CK | O| Clock signal 0 C121 3__| VidEOt [0] Video select signal 54] 01 __[ 1 | Data signal from 10121 4 | ViDEO2 |O| Video select signal 55] 00 | O| Data signal to 1121 5 _| PROTECT | 1 | Protector signal input 56] OCSi_| 1 | COMPULINK signal input 6 | POWER |O| Power ON/OFF control 57| DCSO_| | COMPULINK signal output 7 Kio__[ 1 | Key matrix input 58[ DSP ERR | 1 | Error flag input 8 Kit__[1 | Key matrix input ‘59 [DSP IFOK] 1 | Oreration flag input 3 Ki2_[1 | Key matrix input 60 | DSP ACK | 1 | Acknowledge signal input 40 Kis_[1 | Key matrix input 61] DSPCS | O| Chip serect signal output 11_| vor sic [1 | VCR SIC serect signal input___[62| TMUTE | O| Tuner mute signal output 12_[ G11 [0] Grid control signal output 63] S.MUTE | O| Source muting contro! 13_| G10 [0] Grid control signal output 64] TV. CONT | - | Pull down 14 G3_[O] Grid control signal output 65| TvouT | -| Pulldown 15 G8__[O| Grid control & Key matrix output [66| VCR OUT | - | Pull down 16 G7__[O] Grid control & Key matrix output [67 VCRIN_| - | Pulldown 7 G6 [0] Grid control & Key matrix output [68 [RESET IN| 1 | Reset signal input 18 G5 [0] Grid control & Key matrix output [69] _x1__| - | Connect to GND 19 G4__ [0] Grid control signal output 70[ _x2__| = | Non connect 20 G3 [0] Grid contro! & Key matrix output {71| _Vss__| - | Connect to GND. 21 G2__[0| Grid control & Key matrix output [72 | OSC2_| - | Oscillation terminal 22_| a1Ko7 [0] Grid contro! & Key matrix output [73[ Osc1_| - | Oscillation terminal 23 | Vpp [= | Power supply for FL display 74|__vod_| - | Power supply [24~39| S1~S16 [0] Segment control signal output__|75| _SET1_| O| SETTING indication control 40_| Dvp sic [1] DVD SIC select signal input 76| ADJ | 0| ADJUST indication control 41_|CLKD [O| Clock signal to 10601 77| SURI | O| SURROUND indication control 42 _ [DATA OUT [O| Data signal to IC601 78 |SOURCE.|| O| SOURCE indication control 43_[_DATAIN [1 [ Data signal from IC601 73| SEAI_ | O[ SEA indication control 44_[ INH [1 | inhibit signal input 80| BAND’ | 0] TUNERIBANDindication contor 45_| ROS CLK [0] Clock signal output @1| STB | O| Strobe signal to 46_| RDS DATA 1 | Data signal input 10341 ~343,252.321.302 47_|RDSRESET|O | Reset signal output @2[ DATA | O| Data signal to 48 RM___[1| Remocon signal from 1C402 1C341~943,252.921.922.404 49_| D-STAAT | 1 | Data start signal input 3] CLK | O] Clock signal to 50_| STEREO | 1 | Stereo signal input IC341~343.252.321.322.404 51_| TUNED | 1 | Tuning signal input 84 STB(EX) | O| Strobe signal to 1C404 BA— Sova }—+| —] sasise:tos [>| aoe >| >| Ie sibzos b+— Tova OTT) |-—+| seisBeroog | — ova [—| 1S >| +f Woav }+— Tt seybaois be @oav | neg | I-NON i 2a ft 38 i >p01a OV §§TC9471F(IC601):Dolby Prologic 1.Block Diagram RX554RBK — + ao xp wera <4 + a) \ oat ] 2 la wo) + ur ls t 5 azexm, ‘uo + got x ro aol x moze ‘agi x mogz abe x masz owId — Wvus0 Wd woud, Wyud Woke t z z Z ; “py 607 un ues bet pt © by ov un 9 4a 1 itt ar ttt it Et J) eos Ge) wo tun | | \ ° snga 222-a.Pin Function RX554RBK PinNo. | _Symbol__| v0 Function i ECKO__|_O | Amplifier output terminal for external clock input. 2 ECKI | Amplifier input terminal for external clock input. 3 GNDX__|_- | Ground terminal. (For crystal oscillator circuit) 4 GNDAL | - | Ground terminal (For DAC L channel) 5 ‘AOL (© | DAC analog signal output terminal.(L channel) 6 VAL -__| Reference voltage terminal.(For DAC L channel) 7 VOAL =| Power supply terminal.(For DAC L channel) 8 voaR _|_— | Power supply terminal.(For DAC R channel) 9 VAR ~__| Reference voltage terminal (For DAC A channel) i0 ‘AOR. ‘© | DAC analog signal output terminal.(R channel) 1 GNDAR_|— | Ground terminal.(For DAC R channel), 12 Gnpac | — | Ground terminal.(For DAC C channel) 13 ‘AOC. ‘© | DAC analog signal output terminal.(C channel) 4 ‘oct | _O | DAC analog signal output terminal with attenuator. (For C channel) 15 VRC. =| Reference voltage terminal.(For DAC C channel) 16 VDAC =_| Power supply terminal. (For DAC C channel) 7 ‘VRO (© | Reference voltage terminal for attenuator (Output buffer) 18 VAI 1_| Reference voltage terminal for attenuator (Input buffer) 19 VDAS. =| Power supply terminal (For DAC S channel) 20 VRS =_| Reference voltage terminal.(For DAG § channel) 24 ‘AOST | © | DAC analog signal output terminal with attenuator (For S channel) A ‘AOS (©_| DAC analog signal output terminal (S channel) 23 GNDAS_|_- | Ground terminal.(For DAC S channel) 24 GND =| Ground terminal. 25~29 | Tpo~4 | © | Test data output terminal, normally open. 30, ‘VoD. ~_| Power supply terminal. 31 voor |" = | Power supply terminal.(For DLRAM) 32 GNoR__|_— | Ground terminal.(For DLRAM) 33~40 | Te5~12 | 0 | Test data output terminal normally open. a FS ‘0 | Clock output terminal.(1fs) 42 KOO [0 | Clock output terminal 0. 43 cKo1__| _O | Clock output terminal 1. 44 GND =| Ground terminal 5 7P13 | © | Test data output terminal normally open. 46 mck | 0 | Master clock output terminal. (256fs/5 1218/(384/768f6)) 47 VoD, -_| Power supply terminal 48~53 | TP14~19 | _O | Test data output terminal;normally open. 54 CKS 1_| Master clock select terminal. 55 STEPO_|_1_| Operation step select terminal 0 56 ‘STEP1 1_| Operation step select terminal 1 57 RST 1_| Reset signal input terminal 23RX554RBK 2a 2-bPin Function Pino. | Symbol | vO Function 38 VoD =_| Power supply terminal 59, SYNC__|_1_| Synchronous signal input terminal 60, ELRO__|_1_| LR clock input terminal for serial data output. Gl ELRI T_| ER clock input terminal for serial data input. 2 EBCO__| |_| Bitclock input terminal for serial data output. 63 EBC! T_ | Bit clock input terminal for serial data input. 64 DIN |_| Serial data input terminal 65 DouT |__| Serial data output terminal. 66 EMO 1_| De-emphasis select terminal 0. 67 EM1 |_| De-emphasis select terminal 1. 68 IFFO 1 | Interface flag terminal 0. 69 FE [Interface flag terminal 1 70. FF | Interface flag terminal 2 7H ‘GND =_| Ground terminal. 72 cs 1_| Chip select signal input terminal (MCU interface) 73 TECK 1 | Data sift clock input terminal (MCU interface) 74 1FD| | UO | Data input terminal.(MCU interface) At the IC bus mode.data input /output terminal. % 1FDO | © | Data output terminal.(MCU interface) At the IC bus mode,normally open. 76 IFOK |__| Operation flag output terminal, (MCU interface) 77, ‘ACK | _O_| Acknowledge signal output terminal.(MCU interface) 78. ERR | _O_| Error flag output terminal(MCU interface) 73, 12cS, 1_[ IC bus mode select terminal. 80, Boot _|_1_| Self-boot control terminal. at BAO 1_| Boot address select terminal 0. 2 BAI 1_| Boot address select terminal 1. 83 ‘VoD =| Power supply terminal 84~87 | TSTO~3_|_1_| Test data input torminal normally ixed'L "level 88 GND. ~_| Ground terminal 89 VSAL = [Analog ground terminal.(For ADC L channel) 90 LIN 1 [ADC analog signal input terminal. (L channel) ot AVAL =| Reference voltage terminal.(For ADC L channel) 92, VDL = _| Analog power supply terminal.(For ADC L channel) 93, VOR =| Analog power supply terminal.(For ADC Ri channel) 34 ‘AVRR | -_| Reference voltage terminal.(For ADC R channel) 95 RIN 1_[ ADC analog signal input terminal.(R channel) 96 VsAR__|_-__| Analog ground terminal(For ADC R channel) 7 GNDX__| =| Ground terminal. (For crystal oscillator circuit) 98 XI _| Crystal oscillator connection terminal.} ariaoine >} sanneass [>] RECONSTRUCTION AND guauryar | i FILTER (8th ORDER) DIVIDER ENETATOR ¥ ] —____F tet « |—+{— costas oop BPRASE [74 ctooKeo VARRIASLE AND »| Sywoot prrrenennal} fo) [COMPARATOR], | FIXWD DIVIDER DECODER| >» 3 > i +175] Lock REFERENOE TESTLOGIC ANO OUTPUT at VOLTEGE REGENERATION SELECTOR SWITCH fl O f f T TJ bol eyRXS54RBK 9M5243P12(IC251):S.E.A. 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UH H_ | vins —fe]v+ ' i t 5] vinRX554RBK Internal Connections for FL Display Tube QLF0002-001 (D1401):FL DISPLAY TUBE ba ‘98 | MUTE (TUNED) VISUAL CONFIRMATION BLEED) Sea 8D-PHONICL, AUTO [STEREO] PAO LOGIC SCH LOGICHALL CSAP || LOUDNESS cor | el ola [sEaeon GH- ind Bee if Ta a) vii e| ieee 36 6 7G 86 36 6 fnysiuaun il Vin "= bp =F" (26-96) ANODE CONNECTION 1G. 2G. anes | 76 8G 96 126 ve | e1 | MUTE AUTO * e |e e [| = BI re | [TUNED i i » te |. 2 | EON °3 | (STEREO) 7 7 > | 8 | CTA P4 |ISUAL CONFIRMATION, « « x « « Ba DNEWS | n » fom ® as _| SINFO ‘ it 98 = * = [Le = 27 = a fs 2 28 = = = |. e 29 = a a ae . an oa > [uous | - 6 e a « [ca ~ be MHZ | stone | - | - [kHz | VOT PIN CONNECTION _ PIN NO. aaa SSSI E : connection felehyultlelelelielsialalls Wdepleleb | |RX554RBK i reva~zer TONAL I~ 2 =, bewiiatco] [alfa] [fuot Sow waQNVa Terg~arra SIRE oe BES] | woltSou EYED (ses, 38: wourl pees eoro oro | 42? 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FX PIOID SICK. RX-554RBK 219RX-554RBK IPOWER SUPPLY SECTION UAUS/UT/ALE TO SHEET 2/7we PTT Tera To SHEET 277 VERSION CODES EN: NORDIC COUNTRIES E+ CONTINENTAL EUROPE EE: EASTERN EUROPE BUNK c! CANADA oe Usa. US: SINGAPORE, UT: TAIWAN UF CHINA Us UNIVERSAL EXCEPT ALL OF ABOVES eset DETAILS MAE EXALAINED NEAR THE MAK EXPLANATION GF OVERALL OF SCHEMA. MODEL _AX=S5aVSX/AX-SSaBBIC 8/8] 8) $] S1S|g8 ql arts are safety assurarce parts. (4 rer Selating hse Gores ke ture {o'use the specifica one- DT E T F T GBHAUDIO / VIDEO SIGNAL INPUT SECTIONRX-554RBK "se ma EE Gaede 221RX-554RBK SYSTEM CONTROL SECTION 2-22GEA SIO,IETUNER SECTION pee Alf fade thy|Mertens dlls Hime | Gz Lt “_ (Einabitta = AWRADIO MAIN SIGNAL PE AUAADIO SIGNAL RX-554RBK 223