SIC_CURS_02

interfete seriale
 I/O Synchronization
Scop: realizarea conexiunii dintre un uC si un dispozitiv extern

Marimi caracteristice transferului de date:

-LATENCY- (hardware delay+soft delay);
latency pt input device&output device

-REAL-TIME system garanteaza valoarea maxima a ‘LATENCY’.

-BANDWIDTH <bytes/second>

-PRIORITY
 Moduri de realizare a sincronizarii
(blind; busy-wait;interrupt; pooling; dma)
idle, busy & ready states
interface a flag

• The hardware will set the flag when the hardware component is complete
• The software can read the flag to determine if the device is busy or ready.
• The software can clear the flag, signifying the software component is complete
• This flag serves as the hardware triggering event for an interrupt.
I/O bound-unbuffered nterfacing
Utilizarea memoriilor de tip
FIFO
 Buffered interfacing
First-In/First-Out (FIFO) Queues
Fifo_Put Fifo_Get

Source process FIFO Sink process

Producer Consumer

Order preserving
Producer(s) put (on tail end)
Consumer(s) get (from head end)
Buffer decouples producer & consumer
 Even out temporary mismatch in rates
 FIFO Operation

• I/O bound input interface

Input busy done busy done
device
Interrupt
service b b
routine
Main a c d a c d a
program
Elements empty 1 empty 1 empty
in FIFO

a- stare de asteptare
b- FIFO_put
c- FIFO_get
d-prelucrarea datei
 FIFO Operation

• High bandwidth input burst (cpu bound)

Input busy done busy done busy done busy done busy done busy
device
Interrupt
service b b b b b
routine
Main a c d c d
program
Elements empty 1 empty 1 2 3 2 3
in FIFO

a- stare de asteptare
b- FIFO_put
c- FIFO_get
d-prelucrarea datei
 FIFO Queue Synchronization

Input ISR Output ISR

Input
Read data Empty
from input TxFifo
Empty Output Not empty
RxFifo Full
RxFifo TxFifo_Get
Not empty Not full Full Not full Disarm
TxFifo
RxFifo_Get RxFifo_Put Write data output
TxFifo_Put to output
return ERROR
Arm output
return
 Universal Asynchronous
Receiver/Transmitter (UART)
• UART (Serial Port) Interface
One frame

Serial port Start b b b b b b

3.3V
0 2 3 4 b b 7
Stop
1 5 6 0V
– Send/receive a frame of (5-8) data bits with a single
(start) bit prefix and a 1 or 2 (stop) bit suffix
– Baud rate is total number of bits per unit time
• Baudrate = 1 / bit-time
– Bandwidth is data per unit time
• Bandwidth = (data-bits / frame-bits) * baudrate
 RS-232 Serial Port
+3.3V
0.1F
16 0.1F DB9 female
1
0.1F MAX 2 Vss
TM4C123 3 +5.5V
3232 5
4 6 -5.5V
0.1F 0.1F 9
5 4

PA1/U0Tx RxD 9 8 Sin 8

0
PA0/U1Rx 3
PB1/U1Tx TxD 10 7 Sout 7
PB0/U1Rx 2
PD7/U2Tx
PD6/U2Rx 6
15
1
DB25 RS232 DB9 EIA-574 Signal Description True DTE DCE
Pin Name Pin Name
2 BA 3 103 TxD Transmit Data -5.5V out in
3 BB 2 104 RxD Receive Data -5.5V in out
7 AB 5 102 SG Signal Ground

data terminal equipment (DTE) = calculator

data communication equipment (DCE))= printer
 Serial I/O
• Serial communication
– Transmit Data (TxD), Receive Data (RxD), and
Signal Ground (SG) implement duplex
communication link
– Both communicating devices must operate at the
same bit rate
– Least significant bit sent first

Full duplex
Half duplex
Simplex
 UART - Transmitter

Stop 7 6 5 4 3 2 1 0 Start
Shift 1 Data 0 U0Tx
clock
Transmit shift register
16-element
FIFO TXEF Fifo empty flag

TXFF Fifo full flag

Write data UART0_DR_R
Transmit data register
 UART - Transmitter

• Tx Operation
– Data written to UART0_DR_R
• passes through 16-element FIFO
• permits small amount of data rate matching between
processor and UART
– Shift clock is generated from 16x clock
• permits differences in Tx and Rx clocks to be reconciled
One frame

Serial port Start b b b b b b

3.3V
0 2 3 4 5 b6
b 7 Stop
1 0V
 UART - Receiver

Stop 7 6 5 4 3 2 1 0 Start
Shift 1 Data 0 U0Rx
clock OE BE PE FE Receive shift register
RXFE Fifo empty flag
12-bit, 16-element
FIFO
RXFF Fifo full flag
Read data UART0_DR_R
Receive data register
 UART - Receiver

• Rx Operation
– RXFE is 0 when data are available
– RXFF is 1 when FIFO is full
– FIFO entries have four control bits
• BE set when Tx signal held low for more than one frame
(break)
• OE set when FIFO is full and new frame has arrived
• PE set if frame parity error
• FE set if stop bit timing error
One frame

Serial port Start b b b b b b

3.3V
0 2 3 4 5 b6
b 7 Stop
1 0V
 UART – Overrun Error

CDEFGHIJKLMNO
"A"=$41 "B"=$42 "P"=$50 "Q"=$51
s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s s 0 1 2 3 4 5 6 7 s

RXFE=0 RXFF=1 OE=1

17 frames transmitted and none read

=> overrun error
 Implementarea
bitului de paritate
UART-esantionarea semnalului
Codul manchester
unipolar
Codul manchester
bipolar
 Comunicatii seriale
sincrone_caracteristici
• Este transmisa data si clock-ul asociat
• Conversia serie paralel se face cu circuite simple
• In sistem exista un singur Master si unul sau mai multi sclavi
 Mod de selectie
mod de transmisie
 MICROWIRE

• Rata<1Mbit/s
• Bitstart-cod operatie-adr-data
 SPI (Serial Peripheral
Interface)
• Rata <3Mbiti/s
• Cuvintele sunt de 8biti
• Are semnal de ‘HOLD’
• Poate transmite ‘blocuri’ de date
 Network Communications

• Implica existenta unui bus de transmisie

• Pot exista mai multi ‘master-i’
• Dispozitivele care raspund cererii sunt ‘sclavi’
• Un dispozitiv poate fi si ‘master’ si ‘slave’.
• Un ‘master’ poate transmite informatii simultan
mai multor sclav.
• Viteza de transmisie e mica
 I2C (Inter-Intercomputer
communications)
• Viteze maxime 100kbps si 400kbps;
3.4Mbps.
• Modul de realizare al clock-ului
• Sincronizarea master master
• Sincronizarea master-slave
• Arbitrarea
• Este generata adresa sclavului
Conditia de START si STOP
 Transferul de date pe I2C

-Generarea unei stari de tip ‘wait’

 Modul de confirmare a
primirii datelor

-dupa fiecare Byte (daca nu e adresa)

 Sincronizarea ceasului
Fiecare MASTER are un timp pentru LOW si unul pentru HIGH
Temporizarile se realizeaza cu un numarator
Numaratorul se reset-eaza automat ce linia isi modifica starea din H in L
Daca linia nu se modifica din L in H, sistemul intra in stare de asteptare
Arbitrarea pe magistrala
EX_EEPROM
 I2C write
Ciclul de write este singurul ce fixeaza adresa
 I2C Read
Atresa este fixata de un ciclu de write
 CAN
(Controller Area Network)
generalitati
-viteza-1Mbps
-insensibila la interferente electromagnetice deoarece este DIFERENTIALA
-simpla –are pini putini
-dispozitivele pot fi conectate si deconectate in timpul functionarii
-NU genereaza adrese ci TIPUL de date ce este transmis
Dialog pe magistrala
Sunt 2 stari;
DOMINANT =Logic 0
RECESSIVE=Logic 1
Nivele de tensiune-codari
Realizarea fizica a BUS-ului
 Frames
(pachete de date-mesaje)

Data frame-date transmise

Remote frame-cerere pentru un anumit tip de date
Error frame-se trimite cand o unitate detecteaza o eroare pe
CAN bus
Overload frame-trimis pentru a intarzia alte pachete de date
Interframe space-separa pachetele de date sau de ‘remote’
 Data frame
• Start of frame-1bit=0
• Arbitration field (11-identifier, 1-Remote Transmision Request=0 pt date; =1 pt
remote
• Control field (datele pot fi 0-8)
• CRC field-Cyclic Redundancy Check (include toti bitii de la start la CRC delimiter-
1L)
• ACK- Master-trimite recessive si slave pune pe dominant
• End of frame=7 biti
Arbitrare, prioritate
Bit timming
Exemplu de realizare
pentru ‘bit timming’
Ajustarea ratei de
transfer
Implementarea fizica si
performante