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Colour Television Chassis

QV14.1E
LA

Contents Page
1. Revision List 2
2. Technical Specs, Diversity, and Connections 2
3. Precautions, Notes, and Abbreviation List 6
4. Mechanical Instructions 10
5. Service Modes, Error Codes, and Fault Finding 21
6. Alignments 34
7. Circuit Descriptions 37
8. IC Data Sheets 48
9. Block Diagrams 49
10. Circuit Diagrams and PWB Layouts Drawing PWB
715RLPCB0000000055 SSB 71 128 - 129
715RLPCB0000000303 SSB 130 186 - 187
715RLPCB0000000401 SSB 188 189 - 190
715RLPCB0000000252 BOLT-ON 191 210 - 211
715RLPCB0000000094 AmbiLight 212
715RLPCB0000000103 AmbiLight 214
715RLPCB0000000113 AmbiLight 216
715RLPCB0000000123 AmbiLight 218
715RLPCB0000000194 AmbiLight 220
715RLPCB0000000223 AmbiLight 223
715RLPCB0000000232 AmbiLight 226
715RLPCB0000000312 AmbiLight 229
715RLPCB0000000322 AmbiLight 232
715RLPCB0000000451 AmbiLight 234
715RLPCB0000000461 AmbiLight 236
11. Styling Sheets
79xx series 49" 238
79xx series 55" 239
81x9 and 82x9 series 48" - 55" 240
88x9 series 55" 241
89x9 curved series 55" 242
91xx series 55" - 65" 243
98xx series 65" 244

Published by PvH/EL 1443 Consumer Care Printed in the Netherlands Subject to modification EN 3122 785 19573
2014-Oct-22

©
2014 TP Vision Netherlands B.V.
All rights reserved. Specifications are subject to change without notice. Trademarks are the
property of Koninklijke Philips Electronics N.V. or their respective owners.
TP Vision Netherlands B.V. reserves the right to change products at any time without being obliged to adjust
earlier supplies accordingly.
PHILIPS and the PHILIPS’ Shield Emblem are used under license from Koninklijke Philips Electronics N.V.
EN 2 1. QV14.1E LA Revision List

1. Revision List
Manual xxxx xxx xxxx.0 Manual xxxx xxx xxxx.2
• First release. Added CTN’s of 79xx series:
• Chapter 2: Table 2-1 updated.
Manual xxxx xxx xxxx.1 • Chapter 4: added cable dressing.
Added CTN’s of 91xx and 98xx series: • Chapter 7: updated description.
• Chapter 2: Table 2-1 updated. • Chapter 9: added wiring diagrams.
• Chapter 4: added cable dressing. • Chapter 11: added styling sheets.
• Chapter 7: updated description.
• Chapter 9: added wiring diagrams. Manual xxxx xxx xxxx.3
• Chapter 10: added AmbiLight schematics. Added CTN’s 55” 8909 curved and 55” 9109 series:
• Chapter 11: added styling sheets. • Chapter 2: Table 2-1 updated.
• Chapter 4: added cable dressing.
• Chapter 6: added white tone values Table 6-5.
• Chapter 9: added wiring diagrams.
• Chapter 11: added styling sheets.

2. Technical Specs, Diversity, and Connections


Index of this chapter: Notes:
2.1 Technical Specifications • Figures can deviate due to the different set executions.
2.2 Directions for Use • Specifications are indicative (subject to change).
2.3 Connections
2.4 Chassis Overview

2.1 Technical Specifications


For on-line product support use the CTN links in Table 2-1. This
site provides product information, how to get started, user
manuals, frequently asked questions, software & drivers.

Table 2-1 Described Model Numbers and Diversity

2 4 7 9 10 11
Mechanics Descr. Block Diagrams Schematics Styling
(WiFi LAN USB, Light Sensor, IR/LED Module)
General Power Architecture

(Keyboard Control Module)


Connection Overview

Assembly Removal

(Sensor Module)
Control & Clock
Wiring Diagram
Cable Dressing

Power Supply

Power Supply
Supply lines

(AmbiLight)
Bolt-On

Styling
Audio
Video

SSB
I2C

CTN
48PFS8109/12 2.3 4-1 4.3 7.3 7.3 9.1 - - - - 7.3 - 10.1 - - - - 10.9 11.3
48PFS8109/60 4-2 9.2 9.22
48PFS8159/12 4-3
48PFS8159/60
48PFS8209/12
48PFS8209/60
49PUK7909/12 2.3 4-4 4.3 7.3 7.3 9.3 - - - - 7.3 - 10.3 - - - - 10.6 11.1
4-5 9.4 9.22
49PUS7909/12 2.3 4-4 4.3 7.3 7.3 9.3 - - - - 7.3 - 10.3 - - - - 10.6 11.1
49PUS7909/60 4-5 9.4 9.22
55PUS7909/12 2.3 4-6 4.3 7.3 7.3 9.5 - - - - 7.3 - 10.3 - - - - 10.6 11.2
55PUS7909/60 4-7 9.6 9.22
55PFS8109/12 2.3 4-8 4.3 7.3 7.3 9.7 - - - - 7.3 - 10.1 - - - - 10.10 11.3
55PFS8109/60 4-9 9.8 9.22 10.11
55PFS8159/12
55PFS8159/60
55PFS8209/12
55PFS8209/60

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Technical Specs, Diversity, and Connections QV14.1E LA 2. EN 3

2 4 7 9 10 11
Mechanics Descr. Block Diagrams Schematics Styling

(WiFi LAN USB, Light Sensor, IR/LED Module)


General Power Architecture

(Keyboard Control Module)


Connection Overview

Assembly Removal

(Sensor Module)
Control & Clock
Wiring Diagram
Cable Dressing

Power Supply

Power Supply
Supply lines

(AmbiLight)
Bolt-On

Styling
Audio
Video

SSB
I2C
CTN
55PUS8809/12 2.3 4-10 4.3 7.3 7.3 9.9 - - - - 7.3 - 10.2 10.4 - - - 10.5 11.4
55PUS8809/60 4-11 9.22 10.6
10.8
55PUS8909C/12 4-12 7.3 7.3 9.10 - - - - 7.3 - 10.2 10.4 - - - 10.8 11.5
4-13 9.11 9.22 10.14
10.15
55PUS9109/12 4-14 7.3 7.3 9.12 - - - - 7.3 - 10.2 10.4 - - - 10.6 11.6
55PUS9109/60 4-15 9.13 9.22 10.12
10.13
65PUS9109/12 2.3 4-16 7.3 7.3 9.12 - - - - 7.3 - 10.2 10.4 - - - 10.6 11.6
65PUS9109/60 4-17 9.13 9.22 10.12
10.13
65PUS9809/12 2.3 4-18 7.3 7.3 9.14 - - - - 7.3 - 10.2 10.4 - - - 10.5 11.7
65PUS9809/60 4-19 9.15 9.22 10.7

2.2 Directions for Use


You can download this information from the following websites:
http://www.philips.com/support
http://www.p4c.philips.com

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EN 4 2. QV14.1E LA Technical Specs, Diversity, and Connections

2.3 Connections

Side Connectors

COMMON INTERFACE 2
CI+ / CAM
Rear Connectors
1

15 16 17 18 19 20

SERVICE
AUDIO IN

COMMON INTERFACE 1
NETWORK
Pb L

CI+ / CAM
2
Pr R
SCART

USB
3

USB
Bottom Rear Connectors 4

AUDIO OUT ANTENNA SAT 1 SAT 2 USB HDMI HDMI


HDMI

OPTICAL 1 2 5
4
HDMI

6
3

14 13 12 11 10 9 8 7

19570_007_140513.eps
14-05-13

Figure 2-1 Connection overview

Note: The following connector colour abbreviations are used 3 - Data (+) jk
(acc. to DIN/IEC 757): Bk= Black, Bu= Blue, Gn= Green, Gy= 4 - Ground Gnd H
Grey, Rd= Red, Wh= White, Ye= Yellow.
5, 6, 7 and 8 - HDMI 4, HDMI 3, HDMI 2 and HDMI 1
2.3.1 Connections Digital Video - In, Digital Audio with ARC - In/Out
19 1
1 and 2 - Common Interface 1 and Common interface 2 18 2

68p - jk 10000_017_090121.eps
090428

3, 4 and 9- USB2.0
Figure 2-3 HDMI (type A) connector

1 2 3 4 1 - D2+ Data channel j


10000_022_090121.eps 2 - Shield Gnd H
090121
3 - D2- Data channel j
4 - D1+ Data channel j
Figure 2-2 USB (type A)
5 - Shield Gnd H
6 - D1- Data channel j
1 - +5V k 7 - D0+ Data channel j
2 - Data (-) jk 8 - Shield Gnd H

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Technical Specs, Diversity, and Connections QV14.1E LA 2. EN 5

9 - D0- Data channel j Rd - Video Pr 0.7 VPP / 75 ohm jq


10 - CLK+ Data channel j
11 - Shield Gnd H 17 - Service
12 - CLK- Data channel j 1 - Ground Gnd H
13 - Easylink/CEC Control channel jk 2 - UART_TX Transmit k
14 - ARC Audio Return Channel k 3 - UART_RX Receive j
15 - DDC_SCL DDC clock j
16 - DDC_SDA DDC data jk
18 - Audio - In: Left/Right (VGA/DVI)
17 - Ground Gnd H Bu - Audio L/R in 0.5 VRMS / 10 kohm jq
18 - +5V j
19 - HPD Hot Plug Detect j
19 - Cinch: Audio - In
20 - Ground Gnd H
Rd - Audio - R 0.5 VRMS / 10 kohm jq
Wh - Audio - L 0.5 VRMS / 10 kohm jq
10 and 11 - SAT 2 and SAT 1 - In
- - F-type Coax, 75 ohm D
20 - Video RGB - In, CVBS - In/Out, Audio - In/Out
20 2
12 - Antenna - In
- - IEC-type (EU) Coax, 75 ohm D
21 1
13 - Head phone (Output) 10000_001_090121.eps
090121
Bk - Head phone 32 - 600 ohm / 10 mW ot
Figure 2-5 SCART connector
14 - Audio - Out: S/PDIF - Out
- - Optical kq 1 - n.c.
2 - Audio R 0.5 VRMS / 10 kohm j
15 - RJ45: Ethernet 3 - n.c.
4 - Ground Audio Gnd H
5 - Ground Blue Gnd H
6 - Audio L 0.5 VRMS / 10 kohm j
7 - Video Blue 0.7 VPP / 75 ohm jk
8 - Function Select 0 - 2 V: INT
10000_025_090121.eps
120320 4.5 - 7 V: EXT 16:9
9.5 - 12 V: EXT 4:3 j
Figure 2-4 Ethernet connector 9 - Ground Green Gnd H
10 - n.c.
1 - TD+ Transmit signal k 11 - Video Green 0.7 VPP / 75 ohm j
2 - TD- Transmit signal k 12 - n.c.
3 - RD+ Receive signal j 13 - Ground Red Gnd H
4 - CT Centre Tap: DC level fixation 14 - Ground P50 Gnd H
5 - CT Centre Tap: DC level fixation 15 - Video Red 0.7 VPP / 75 ohm j
6 - RD- Receive signal j 16 - Status/FBL 0 - 0.4 V: INT
7 - GND Gnd H 1 - 3 V: EXT / 75 ohm j
8 - GND Gnd H 17 - Ground Video Gnd H
18 - Ground FBL Gnd H
19 - n.c.
16 - Cinch: Video YPbPr - In
20 - Video CVBS 1 VPP / 75 ohm j
Gn - Video Y 1 VPP / 75 ohm jq
21 - Shield Gnd H
Bu - Video Pb 0.7 VPP / 75 ohm jq

2.4 Chassis Overview


Refer to chapter 9. Block Diagrams for PWB/CBA locations.

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EN 6 3. QV14.1E LA Precautions, Notes, and Abbreviation List

3. Precautions, Notes, and Abbreviation List


Index of this chapter: • Where necessary, measure the waveforms and voltages
3.1 Safety Instructions with (D) and without (E) aerial signal. Measure the
3.2 Warnings voltages in the power supply section both in normal
3.3 Notes operation (G) and in stand-by (F). These values are
3.4 Abbreviation List indicated by means of the appropriate symbols.

3.3.2 Schematic Notes


3.1 Safety Instructions
• All resistor values are in ohms, and the value multiplier is
Safety regulations require the following during a repair:
often used to indicate the decimal point location (e.g. 2K2
• Connect the set to the Mains/AC Power via an isolation
indicates 2.2 k).
transformer (> 800 VA).
• Resistor values with no multiplier may be indicated with
• Replace safety components, indicated by the symbol h,
either an “E” or an “R” (e.g. 220E or 220R indicates 220 ).
only by components identical to the original ones. Any
• All capacitor values are given in micro-farads (  10-6),
other component substitution (other than original type) may
nano-farads (n  10-9), or pico-farads (p  10-12).
increase risk of fire or electrical shock hazard.
• Capacitor values may also use the value multiplier as the
decimal point indication (e.g. 2p2 indicates 2.2 pF).
Safety regulations require that after a repair, the set must be
• An “asterisk” (*) indicates component usage varies. Refer
returned in its original condition. Pay in particular attention to
to the diversity tables for the correct values.
the following points:
• The correct component values are listed on the Philips
• Route the wire trees correctly and fix them with the
Spare Parts Web Portal.
mounted cable clamps.
• Check the insulation of the Mains/AC Power lead for
external damage. 3.3.3 Spare Parts
• Check the strain relief of the Mains/AC Power cord for
proper function. For the latest spare part overview, consult your Philips Spare
• Check the electrical DC resistance between the Mains/AC Part web portal.
Power plug and the secondary side (only for sets that have
a Mains/AC Power isolated power supply): 3.3.4 BGA (Ball Grid Array) ICs
1. Unplug the Mains/AC Power cord and connect a wire
between the two pins of the Mains/AC Power plug. Introduction
2. Set the Mains/AC Power switch to the “on” position For more information on how to handle BGA devices, visit this
(keep the Mains/AC Power cord unplugged!). URL: http://www.atyourservice-magazine.com. Select
3. Measure the resistance value between the pins of the “Magazine”, then go to “Repair downloads”. Here you will find
Mains/AC Power plug and the metal shielding of the Information on how to deal with BGA-ICs.
tuner or the aerial connection on the set. The reading
should be between 4.5 M and 12 M.
BGA Temperature Profiles
4. Switch “off” the set, and remove the wire between the
For BGA-ICs, you must use the correct temperature-profile.
two pins of the Mains/AC Power plug.
Where applicable and available, this profile is added to the IC
• Check the cabinet for defects, to prevent touching of any
Data Sheet information section in this manual.
inner parts by the customer.

3.3.5 Lead-free Soldering


3.2 Warnings
Due to lead-free technology some rules have to be respected
• All ICs and many other semiconductors are susceptible to by the workshop during a repair:
electrostatic discharges (ESD w). Careless handling • Use only lead-free soldering tin. If lead-free solder paste is
during repair can reduce life drastically. Make sure that, required, please contact the manufacturer of your soldering
during repair, you are connected with the same potential as equipment. In general, use of solder paste within
the mass of the set by a wristband with resistance. Keep workshops should be avoided because paste is not easy to
components and tools also at this same potential. store and to handle.
• Be careful during measurements in the high voltage • Use only adequate solder tools applicable for lead-free
section. soldering tin. The solder tool must be able:
• Never replace modules or other components while the unit – To reach a solder-tip temperature of at least 400°C.
is switched “on”. – To stabilize the adjusted temperature at the solder-tip.
• When you align the set, use plastic rather than metal tools. – To exchange solder-tips for different applications.
This will prevent any short circuits and the danger of a • Adjust your solder tool so that a temperature of around
circuit becoming unstable. 360°C - 380°C is reached and stabilized at the solder joint.
Heating time of the solder-joint should not exceed ~ 4 sec.
Avoid temperatures above 400°C, otherwise wear-out of
3.3 Notes tips will increase drastically and flux-fluid will be destroyed.
To avoid wear-out of tips, switch “off” unused equipment or
3.3.1 General reduce heat.
• Mix of lead-free soldering tin/parts with leaded soldering
• Measure the voltages and waveforms with regard to the tin/parts is possible but PHILIPS recommends strongly to
chassis (= tuner) ground (H), or hot ground (I), depending avoid mixed regimes. If this cannot be avoided, carefully
on the tested area of circuitry. The voltages and waveforms clear the solder-joint from old tin and re-solder with new tin.
shown in the diagrams are indicative. Measure them in the
Service Default Mode with a colour bar signal and stereo 3.3.6 Alternative BOM identification
sound (L: 3 kHz, R: 1 kHz unless stated otherwise) and
picture carrier at 475.25 MHz for PAL, or 61.25 MHz for It should be noted that on the European Service website,
NTSC (channel 3). “Alternative BOM” is referred to as “Design variant”.

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Precautions, Notes, and Abbreviation List QV14.1E LA 3. EN 7

The third digit in the serial number (example: 3.4 Abbreviation List
AG2B0335000001) indicates the number of the alternative
B.O.M. (Bill Of Materials) that has been used for producing the 0/6/12 SCART switch control signal on A/V
specific TV set. In general, it is possible that the same TV
board. 0 = loop through (AUX to TV),
model on the market is produced with e.g. two different types
6 = play 16 : 9 format, 12 = play 4 : 3
of displays, coming from two different suppliers. This will then format
result in sets which have the same CTN (Commercial Type
AARA Automatic Aspect Ratio Adaptation:
Number; e.g. 28PW9515/12) but which have a different B.O.M.
algorithm that adapts aspect ratio to
number. remove horizontal black bars; keeps
By looking at the third digit of the serial number, one can
the original aspect ratio
identify which B.O.M. is used for the TV set he is working with.
ACI Automatic Channel Installation:
If the third digit of the serial number contains the number “1” algorithm that installs TV channels
(example: AG1B033500001), then the TV set has been
directly from a cable network by
manufactured according to B.O.M. number 1. If the third digit is
means of a predefined TXT page
a “2” (example: AG2B0335000001), then the set has been ADC Analogue to Digital Converter
produced according to B.O.M. no. 2. This is important for
AFC Automatic Frequency Control: control
ordering the correct spare parts!
signal used to tune to the correct
For the third digit, the numbers 1...9 and the characters A...Z frequency
can be used, so in total: 9 plus 26= 35 different B.O.M.s can be
AGC Automatic Gain Control: algorithm that
indicated by the third digit of the serial number.
controls the video input of the feature
box
Identification: The bottom line of a type plate gives a 14-digit
AM Amplitude Modulation
serial number. Digits 1 and 2 refer to the production centre (e.g.
AP Asia Pacific
SN is Lysomice, RJ is Kobierzyce), digit 3 refers to the B.O.M. AR Aspect Ratio: 4 by 3 or 16 by 9
code, digit 4 refers to the Service version change code, digits 5
ASF Auto Screen Fit: algorithm that adapts
and 6 refer to the production year, and digits 7 and 8 refer to
aspect ratio to remove horizontal black
production week (in example below it is 2010 week 10 / 2010 bars without discarding video
week 17). The 6 last digits contain the serial number.
information
ATSC Advanced Television Systems
Committee, the digital TV standard in
the USA
ATV See Auto TV
Auto TV A hardware and software control
system that measures picture content,
and adapts image parameters in a
dynamic way
AV External Audio Video
AVC Audio Video Controller
AVIP Audio Video Input Processor
B/G Monochrome TV system. Sound
carrier distance is 5.5 MHz
BDS Business Display Solutions (iTV)
BLR Board-Level Repair
BTSC Broadcast Television Standard
Committee. Multiplex FM stereo sound
system, originating from the USA and
used e.g. in LATAM and AP-NTSC
countries
B-TXT Blue TeleteXT
10000_053_110228.eps
110228
C Centre channel (audio)
CEC Consumer Electronics Control bus:
Figure 3-1 Serial number (example) remote control bus on HDMI
connections
3.3.7 Board Level Repair (BLR) or Component Level Repair CL Constant Level: audio output to
(CLR) connect with an external amplifier
CLR Component Level Repair
If a board is defective, consult your repair procedure to decide ComPair Computer aided rePair
if the board has to be exchanged or if it should be repaired on CP Connected Planet / Copy Protection
component level. CSM Customer Service Mode
If your repair procedure says the board should be exchanged CTI Color Transient Improvement:
completely, do not solder on the defective board. Otherwise, it manipulates steepness of chroma
cannot be returned to the O.E.M. supplier for back charging! transients
CVBS Composite Video Blanking and
3.3.8 Practical Service Precautions Synchronization
DAC Digital to Analogue Converter
• It makes sense to avoid exposure to electrical shock. DBE Dynamic Bass Enhancement: extra
While some sources are expected to have a possible low frequency amplification
dangerous impact, others of quite high potential are of DCM Data Communication Module. Also
limited current and are sometimes held in less regard. referred to as System Card or
• Always respect voltages. While some may not be Smartcard (for iTV).
dangerous in themselves, they can cause unexpected DDC See “E-DDC”
reactions that are best avoided. Before reaching into a D/K Monochrome TV system. Sound
powered TV set, it is best to test the high voltage insulation. carrier distance is 6.5 MHz
It is easy to do, and is a good service precaution. DFI Dynamic Frame Insertion

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EN 8 3. QV14.1E LA Precautions, Notes, and Abbreviation List

DFU Directions For Use: owner's manual SDI), is a digitized video format used
DMR Digital Media Reader: card reader for broadcast grade video.
DMSD Digital Multi Standard Decoding Uncompressed digital component or
DNM Digital Natural Motion digital composite signals can be used.
DNR Digital Noise Reduction: noise The SDI signal is self-synchronizing,
reduction feature of the set uses 8 bit or 10 bit data words, and has
DRAM Dynamic RAM a maximum data rate of 270 Mbit/s,
DRM Digital Rights Management with a minimum bandwidth of 135
DSP Digital Signal Processing MHz.
DST Dealer Service Tool: special remote iTV Institutional TeleVision; TV sets for
control designed for service hotels, hospitals etc.
technicians LS Last Status; The settings last chosen
DTCP Digital Transmission Content by the customer and read and stored
Protection; A protocol for protecting in RAM or in the NVM. They are called
digital audio/video content that is at start-up of the set to configure it
traversing a high speed serial bus, according to the customer's
such as IEEE-1394 preferences
DVB-C Digital Video Broadcast - Cable LATAM Latin America
DVB-T Digital Video Broadcast - Terrestrial LCD Liquid Crystal Display
DVD Digital Versatile Disc LED Light Emitting Diode
DVI(-d) Digital Visual Interface (d= digital only) L/L' Monochrome TV system. Sound
E-DDC Enhanced Display Data Channel carrier distance is 6.5 MHz. L' is Band
(VESA standard for communication I, L is all bands except for Band I
channel and display). Using E-DDC, LPL LG.Philips LCD (supplier)
the video source can read the EDID LS Loudspeaker
information form the display. LVDS Low Voltage Differential Signalling
EDID Extended Display Identification Data Mbps Mega bits per second
(VESA standard) M/N Monochrome TV system. Sound
EEPROM Electrically Erasable and carrier distance is 4.5 MHz
Programmable Read Only Memory MHEG Part of a set of international standards
EMI Electro Magnetic Interference related to the presentation of
EPG Electronic Program Guide multimedia information, standardised
EPLD Erasable Programmable Logic Device by the Multimedia and Hypermedia
EU Europe Experts Group. It is commonly used as
EXT EXTernal (source), entering the set by a language to describe interactive
SCART or by cinches (jacks) television services
FDS Full Dual Screen (same as FDW) MIPS Microprocessor without Interlocked
FDW Full Dual Window (same as FDS) Pipeline-Stages; A RISC-based
FLASH FLASH memory microprocessor
FM Field Memory or Frequency MOP Matrix Output Processor
Modulation MOSFET Metal Oxide Silicon Field Effect
FPGA Field-Programmable Gate Array Transistor, switching device
FTV Flat TeleVision MPEG Motion Pictures Experts Group
Gb/s Giga bits per second MPIF Multi Platform InterFace
G-TXT Green TeleteXT MUTE MUTE Line
H H_sync to the module MTV Mainstream TV: TV-mode with
HD High Definition Consumer TV features enabled (iTV)
HDD Hard Disk Drive NC Not Connected
HDCP High-bandwidth Digital Content NICAM Near Instantaneous Compounded
Protection: A “key” encoded into the Audio Multiplexing. This is a digital
HDMI/DVI signal that prevents video sound system, mainly used in Europe.
data piracy. If a source is HDCP coded NTC Negative Temperature Coefficient,
and connected via HDMI/DVI without non-linear resistor
the proper HDCP decoding, the NTSC National Television Standard
picture is put into a “snow vision” mode Committee. Color system mainly used
or changed to a low resolution. For in North America and Japan. Color
normal content distribution the source carrier NTSC M/N= 3.579545 MHz,
and the display device must be NTSC 4.43= 4.433619 MHz (this is a
enabled for HDCP “software key” VCR norm, it is not transmitted off-air)
decoding. NVM Non-Volatile Memory: IC containing
HDMI High Definition Multimedia Interface TV related data such as alignments
HP HeadPhone O/C Open Circuit
I Monochrome TV system. Sound OSD On Screen Display
carrier distance is 6.0 MHz OAD Over the Air Download. Method of
I2 C Inter IC bus software upgrade via RF transmission.
I2 D Inter IC Data bus Upgrade software is broadcasted in
I2 S Inter IC Sound bus TS with TV channels.
IF Intermediate Frequency OTC On screen display Teletext and
IR Infra Red Control; also called Artistic (SAA5800)
IRQ Interrupt Request P50 Project 50: communication protocol
ITU-656 The ITU Radio communication Sector between TV and peripherals
(ITU-R) is a standards body PAL Phase Alternating Line. Color system
subcommittee of the International mainly used in West Europe (colour
Telecommunication Union relating to carrier = 4.433619 MHz) and South
radio communication. ITU-656 (a.k.a. America (colour carrier

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Precautions, Notes, and Abbreviation List QV14.1E LA 3. EN 9

PAL M = 3.575612 MHz and SVGA 800 × 600 (4:3)


PAL N = 3.582056 MHz) SVHS Super Video Home System
PCB Printed Circuit Board (same as “PWB”) SW Software
PCM Pulse Code Modulation SWAN Spatial temporal Weighted Averaging
PDP Plasma Display Panel Noise reduction
PFC Power Factor Corrector (or SXGA 1280 × 1024
Pre-conditioner) TFT Thin Film Transistor
PIP Picture In Picture THD Total Harmonic Distortion
PLL Phase Locked Loop. Used for e.g. TMDS Transmission Minimized Differential
FST tuning systems. The customer Signalling
can give directly the desired frequency TS Transport Stream
POD Point Of Deployment: a removable TXT TeleteXT
CAM module, implementing the CA TXT-DW Dual Window with TeleteXT
system for a host (e.g. a TV-set) UI User Interface
POR Power On Reset, signal to reset the uP uP Microprocessor
PSDL Power Supply for Direct view LED UXGA 1600 × 1200 (4:3)
backlight with 2D-dimming V V-sync to the module
PSL Power Supply with integrated LED VESA Video Electronics Standards
drivers Association
PSLS Power Supply with integrated LED VGA 640 × 480 (4:3)
drivers with added Scanning VL Variable Level out: processed audio
functionality output toward external amplifier
PTC Positive Temperature Coefficient, VSB Vestigial Side Band; modulation
non-linear resistor method
PWB Printed Wiring Board (same as “PCB”) WYSIWYR What You See Is What You Record:
PWM Pulse Width Modulation record selection that follows main
QRC Quasi Resonant Converter picture and sound
QTNR Quality Temporal Noise Reduction WXGA 1280 × 768 (15:9)
QVCP Quality Video Composition Processor XTAL Quartz crystal
RAM Random Access Memory XGA 1024 × 768 (4:3)
RGB Red, Green, and Blue. The primary Y Luminance signal
color signals for TV. By mixing levels Y/C Luminance (Y) and Chrominance (C)
of R, G, and B, all colors (Y/C) are signal
reproduced. YPbPr Component video. Luminance and
RC Remote Control scaled color difference signals (B-Y
RC5 / RC6 Signal protocol from the remote and R-Y)
control receiver YUV Component video
RESET RESET signal
ROM Read Only Memory
RSDS Reduced Swing Differential Signalling
data interface
R-TXT Red TeleteXT
SAM Service Alignment Mode
S/C Short Circuit
SCART Syndicat des Constructeurs
d'Appareils Radiorécepteurs et
Téléviseurs
SCL Serial Clock I2C
SCL-F CLock Signal on Fast I2C bus
SD Standard Definition
SDA Serial Data I2C
SDA-F DAta Signal on Fast I2C bus
SDI Serial Digital Interface, see “ITU-656”
SDRAM Synchronous DRAM
SECAM SEequence Couleur Avec Mémoire.
Colour system mainly used in France
and East Europe. Colour
carriers = 4.406250 MHz and
4.250000 MHz
SIF Sound Intermediate Frequency
SMPS Switched Mode Power Supply
SoC System on Chip
SOG Sync On Green
SOPS Self Oscillating Power Supply
SPI Serial Peripheral Interface bus; a
4-wire synchronous serial data link
standard
S/PDIF Sony Philips Digital InterFace
SRAM Static RAM
SRP Service Reference Protocol
SSB Small Signal Board
SSC Spread Spectrum Clocking, used to
reduce the effects of EMI
STB Set Top Box
STBY STand-BY

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EN 10 4. QV14.1E LA Mechanical Instructions

4. Mechanical Instructions
Index of this chapter: Notes:
4.1 Cable Dressing • Figures below can deviate slightly from the actual situation,
4.2 Service Positions due to the different set executions.
4.3 Assy/Panel Removal • For cable position numbering, refer to the Wiring Diagrams
4.4 Set Re-assembly in chapter 9. Block Diagrams.

4.1 Cable Dressing

19570_008_140514.eps
14-07-25

Figure 4-1 Cable dressing 48" 8109/8159/8209 series

19570_009_140514.eps
14-07-10

Figure 4-2 Cable dressing back cover 48" 8109/8159/8209 series

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Mechanical Instructions QV14.1E LA 4. EN 11

19570_177_140728.eps
14-07-28

Figure 4-3 Cable dressing detail 48” and 55" 8109/8159/8209 series (55" shown)

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EN 12 4. QV14.1E LA Mechanical Instructions

19572_001_140907.eps
14-09-07

Figure 4-4 Cable dressing 49" 7909 series

19572_002_140907.eps
14-09-07

Figure 4-5 Cable dressing back cover 49" 7909 series

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Mechanical Instructions QV14.1E LA 4. EN 13

19572_003_140907.eps
14-09-07

Figure 4-6 Cable dressing 55" 7909 series

19572_004_140907.eps
14-09-07

Figure 4-7 Cable dressing back cover 55" 7909 series

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EN 14 4. QV14.1E LA Mechanical Instructions

19570_010_140514.eps
14-05-15

Figure 4-8 Cable dressing 55" 8109/8159/8209 series

19570_011_140514.eps
14-07-10

Figure 4-9 Cable dressing back cover 55" 8109/8159/8209 series

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Mechanical Instructions QV14.1E LA 4. EN 15

19570_012_140514.eps
14-07-10

Figure 4-10 Cable dressing 55" 8809 series

19570_013_140514.eps
14-07-11

Figure 4-11 Cable dressing back cover 55" 8809 series

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EN 16 4. QV14.1E LA Mechanical Instructions

19573_003_141015.eps
14-10-16

Figure 4-12 Cable dressing 55" 8909 curved series

19573_004_141015.eps
14-10-16

Figure 4-13 Cable dressing back cover 55" 8909 curved series

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Mechanical Instructions QV14.1E LA 4. EN 17

19573_001_141008.eps
14-10-08

Figure 4-14 Cable dressing 55" 9109 series

19573_002_141015.eps
14-10-16

Figure 4-15 Cable dressing back cover 55" 9109 series

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EN 18 4. QV14.1E LA Mechanical Instructions

19570_190_140804.eps
14-08-05

Figure 4-16 Cable dressing 65" 9109 series

19570_191-140804.eps
14-08-07

Figure 4-17 Cable dressing back cover 65" 9109 series

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Mechanical Instructions QV14.1E LA 4. EN 19

19570_192_140804.eps
14-08-07

Figure 4-18 Cable dressing 65" 9809 series

19570_193_140804.eps
14-08-07

Figure 4-19 Cable dressing back cover 65" 9809 series

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EN 20 4. QV14.1E LA Mechanical Instructions

4.2 Service Positions care that these always support the cabinet and never only the
display.
For easy servicing of a TV-set, the set should be put face down Caution: Failure to follow these guidelines can seriously
on a soft flat surface, foam buffers or other specific workshop damage the display!
tools. Ensure that ESD safe measures are taken.
Ensure that a stable situation is created to perform
measurements and alignments. When using foam bars take

4.3 Assy/Panel Removal

4.3.1 Rear Cover

Warning: Disconnect the mains power cord before removing 4.3.3 SSB
the rear cover.
Attention: For Ambilight sets, remove the leading edge cover. Refer to Figure 4-22 and Figure 4-23 for details.
Some SSBs have a dedicated LVDS connector, requiring
It is mandatory to remove the leading edge cover and pressing two catches as indicated in the figure, before
disconnect the cables prior to removal of the rear cover! removing the LVDS cable.
See Figure 4-20 and Figure 4-21 for details.
1. For sets equipped with Ambilight: remove the stand and
swivel block [1].
2. Remove the leading edge hatch that covers the Ambilight
connector [2].
3. Unplug the Ambilight connectors located underneath the
hatch [3].
4. Lift the rear cover from the TV. Make sure that wires and
flat foils are not damaged while lifting the rear cover from
the set.

19054_001_111010.eps
111010
1
3
Figure 4-22 SSB LVDS connector catches (optional) -1-

Upon re-connecting the LVDS cable, ensure the catches are


1
3 locked after having inserted the LVDS cable.
2 2

19370_080_130208.eps
130208
Click!

Figure 4-20 Rear cover removal Ambilight models -1-

LVDS flat foil

3 3
Click!

19370_081_130208.eps 19222_001_120626.eps
130208 120626

Figure 4-21 Rear cover removal Ambilight models -2- Figure 4-23 SSB LVDS connector catches (optional) -2-

4.3.2 Ambilight units in Rear Cover 4.4 Set Re-assembly


To re-assemble the whole set, execute all processes in reverse
order.
The Ambilight units are affixed in the rear cover and will
self-destruct upon removal.
Attention: Do not forget to remove the remains of any Notes:
adhesive that might be left on the inside of the rear cover! • While re-assembling, make sure that all cables are placed
and connected in their original position.
• Pay special attention not to damage the EMC foams in the
The new units come with double-sided adhesive tape. Ensure
set. Ensure that EMC foams are mounted correctly.
a correct mounting to avoid uneven light emission of the units.

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 21

5. Service Modes, Error Codes, and Fault Finding


Index of this chapter: Every time the TV-set is switched “on/off” 0,5 hours is
5.1 Test Points added to this number.
5.2 Service Modes • Errors (followed by maximum 10 errors). The most
5.3 Start-up recent error is displayed at the upper left, for an
5.4 Service Tools explanation of the errors refer to section “5.5 Error Codes”.
5.5 Error Codes • Reset Error Buffer. To reset the error buffer, press the
5.6 The Blinking LED Procedure “cursor right” button (or “OK”) and the “OK” button.
5.7 Protections • Alignments. This will activate the “ALIGNMENTS”
5.8 Fault Finding and Repair Tips sub-menu. Refer to Chapter 6. Alignments.
5.9 Software Upgrading • Options numbers. Provides extra features for Service.
For more info refer to chapter 6. Alignments.
5.1 Test Points Note that if the option code numbers are changed, these
As most signals are digital, it will be difficult to measure have to be confirmed with pressing the “OK” button before
waveforms with a standard oscilloscope. However, several key the options are stored, otherwise changes will be lost.
ICs are capable of generating test patterns, which can be • Initialise NVM. (Not applicable) The moment the
controlled via ComPair. In this way it is possible to determine processor recognizes a corrupted NVM, the “initialize
which part is defective. NVM”-line will be highlighted. Now, two actions are
possible (depending on the service instructions of that
moment):
5.2 Service Modes – Before initializing, save the content of the NVM for
The Service Modes are used for different purposes:
development analysis, This will give the service
• Service Alignment Mode (SAM) offers several features for
department an extra possibility for diagnosis (e.g.
the service technician.
• Customer Service Mode (CSM) is used for communication when Development asks it).
– Initialise the NVM.
between the call centre and the customer.

Note: When the NVM is corrupt or when it has been replaced,


Note: Sets within the new model range require a new remote
control (RC). Some buttons carry a new name or symbol. there is a change that no picture appears because the display
code is not correct.
This has an impact on the activation of the Service Modes.
So, before initializing the NVM via the SAM, enter the correct
For instance the “MENU” button is now called “HOME” or is
marked with a “house” icon. display option to have the necessary picture.
Apply the following method to adapt this option via the standard
remote control. Refer to Chapter 6. Alignments for details and
5.2.1 Service Alignment Mode (SAM)
correct option number values.
How to change the display option
Purpose 1. On the standard RC, key in code “062598” and press the
In this mode a technician can: “MENU” or "HOME" button.
• perform (software) alignments, 2. Replace the digits of string “XXX” by the decimal display
• change option settings, code present on the sticker in the set.
• easily identify the actual software version, Make sure to key in all three digits (include leading zero’s).
• view operation hours,
• display or clear the error code buffer.

How to Activate SAM


Using a standard RC transmitter: Display Option
Code
1. Key in code “062596” and press the “INFO” or “OK” button.
When the SAM is active, a service warning message will
appear on the screen.
39mm
2. Continue pressing the “OK” button on the RC.
PHILIPS 040
27mm

MODEL:
32PF9968/10
Contents of SAM PROD.SERIAL NO:
AG 1A0620 000001
• Hardware Info.
(CTN Sticker)
– A. Software version: Displays the version of the main
software. 10000_038_090121.eps
The structure is “AAABB_X.Y.W.Z”, with: 090819
• AAA: the chassis name.
• BB: the Product ID. Figure 5-1 Location of Display Option Code sticker
• X.Y.W.Z: the software version, where “X” is the
main version number (different numbers are not When the action above is successful, the front LED will go out,
compatible with each other) and “Y.W.Z” is the sub indicating that the RC sequence was correct.
version number (a higher number is always After the display option in the NVM is changed, the TV-set will
compatible with a lower number). go to standby mode.
Example: AND1E_1.2.3.4 When the NVM was corrupted or empty before this action, it will
– B. Standby processor version: Displays the software first be initialized (loaded with default values). The initialization
version of the standby processor. can take up to 20 seconds.
– C. Production Code: Displays the production code of • Store (go right). Press button “cursor right” or “OK” to
the TV-set. It is the serial number, which is printed on store all options and alignments.
the back of the set. • Software maintenance.
Note: If the NVM has been replaced or initialized after In case of specific problems, Development can ask for this
corruption, then re-write the production code to NVM. logging.
The update can be done via the NVM editor available – SW Events.
in SAM. – HW Events.
• (Shop) Operation hours. Displays the accumulated total - Event 26: is logged after the TV-set reboots due to a
of operation hours (not the standby hours). power dip.
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EN 22 5. QV14.1E LA Service Modes, Error Codes, and Fault Finding

• Test settings. For development purposes only. When CSM is activated and there is an USB stick connected to
• RF4CE pairing tables. Clear paired remote control. the TV-set, the software will dump the CSM content to the USB
For re-pairing (coldboot of platform possibly needed) press stick. A file “CSM_model number.txt” will be saved in folder
the red/blue hot keys simultaneously for a few seconds. “CSM” of the USB stick. This data can be handy if no
Make sure that the distance between the remote control information is displayed.
and the RF4CE receiver of the TV-set is less then 30cm.
A message like “Pairing successful”, confirms the In addition in CSM mode (with USB stick connected), pressing
match-make. “OK” will create an extended CSM dump file on the USB stick,
• Wi-Fi Direct settings. Reset Wi-Fi Direct group. located in folder “ECSM”. This file “Extended_CSM_model
• Development 1 file versions. Not useful for Service number_serial number.xml” contains:
purposes, this information is mainly used by Development. • The normal CSM dump information,
• Development 2 file versions. Not useful for Service • All items (from SAM “load to USB”, but in readable format),
purposes, this information is mainly used by Development. • Operating hours,
• Upload/Download to USB. To upload several settings • Error codes,
from the customer TV-set to an USB stick (connected to its • SW/HW event logs.
SSB).
Note: Upload is only possible when the software is running When CSM is activated, the LAYER 1 error is displayed via
and preferably when a picture is available. blinking LED. (see also section 5.5 Error Codes).
To upload the settings:
1. Press button “cursor right” or “OK” How to Activate CSM
A message “Done” should appear to indicate the Using a standard RC transmitter, key in code “123654”.
settings are successfully stored on the USB stick. Note: The CSM can only be activated when there is no (user)
2. If a message “Failure” appears (upload failed), then menu on the screen.
check if the USB stick is properly connected and if a
directory “repair” is present in the root. How to Navigate
• Download from USB. To download several or all settings Use the “CURSOR-DOWN/UP” knob on the RC-transmitter to
from an USB stick into a TV-set or on another SSB. navigate through the menus.
The procedure is the same as for “Upload to USB”. The
“All” item option allows downloading all items at once.
Contents of CSM
• NVM editor. Allows to correctly enter codes via the
The contents are reduced to 3 pages: General, Software
RC-transmitter. Correct data must be entered (this is
versions and Quality items. The names of these pages are not
present on the side or rear sticker):
shown in the CSM menu.
• “Type number” (Smart TV)
• “Production code” (factory location code),
• “18AC SSB”, General
• “18AC display”, • 1.1Set type. This information is very helpful for a
• “18AC supply”. helpdesk/workshop as reference for further diagnosis. In
this way, it is not necessary for the customer to look at the
rear of the TV-set. Note that if an NVM is replaced or is
How to Navigate
initialized after corruption, the set type content has to be
• In SAM, the menu items can be selected with the
re-written to NVM.The update can be done via the NVM
“CURSOR UP/DOWN” key on the RC-transmitter. The
editor available in SAM.
selected item will be highlighted. When not all menu items
• 1.2Production code. Displays the production code (the
fit on the screen, move the “CURSOR UP/DOWN” key to
serial number) of the TV. Note that if an NVM is replaced
display the next/previous menu items.
or is initialized after corruption, the production code content
• With the “CURSOR LEFT/RIGHT” keys, it is possible to:
has to be re-written to NVM. The update can be done via
– (De) activate the selected menu item.
the NVM editor available in SAM.
– (De) activate the selected sub menu.
• 1.3 Installed date. Indicates the date of the first installation
• With the “OK” key, it is possible to activate the selected
of the TV. This date is acquired by time extraction.
action.
• 1.4a Options 1. Displays the option codes numbers of
option group 1 as set in SAM (Service Alignment Mode).
How to Exit SAM • 1.4b Options 2. Displays the option codes numbers of
Use one of the following methods: option group 2 as set in SAM (Service Alignment Mode).
• Switch the TV-set to STANDBY via the RC-transmitter. • 1.5 18ACSSB. Gives an identification of the SSB as stored
• Via a standard RC-transmitter, key in “00” sequence, or in NVM. Note that if an NVM is replaced or is initialized after
select the “BACK” key. corruption, this identification number has to be re-written to
NVM. The update can be done via the NVM editor available
5.2.2 Customer Service Mode (CSM) in SAM. This identification number is the 18ac number of
the SSB.
Purpose • 18AC display. Shows the 18AC of the display. Note that if
The Customer Service Mode shows error codes and an NVM is replaced or is initialized after corruption, this
information on the TV operation settings. identification number has to be re-written to NVM. The
The call centre can instruct the customer (by telephone) to update can be done via the NVM editor available in SAM.
enter CSM in order to identify the status of the set. This helps • 18AC supply. Shows the 18AC of the power supply. Note
the call centre to diagnose problems and failures in the TV-set that if an NVM is replaced or is initialized after corruption,
before making a service call. this identification number has to be re-written to NVM. The
Note: The CSM is a read-only mode, so modifications are not update can be done via the NVM editor available in SAM.
possible in this mode. • 18AC sensor board.
• 18AC QFHD board.
Provided CSM is activated, every menu from CSM can be used
as a check for the back end chain video.So for all CSM content Software versions
displayed, it could be determined that the back end video chain • 2.1 Current main software. Displays the build-in main
is working. software version. In case of field problems related to
software, upgrade can be done. As this software is

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 23

consumer upgradeable, it will also be published on the


Internet.
Example: AND1E-1.2.3.4
• 2.2 Standby software. Displays the build-in standby
processor software version. Upgrading this software,
embedded with the main software update.5.9 Software
Upgrading).
Example: STDBY_14.01.02.00
• 2.3 e-UM version. Displays the electronic user manual
SW-version. Most significant number here is the data string
part.
• 2.4 Strings database version. Reflects the latest
embedded string database version.
• 2.5 PQ back-end version.Displays the Scan/backlight
microProcessor software version.Device processes the
backlight + boost pwm control, scanning, 3D drive.
• 2.6 NT 72314 software.Software version Novatek 72314
(Frame Rate Convertor) device.
• 2.9 RF4CE software.Software version for the RF4CE
board.
• 2.10 Channel package version.
• 2.11 UHD FPGA software.
• 2.12 HDCP 2.2 Rogue software.
• 2.13 EDID Rogue version.

Quality items
• 3.1 Signal quality. Bad / average /good (not for DVB-S).
• 3.4 Ethernet MAC address. Displays the MAC address
present in the SSB.
• 3.5 Wireless MAC address. Displays the wireless MAC
address to support the Wi-Fi functionality.
• 3.6 Netflix key. Netflix electronic serial number.
• 3.7 CI module. Displays status if the common interface
module is detected.
• 3.8 CI + protected service. Yes/No.
• 3.9 Event counter :
S : 000X 0000(number of software recoveries : SW
EVENT-LOG #(reboots)
S : 0000 000X (number of software events : SW
EVENT-LOG #(events)
H : 000X 0000(number of hardware errors)
H : 0000 000X (number of hardware events : SW
EVENT-LOG #(events).

How to Exit CSM


On the RC-transmitter press button “MENU” (or "HOME") and
button “Back”.

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EN 24 5. QV14.1E LA Service Modes, Error Codes, and Fault Finding

5.3 Start-up
The flowcharts on the following pages show the process from
start-up. For each phase they show which supplies are active.

5.3.1 Transition Overview

Off
Mains Mains
off on

- WakeUp requested WakeUp


- Acquisition needed requested

St by Semi
- stby requested and Active
no data Acquisition St by St by
required requested

GoToProtection
(triggered during startup
by standby µP) WakeUp
requested
(SDM)
GoToProtection
GoToProtection

Protection
On

19210_076_120504.eps
120504

Figure 5-2 Transition diagram

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 25

5.3.2 “Off” to “Semi Standby” (part 1)

Off
AC~ Mains is applied Stand by or
Protection
Standby Supply starts running.
All standby supply voltages become available.

st-by µP resets, resulting in a high impedant output


stage of the I/O ports.

Initialise I/O pins of the st-by µP


- Keep AVC system in reset (internal signal)
- Switch RESET-FUSION-OUTn LOW If the protection state was left by short circuiting the
- Switch RESET-HDMI-MUXn LOW SDM pins, detection of a protection condition during
- Switch RESET-ETHERNETn LOW startup shall stall the startup. Protection conditions
- Switch AUDIO-MUTEn LOW occuring in a playing set shall be ignored. The
- Switch SPLASH-ON LOW protection mode shall not be entered.
- Switch LCD-PWR-ONn High

Switch ENABLE-WOLAN high to power Ethernet PHY


and Wifi dongle Switch ENABLE-WOLANn high to power Ethernet
PHY and internal Wifi dongle if Networked Standby
was Off in the Standby mode.
start keyboard scanning, RC detection.
Wake up reasons are off.

Switch ON Platform supply by switching High the


STANDBYn line.

Startup shall continue from the


moment a valid detection is received.
12V platform is turned on, automatically enabling the
low voltage DCDC converter outputs

12V error:
Detect2 high received
No Layer1: 3
within 2 seconds?
Layer2: 16

Yes
Enter protection
Wait 300ms

Enable the supply detection algorithm


All display related I/O lines should be
LOW as long as the Tcon is not
powered to avoid leakage current and
tcon startup problems.
Start AVC system These lines will furtheron be
dynamically controlled by the mainSW.
No

Switch following lines asap:(part of preBOOT)

(GPIO2): LOW
CTRL-DISP2 (GPIO3): LOW
CTRL-DISP3 (GPIO8): LOW
CTRL-DISP4 (BKLGON): LOW
3D-LR (PWM0): LOW
BL-SPI-CS_BL-I-CTRL (PWM1): LOW
BL-DIM (BOOST): LOW Small delay between AVC boot and
other platform ICs is preferred to limit
rush-in current on Platform.

Wait 10ms

Switch RESET-FUSION-OUTn, RESET-


HDMI-MUXn , RESET-ETHERNETn High

19210_080_120504.eps
120504

Figure 5-3 “Off” to “Semi Standby” flowchart (part 1)

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EN 26 5. QV14.1E LA Service Modes, Error Codes, and Fault Finding

5.3.3 “Off” to “Semi Standby” (part 2)

Wake up reason
No
coldboot to Active mode?

No yes

AUDIO-MUTEn is switched by MIPS code No Startup screen cfg file


later on in the startup process when audio present?
needs to be released

Standby µP monitors MIPS boots yes


boot process and will
init a restart if Boot
process hampers
Reset-lines are switched MIPS sends out startup screen
Boot is failing

TV application starts MIPS starts up the display.

Set was
started with
SDM pin?
Startup screen visible

Wait 4 seconds before restarting

No

Yes

No Switch AVC in reset

Switch RESET-FUSION-OUTn, RESET-


HDMI-MUXn , RESET-ETHERNETn Low
Semi-Standby
3-th try?Switch Standby I/O line LOW

Yes
Ignore boot failure:
Stall the startup process.
Blink error code
Blink Layer2 error 53.
Layer 1 error 2
Enter protection without
turning off the supplies

Enter protection

19210_081_120504.eps
120504

Figure 5-4 “Off” to “Semi Standby” flowchart (part 2)

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 27

5.3.4 “Semi Standby” to “Active”

Semi Standby
The assumption here is that a fast toggle (<2s) can
Wait until previous on-state is left more than 2
only happen during ON->SEMI ->ON. In these states,
seconds ago. (to prevent LCD display problems)
the AVC is still active and can provide the 2s delay. A
transition ON->SEMI->STB Y->SEMI->ON cannot be
made in less than 2s, because the standby state will
be maintained for at least 4s. Assert RGB video blanking
and audio mute

Display already on?


(cold boot with splash
screen) Yes
Initialize audio and video
No processing IC's and functions
according needed use case.

Startup display
(see separate tab)

Start POWER-OK line


detection algorithm as defined Wait until valid and stable audio and video, corresponding to the
in the CHS service. requested output is delivered
AND
the backlight has been switched on for at least the time which is
indicated in the display file as preheat time

return
Release audio mute

unblank the video

Set the Ambilight functionality according the last status


settings

Display cfg file present


and up to date, according
correct display option?

No
Yes
Prepare Start screen Display config
file and copy to Flash

Active
19210_079_120504.eps
120504

Figure 5-5 “Semi Standby” to “Active” flowchart

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EN 28 5. QV14.1E LA Service Modes, Error Codes, and Fault Finding

5.3.5 “Active” to “Semi Standby”

Active

Mute all sound outputs according


information in the FMS AUDIO

Wait 100ms

Switch off POK line detection


algorithm (see CHS service)

Switch Off LCD backlight

Mute all video outputs switch off Ambilight (see CHS ambilight)

Shut down the display Wait until Ambilight has faded out:
(see separate sheet) Output power Observer should be zero

Semi Standby
19210_077_120504.eps
120504

Figure 5-6 “Active” to “Semi Standby” flowchart

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 29

5.3.6 “Semi Standby” to “Standby”

Semi Stand by

If ambientlight functionality was used in semi-standby


(lampadaire mode), switch off ambient light (see CHS
ambilight)

Delay transition until ramping down of ambient light is *) If this is not performed and the set is
finished. *) switched to standby when the switch off of
the ambilights is still ongoing, the lights will
switch off abruptly when the supply is cut.

transfer Wake up reasons to the Stand by µP.

transfer specific Firmware and Wake up reasons to the


Wifi dongle to allow networked standby

Switch AVC system in reset state


Switch reset-USB, Reset-Ethernet and Reset-DVBs
LOW

Switch RESET-FUSION-OUTn, RESET-HDMI-MUXn ,


RESET-ETHERNETn Low

Wait 10ms

Disable all supply related protections and switch off


the DC/DC converters (ENABLE-3V3n)

Switch OFF all supplies by switching HIGH the


Standby I/O line

Important remarks:
Networked Standby No
release reset audio 10 sec after entering required?
standby to save power

Also here, the standby state has to be Switch ENABLE-WOLAN Low to


maintained for at least 4s before starting power off the Ethernet PHY and
another state transition. Internal Wifi dongle.
Yes

Stand by

19210_078_120504.eps
120504

Figure 5-7 “Semi Standby” to “Standby” flowchart

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EN 30 5. QV14.1E LA Service Modes, Error Codes, and Fault Finding

5.4 Service Tools 5.5.2 How to Read the Error Buffer

5.4.1 ComPair Use one of the following methods:


• On screen via the SAM (only when a picture is visible).
The ComPair Tool is no longer supported here.Still, the E.g.:
interface box can be used as level shifter between the TV – 00 00 00 00 00: No errors detected
chassis and PC. – 23 00 00 00 00: Error code 23 is the last and only
detected error.
– 37 23 00 00 00: Error code 23 was first detected and
5.5 Error Codes error code 37 is the last detected error.
– Note that no protection errors can be logged in the
5.5.1 Introduction
error buffer.
• Via the blinking LED procedure. See section 5.5.3 How to
The latest logged errors, stored in the NVM, are shown in the Clear the Error Buffer.
Service Alignment Menu. This is called the error buffer.The
error code buffer contains all detected errors since the last time
5.5.3 How to Clear the Error Buffer
the buffer was erased. The buffer is written from left to right,
new errors are logged at the left side, and all other errors shift
one position to the right. Use one of the following methods:
• By activation of the “RESET ERROR BUFFER” command
When an error occurs, it is added to the list of errors, provided
in the SAM menu.
the list is not full. When an error occurs and the error buffer is
full, the new error is not added, and the error buffer stays intact • If the content of the error buffer has not changed for 50+
hours, it resets automatically.
(history is maintained).
To prevent that an occasional error stays in the list forever, the
error is removed from the list after more than 50 hrs. of 5.5.4 Error Buffer
operation.
When multiple errors occur (errors occurred within a short time In case of non-intermittent faults, clear the error buffer before
span), there is a high probability that there is some relation starting to repair (before clearing the buffer, write down the
between them. content, as this history can give significant information). This to
ensure that old error codes are no longer present.
• If no errors are there, the LED should not blink at all in CSM If possible, check the entire contents of the error buffer. In
or SAM. No spacer must be displayed as well. some situations, an error code is only the result of another error
• There is a simple blinking LED procedure for board level code and not the actual cause.(e.g. a fault in the protection
repair (home repair) so called LAYER 1 errors next to the detection circuitry can also lead to a protection)
existing errors which are LAYER 2 errors (see Table 5-1). There are several mechanisms of error detection:
– LAYER 1 errors are one digit errors, displayed in CSM. • Via error bits in the status registers of ICs.
– LAYER 2 errors are 2 digit errors, displayed in SAM.. • Via polling on I/O pins going to the standby processor.
• In protection mode. • Via sensing of analog values on the standby processor or
– From consumer mode: LAYER 1. the SOC.
• Fatal errors, if I2C bus is blocked and the set reboots, CSM • Via a “not acknowledge” of an I2C communication.
and SAM are not selectable.
– From consumer mode: LAYER 1. Take notice that some errors need several minutes before they
• In CSM mode. start blinking or before they will be logged. So in case of
– When entering CSM: error(s) LAYER 1 will be problems wait 2 minutes from start-up onwards, and then
displayed via blinking LED.(attention: any new remote check if the front LED is blinking or if an error is logged.
control press will disable the error blinking LED
sequence, recovery by exit and invoke CSM again for
re-enabling the error blinking).
• In SAM mode.
– When SAM is entered via Remote Control, LAYER 2 is
displayed via blinking LED.
• Error display on screen.
– In CSM no error codes are displayed on screen.
– In SAM the complete error list is shown.

Basically there are three kinds of errors:


• Errors detected by the Standby software which lead to
protection. These errors will always lead to protection and
an automatic start of the blinking LED LAYER 1 error.
(see section “5.6 The Blinking LED Procedure”).
• Errors detected by the Standby software which not
lead to protection. In this case the front LED should blink
the involved error. See also section “5.5 Error Codes, 5.5.4
Error Buffer”. Note that it can take up several minutes
before the TV-set starts blinking the error (e.g. LAYER 1
error = 2, LAYER 2 error = 18 or 53).
• Errors detected by main software (SOC). In this case the
error will be logged into the error buffer and can be read out
via blinking LED procedure : LAYER 1-2 error, or in case
picture is visible, via SAM.

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 31

Table 5-1 Error code overview

Monitored Error/ Error Buffer/


Description Layer 1 Layer 2 by Prot Blinking LED Device Defective Board
FE-bus 2 11 SOC E BL / EB SSB SSB
Cypress bus 2 12 SOC E BL / EB SSB SSB
BE bus 2 13 SOC E BL / EB SSB SSB
HDMI bus 2 14 SOC E BL / EB SSB SSB
Soc doesn’t boot (HW cause) 2 18 Stby µP P BL SSB SSB
12V 3 16 Stby µP P BL / Supply
Display supply (POK) 3 17 SOC E EB / Supply
Vcore 3V3 2 21 SOC E EB 88PG867 SSB
Vcpu 1V8 2 22 SOC E EB 88PG867 SSB
HDMI mux 2 23 SOC E EB SiI9287 SSB
I2C switch 2 24 SOC E EB PCA9546 SSB
I2C switch PMIC 2 25 SOC E EB PCA9543 SSB
Cypress 2 26 SOC E EB 88DE6010 SSB
Channel decoder 1 2 27 SOC E EB SSB
Channel decoder 2 2 28 SOC E EB SSB
Rogue (HDMI2.2) 2 29 SOC E EB siI9679 SSB
Lnb Single/Dual 2 31 SOC E EB LNBH25/26 SSB
Hybrid Tuner 2 34 SOC E EB SUT-PE531 SSB
Analog demodulator 2 35 SOC E EB TDA 8296 SSB
Class-D 2 37 SOC E EB TAS 5760 SSB
FPGA PQ 2 38 SOC E EB / SSB
FPGA UHDr 2 39 SOC E EB / SSB
T° sensor SSB/set 2 42 SOC E EB LM75 T° sensor/SSB
Light sensor 6 43 SOC E EB TSL2571 Set
RF4CE 6 46 SOC E EB CC2533 Set
SOC doesn’t boot (SW cause) 2 53 Stby µP P BL Marvell SSB
NT72314 9 61 SOC E EB NT72314 Back-end
I2C switch back-end 9 63 SOC E EB PCA9543 Back-end
Splash error 9 65 SOC E EB NT314, SOC SSB

Extra Info 5. When all the error codes are displayed, the sequence
• Rebooting. When a TV-set is constantly rebooting due to finishes with a LED blink of 3 seconds (spacer).
internal problems, most of the time no errors will be logged 6. The sequence starts again.
or blinked. This rebooting can be recognized via
Hyperterminal (for Hyperterminal settings, see section “5.8 Example: Error 12 8 6 0 0.
Fault Finding and Repair Tips, 5.8.5 Logging). It’s shown After activation of the SAM, the front LED will show:
that the loggings which are generated by the main software 1. One long blink of 750 ms (which is an indication of the
keep continuing. decimal digit) followed by a pause of 1.5 s
2. Two short blinks of 250 ms followed by a pause of 3 s
5.6 The Blinking LED Procedure 3. Eight short blinks followed by a pause of 3 s
4. Six short blinks followed by a pause of 3 s
5.6.1 Introduction 5. One long blink of 3 s to finish the sequence (spacer).
6. The sequence starts again.
The blinking LED procedure can be split up into two situations:
• Blinking LED procedure LAYER 1 error. In this case the 5.6.2 How to Activate
error is automatically blinked when the TV-set is put in
CSM. This will be only one digit error, namely the one that Use one of the following methods:
is referring to the defective board (see table “5-1 Error code • Activate the CSM. The blinking front LED will show the
overview”) which causes the failure of the TV. This layer 1 error(s), this works in “normal operation” mode or
approach will especially be used for home repair and call automatically when the error/protection is monitored by the
centres. The aim here is to have service diagnosis from a standby processor.
distance. In case no picture is shown and there is no LED blinking,
• Blinking LED procedure LAYER 2 error. Via this read the logging to detect whether “error devices” are
procedure, the contents of the error buffer can be made mentioned. (see section “5.8 Fault Finding and Repair
visible via the front LED. In this case the error contains Tips, 5.8.5 Logging”).
2 digits (see table “5-1 Error code overview”) and will be • Activate the SAM. The blinking front LED will show the
displayed when SAM is activated.This is especially useful entire content of the LAYER 2 error buffer, this works in
for fault finding and gives more details regarding the root “normal operation” mode.
cause of the defective board.
Important remark: 5.7 Protections
For an empty error buffer, the LED should not blink at all in
CSM or SAM. No spacer will be displayed. 5.7.1 Software Protections

When one of the blinking LED procedures is activated, the front Most of the protections and errors use either the standby
LED will show (blink) the contents of the error buffer. Error microprocessor or the SOC controller as detection device.
codes greater then 10 are shown as follows: Since in these cases, checking of observers, polling of ADCs,
1. “n” long blinks (where “n” = 1 to 9) indicating decimal digit and filtering of input values are all heavily software based,
2. A pause of 1.5 s these protections are referred to as software protections.
3. “n” short blinks (where “n”= 1 to 9) There are several types of software related protections, solving
4. A pause of approximately 3 s, a variety of fault conditions:
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EN 32 5. QV14.1E LA Service Modes, Error Codes, and Fault Finding

• Related to supplies: presence of the +5V,+2V5, +1V5, - Select the correct database (open file “QFUX.X”, this will set
+1V2 and +1V0 needs to be measured, no protection the ComPair interface in the appropriate mode).
triggered here. - Close ComPair
• Protections related to breakdown of the safety check After start-up of the Hyperterminal, fill in a name (f.i. “logging”)
mechanism. E.g. since the protection detections are done in the “Connection Description” box, then apply the following
by means of software, failing of the software will have to settings:
initiate a protection mode since safety cannot be 1. COMx
guaranteed any more. 2. Bits per second = 115200
3. Data bits = 8
Remark on the Supply Errors 4. Parity = none
The detection of a supply dip or supply loss during the normal 5. Stop bits = 1
playing of the set does not lead to a protection, but to a cold 6. Flow control = none
reboot of the set. If the supply is still missing after the reboot, During the start-up of the TV-set, the logging will be displayed.
the TV-set will go to protection. This is also the case during rebooting of the TV-set (the same
logging appears over and over). Tip: when there is no picture
Protections during Start-up available during rebooting you are able to check for “error
During TV start-up, some voltages and IC observers are devices” in the logging (LAYER 2 error) which can be very
actively monitored to be able to optimize the start-up speed, helpful to determine the failure cause of the reboot. For
and to assure good operation of all components. If these protection state, there is no logging.
monitors do not respond in a defined way, this indicates a
malfunction of the system and leads to a protection. As the 5.8.6 Guidelines Uart logging
observers are only used during start-up, they are described in
the start-up flow in detail (see section “5.3 Start-up”). Description possible cases:

5.8 Fault Finding and Repair Tips Uart loggings are displayed:
Read also section “5.5 Error Codes, 5.5.4 Error Buffer, Extra • When Uart loggings are coming out, the first conclusion we
Info”. can make is that the TV-set is starting up and
communication with the flash RAM seems to be supported.
5.8.1 Ambilight The Marvell processor is able to read and write in the
DRAMs.
• We can not yet conclude: Flash RAM and DRAMs are fully
Due to the aging process of the LED’s fitted on the Ambilight
operational/reliable.There still can be errors in the data
module, there can be a difference in the colour and/or light
transfers, DRAM errors, read/write speed and timing
output of the spare ambilight modules in comparison with the
control.
originals ones contained in the TV-set. Via SAM=> ambilight,
Uart loggings reporting fault conditions, error messages, error
the spare module can be fine-tuned.(Brightness)
codes, fatal errors:
• Some failures are indicated by error codes in the logging,
5.8.2 CSM check with error codes table (see Table “5-1 Error code
overview”). e.g. => <<<ERROR>>>PLFPOW_MERR.C :
When CSM is activated and there is a USB stick connected to First Error (id=10,Layer_1=2,Layer_2=23).
the TV, the software will dump the complete CSM content to the • I2C bus errors.
USB stick. The file (Csm.xml) will be saved under folder “CSM” • Not all failures or error messages should be interpreted as
of the USB stick. If this mechanism works it can be concluded fault. For instance root cause can be due to wrong option
that a large part of the operating system is already working codes settings.
(SOC, USB...)
5.8.7 Loudspeakers
5.8.3 Power Supply Unit
Make sure that the volume is set to minimum during
For fault finding tips, refer to section 7.3.1. disconnecting the speakers in the ON-state of the TV. The
audio amplifier can be damaged by disconnecting the speakers
5.8.4 Exit “Factory Mode” during ON-state of the set!

This mode can be recognized as state of no respons on any 5.8.8 Power Supply
random remote control request, this mode manifest by flashing
LED, visualized in front of the TV. In case of no picture, during CSM (test pattern) is invoked and
To exit this mode, push the “VOLUME minus” button on the no backlight supported, it’s recommended first to check the
TV’s local keyboard for 10 seconds (this disables the LED drivers on the power supply.
continuous mode). Attention point for cable handling: (dis)connection for power
Then push the “SOURCE” button for 10 seconds until to exit the cable (power supply <=> SSB) should always be executed
“Factory mode”. without any bending or mechanical stress on the outisdes of
the connector.Risk of double pins inside the connector should
5.8.5 Logging be avoid in this way.

When something is wrong with the TV-set (f.i. the set is 5.8.9 Display option code
rebooting) you can check for more information via the logging
in Hyperterminal. The Hyperterminal is available in every Attention: In case the SSB is replaced, always check the
Windows application via Programs, Accessories, display option code number (group 2, first option number e.g.
Communications, Hyperterminal. Connect a “ComPair “44855”) in SAM, even when picture is available. Performance
UART”-cable (3138 188 75051) from the service connector in with the incorrect display option code can lead to unwanted
the TV-set to the “multi function” jack at the front of ComPair II side-effects for certain conditions.
box.
Required settings in ComPair before starting to log:
- Start up the ComPair application.

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Service Modes, Error Codes, and Fault Finding QV14.1E LA 5. EN 33

Also supported in this chassis: • ProcessNVM_AND1E_x.x.x.x.zip. Default NVM content.


The display option code can be changed by “062598 HOME Must be programmed via USB, be aware that all
XXX” special SAM command (XXX=display option in 3 digits). alignments stored in NVM are overwritten here.

5.9 Software Upgrading 5.9.4 UART logging 2K13 (see section “5.8 Fault Finding and
Repair Tips, 5.8.5 Logging).
Always check for the latest software version in relation to
the correct CTN. Refer to the service website.

5.9.1 Introduction

The set software and security keys are stored in an EMMC


Flash, which is connected to the Marvell processor.

The user can upgrade the main software via the USB port.
This allows replacement of a software image in a stand alone
set, without the need of an E-JTAG debugger.
For a description on how to upgrade the main software refer to
the electronic User Manual (eUM).

Important: When the EMMC IC device is to be replaced, a new


SSB must be ordered, due to the presence of the security keys!
(CI +, MAC address, ...).
Perform the following actions after SSB replacement:
1. Set the correct option numbers (see rear cover sticker).
2. Update the TV software => refer to the instructions in the
electronic User Manual (eUM).
3. Perform the alignments as described in chapter 6 (section
6.5 Reset of Repaired SSB).
4. Check in CSM if Set type and MAC address are valid.
When ordering a new SSB, always refer to the Spare Parts list
to use the correct order number!

5.9.2 Main Software Upgrade

Automatic Software Upgrade


In “normal” conditions, so when there is no major problem with
the TV, the main software and the default software upgrade
application can be upgraded with the “AUTORUN.UPG” from
the “Philips” P4C/S website. This can also be done by the
consumers themselves, but they will have to get their software
from the commercial Philips website or via the Software Update
Assistant in the user menu (see eUM). The “autorun.upg” file
must be placed in the root of the USB stick.
How to upgrade:
1. Copy “AUTORUN.UPG” to the root of the USB stick.
2. Make sure the set is operational and insert the USB stick.
The set will restart, then the upgrading will start
automatically.
3. As soon as the programming is finished, a message is
shown to remove the USB stick and to restart the set.

5.9.3 Content and Usage of the One-Zip Software File

Below the content of the One-Zip file is explained, and


instructions on how and when to use it.
• FullUpgrade_AND1E_x.x.x.x.zip. Contains the “upg” file
which is needed to upgrade the TV main software and the
standby software at once.
• PQFPGA_AND1E_x.x.x.x.zip. Contains the BLCtrlµP
software in “upg” format.SW version available in CSM 2.5
PQ back-end software version.
• NovatekAfterburner314_AND1E_x.x.x.x.zip. Contains
the software in “upg” format to drive the Novatek 72314
(Frame Rate Convertor) device.SW version in CSM 2.6 NT
72314 software.
• RF4CE_AND1E_x.x.x.x.zip.Contains the software in
“upg” format to drive the RF4CE device.SW version
available in CSM 2.9
• UHDFPGA_AND1E_x.x.x.x.zip.SW version available in
CSM 2.11

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EN 34 6. QV14.1E LA Alignments

6. Alignments
Index of this chapter: • LATAM models: an NTSC M TV-signal with a signal
6.1 General Alignment Conditions strength of at least 1 mV and a frequency of 61.25 MHz
6.2 Hardware Alignments (channel 3).
6.3 Software Alignments
6.4 Option Settings 6.3.1 White Point
6.5 Reset of Repaired SSB
6.6 Total Overview SAM modes
• Choose “Home”, “Apps”, “Setup” and then “Picture” and set
picture settings as follows:
6.1 General Alignment Conditions Picture Setting
Perform all electrical adjustments under the following
Contrast 100
conditions:
Brightness 50
• Power supply voltage (depends on region):
Colour 0
– AP-NTSC: 120 VAC or 230 VAC / 50 Hz ( 10%).
Light Sensor Off
– AP-PAL-multi: 120 - 230 VAC / 50 Hz ( 10%).
Picture format Unscaled
– EU: 230 VAC / 50 Hz ( 10%).
– US: 120 VAC / 60 Hz ( 10%).
• In menu “Picture”, choose “Advanced” and set picture
– LATAM-NTSC: 120 - 230 VAC / 50 Hz ( 10%).
settings as follows:
• Connect the set to the mains via an isolation transformer
with low internal resistance. Picture Setting

• Allow the set to warm up for approximately 15 minutes. Dynamic Contrast Off

• Measure voltages and waveforms in relation to correct Dynamic Backlight Off

ground (e.g. measure audio signals in relation to Colour Enhancement Off

AUDIO_GND). Caution: It is not allowed to use heat sinks Gamma (advanced) 0

as ground.
• Test probe: Ri > 10 M, Ci < 20 pF. • Go to the SAM and select “Alignments”-> “White point”.
• Use an isolated trimmer/screwdriver to perform
alignments. White point alignment LCD screens:
• Use a 100% white screen (format: 720p50) to the HDMI
6.1.1 Alignment Sequence input and set the following values:
– “Colour temperature”: “Cool”.
– All “White point” values to: “127”.
• First, set the correct options:
– In SAM, select “Option numbers”.
In case you have a colour analyser:
– Fill in the option settings for “Group 1” and “Group 2”
• Measure, in a dark environment, with a calibrated
according to the set sticker (see also paragraph 6.4
contactless color analyser (e.g.Minolta CA-210) in the
Option Settings).
centre of the screen and note the x, y value.
– Press OK on the remote control before the cursor is
• Apply a 90% full white screen to the HDMI input and select
moved to the left.
this input.Format : 720p50.If a Quantum Data generator is
– In submenu “Option numbers” select “Store” and press
used, it’s recommended to select the “FLAT” predefined
OK on the RC.
setting from the device.
• OR:
• Adjust the correct x, y coordinates (while holding one of the
– In main menu, select “Store” again and press OK on
White point registers R, G or B on 127) by means of
the RC.
decreasing the value of one or two other white points to the
– Switch the set to standby.
correct x, y coordinates (see Table). Tolerance: dx: 
• Warming up (>15 minutes).
0.002, dy:  0.002.
• Repeat this step for the other colour temperatures that
6.2 Hardware Alignments need to be aligned.
Not applicable. • When finished press OK on the RC and then press STORE
(in the SAM root menu) to store the aligned values to the
6.3 Software Alignments NVM.
Put the set in SAM mode (see Chapter 5. Service Modes, Error • Restore the initial picture settings after the alignments.
Codes, and Fault Finding). The SAM menu will now appear on
the screen. Select ALIGNMENTS and go to one of the sub Table 6-1 White D alignment values:
menus. The alignments are explained below.
The following items can be aligned: Value Cool (11000K) Normal (9000K) Warm (6500K)
• White point x tbd tbd tbd
• Ambilight. y tbd tbd tbd

To store the data:


• Press OK on the RC before the cursor is moved to the If you do not have a colour analyser, you can use the default
left values. This is the next best solution. The default values are
• In main menu select “Store” and press OK on the RC average values coming from production(statistics).
• Switch the set to standby mode. • Select a COLOUR TEMPERATURE (e.g. COOL,
NORMAL, or WARM).
For the next alignments, supply the following test signals via a • Set the RED, GREEN and BLUE default values according
video generator to the RF input: to the values in Table 6-2 and following.
• EU/AP-PAL models: a PAL B/G TV-signal with a signal • When finished press OK on the RC, then press STORE (in
strength of at least 1 mV and a frequency of 475.25 MHz the SAM root menu) to store the aligned values to the NVM.
• US/AP-NTSC models: an NTSC M/N TV-signal with a • Restore the initial picture settings after the alignments.
signal strength of at least 1 mV and a frequency of 61.25
MHz (channel 3).

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Alignments QV14.1E LA 6. EN 35

Table 6-2 White tone default settings 48PFS81x9 you can set all options very quickly. All options are controlled
via eight option numbers.
White Tone 48PFS8109/x When the NVM is replaced, all options will require resetting. To
Colour Temp R G B be certain that the factory settings are reproduced exactly, you
Normal 127 115 89 must set both option number lines. You can find the correct
Cool 125 122 127 option numbers on the rearcover sticker from the TV-set.
Warm 127 99 58 Example: The options sticker gives the following option
numbers:
• Group 1 : 08192 00133 01387 45160
Table 6-3 White tone default settings 55PFS81x9 • Group 2 : 12232 04256 00164 00000
The first line (group 1) indicates hardware options 1 to 4, the
White Tone 55PFS8109/x second line (group 2) indicate software options 5 to 8.
Colour Temp R G B Every 5-digit number represents 16 bits (so the maximum value
Normal 127 116 80 will be 65536 if all options are set).
Cool 127 125 116 When all the correct options are set, the sum of the decimal
Warm 127 100 46 values of each Option Byte (OB) will give the option number.

Table 6-4 White tone default settings 55PFS82x9 Diversity


Not all sets with the same Commercial Type Number (CTN)
White Tone 55PFS8209/x necessarily have the same option code!
Colour Temp R G B Use of Alternative BOM => an alternative BOM number usually
Normal 127 114 83 indicates the use of an alternative display or power supply. This
Cool 127 123 115 results in another display code thus in another Option code.
Warm 127 99 47 Refer to Chapter 2. Technical Specs, Diversity, and
Connections.
Table 6-5 White tone default settings 55PUS8809
6.5 Reset of Repaired SSB
The NVM on an SSB coming from repair (on component level
White Tone 55PUS88x9/x
in a Service shop) must always be reset.
Colour Temp R G B
After a repaired SSB has been mounted in the set (set repair
Normal 127 103 99
on board level), set the type number (CTN) and production
Cool 127 110 118
code + 18AC’s (SSB, display and supply) of the TV-set
Warm 127 90 62
according to the data on the type plate of the set (no info on
18AC’s here). For this, you can use the NVM editor in SAM.
6.4 Option Settings This action also ensures correct functioning of the “Smart TV”
feature and access to the Smart TV portals.
6.4.1 Introduction After SSB repair, the original channel map can be restored,
provided that:
The microprocessor communicates with a large number of I2C • the original channel map was stored on USB stick before
repair was started, and
ICs in the set. To ensure good communication and to make
• the basic functionality of the TV, needed for this procedure,
digital diagnosis possible, the microprocessor has to know
which ICs to address. was not hampered as a result of the defect.
The procedure of “channel map cloning” is clearly described in
the (electronic) user manual.
Notes:
• After changing the option number(s), save them by
pressing the “OK” button on the RC before the cursor is 6.5.1 SSB identification
moved to the left, select “STORE” in the SAM root menu
and press “OK” on the RC. When ordering a new SSB (“Service” SSB), make sure to use
• The new option setting is only active after the TV-set is the correct ordering number.
switched “off” / “standby” and “on” again with the mains The ordering number is an 18AC (18 alphanumeric code), with
switch (the NVM is then read again). structure <18AC SSB><serial number>. It is present on a bar
code sticker located on the SSB (see Figure).
6.4.2 (Service) Options If the sticker contains two or more ordering numbers, then use
the one preceded by character “S”.
From 2011 onwards, it is not longer possible to change
individual option settings in SAM. Options can only be changed
all at once by using the option codes as described in section
6.4.4.

6.4.3 Option Code Overview

Refer to the rearcover sticker in the set for the correct option
codes.
Important: After having edited the option numbers as
described above, press OK on the remote control before the
cursor is moved to the left!

6.4.4 Opt. No. (Option numbers)

Select this sub menu to set all options at once (expressed in


two long strings of numbers).
An option number (or “option byte”) represents a number of
different options. When you change these numbers directly, Figure 6-1 SSB identification

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EN 36 6. QV14.1E LA Alignments

6.6 Total Overview SAM modes

Table 6-6 SAM mode overview

Main Menu Sub-menu 1 Sub-menu 2 Sub-menu 3 Description


Hardware Info A. SW version e.g. “AND1E_0.7.31.0E Display TV & Standby SW version and CTN serial
B. Standby processor version e.g. “14.01.02.00” number

C. Production code e.g. “see type plate”


Operation hours Displays the accumulated total of operation hours.TV
switched “on/off” & every 0.5 hours is increase one
Shop operation hours Displays the accumulated total of operation hours in
“shop mode”
Errors Displays the most recent errors
Reset error buffer Clears all content in the error buffer
Alignment White point Colour temperature Normal 3 different modes of colour temperature can be
Normal selected

Warn
Cool
White point red LCD White Point Alignment. For values,
White point green see Table 6-2 White tone default settings
48PFS81x9 and following.
White point blue
Ambilight Select module
Brightness
Option numbers Group 1
Group 2
Store
Initialise NVM
Store Select Store in the SAM root menu after making any
changes
Software maintenance Software events Display Display information is for development purposes
Clear
Test reboot
Test kernel crash
Test application crash
Hardware events Display Display information is for development purposes
Clear
Test setting Digital info Current frequency: 538
QAM modulation: 64-qam Display information is for development purposes
Symbol rate:
Original network ID: 12871
Network ID: 12871
Transport stream ID: 2
Service ID: 3
Hierarchical modulation: 0
Selected video PID: 35
Selected main audio PID: 99
Selected 2nd audio PID: 8191
Install start frequency 000 Install start frequency from “0” MHz
Install end frequency 999 Install end frequency as “999” MHz
Default install frequency
Installation Digital only Select Digital only or Digital + Analogue before
Digital + Analogue installation

RF4CE pairing tables Clear paired remote control


Wi-Fi Direct settings Reset Wi-Fi Direct Group
Development file Development 1 file version Display information is for development purposes
versions

Development 2 file version 18AC one zip software Display information is for development purposes
Initial main software
NVM version
e-Sticker software
Upload to USB

Download from USB Item “Channel list” removed from the user interface

NVM editor Type number see type plate NVM editor; re key-in type number and production
Production code see type plate code after SSB replacement

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Circuit Descriptions QV14.1E LA 7. EN 37

7. Circuit Descriptions
Index of this chapter:
7.1 Introduction
UHD100
7.2 Marvell platform
7.3 Power Supply

Notes: + 1x
FPGA
• Only new circuits that are not published recently) are
described. BG2Q
• Figures can deviate slightly from the actual situation, due Copper layer 6 Cypress
to different set executions.
• For a good understanding of the following circuit HDMI
descriptions, refer to the wiring- and blockdiagrams of
Chapter 9. Block Diagrams and the circuit diagrams of SUT-PE531

SUT-PE231

Chapter 10. Circuit Diagrams and PWB Layouts.


Where necessary, you will find a separate drawing for

F-Type

F-Type
IEC-Type
clarification. Copper layer 9

19570_182_140728.eps
7.1 Introduction 14-07-28
The QV14.1E LA is a new platform launched in Europe in 2014.
This chassis contains the Marvell BQ-2. The major deltas Figure 7-2 UHD100
versus its predecessor are DVB-TC; DVB-TC/T2, DVB-TC/S2
with also multimedia, 3D, AmbiLight, WiFi, Smart TV and Light
Sensor functionality.
UHD50
The QV14.1E LA covers sets in the following series:
• xxPUX790x (49” and 55”, UHD 50Hz QLED),
• xxPFS810x (48” and 55”, FHD 100Hz QLED), 314
• xxPFS820x (48” and 55”, FHD 100Hz QLED),
• 55PUS88xx (UHD 100Hz QLED),
BG2Q
• 55PUS89xxc (UHD 100Hz QLED, curved), Cypress
Dur
ang
• xxPUS91xx (55” and 65”, UHD 100Hz QLED), o

• 65PUS98xx (UHD 100Hz 2DD).


SUT-PE531

SUT-PE231

The xxPFS8xxx sets have the following styling:


• xxPFS810x have a silver edge and edge feets,
F-Type

F-Type
IEC-Type

• xxPFS820x have a white edge and edge feets, Copper layer 13


• xxPFS815x have a silver edge and a central stand.
19570_183_140728.eps
14-07-28
7.2 Marvell platform
Figure 7-3 UHD50
7.2.1 Diversity

7.2.2 Architectures

FHD100
The following Figures give an overview.
Refer to chapter 9. Block Diagrams for larger diagrams.
• for the 81xx- and 82xx series:
314 9.16 Architecture - FHD,
• for the 88xx series:
BG2Q
9.18 Architecture - UHD,
Cypress • for the 79xx series:
9.20 Architecture - UHD50.

SUT-PE531

SUT-PE231
F-Type

F-Type
IEC-Type

Copper layer 3

19570_181_140728.eps
14-07-28

Figure 7-1 FHD100

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EN 38 7. QV14.1E LA Circuit Descriptions

Marvell BG2-Q Architecture FHD100


11n 2x2

2x DDR3 2x DDR3 DDR3 2x DDR3


Wifi 1600 1600 eMMC 1600 1600
4Gb 4Gb 4GB 2Gb 2Gb
32 32 16 32

USB2.0 FPGA
LX75
USB
U SB
SB USB2.0 I2S
=Anaconda
2 Wifi
W i fi ETH
USB
U SB
USB Noise
W i fi
2 Wifi
USB3.0 3D-LR 3D-LR FRC
HUB reduction
USB Local contrast
NT72314
2 Wifi FHD 100Hz 3D-Goggle
BL-PWM (8
SplashscreenOn
Disp-Ctr (4

SPI
BG2-Q UART
3D-LR
BL-Boost

DVB- Quad Core A9


S-Tuner
T/C/S/ CiMax 4x16bit DDR3 AL-SPI/Ctrl
T2/C2/S2 TS-out AL-SPI SPI AL-SPI
swtich
DVB- TS-in
Hybrid
tuner T/C/S/
T2/C2/S2 I2S Audio
TS-in
AMP
G
GLUE
LUE LR
IF
SPDIF SPDIF
TTL I2S

GLUE
GLUE
GLUE
GLUE
HDMI GLUE
GLUE
GLUE
GL4UE
to
1
GLUE
GLU
UE G
GLUE
LUE

Analog
demod. GLUE
GLUE Cypress C0
YPbPr
GLUE
Audio L/R

RGB
GLUE GLUE
GLUE CVBS GLUE
GLUE

19570_161_140721.eps
14-07-21

Figure 7-4 Marvell BG-Q2 Architecture FHD100

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Circuit Descriptions QV14.1E LA 7. EN 39

Marvell BG2-Q Architecture UHD100

11n 2x2

Wifi 2x DDR3
1600
2x DDR3
1600 eMMC
DDR3
1600
2x DDR3
1600
BoltOn
4Gb 4Gb 4GB 2Gb 2Gb
32 32 16 32

USB2.0 FPGA
LX75
U
USB
SB USB2.0 I2S =Anaconda
W i fi
2 Wifi ETH AL-SPI
USB
U
USB
SB
USB3.0
Noise
HUB
W i fi
2 Wifi 3D-R/QFHD
HD 3D-LR FRC Master
reduction
USB NT72314
Local contrast
2 Wifi UHD 100Hz
SplashscreenOn
hscreenOn
3
3D-Goggle
BG2-Q BL-PWM (8x)
B
Disp-Ctrl (4x)
D
Quad Core A9 3
3D-LR
SPI 4x16bit DDR3 UART BL-BOOST
B
DVB-
S-Tuner T/C/S/
CiMax
T2/C2/S2
TS-out AL-SPI AL-SPI

DVB- TS-in
Hybrid
T/C/S/ FRC Slave
tuner
T2/C2/S2 I2S Audio NT72314
TS-in AMP UHD 100Hz
GLUE
GLUE LR
IF SPDIF
SPDIF
TTL I2S 4K FPGA LX25/45

2x DDR3
To HDMI ARC TTL to LVDS

1600
1Gb
1G
ADV7619

32
32
Panel rotation

Gb
SPDIF
420 to 444
= BOA
GLUE
GLUE

Cypress C0GLUE
GLUE
UE
GLUE
GLUE
UE
GLUE
UE

Analog SiI9573 SiI9679


LU
LU
GLU

demod. GLUE
GLUE
=Rogue
G
G

YPbPr
GLUE
Audio L/R

RGB
GLUE GLUE
GLUE CVBS GLUE
GLUE

19570_162_140721.eps
14-07-21

Figure 7-5 Marvell BG-Q2 Architecture UHD100

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EN 40 7. QV14.1E LA Circuit Descriptions

Marvell BG2-Q Architecture UHD50


17511n 2x2
2x DDR3 2x DDR3 DDR3 2x DDR3
Wifi 1600 1600 eMMC 1600 1600
4Gb 4Gb 4GB 1Gb 2Gb
32 32 16 32

USB2.0
FPGA
USB
U SB USB2.0 I2S LX75
2 Wifi
W i fi ETH =Anaconda+
AL-SPI
USB
USB
U SB
USB3.0 FRC Master
HUB
2 Wifi
W i fi 3D-LR/QFHD
HD
D FHD: 3D-LR
USB Noise reduction NT72314
2 Wifi Local contrast UHD 50Hz 3D-Goggle
3
SplashscreenOn
eenOn JPEG: BL-PWM (8
B
UHD Stitching
BG2-Q UHD:
Gfx blending + Boa
D
Disp-Ctr (4
3D-LR
SPI BL-Boost
B
Quad Core A9 functionality
DVB- 4x16bit DDR3
S-Tuner T/C/S/ CiMax
T2/C2/S2 TS-out AL-SPI AL-SPI

DVB- TS-in
Hybrid
tuner T/C/S/
T2/C2/S2 I2S Audio
TS-in AMP

GLUE
GLUE LR
IF SPDIF
SPDIF
TTL I2S

To HDMI ARC
SPDIF ADV7619

GLUE
GLUE

Cypress C0
GLUE
UE
GLUE
UE
GLUE
UE

Analog GLUE SiI9573 SiI9679


GLU
LU
GLU

GLUE
GLUE
demod. =Rogue
G

YPbPr
GLUE
Audio L/R

RGB
GLUE GLUE
GLUE CVBS GLUE
GLUE

19570_163_140721.eps
14-07-21

Figure 7-6 Marvell BG-Q2 Architecture UHD50

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Circuit Descriptions QV14.1E LA 7. EN 41

7.2.3 Marvell Copper Layouts Refer to Chapter 9 for detailed Architecture and Connections:
• 9.16 Architecture - FHD, 9.17 Connections - FHD,
The following Figures show the layout of the different SSB’s • 9.18 Architecture - UHD, 9.19 Connections - UHD Rogue,
and of the Bolt-on. They also give the location of parts and • 9.20 Architecture - UHD50, 9.21 Connections - UHD60
principal components. Rogue,

POWER COMMON INTERFACE

BACK-END CI2

CIMax

FRC eMMC flash


NT72314
MV BG2-Q
CI1

SOC1
HDMI
PQ FPGA SI9287B
Anaconda MV Cypress 4:1 mux

USB 2x
SERVICE

LAN
Audio Class-D
FRONT-END
TAS5760
HDMI 2x
Channel decoders
Si21xx ANALOG SCART
Dual Tuner
PE531

USB HDMI 2x
Headphone SPDIF I/O
Hybrid Satellite

19570_164_140721.eps
14-07-31

Figure 7-7 Marvell BG2-Q Copper 3 layout (FHD100)

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EN 42 7. QV14.1E LA Circuit Descriptions

POWER COMMON INTERFACE

BACK-END HDMI to TTL CI2


ADV7619

4k FPGA CIMax
Boa

eMMC flash
MV BG2-Q
CI1

SOC1
HDMI
PQ FPGA 6:2 mux
Anaconda MV Cypress
USB

SERVICE

USB

LAN
Audio Class-D HDMI
FRONT-END Rogue HDMI 2.0
TAS5760
Channel decoders
HDMI 2.0
Si21xx ANALOG SCART
Dual Tuner
PE531

HDCP 2.2
USB
Headphone SPDIF
+ HDMI 2.0 HDMI 2.0 I/O
Hybrid Satellite

19570_165_140721.eps
14-07-31

Figure 7-8 Marvell BG2-Q Copper 9 layout (UHD100)

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Circuit Descriptions QV14.1E LA 7. EN 43

FRC Master
FRC Slave N314
N314

19570_167_140721.eps
14-07-22

Figure 7-9 Bolt-on copper 6 layout

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EN 44 7. QV14.1E LA Circuit Descriptions

7.3 Power Supply fuse with one with the correct specifications! This part is
available in the regular market.
7.3.1 Power Supply Unit Consult the Philips Service web portal for the order codes of the
boards.
All power supplies are a black box for Service. When any of
these power supplies is defective, a new board must be 7.3.2 Power Architecture
ordered and the defective one must be returned, unless the
main fuse of the board is broken. Always replace a defective For the power architecture, refer to the following Figures.

Connector from PSU

X090 +3V5-STANDBY +12V-AL

SIP32429DN-GE4 or
AOZ1360DIL U022U
U003U U001U U004U
+3V5-STANDBY
LDO LDO + WOLAN-ENABLE Over
RT9193- switch current (2 sides AL)
33GB RT9187GSP protection

+12V +3V3-STANDBY +3V3-LAN

AMBI-POWER

+12V-AL

IR sensor,
Ambilight
Keyboard Wifi X031
To RF4CE X026
X026 connector
connector
connector

19570_171_140723.eps
14-07-23

Figure 7-10 Power Architecture FHD100/UHD100/UHD50 - PSU-connector

RT7297CHZSP for FHD


+12V

U017U U018U U027U U019U U001F


DC/DC DC/DC DC/DC DC/DC DC/DC i2C
DETECT12V RT8288A ENABLE+3V3 RT8288A TPS5452 ENABLE+1V5-BE RT8288A ENABLE+5V-USB LNBH26
ZSP ZSP 7DDA ZSP LSPQR

+3V5-STANDBY
+5V-FE +3V3 +1V5-BE +5V-USB
+V-LNB-DT +V-LNB

+VPMIC +2V5-TUNER
U007F
EN1 +5V-FE EN2 +5V-FE EN1 +5V-FE LDO
RT9187GS TPS54427 for UHD 50Hz & FHD LNB
EN2 +VPMIC U007U U008U U005F USB 1, 2, 3
U011U P
DC/DC LDO
PMIC PMIC +3V3
TPS5431 AZ1117CH
88PG867RB0 88PG867SB0 Tuner
9RTE DDR-ENABLE -3.3G1 +3V3-CIMAX
+3V3-MRV U011F
+1V5-MRV +1V8-STANDBY
ST
TAN +VCPU VCORE Skype
+3V3-DVB LDO
AZ1117CH
-1.8G1
USB Hub
+1V8-TUNER
Marvell DDR Marvell DG2-Q Marvell (SM)
+3V3-STANDBY +3V3-TUNER
U006F +1V2-CIMAX
CAM 1&2 (CI)
+1V8-AVDD LDO
RT9025 CiMAX
+VTT EMMC
(Marvell) +5V-FE
U013U Chanel
decoder
LDO +1V2-DVB 3D emitter
T/T2/C/C2/S
TPS51200 U021C
/S2
DRCR Cypress
+1V0-C LDO
RT9025 UHD
U009U +1V8-MRV
+3V3-MRV
Switch +5V-FE
AO3414 U004H +1V3-HDMI
HDMI MUX
HDCP2,2 UHD:
Rogue LDO SIL9573
+5V-FE UHD RT9025 FHD:
SII9287B
U003B +5V-FE
+1V8
UHD ADV7619 LDO
Ethernet (HDMI) RT9025 U001H
+3V3-HDMI
Switch
+5V-FE AO3414

+5V-FE

BE

19570_172_140723.eps

Figure 7-11 Power Architecture FHD100/UHD100/UHD50 - Front end

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Circuit Descriptions QV14.1E LA 7. EN 45

+3V3 +12V
+12V BE-ENABLE ENABLE+1V5+2V5

U028B
U010U
Dual DC/DC
DC/DC ENABLE+3V3
TPS54494PWP
ENABLE+3V3
TPS5442
7DDA
+1V0-M +1V5-M

+1V2

+1V5-BE +3V3 +1v5-BE


U026B
+2V5-M
RT9187GS

U021B
P FRC
DDR
U029B
Novatec Novatek
DDR FPGA interface +2V5-BE LDO DDR’s
FPGA LX75 RT9187G Switch IO supply
NT72314
(PQ, NR, LC) Anaconda SP RT9715EG voltages FHD 100Hz
B Novatek
+3V3 +3V3-NVT

ENABLE+3V3-NVT

19570_173_140723.eps
14-07-23

Figure 7-12 Power Architecture FHD100 - Back end

+12V
+3V3 +3V3

U010U

DC/DC
ENABLE+1V2-FPGA TPS5442
7DDA

+1V2
+3V3
+3V3
+1V5-BE

U021B
DDR FPGA LDO
1&2 FPGA LX25 FPGA LX75 +2V5-BE
RT9187G
(HDMI2,0) Boa (PQ, NR, LC) Anaconda+ SP

+3V3

19570_174_140723.eps
14-07-23

Figure 7-13 Power Architecture UHD100 - Back end

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EN 46 7. QV14.1E LA Circuit Descriptions

+12V
+3V3 +3V3

U010U

DC/DC
ENABLE+1V2-FPGA TPS5442
7DDA

+1V2
+3V3
+3V3
+1V5-BE

U021B
DDR FPGA LDO
1&2 FPGA LX25 FPGA LX75 +2V5-BE
RT9187G
(HDMI2,0) Boa (PQ, NR, LC) Anaconda+ SP

+3V3

19570_174_140723.eps
14-07-23

Figure 7-14 Power Architecture UHD50 - Back end

7.3.3 Low Voltage Differential Signalling


9809 series 65” - 75”
8xx9 series 48” - 55“

41p51
LVDS X050

51p51
LVDS X051 SSB BLD
Marvell
X055
FHD PSU X010 X053
X056 51p LVDS X056

100 Hz
BOLT-ON X054 51p LVDS X054 SSB
X318 Marvell
X051 51p LVDS X051
X060 X061 UHD

75” only
41 51

Samsung TCON

19570_202_140822.eps
14-08-22
Samsung TCON
Figure 7-15 FHD100
19570_204_140822.eps
14-08-22

9109 series 55” - 65” Figure 7-17 UHD50

X056 51p LVDS X056


X010 X053

BOLT-ON X054 51p LVDS X054 SSB


X318 Marvell
X051 51p LVDS X051
X060 X061 UHD

41 51

Samsung TCON

19570_203_140822.eps
14-08-22

Figure 7-16 UHD100

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Circuit Descriptions QV14.1E LA 7. EN 47

7.3.4 Power Layout

e
issu
t i m e of
le a t
t availab
No

19570_178_140728.eps
14-07-28

Figure 7-18 Power Top View

e
issu
t i m e of
a t
va i l able
Not a

19570_178_140728.eps
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Figure 7-19 Power Bottom View

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EN 48 8. QV14.1E LA IC Data Sheets

8. IC Data Sheets
This chapter shows the internal block diagrams and pin electrical diagrams (with the exception of “memory” and “logic”
configurations of ICs that are drawn as “black boxes” in the ICs).

8.1 Diagram, Marvell BG2-Q


For Circuit Diagrams refer to 10. Circuit Diagrams and PWB
Layouts.

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Block Diagrams QV14.1E LA 9. EN 49

9. Block Diagrams
9.1 Wiring Diagram 81x9 and 82x9 series 48"

Wiring Diagram 48” 8xx9 series

48PFS8109

0
8SK3
8PS316 S90
8P
8TC60

8TC61

PSU

8CA26

8C
A3
1

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Block Diagrams QV14.1E LA 9. EN 50

9.2 Wiring Diagram 81x9 and 82x9 series 48" Backcover

Wiring diagram 48" 8xx9 series (inside View Backcover)

48PFS8109

8AL01

8CA05

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Block Diagrams QV14.1E LA 9. EN 51

9.3 Wiring Diagram 79xx series 49"

Wiring diagram 49" 79xx series

R L

90
8PS

8TC51

8CA26
8CA31

PHILIPS
49PUS7909

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Block Diagrams QV14.1E LA 9. EN 52

9.4 Wiring Diagram 79xx series 49" Backcover

Wiring diagram 49" 79xx series - Backcover (inside view)

L R

8AL02

8AL01

49PUS7909 Backcover

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Block Diagrams QV14.1E LA 9. EN 53

9.5 Wiring Diagram 79xx series 55"

Wiring diagram 55" 79xx series

R L
8AL02

8PS90

8TC51

8AL01

8CA31
8CA26

PHILIPS
55PUS7909

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Block Diagrams QV14.1E LA 9. EN 54

9.6 Wiring Diagram 79xx series 55" Backcover

Wiring diagram 55" 79xx series - Backcover (X-ray view = view from outside!)

R L

02
8AL

8AL01

55PUS7909 Backcover

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Block Diagrams QV14.1E LA 9. EN 55

9.7 Wiring Diagram 81x9 and 82x9 series 55"

Wiring diagram 55" 8xx9 series

55PFS8109

0
8SK3
8PS316 S90
8P
8TC60

8TC61

PSU

8CA26

8C
A3
1

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Block Diagrams QV14.1E LA 9. EN 56

9.8 Wiring Diagram 81x9 and 82x9 series 55" Backcover

Wiring diagram 55" 8xx9 series (inside View Backcover)

55PFS8109

8AL01

05
8CA

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Block Diagrams QV14.1E LA 9. EN 57

9.9 Wiring Diagram 88x9 series 55" (including Backcover in X-ray view)

Wiring diagram 55" 88x9 series

1171 - Ambilight Module 1172 - Ambilight Module 1171 - Ambilight Module

8AL03 8AL04
30 8AL05
8AL02
8PS316 8SK
8FR91
8PS90

8FP51

1170 - Ambilight Module


1170 - Ambilight Module

8PS10
8FP54
1113 - BOLTON
8FP56 1111 - SSB
X316 X010

8TC60 8TC61
X090
8CA26
1050 - PSU
8CA31

8AL01 1011 - Bluetooth

1028 - Camera

5211 - Speaker

5211 - Speaker

1010 - CAB 1011 - Wordmark 55PUS8809


1012 - CIP
Note: Ambilight modules and wires in backcover (dashed lines)

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Block Diagrams QV14.1E LA 9. EN 58

9.10 Wiring Diagram 89x9 series 55" curved

Wiring diagram 55" 89xx curved series

R L
8P
S3 8P
1004 - TFT screen 16 S3
19

Mandatory
position

M pos
8F

an i 
R9

da on
0

to
ry
1111 - SSB
0 5210 - Speaker 8FR51
9
1050 - PSU 8 PS
8FR54

Mandatory 8FR56
Attention: Live parts! position

Primary zone

0
S1
Keep any cable out of this area
8P

1113 - Bolt-on

8TC61
8TC60

8CA
31 8CA26
8S
K3
0

5211 - Speaker 5211 - Speaker

1010 - WiFi USB IEEE sensor module 1028 - Camera module 55PUS8909 curved
1012 - IR module 1011 - LED module
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Block Diagrams QV14.1E LA 9. EN 59

9.11 Wiring Diagram 89x9 series 55" curved Backcover

Wiring diagram 55" 89xx curved series

L 1170 - Am7ilight Module 7 LED 1171 - Am7ilight Module 8 LED 1170 - Am7ilight Module 7 LED
R

8AL05 8AL04 8AL03 8AL02


1172 - Ambilight Module 10 LED

1172 - Ambilight Module 10 LED


0011 - Backcover

8AL01

55PUS8909 curved

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Block Diagrams QV14.1E LA 9. EN 60

9.12 Wiring Diagram 91x9 series 55" - 65"

Wiring diagram 55" - 65" 91x9 series

R L

1004 - TFT screen

0661 - Deco back

8PS90
65" only
8PS319

0
8PS316 8C

K3
A2

8S
6 91
R
8F
1111 - SSB
8FR51

8FR54

1113 - Ultra HD Module 8FR56

1050 - PSU
8TC60 8TC61

8CA26

8C
A3
1

1020
5211 - Speaker Camera module 5211 - Speaker

1010 - WiFi USB IEEE sensor module


1012 - IR module 1011 - LED module
55PUS9109
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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 61

9.13 Wiring Diagram 91x9 series 55" - 65" Backcover (in X-ray view)

Wiring diagram 55" - 65" 91x9 series - Backcover (X-ray view = view from outside!)

R L

0661 - Deco Back

1170 - AmbiLight module Top 1170 - AmbiLight module Top

8PS10
8AL02 8AL03 8AL04
1171 - AmbiLight module Side

1171 - AmbiLight module Side


0074 - AmbiLight door (65" only)

0011 - Backcover

8AL01

8AL06
8AL05
8AL07

1172 - AmbiLight module 8 LED 1172 - AmbiLight module 8 LED

55PFL9109 Backcover
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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 62

9.14 Wiring Diagram 98x9 series 65"

Wiring diagram 65" 98x9 series

1004 - TFT screen

8P

91
S3

R
19

0
8F

8PS9
3
8FR5
0
8PS1

8FR51

8FR54
1113 - Ultra HD Module 8FR56
1050 - PSU

8PS3 1111 - SSB


16

8CA26 8TC60 8TC61

5211 - Speaker 8S 5211 - Speaker


K
30
8C
A3
1

1010 - WiFi USB IEEE sensor module 1028 - Camera module


1012 - IR module 1011 - LED module

65PUS9809
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Block Diagrams QV14.1E LA 9. EN 63

9.15 Wiring Diagram 98x9 series 65" Backcover (inside view)

Wiring diagram 65" 98x9 series (view inside backcover)

L 1172 - Ambilight Module 9 LED 1171 - Ambilight Module 7 LED 1172 - Ambilight Module 9 LED R
1171 - Ambilight Module 7 LED

1171 - Ambilight Module 7 LED


8AL06 8AL05 8AL04 8AL03

0011 - Backcover

8AL07
8AL02
1171 - Ambilight Module 7 LED

1171 - Ambilight Module 7 LED


8AL01

8AL08
8AL11
8AL09 8AL10

1170 - Ambilight Module 9 LED 1171 - Ambilight Module 7 LED 1170 - Ambilight Module 9 LED

65PUS9809 Backcover
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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 64

9.16 Architecture - FHD

Marvell BG2-Q Architecture FHD100

11n 2x2

2x DDR3 2x DDR3 DDR3 2x DDR3


Wifi 1600 1600 eMMC 1600 1600
4Gb 4Gb 4GB 2Gb 2Gb
32 32 16 32

USB2.0 FPGA
LX75
USB
U SB
SB USB2.0 I2S
=Anaconda
2 Wifi
W i fi ETH
USB
U SB
USB Noise
2 Wifi
W i fi
USB3.0 3D-LR 3D-LR FRC
HUB reduction
USB Local contrast
NT72314
2 Wifi FHD 100Hz 3D-Goggle
BL-PWM (8
SplashscreenOn
Disp-Ctr (4

SPI
BG2-Q UART
3D-LR
BL-Boost

DVB- Quad Core A9


S-Tuner
T/C/S/ CiMax 4x16bit DDR3 AL-SPI/Ctrl
T2/C2/S2 TS-out AL-SPI SPI AL-SPI
swtich
DVB- TS-in
Hybrid
tuner T/C/S/
T2/C2/S2 I2S Audio
TS-in
AMP
GLUE
GLUE LR
IF
SPDIF SPDIF
TTL I2S

GLUE
GLUE
GLUE
GLUE
HDMI GLUE
GLUE
GLUE
GL4UE
to
1
GLUE
GLUE GLUE
GLU
UE

Analog
demod. GLUE
GLUE Cypress C0
YPbPr
GLUE
Audio L/R

RGB
GLUE GLUE
GLUE CVBS GLUE
GLUE

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Block Diagrams QV14.1E LA 9. EN 65

9.17 Connections - FHD

400kHz C&C Architecture

DDR3-1866

DDR3-1866

DDR3-1866

DDR3-1866
HDMI EDID0
2014 Marvell BG2-Q

4GByte
eMMC
0xA0

4Gbit

4Gbit

4Gbit

4Gbit
SYSTEM-RESETn eMMC-RESETn
400kHz
FHD

I2C 4:1 MUX


HDMI EDID1
0xA0

X340
DVBS2-Tuner Analog Demod 400kHz Serial Flash
0xC6 0x84 128Mbit=16MB
HDMI EDID2
0xA0 x16 x16 x16 x16 x8
Hybrid-Tuner 400kHz I²C-TUNER DVB-T/C/S/T2/C2/S2 400kHz
DDR3 Controller 2x 32 bits eMMC
0xC0 Channel Decoder HDMI EDID3
0xC8 V4.41
0xA0 0xE4 X307

16Mbit=2MB
DDR3-1600

DDR3-1600

Serial Flash
X020-X025-X026
DT-Hybrid-Tuner

1Gbit

1Gbit
SoC-SPI-SerialFlash
DVBS LNB (ST & DT)
0xC0 0x10
Bypass Reset BE-RESETn
400kHz X322 opons Generator

SPI-AMBI
DT-DVBS2-Tuner I²C-DT-TUNER DT DVB-T/C/S/T2/C2/S2 I²C-FE 0
0xC6 Channel Decoder

X342
0xCE
400kHz X320
SYSTEM-RESETn I²C-TW1 x16 x16 SPI
Class D Amplifier TW1 SPI-Switch
SoC-SPI-AMBI

SPI
0xD8 (in FPGA) DDR3 2x16 SPI
100kHz
X328
400kHz
I²C-CYPRESS 2 NT-SPI-AMBI

SPI
CYPRESS-RESETn
Marvell Cypress
0x40-0x42 400kHz
X327 BE-RESETn FRC-M
HDMI-MUX-RESETn I²C-HDMI 3 X323 100kHz
HDMI-MUX (6:2 or 4:1) NT72314

I²C-M
400kHz

I²C-S
Table I²C-BE
400kHz TW0

SSB Temp-Sensor UART1 UART2 0x34


0x98

I2C 4:1 MUX


Opon to PQ-IC
PMIC Vcore & 0x90 X314
3V3
X020-X025-X026

X020-X025-X026
X321 X313 X312
100kHz
I²C-SRF 1
Light Sensor
0x52 100kHz SYSTEM-RESETn
0xE2

2Mbit=256kB
64Mbit =8MB
DDR3-1600

DDR3-1600

DDR2-1066

DDR2-1066

Serial Flash
Serial Flash

256 Mbit

256 Mbit
1Gbit

1Gbit
100kHz
Set Temp
X071

X071

Bypass
Sensor 0x98 opons
X332

I2C 2:1 MUX

X345
SYSTEM-RESETn

X344
PMIC I²C-PMIC1 1
I²C-BE

Quad Core A9
Vcore & 3V3 0x32 400kHz
X330 X329 x16 x16 SPI x16 x16 SPI

BG2-Q
PMIC I²C-PMIC0 0 I²C-PMIC DDR3 2x16 SPI DDR2 2x16 SPI
I²C-HDMI2LVDS

EEPROM
SM-TW2

16kbit
Vcpu & 1V8 0x32 400kHz 400kHz

I²C
0xE0 BE-RESETn
PQ-FPGA HDMI X334
SM-GPIO4
Anaconda To
I²C-BE

I²C
X311

I²C
115kBaud UART-RF4CE LVDS
X027

CC2533
X027

UART1 0x84
RF4CE 0xA4

TI-RF4CE-DEBUG X310
RF4CE-RESETn

Mini-Jack UART-SERVICE
X206

UART0
X303 Bypass
X029 5pins 5V
opon
USB Skype X324

USB2 USB1 USB0


X030 8pins 5V
I²C-BL-Bus

X0..

X0..
1 BackLight
Wi-Fi

USB
USB 100kHz

PCA9543
I2C MPX
X031 6pins 3V3-WOLAN

X051 -1G55

X051 -1G55
USB USB X325
X280 USB-type A
0 I²C-DISP-Bus Display
Legend USB
0xE0
X281 USB-type A 100kHz
Delta with previous USB-HUB USB
X282 USB-type A

BE-RESETn
Removed MCU USB

Locaon Opons (System Manager)


SPI-CIMAX CIMax

SPI
I²C Subject to diversity
UART Customer Connectors X341
Ethernet

Ethernet
RESET Producon Connectors X296 RJ45 Connectors - Applicationata
I²C SW Bus ID
USB-Eth Debug Connectors Position Application
HW-Bus SW-Bus ID
Power RESET X000 - X099 Internal connectors
Name Hex
RF4CE-RESETn X100 - X199 Internal connectors (spare)
I2C
Flash eMMC-RESETn X200 - X299 User connectors
UART TW0 = BE-bus 0x0F
RESET

X300 - X399 Debug connectors


RESET

DDR SPI DISP-bus 0x00


SYSTEM-RESETn X300 - X309 (E)JTAG (incl. µP-debug-IF)
BL-Bus 0x01
Flash X310 - X319 UART
Level Shi TW1-bus 0x1F SOC-RESET-INn MCU-RESET-INn Reset
(E)JTAG Reset X320 - X329 I²C
FE-bus 0x10 Generator
GPIO USB&Ethernet SRF-bus 0x11 Generator MCU-RESET-OUTn X330 - X339 I²C (spare)
Power Cypress-bus 0x12 JTAG JTAG X340 - X349 SPI
ADC HDMI-bus 0x13 Buon Buon X350 - X359 CTRL
GPIO X301 X300 X360 - X369 UART (spare)
TW2 = PMIC 0x2F JTAG-BG2Q JTAG-MCU
8bits I2C address ADC PMIC1-bus 0x20 X370 - X379 USB
Other X392 X391 X380 - X389 Other
PMIC0-bus 0x21

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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 66

9.18 Architecture - UHD

Marvell BG2-Q Architecture UHD100

11n 2x2

Wifi 2x DDR3
1600
2x DDR3
1600 eMMC
DDR3
1600
2x DDR3
1600
BoltOn
4Gb 4Gb 4GB 2Gb 2Gb
32 32 16 32

USB2.0 FPGA
LX75
USB
U SB USB2.0 I2S =Anaconda
W i fi
2 Wifi ETH AL-SPI
USB
USB
U SB
USB3.0
Noise
HUB
W i fi
2 Wifi 3D-R/QFHD
HD 3D-LR FRC Master
reduction
USB NT72314
Local contrast
2 Wifi UHD 100Hz
SplashscreenOn
hscreenOn
3
3D-Goggle
BG2-Q BL-PWM (8x)
B
Disp-Ctrl (4x)
D
Quad Core A9 3D-LR
3
SPI 4x16bit DDR3 UART BL-BOOST
B
DVB-
S-Tuner T/C/S/
CiMax
T2/C2/S2
TS-out AL-SPI AL-SPI

DVB- TS-in
Hybrid
T/C/S/ FRC Slave
tuner
T2/C2/S2 I2S Audio NT72314
TS-in AMP UHD 100Hz
GLUE
GLUE LR
IF SPDIF
SPDIF
TTL I2S 4K FPGA LX25/45

2x DDR3
To HDMI ARC TTL to LVDS

1600
1G
1Gb
ADV7619

32
32
Panel rotation

Gb
SPDIF
420 to 444
= BOA
GLUE
GLUE

Cypress C0GLUE
GLUE

GLUE
GLUE
UE
GLUE
UE
UE
Analog SiI9573 SiI9679
LU
LU
GLU
demod. GLUE
GLUE
=Rogue
G
G
YPbPr
GLUE
Audio L/R

RGB
GLUE GLUE
GLUE CVBS GLUE
GLUE

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Block Diagrams QV14.1E LA 9. EN 67

9.19 Connections - UHD Rogue

400kHz C&C Architecture

DDR3-1866

DDR3-1866

DDR3-1866

DDR3-1866
HDMI EDID0
2014 Marvell BG2-Q

4GByte
eMMC
0xA0

4Gbit

4Gbit

4Gbit

4Gbit
SYSTEM-RESETn eMMC-RESETn
400kHz
UHD Rogue .1

I2C 4:1 MUX


HDMI EDID1
0xA0

X340
DVBS2-Tuner Analog Demod 400kHz Serial Flash
0xC6 0x84 128Mbit=16MB
HDMI EDID2
0xA0 x16 x16 x16 x16 x8
Hybrid-Tuner 400kHz I²C-TUNER DVB-T/C/S/T2/C2/S2 400kHz
DDR3 Controller 2x 32 bits eMMC

32Mbit=4MB (UHD)

32Mbit=4MB (UHD)
0xC0 Channel Decoder HDMI EDID3
0xC8 V4.41 X307
0xA0 0xE4

Serial Flash

Serial Flash
DDR3-1600

DDR3-1600

DDR3-1600

DDR3-1600
X020-X025-X026
DT-Hybrid-Tuner

1Gbit

1Gbit

1Gbit

1Gbit
SoC-SPI-SerialFlash
DVBS LNB (ST & DT)
0xC0 0x10
Reset BE-RESETn
400kHz X322 Generator

SPI-AMBI
DT-DVBS2-Tuner I²C-DT-TUNER DT DVB-T/C/S/T2/C2/S2 I²C-FE 0
0xC6 Channel Decoder

X342

X343
0xCE
400kHz X320
I²C-TW1 x16 x16 SPI x16 x16 SPI
Class D Amplifier TW1 SPI-Switch
0xD8 SoC-SPI-AMBI

SPI
100kHz (in FPGA) DDR3 2x16 SPI DDR3 2x16 SPI
X335 400kHz
NT-SPI-AMBI

SPI

SPI
EDID EEPROM HDCP 2.2
0xA0 I²C-HDCP 0x70 BE-RESETn FRC-M BE-RESETn FRC-S
SPI 100kHz
X346
X323
400kHz NT72314 X326
NT72314

I²C-M
I²C-M
I²C-BE I²C-NT

I²C-S

I²C-S
X0..

X0..
Serial Flash TW0
1Mbit=128kByte 400kHz UART1 UART2 0x34
400kHz
UART1 UART2 0x34
400kHz
HDMI2TTL 0x98 SYSTEM-RESETn
ADV7619 Table X314 X317
X020-X025-X026

X020-X025-X026
X321
100kHz X313 X312 X315 X316
I²C-SRF 1
Light Sensor
0x52 100kHz

64Mbit = 8MB
DDR3-1600

DDR3-1600

DDR3-1600

DDR3-1600
Serial Flash

Serial Flash
16/32Mbit
100kHz

=2/4MB
1Gbit

1Gbit

1Gbit

1Gbit
Set Temp
X071

X071

Sensor 0x98

I2C 4:1 MUX


SYSTEM-RESETn

X344

X347
Quad Core A9
x16 x16 SPI x16 x16 SPI
X328

BG2-Q
I²C-CYPRESS 2 DDR3 2x16 SPI DDR3 2x16 SPI
CYPRESS-RESETn
Marvell Cypress
0x40-0x42 400kHz
X327 BE-RESETn BE-RESETn
I²C-HDMI 3
PQ-FPGA UHD-FPGA
SSB Temp-Sensor
0x98
400kHz 0xE2 Anaconda Boa
I²C-BE

I²C

I²C
HDMI-MUX-RESETn
HDMI-MUX (6:2 or 4:1)
Table 0x84 400kHz 400kHz 0x86

X332
I2C 2:1 MUX

PMIC I²C-PMIC1 1 SYSTEM-RESETn


Vcore & 3V3 0x32 400kHz X029 5pins 5V Bypass
X330 X329 Skype opon
USB X324

USB2 USB1 USB0


PMIC I²C-PMIC0 0 I²C-PMIC X030 8pins 5V
I²C-BL-Bus

X0..

X0..
SM-TW2 1
Vcpu & 1V8 0x32 400kHz 400kHz Wi-Fi BackLight

USB
USB
100kHz

PCA9543
X031 6pins 3V3-WOLAN

I2C MPX
0xE0
USB USB

X051 -1G55

X051 -1G55
X280 X325
USB-type A
X311 USB 0 I²C-DISP-Bus Display
Legend UART-RF4CE X281 USB-type A 0xE0
X027

CC2533
X027

UART1 SYSTEM-RESETn 100kHz


USB-HUB USB
Delta with previous RF4CE X282 USB-type A
115kBaud

BE-RESETn
USB
RF4CE-RESETn

Removed MCU
X310 (System Manager)
Locaon Opons CIMax SYSTEM-RESETn
SPI-CIMAX

SPI
X303 Mini-Jack UART-SERVICE
X206

I²C Subject to diversity UART0


TI-RF4CE-DEBUG X341
UART Customer Connectors
Ethernet

Ethernet
RESET X296 RJ45 Connectors - Applicationata
Producon Connectors
I²C SW Bus ID
USB-Eth Debug Connectors Position Application
HW-Bus SW-Bus ID
Power RESET X000 - X099 Internal connectors
Name Hex RF4CE-RESETn
I2C X100 - X199 Internal connectors (spare)
Flash eMMC-RESETn X200 - X299 User connectors
TW0 = BE-bus 0x0F
RESET

UART
RESET

DISP-bus 0x00 X300 - X399 Debug connectors


DDR SPI SYSTEM-RESETn
BL-Bus 0x01 X300 - X309 (E)JTAG (incl. µP-debug-IF)
Flash SOC-RESET-INn Reset X310 - X319 UART
Level Shi TW1-bus 0x1F Reset MCU-RESET-INn
(E)JTAG FE-bus 0x10 Generator X320 - X329 I²C
Generator MCU-RESET-OUTn
GPIO USB&Ethernet SRF-bus 0x11 X330 - X339 I²C (spare)
JTAG JTAG X340 - X349 SPI
Power Cypress-bus 0x12
ADC Buon Buon X350 - X359 CTRL
GPIO HDMI-bus 0x13
X301 X300 X360 - X369 UART (spare)
TW2 = PMIC 0x2F JTAG-BG2Q JTAG-MCU
8bits I2C address ADC PMIC1-bus 0x20 X370 - X379 USB
X392 X391
Other PMIC0-bus 0x21 X380 - X389 Other

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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 68

9.20 Architecture - UHD50

Marvell BG2-Q Architecture UHD50

17511n 2x2
2x DDR3 2x DDR3 DDR3 2x DDR3
Wifi 1600 1600 eMMC 1600 1600
4Gb 4Gb 4GB 1Gb 2Gb
32 32 16 32

USB2.0
FPGA
USB
U SB
SB USB2.0 I2S LX75
W i fi
2 Wifi ETH =Anaconda+
AL-SPI
USB
USB
U SB
USB3.0 FRC Master
HUB
W i fi
2 Wifi 3D-LR/QFHD
HD
D FHD: 3D-LR
USB Noise reduction NT72314
2 Wifi Local contrast UHD 50Hz 3D-Goggle
3
SplashscreenOn
eenOn JPEG: BL-PWM (8
B
UHD Stitching
BG2-Q UHD:
Gfx blending + Boa
D
Disp-Ctr (4
3D-LR
SPI BL-Boost
B
Quad Core A9 functionality
DVB- 4x16bit DDR3
S-Tuner T/C/S/ CiMax
T2/C2/S2 TS-out AL-SPI AL-SPI

DVB- TS-in
Hybrid
tuner T/C/S/
T2/C2/S2 I2S Audio
TS-in AMP

GLUE
GLUE LR
IF SPDIF
SPDIF
TTL I2S

To HDMI ARC
SPDIF ADV7619

GLUE
GLUE

Cypress C0
GLUE
GLUE
GLUE
UE
UE
UE
Analog GLUE SiI9573 SiI9679
LU
LU
GLU
GLUE
GLUE
demod. =Rogue
G
G
YPbPr
GLUE
Audio L/R

RGB
GLUE GLUE
GLUE CVBS GLUE
GLUE

19570_163_140721.eps
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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 69

9.21 Connections - UHD60 Rogue

400kHz C&C Architecture

DDR3-1866

DDR3-1866

DDR3-1866

DDR3-1866
HDMI EDID0
2014 Marvell BG2-Q

4GByte
eMMC
0xA0

4Gbit

4Gbit

4Gbit

4Gbit
SYSTEM-RESETn eMMC-RESETn
400kHz
UHD60 Rogue .1

I2C 4:1 MUX


HDMI EDID1
0xA0

X340
DVBS2-Tuner Analog Demod 400kHz Serial Flash
0xC6 0x84 128Mbit=16MB
HDMI EDID2
0xA0 x16 x16 x16 x16 x8
Hybrid-Tuner 400kHz I²C-TUNER DVB-T/C/S/T2/C2/S2 400kHz
DDR3 Controller 2x 32 bits eMMC
0xC0 Channel Decoder HDMI EDID3
0xC8 V4.41

16Mbit=2MB
0xA0 0xE4 X307

Serial Flash

(UHD60))
DDR3-1600

DDR3-1600
X020-X025-X026
DT-Hybrid-Tuner

1Gbit

1Gbit
SoC-SPI-SerialFlash
DVBS LNB (ST & DT)
0xC0 0x10
Reset BE-RESETn
400kHz X322 Generator

SPI-AMBI
DT-DVBS2-Tuner I²C-DT-TUNER DT DVB-T/C/S/T2/C2/S2 I²C-FE 0
0xC6 Channel Decoder

X342
0xCE
400kHz X320
I²C-TW1 x16 x16 SPI
Class D Amplifier TW1 SPI-Switch
0xD8 SoC-SPI-AMBI

SPI
100kHz (in FPGA) DDR3 2x16 SPI
X335 400kHz
NT-SPI-AMBI

SPI
EDID EEPROM HDCP 2.2
0xA0 I²C-HDCP 0x70 BE-RESETn FRC-M
SPI 100kHz
X346

X323
400kHz NT72314

I²C-M
400kHz

I²C-S
I²C-BE
Serial Flash TW0
1Mbit=128kByte 400kHz UART1 UART2 0x34
HDMI2TTL 0x98 SYSTEM-RESETn
ADV7619 Table X314
X020-X025-X026

X020-X025-X026
X321
100kHz X313 X312
I²C-SRF 1
Light Sensor
0x52 100kHz

64Mbit = 8MB
DDR3-1600

Serial Flash
100kHz

1Gbit
Set Temp
X071

X071

Sensor 0x98

I2C 4:1 MUX


SYSTEM-RESETn

X344
Quad Core A9
x16 SPI
X328

BG2-Q
I²C-CYPRESS 2 DDR3 1x16 SPI
CYPRESS-RESETn
Marvell Cypress
0x40-0x42 400kHz
X327 BE-RESETn
I²C-HDMI 3
PQ-FPGA
SSB Temp-Sensor
0x98
400kHz 0xE2 Durango
I²C-BE

I²C
HDMI-MUX-RESETn
HDMI-MUX (6:2 or 4:1)
Table 0x84 400kHz

X029 5pins 5V Bypass


X332
Skype opon
USB X324

USB2 USB1 USB0


I2C 2:1 MUX

PMIC I²C-PMIC1 1 SYSTEM-RESETn


X030 8pins 5V
I²C-BL-Bus

X0..

X0..
Vcore & 3V3 0x32 400kHz 1
Wi-Fi BackLight

USB
X330 X329 USB
100kHz

PCA9543
X031 6pins 3V3-WOLAN

I2C MPX
PMIC I²C-PMIC0 0 I²C-PMIC
SM-TW2 USB USB

X051 -1G55

X051 -1G55
Vcpu & 1V8 0x32 400kHz 400kHz X280 USB-type A X325
0xE0 USB 0 I²C-DISP-Bus Display
Legend X281 USB-type A 0xE0
SYSTEM-RESETn 100kHz
USB-HUB USB
Delta with previous X282 USB-type A
X311

BE-RESETn
Removed MCU USB
UART-RF4CE
X027

CC2533
X027

UART1 (System Manager)


Locaon Opons RF4CE CIMax SYSTEM-RESETn
115kBaud SPI-CIMAX
SPI
RF4CE-RESETn

I²C Subject to diversity


X310 X341
UART Customer Connectors
Ethernet

X303 Mini-Jack UART-SERVICE Ethernet


X206

UART0 X296 RJ45 Connectors - Applicationata


RESET Producon Connectors
TI-RF4CE-DEBUG
I²C SW Bus ID
USB-Eth Debug Connectors Position Application
HW-Bus SW-Bus ID
Power RESET X000 - X099 Internal connectors
Name Hex RF4CE-RESETn
I2C X100 - X199 Internal connectors (spare)
Flash eMMC-RESETn
TW0 = BE-bus 0x0F X200 - X299 User connectors
RESET

UART
RESET

DISP-bus 0x00 SYSTEM-RESETn X300 - X399 Debug connectors


DDR SPI
BL-Bus 0x01 X300 - X309 (E)JTAG (incl. µP-debug-IF)
Flash SOC-RESET-INn Reset X310 - X319 UART
Level Shi TW1-bus 0x1F Reset MCU-RESET-INn
(E)JTAG FE-bus 0x10 Generator X320 - X329 I²C
Generator MCU-RESET-OUTn
GPIO USB&Ethernet SRF-bus 0x11 X330 - X339 I²C (spare)
JTAG JTAG
Power Cypress-bus 0x12 X340 - X349 SPI
Buon Buon X350 - X359 CTRL
ADC HDMI-bus 0x13
GPIO X301 X300 X360 - X369 UART (spare)
TW2 = PMIC 0x2F JTAG-BG2Q JTAG-MCU
8bits I2C address ADC PMIC1-bus 0x20 X392 X391 X370 - X379 USB
Other PMIC0-bus 0x21 X380 - X389 Other

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2014-Oct-22 back to
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Block Diagrams QV14.1E LA 9. EN 70

9.22 Power supply lines - Connector and Front end

Connector from PSU

X090
+3V5-STANDBY +12V-AL

SIP32429DN-GE4 or
AOZ1360DIL U022U
U003U U001U U004U
+3V5-STANDBY
LDO LDO + WOLAN-ENABLE Over
RT9193- switch current (2 sides AL)
33GB RT9187GSP protection

+12V +3V3-STANDBY +3V3-LAN

AMBI-POWER

+12V-AL

IR sensor,
Ambilight
Keyboard Wifi X031
To RF4CE X026
X026 connector
connector
connector

RT7297CHZSP for FHD


+12V

U017U U018U U027U U019U U001F


DC/DC DC/DC DC/DC DC/DC DC/DC i2C
DETECT12V RT8288A ENABLE+3V3 RT8288A TPS5452 ENABLE+1V5-BE RT8288A ENABLE+5V-USB LNBH26
ZSP ZSP 7DDA ZSP LSPQR

+3V5-STANDBY
+5V-FE +3V3 +1V5-BE +5V-USB
+V-LNB-DT +V-LNB

+VPMIC +2V5-TUNER
U007F
EN1 +5V-FE EN2 +5V-FE EN1 +5V-FE LDO
RT9187GS TPS54427 for UHD 50Hz & FHD LNB
EN2 +VPMIC U007U U008U U005F USB 1, 2, 3
U011U P
DC/DC LDO
PMIC PMIC +3V3
TPS5431 AZ1117CH
88PG867RB0 88PG867SB0 Tuner
9RTE DDR-ENABLE -3.3G1 +3V3-CIMAX
+3V3-MRV U011F
+1V5-MRV +1V8-STANDBY
ST
TAN +VCPU VCORE Skype
+3V3-DVB LDO
AZ1117CH
-1.8G1
USB Hub
+1V8-TUNER
Marvell DDR Marvell DG2-Q Marvell (SM)
+3V3-STANDBY +3V3-TUNER
U006F +1V2-CIMAX
CAM 1&2 (CI)
+1V8-AVDD LDO
RT9025 CiMAX
+VTT EMMC
(Marvell) +5V-FE
U013U Chanel
decoder
LDO +1V2-DVB 3D emitter
T/T2/C/C2/S
TPS51200 U021C
/S2
DRCR Cypress
+1V0-C LDO
RT9025 UHD
U009U +1V8-MRV
+3V3-MRV
Switch +5V-FE
AO3414 U004H +1V3-HDMI
HDMI MUX
HDCP2,2 UHD:
Rogue LDO SIL9573
+5V-FE UHD RT9025 FHD:
SII9287B
U003B +5V-FE
+1V8
UHD ADV7619 LDO
Ethernet (HDMI) RT9025 U001H
+3V3-HDMI
Switch
+5V-FE AO3414

+5V-FE

BE

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 71

10. Circuit Diagrams and PWB Layouts


10.1 715RLPCB0000000055 SSB
10-1-1 B, DVB DUAL TUNER

DVB DUAL TUNER


B B
C017F 10pF
L007F
+3V3-DVB SDA-TUNER R002F 47 50V
30H C018F 10pF
L008F
SCL-TUNER R003F 47 50V
30H L011F
IF-N-DVBT2 C097F 100nF
16V 1KH
L012F

22uF 16V
C029F
L006F

IF-P-DVBT2 C100F 100nF


30H

16V 1KH

10pF

10pF
50V

50V
C019F

C020F
+3V3-TUNER
I011F
100nF
10pF

R004F
IF-AGC-DVBT2 F039F
50V

16V
C016F

C012F

22K
1K

10pF
50V
R015F

C021F
F036F
F037F
F035F

F023F F038F
+2V5-TUNER
RES
U007F
10uF
C049F

R007F

22K
RT9187GSP
1%
R063F

47K

F022F 1 3 F040F
+3V3 VIN1 VOUT1 I007F
DVBS-IP C038F 100nF I2C
RES

2 4 16V X292
VIN2 VOUT2 F034F
16V 10nF

SUT-PEX31ZX address
10uF

C050F

NC
7 F041F S012F 1
ANT_5V/GND =
DVBS-QP C039F 100nF 50m 2
C043F

8
EN BP|ADJ
5 I058F 16V
+3V3-TUNER
3
VCC
SDA
0XC0
4
RES

SCL
1%

GND GND_HS 5
F011F IF_N
DVBS-AGC 6
SUT-PE231ZN
470K

IF_P
R062F

22K
R008F

7
SUT-PE531Z
6

AGC_T
8
F024F IOUT
COMMON

10pF

10pF

10pF
9

50V

50V

50V
QOUT
10
AGC_S
11

C051F

C052F

C054F
LNB_IN
12
RES_1
13
RES_2
14
+1V8-TUNER VCC_2
F043F
U011F
15
AZ1117CH-1.8G1 SDA_2
16
SCL_2
C033F 1nF F042F 17
IF_N_2
2 18
L023F I059F OUT_1 F025F 50V IF_P_2
+3V3 3 4
+1V8-TUNER
X002F TUNER-LNB TUNER-LNB 19
IN OUT_2 +V-LNB AGC_T_2
20 SUT-PE531Z only
30H +2V5-TUNER 2.5V

32V
GND
22uF

21
IOUT_2
22uF 16V
C055F

C048F 10pF 22
6.3V

L013F QOUT_2

D001F
DT-SDA-TUNER R023F 47 50V 23
C042F

AGC_S_2
LNBTVS6-221S

30H C053F 10pF 24


L020F F044F LNB_IN_2
DT-SCL-TUNER R024F 47 50V
30H

MT_17
MT_16
MT_15
MT_14
MT_13
MT_12
MT_11
MT_10
F045F

MT_9
MT_8
MT_7
MT_6
MT_5
MT_4
MT_3
MT_2
MT_1
L024F
DT-IF-N-DVBT2

10pF

10pF

10pF
50V

50V

50V
1KH F046F
L025F
DT-IF-P-DVBT2

25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
C103F

C104F

C128F
1KH

10pF

10pF
50V

50V
C082F

C101F
F047F
R030F
DT-IF-AGC-DVBT2
22K

1K

10pF
50V
R031F

C110F F048F
DT-DVBS-IP C036F 100nF
16V

F049F
DT-DVBS-QP C045F 100nF
16V

F029F
DT-DVBS-AGC
10pF

10pF

10pF
50V

50V

50V
C120F

C121F

C122F

C123F 1nF
F051F
50V
DT-TUNER-LNB DT-TUNER-LNB
+V-LNB-DT X008F
32V
D008F
LNBTVS6-221S

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 72

10-1-2 B, ANALOG DEMOD

ANALOG DEMOD
B B

L021F I003F
+3V3-DVB VDD-3V3
30H

1uF

6.3V
C125F
VDD-3V3 VDDA-1V2-1FBO VDD-3V3 VDDA-1V2-1FBO VDDD-1V2-1FB VDDA-1V2-1FBO

2.2

2.2

2.2
10

10

10
L026F I002F

5%

5%

5%

5%

5%

5%
+1V2-DVB VDDA-1V2-1FBO
30H

R038F

R057F

R039F

R058F

R059F

R040F

1uF

6.3V
I008F I009F I012F I013F I014F I016F

C124F
470nF

470nF

470nF

470nF

470nF

470nF
6.3V

6.3V

6.3V

6.3V

6.3V

6.3V
C112F

C113F

C115F

C114F

C116F

C117F
L022F I001F
+1V2-DVB VDDD-1V2-1FB
30H

1uF

6.3V
XTAL C105F 100pF

C119F
50V X006F
VDD-3V3 1 3

15
18

34

4
25

7
RES S029F RES S030F
18pF

18pF U004F
2
4

TDA8296HN
50V

50V
10K

10K

RES L030F L031F RES RES L028F L029F RES

VDDA_DAC1_3V3
VDDA_DAC2_3V3

VDDA_ADC_1V2

VDDDR_3V3

VDDD1_1V2
VDDD2_1V2

VDDA_PLL_1V2
C099F

C102F

8 3.3uH 1.5uH 680nH 680nH

330pF
XIN

680pF

220pF

100pF

100pF
47pF
9
R041F

R042F

RES 50V

RES 50V

50V

50V

50V

50V
XOUT
RES

RES

C011F

C035F

C040F

C133F

C135F

C134F
SYSTEM-RESETn 21

RES
RES

RES
RES
RST

SDA-FE R043F 100 29


SDA
SCL-FE R044F 100 28
SCL I021F F003F
S023F I017F 19
SADDR0 V_IOUTP
14 S025F AV-TUNER-CVBS
S024F 20
SADDR1 I022F
I018F 13
V_IOUTN I025F
33
R050F I019F GPIO0/VSYNC
4.7K 32
VDD-3V3 GPIO1/SCL_O F004F
31
GPIO2/SDA_O S_IOUTP
17 S027F AV-TUNER-SIF
4.7K
F002F R049F I020F
IF-AGC-DVBT2 37 16 I026F
IF_AGC S_IOUTN
10K
R056F I024F
100nF

24 11
1nF

TMS RSET
30
16V

50V

TRST
27
C095F

C098F

100

100
TCK

1K

75

75

75

75
470pF

100nF
23
TDI

R053F

R048F

R047F

R016F

R045F
R061F

R060F
22

50V

16V
TDO

C009F

C096F
R054F
IF-P-DVBT2 100 C107F 100nF 1
IF_POS
2
680

16V IF_NEG
12pF

39
50V
RES

NC
R051F

C106F

6
R055F IC1
VSSA_DAC

VSSA_ADC

VSSA_PLL

IF-N-DVBT2 100 C108F 100nF 36


IC2
VSSDR

VSSD2
VSSD1

38
16V IC3
50V 22pF

HS
22pF
C109F

50V

12

40

35

26

10

41
C111F

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 73

10-1-3 B, CHANNEL DECODER 1

CHANNEL DECODER 1
B B

L001F I029F
+1V2-DVB
30H

100nF

100nF

100nF

100nF
6,3V

6,3V

6,3V
22uF

22uF

22uF

16V

16V
16V
16V
C083F

C081F

C080F

C003F

C004F
C001F

C002F
RES

RES
L002F I027F +3V3-DEMOD1 +3V3-ANA1
+3V3-DVB +3V3-DEMOD1

100nF

100nF

100nF
16V

16V
30H
6,3V
22uF

16V
C005F

C006F

C007F
C084F

X004F
U002F

9
22

7
20
28
48

36
1 3

C022F 100nF

10pF

10pF

VDD_VCORE1
VDD_VCORE2
VDD_VCORE3
VDD_VCORE4

VDD_VANA
VDD_VIO1
VDD_VIO2
2
4
L003F I028F
33

50V

50V
+3V3-DVB +3V3-ANA1 XTAL_I|CLK_IN 16V
1 R005F 10K F008F IF-AGC-DVBT2

C057F

C056F
30H MP_A
6,3V
22uF

10nF

2
MP_B
29
16V

MP_C
32 30 R006F 10K DVBS-AGC
C085F

C064F

XTAL_O MP_D
2.2nF
DVBS-IP 37
S_ADC_IP DISEQC_CMD
4 C093F
C010F 100nF 38
S_ADC_IN 50V
16V 5
DISEQC_IN
DVBS-QP 39
S_ADC_QP
C131F 10pF C013F 100nF 40
S_ADC_QN DISEQC_OUT
6 S004F F22-DISEQC-TX1
50V
L016F RES C058F 16V 50m
IF-P-DVBT2 R052F 4,7uH 10pF 50V C014F 100nF 41 I2C 10 R021F 47 SCL-FE
TC_ADC_P SCL_HOST
IF-N-DVBT2 R067F 47 C015F 100nF 16V 42
TC_ADC_N SDA_HOST
11 R022F 47 SDA-FE
47 C059F 16V address
C129F 10pF L017F 4,7uH RES 10pF 50V 43
RSSI_ADC
= TS_VAL
12 R037F 47 DB005F TS-CD1-VALID
50V
0XC8
R001F
U005F 10K 31
RESETB TS_SYNC
13 R066F 47 DB004F TS-CD1-SYNC
AZ1117CH-3.3G1 +3V3-DEMOD1
RES
SYSTEM-RESETn C008F 100nF 34
ADDR TS_CLK
14 R025F 47 DB003F TS-CD1-CLK
2 16V
L027F I004F OUT_1 F001F
3 4
+3V3-DVB XTAL 44 26 DB002F RES C091F 6,8pF
+5V-FE IN OUT_2 CLK_IN_OUT TS_ERR|GPIO_1
30H 50V R026F
GND R013F 4,7K R019F 47 47 TS-CD1-DATA0
22uF

46 15
+3V3-DEMOD1 SCL_MAST TS_DATA0|TS_SER
22uF 16V
C130F

R014F 4,7K 47 45
6.3V

SDA_MAST
R020F 16
C118F

TS_DATA[1]
17
TS_DATA2
DB001F S001F 3 18
GPIO_0|JTAG_TMS TS_DATA3
SDA-TUNER 50m 8
GND|JTAG_TCLK TS_DATA4
19
21 23
GND|JTAG_TDI TS_DATA5
SCL-TUNER 27
GND|JTAG_TDO TS_DATA6
24
47 25
GND|JTAG_TRSTB TS_DATA7
GND GND_HS

35

49
4

U006F
RT9025
VDD
F007F
3 6
+1V5-BE VIN VOUT +1V2-DVB
R046F
10uF

22uF

2 7
+5V-FE EN ADJ
6.3V

6.3V

1 I005F
1
C127F

C132F
1uF

PGOOD
6.3V

5
C126F

GND_HS

NC
GND
8

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 74

10-1-4 B, SINGLE/ DUAL LNB-SUPPLY

SINGLE/ DUAL LNB-SUPPLY


B B

+12V

100nF
L010F
L032F

30H
30H

16V
C023F
RES
I030F
10uF
16V
10uF
16V

10uF

10uF
10uF 35V

100nF
RES C070F

16V

16V
C069F

C068F
C065F
C066F

16V
C024F
+V-LNB
L015F

U001F

17
L014F
10uH

10uH

LNBH26LSPQR
D007F
RS1D

B230LA-M3
VCC
D004F F005F
21 20
I032F I031F VUP-A VOUT-A +V-LNB
3
LX-A DSQIN-A
22 F22-DISEQC-TX1
1uF

I035F
47uF 35V

47uF 35V

R012F
C074F

C073F

15K 9
25V

ISEL F006F
12
C076F

C077F 470nF
I036F VOUT-B +V-LNB-DT
16
BYP I037F
16V DSQIN-B
24 F22-DISEQC-TX2
R027F
SDA-FE 47 8
SDA

50m
R028F

S017F
SCL-FE 47 7
SCL ADDR
6

RES

220nF

220nF
5

B230LA-M3

B230LA-M3
I033F LX-B

D005F

D003F
S014F
50m

50V

50V
D002F
11

C079F

C078F
VUP-B
D006F I034F B230LA-M3

RES
10
+V-LNB-DT NC
RS1D
GND_HS
1uF
47uF 35V

47uF 35V

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
P-GND
C072F

C071F

S015F

S016F
25V

50m

50m
C075F

RES

RES

13
14
15
18
19
23

25
4

1
2

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 75

10-1-5 B, CHANNEL DECODER 2

CHANNEL DECODER 2
B B

L004F I038F
+1V2-DVB
30H

100nF

100nF

100nF

100nF
6,3V

6,3V

6,3V
22uF

22uF

22uF

16V

16V
16V
16V
C088F

C087F

C086F

C027F

C028F
C025F

C026F
RES

RES
+3V3-DEMOD2 +3V3-ANA2

100nF

100nF

100nF
16V

16V

16V
L005F I039F

C030F

C031F

C032F
+3V3-DVB +3V3-DEMOD2
30H
6,3V
22uF

X005F
U003F

9
22

7
20
28
48

36
1 3
C089F

C047F 100nF

10pF

10pF

VDD_VCORE1
VDD_VCORE2
VDD_VCORE3
VDD_VCORE4

VDD_VANA
VDD_VIO1
VDD_VIO2
2
4
33

50V

50V
XTAL_I|CLK_IN 16V
1 R010F 10K F009F DT-IF-AGC-DVBT2

C061F

C060F
MP_A
2
L009F I040F MP_B
29
+3V3-DVB +3V3-ANA2 MP_C
30H
32
XTAL_O MP_D
30 R011F 10K DT-DVBS-AGC
6,3V
22uF

10nF

2.2nF
DT-DVBS-IP 37 4 C094F
16V

S_ADC_IP DISEQC_CMD
C037F 100nF 38
C090F

C067F

S_ADC_IN 50V
16V 5
DISEQC_IN
DT-DVBS-QP 39
S_ADC_QP I041F
C136F L018F RES C041F 100nF 40
S_ADC_QN DISEQC_OUT
6 S021F F22-DISEQC-TX2
10pF 50V 4,7uH C062F 16V 50m
R068F
DT-IF-P-DVBT2 10pF 50V C044F 100nF 41
TC_ADC_P
I2C SCL_HOST
10 R033F 47 SCL-FE
DT-IF-N-DVBT2 47 C046F 100nF 16V 42
TC_ADC_N SDA_HOST
11 R034F 47 SDA-FE
R069F
47 C063F 16V address
C137F 10pF 50V 43
RSSI_ADC
= TS_VAL
12 R064F 47 DB010F TS-CD2-VALID
10pF 50V L019F 4,7uH RES R009F
0XCE
RES 31
RESETB TS_SYNC
13 R065F 47 DB009F TS-CD2-SYNC
+3V3-DEMOD2
10K
SYSTEM-RESETn C034F 100nF 34
ADDR TS_CLK
14 R035F 47 DB008F TS-CD2-CLK
16V
+3V3-DEMOD2
XTAL 44
CLK_IN_OUT TS_ERR|GPIO_1
26 DB007F RES C092F 6,8pF

50V R036F
+3V3-DEMOD2
R017F 4,7K R029F 47 46
SCL_MAST TS_DATA0|TS_SER
15 47 TS-CD2-DATA0
R018F 4,7K 47 45
SDA_MAST
R032F 16
TS_DATA[1]
17
TS_DATA2
DB006F S018F 3 18
GPIO_0|JTAG_TMS TS_DATA3
DT-SDA-TUNER 50m 8
GND|JTAG_TCLK TS_DATA4
19
21 23
GND|JTAG_TDI TS_DATA5
DT-SCL-TUNER 27
GND|JTAG_TDO TS_DATA6
24
47 25
GND|JTAG_TRSTB TS_DATA7
GND GND_HS

35

49
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 76

10-1-6 B, POWER CONNECTOR

POWER CONNECTOR
B B

+5V-FE +3V3-MRV
+3V5-STANDBY
BE-ENABLE

10uF

22K

22K

22K
330uF 6.3V
C020U
4 S001U 5 RES

C007U

R114U

RES
R115U

R116U
2 S001U 7 RES

RES
F001U
+12V-AL I045U
3 S001U 6 RES ENABLE+1V5-BE

100nF
1uF
1 S001U 8 RES 6

RES

RES
C011U

C001U
2 U025U
U003U BC847BS(COL)
F002U I044U
RT9193
F004U
F003U 1 5 3 1
X090
VIN VOUT +3V3-STANDBY
X090 GND-AL GND-AL I001U I041U
PIN 1 GND-AL 1 3
INH BYP
4 +3V3-STANDBY +1V2
R101U 10K 5 U025U
GND-AL BC847BS(COL)
2

22K
PIN 2 +12V-AL F009U F010U GND

22nF
3

1uF

1uF

1uF
PIN 3 +12V +12V

1uF
4 4

6.3V

6.3V

6.3V
PIN 4 +12V F013U
5 2

C013U

C019U

C014U

C173U
100nF

10K
PIN 5 +12V-Audio +12V-AUDIO

2
6

C012U

C002U

R113U
RES
PIN 6 +12V-Audio F026U

RES
7 PDTA114EU
PIN 7 GND
8 U016U 1
PIN 8 GND
9 F014U F012U RES

R066U
RES
PIN 9 GND-AUDIO F011U
10 3
PIN 10 GND-AUDIO I050U
PIN 11 POWER-ON 11 F015U R034U 100 I047U PWR-ON S003U
PIN 12 PWM-2 12 F016U R053U 100 BL-DIM2 50m
13 F017U R054U 100 BL-DIM1

10K
PIN 13 PWM-1
PIN 14 BL-ON-OFF 14 F018U R055U 100 BL-ON
15

RES
PIN 15 +3V5-STBY
PIN 16 BL-I-CTRL 16 F019U R056U 100 BL-I-CTRL
17

R063U
PIN 17 +12V +12V
PIN 18 +12V 18
I048U
+5V-FE +3V3-MRV
PIN 19 GND-AL 19 I049U R064U 100K POWER-OK I024U
GND-AL BE-ENABLE
PIN 20 +12V-AL 20
21 R065U 100K

22K

22K

22K
PIN 21 GND
PIN 22 GND 22 STANDBYn

R110U
23 F020U R057U 100 BL-DIM3

RES
PIN 23 PWM-3

R111U
PIN 24 PWM-4 24 F021U R058U 100 BL-DIM4
25 F022U R059U 100 BL-DIM5

R109U
PIN 25 PWM-5 I040U
PIN 26 PWM-6 26 F023U R060U 100 BL-DIM6 ENABLE+1V2-FPGA
27 F024U R061U 100 BL-DIM7 +5V-FE

22K
PIN 27 PWM-7
28 F025U R062U 100 BL-DIM8 6
PIN 28 PWM-8
29 30

RES
R112U
2 U024U

22K
TYPE BC847BS(COL)
I039U

RES
3 1
RES

R018U
I038U
100pF

100pF

100pF

100pF

100pF

100pF

100pF

100pF

100pF

100pF

100pF

R042U 100K 5 U024U +5V-USB


+5V-USB BC847BS(COL)
50V

50V

50V

50V

50V

50V

50V

50V

50V

50V

50V

22K
R026U 2.2K I042U
C085U

C086U

C087U

C088U

C089U

C090U

C091U

C092U

C093U

C094U

C095U

1uF
+12V 2 U006U 4

6.3V
BC857BW(COL)

C172U
10K

R108U
1.5K

RES
1 +3V3-STANDBY

220K
RES
3

R122U

RES
R033U
I043U

R013U

22K
+5V-FE

R012U
I094U

22K
DETECT12V F035U

RES
POWER SEQUENCER

R106U
1MEG
100K
I023U
DDR-OK

RES
U012U 2

X002U
BC857BW(COL) +5V-FE +3V3-MRV
R021U

R019U
1 ENABLE+5V-USB
I022U
RES

100K
22K

22K
3

R105U

R107U
R104U
I037U
ENABLE+3V3

2 U023U
BC847BS(COL)
I036U
R118U 47K
+3V3-MRV 3 1

R100U 10K 5 U023U


+1V5-BE BC847BS(COL)
I035U

22K
RES

1uF
4

6.3V
C171U

R102U
RES
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 77

10-1-7 B, WIFI SUPPLY

WIFI SUPPLY
B B
4 S002U 5 RES

3 S002U 6 RES

2 S002U 7 RES
F027U
1 S002U 8 RES
+3V3-LAN

10uF
U001U
RT9187GSP

C009U

1MEG
68K
1 3
+3V5-STANDBY VIN1 VOUT1

1%
10uF
2 4
VIN2 VOUT2

R008U

R004U
RES
7

C008U
NC

8 5 I002U
EN BP|ADJ

GND GND_HS

470K
22K
1%
6

9
R103U 10K

R009U

R005U
+3V3 F054U
RES

WOLAN-ENABLE
+3V5-STANDBY

R002U I005U
C017U 47nF 22K 1 U002U
BC847BW(COL)
I003U

22K
R003U

RES
120K
1%
I004U

10nF
RES
R010U

RES
C010U
R007U I006U
47K C003U 100nF
100K

5% 16V

X001U
5%
R006U

+3V3-LAN
RES X031
F028U C004U 100nF 1
USB-WIFI-DM 2
USB-WIFI-DP F029U 3
4
WOLAN-IRQn F030U 5
6
8 7
F031U

R001U 10K
+3V3-LAN 5 2014-02-21

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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 78

10-1-8 B, AMBILIGHT PROTECTION

AMBILIGHT PROTECTION
B B

* X011U !
T 2A 63V

U004U
SIP32429DN-GE4
** 2-SIDE AMBILIGHT 3- or 4- SIDE AMBILIGHT

* **
F032U
1 9
+12V-AL VIN1 VOUT1 AMBI-POWER
2 10
VIN2 VOUT2
common :
1uF

1uF

C018U
I009U 4

B230LA-M3
EN

RES
D003U
R050U, C006U, C016U and C018U

22uF
C016U

C015U
I008U 5 8
ILIM FLG
and
X011U, C016U AND C018U
I007U 3 7

GND_HS

RES
SS PG F033U

GND
GND-AL
R050U 10K U004U + U022U +
+3V3
1.8K

R011U + or R099U +
GND-AL GND-AL GND-AL
**
100nF

100nF

C005U C164U

11
**
6
**
C006U

C005U

**
R011U

GND-AL

GND-AL GND-AL GND-AL

U022U
AOZ1360DIL
**
1 9
+12V-AL IN_1 OUT_1 AMBI-POWER
2 10
IN_2 OUT_2
11
OUT_PAD
6
EN I057U
7
SET
I032U
GND_PAD

5
SS
NC_1
NC_2

47K
GND
47nF

16V

12
C164U

3
8
**

**R099U

GND-AL GND-AL GND-AL

C072U 100nF

16V
RES

GND-AL

5 2014-02-21

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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 79

10-1-9 B, FPGA SUPPLY

FPGA SUPPLY
B B

RES
RES L020U
L019U
30H
30H

L004U
L011U +12V
+12V 30H

100nF
R047U 22

10uF

10uF

10uF
30H
100nF

R120U 22 4 5
10uF

10uF

10uF

16V
L010U F005U
4 5 R046U 12K C042U 1nF C041U 1nF R047U 22

C148U

C064U

C063U

C057U
16V

L003U F037U +1V2 3 6


+1V2
R121U 22K C169U 1nF C168U 1nF R120U 22 +1V5-BE RES RES 1.5uH
C180U

C179U

C178U

C165U

RES
+1V5-BE 1% I020U
RES RES 3 6 1.5uH R047U 22
RES

1% I054U I021U
R120U 22 C071U 2 7

22uF

22uF

22uF
I055U

100uF 16V
C181U 2 7

C069U
RES 100pF I078U R047U 22

22uF

22uF

22uF

6.3V
100uF 16V
1 8

C182U
100pF I077U R120U 22

220K
RES

C048U

C049U

C068U
6.3V

22K
1 8 RES
470K

C175U

C176U

C177U

RES

RES
22K

R036U
RES I046U

RES

RES
R117U

R119U

I056U

1%
R045U
U010U

8
1%

U027U
8

SN1106041DDA
RES

VIN
TPS54427DDA
I019U
VIN

2 7 C058U 100nF
I053U VFB VBST
2 7 C166U 100nF
VFB VBST
I079U 4 6
SS SW
I076U 4 6
SS SW I018U
I052U
ENABLE+1V2-FPGA 1
EN VREG5
3 C056U 1uF
ENABLE+1V5-BE 1
EN VREG5
3 C174U 1uF
16V

10nF

GND_HS
1nF
16V
10nF

GND_HS

50V

16V

GND
1nF

C040U

C149U
50V

16V

GND
C167U

C170U
RES

9
5

5 2014-02-21

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14-05-23

2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 80

10-1-10 B, DDR SUPPLY

DDR SUPPLY
B B

U011U
L002U F006U
TPS54319RTE I080U
+V-PMIC 1.5uH
+1V5-MRV

18K
100nF

100nF
10uF

10uF

22uF

22uF
1 10
VIN_1 PH_1

1%
2 11

6.3V

6.3V

6.3V

6.3V
16V

16V
VIN_2 PH_2
16 12

C043U

C044U

C038U

C039U

C051U

C052U
VIN_3 PH_3

R039U
I081U
15 13
EN BOOT
I082U
I085U 6
VSENSE PWRGD
14 DDR-OK

22K
7

POWERPAD
COMP

1%
R035U
DDR-ENABLE I086U I083U 8
RT/CLK

4.7K

GND_1
GND_2
9

AGND
SS/TR

3.3nF

220K
10nF

R037U
16V

50V
I084U

17
C045U

C047U

3
4
5
3.3nF
RES

10nF
R038U
50V
C050U

16V
C046U

U013U
TPS51200DRC

F041U
2 3
+1V5-MRV VLDO_IN VO +VTT
I051U
R051U 10K 1 5
+1V5-MRV REFIN VOSNS
F042U
10 6
10K

+3V3-MRV VIN REFOUT VTT-REF


1nF

7 9
GND_HS
50V

+3V3-MRV EN PGOOD
PGND
C078U

GND

100nF

10uF

10uF

10uF
R052U

6,3V

6,3V

6,3V
16V
11

C079U

C075U

C076U

C077U
8

4
1uF

16V
C096U
10uF

10uF
6,3V

6,3V
C073U

C074U

5 2014-02-21

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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 81

10-1-11 B, MARVELL SUPPLY

MARVELL SUPPLY
B B
D001U I058U
+V-PMIC
+3V5-STANDBY
B230LA-M3
D002U
+5V-FE
B230LA-M3

F044U
+VCPU
VCC-PMIC

4.7K
VCC-PMIC

22uF

22uF

22uF
I064U
R022U 10

6.3V

6.3V

6.3V
+V-PMIC VCC-PMIC

C113U

C114U

C115U

100nF
U007U

4.7uF
R078U

4.7K

4.7K
RES
L013U I065U
88PG867RB0

6.3V

16V
1.2uH 3 21

C160U

C021U
SW1_1 SVIN
6
SW1_2

S004U
20

R079U

R080U
50m
RES

RES

RES
I066U SGND
10
F043U FB1
SENSE-VCPU S005U
I067U SCL
16 R030U 100 SCL-PMIC0
50m 1
PGND1_1 SDA
17 R031U SDA-PMIC0
2 9
PGND1_2 EN1 100

C031U

C032U

C033U
I025U R023U 10K

22pF

22pF
7 23
PGND1_3 EN2 +V-PMIC
8

6.3V

6.3V

6.3V

50V

50V
PGND1_4
24 22 I026U R014U 100K

10uF

C099U

C104U
10uF

10uF

10K
PGND1_5 SLEEP +V-PMIC
4
+V-PMIC PVIN1_1
C022U 1uF
5
PVIN1_2

R024U
6.3V

C034U

C152U

C153U
+V-PMIC HS
25 +5V-FE
15 I027U

6.3V

6.3V

6.3V
PVIN2
10uF

220nF

220nF

C035U

C036U

C154U
+12V

100K
12

10K
PGND2_1
13

6.3V

6.3V

6.3V

1uF
+V-PMIC PGND2_2

R040U
10uF

10uF

220nF

6.3V
11 18

C055U

47K
FB2 NC_1
19

R015U
NC_2

R043U
14
SW2
F040U L006U I071U
+1V8-STANDBY
1.5uH
I068U
I2C address = 0x32 3
C116U

C155U

C037U
U005U 5 I030U
6.3V

6.3V

6.3V
BC847BS(COL)
22uF

220nF

10uF
3
U009U 4 6
1 AO3414
2 U005U 2 I031U R016U 100K
F007U
BC847BS(COL) +5V-FE

22K
+1V8-MRV

1uF
R027U
1

6.3V
C061U
100nF

RES
16V
C084U

F008U
+VCORE
4.7K

VCD-PMIC VCD-PMIC
22uF

22uF

22uF

I072U
R025U 10
6.3V

6.3V

6.3V

+5V-FE VCD-PMIC
C097U

C098U

C100U

L015U

100nF
U008U

4.7uF
R048U

4.7K

4.7K
RES

1.2uH 88PG867SB0

6.3V

16V
3 21

C161U

C023U
I073U SW1_1 SVIN
6
SW1_2
S006U

20

R088U

R089U
50m
RES

RES

RES
SGND
F038U I074U
10
FB1
RES
SENSE-VCORE S007U
SCL
16 R032U 100 SCL-BE
50m 1
PGND1_1 SDA
17 R044U I062U SDA-BE
2
PGND1_2 EN1
9
100
RES I063U
C065U

C066U

C070U

I059U R028U 10K +5V-FE

22pF

22pF
7 23
PGND1_3 EN2 +5V-FE
8 R069U 10 SCL-PMIC1
6.3V

6.3V

6.3V

50V

50V
PGND1_4
24 22 I060U R017U 100K R070U 10 SDA-PMIC1

C105U

C106U
10uF

10uF

10uF

10K
PGND1_5 SLEEP +5V-FE
4
+5V-FE PVIN1_1
C024U 1uF
5
PVIN1_2

R029U
6.3V
C080U

C117U

C119U

+5V-FE 25
HS
15 I061U
6.3V

6.3V

6.3V

PVIN2
10uF

220nF

220nF

C081U

C082U

C120U

100K
12
PGND2_1
13
6.3V

6.3V

6.3V

1uF
+5V-FE PGND2_2
10uF

10uF

220nF

6.3V
11 18

C059U
FB2 NC_1
19

R020U
NC_2
14
SW2
F039U L014U
+3V3-MRV 1.5uH
I075U
I2C address = 0x32
C103U

C121U

C083U
6.3V

6.3V

6.3V
22uF

220nF

10uF

5 2014-02-21

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14-05-23

2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 82

10-1-12 B, 3V3 PLATFORM SUPPLY

3V3 PLATFORM SUPPLY


B B

RES
L021U

30H

L005U I093U
+12V
30H

100nF
22uF

16V

16V
C123U

C053U
L012U
+3V3
3.6uH

22uF

22uF
2

6.3V

6.3V
U018U
RT7297CHZSP

C101U

C102U
VIN
I089U
1 C054U 100nF
BOOT I088U
16V
ENABLE+3V3 7
EN SW
3
I087U F045U
C062U 22nF 8
SS FB
5 R082U 68K +3V3
GND-3V3
10nF

16V I092U I090U 1%


6

GND_HS
16V

COMP

1MEG
C060U

GND

22K
3.3nF

100pF

1%
C067U

C118U
50V

50V

R041U
X003U

R067U
RES
GND-3V3
I091U
GND-3V3

GND-3V3 GND-3V3 GND-3V3

6.8K
R077U
GND-3V3

5 2014-02-21

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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 83

10-1-13 B, 5V PLATFORM SUPPLY

5V PLATFORM SUPPLY
B B
L007U
RES
30H
I069U
R095U 22 RES
4 5
L001U 5% 22 L017U F034U
+12V
C109U 1nF C108U 1nF R095U RES
3 6 4.7uH
+5V-FE
30H 5% 22 I012U

100nF
RES RES R095U RES

10uF

10uF
2 7

22uF

22uF

22uF

100uF 16V
5% 22

C162U
R095U RES

C144U

C141U

C026U

6.3V
1 8

C129U

C130U

C131U
5%

RES

RES
I010U
C025U 100nF

7
U017U
I014U RT8288AZSP

VCC
I011U
1 4 C027U 100nF
VIN BOOT

2 R049U 1MEG
SW_1
3
SW_2
DETECT12V 5
EN
6 R074U 120K

GND_HS
FB +5V-FE

GND
1%

1nF
I013U

50V
C150U 100pF

C107U

9
RES

220K
22K
1%

1%
R072U

R097U
L009U
RES
30H I070U
R096U 22 RES
4 5
L008U 5% 22 L018U F036U
+12V
C112U 1nF C111U 1nF R096U RES
3 6 4.7uH
+5V-USB
30H 5% 22 I017U
100nF

RES RES R096U RES


10uF

10uF

2 7

22uF

22uF

22uF

100uF 16V
5% 22

C163U
R096U RES
C147U

C145U

C029U

6.3V
1 8

C132U

C133U

C134U
5%

RES

RES
I015U
C028U 100nF
7

U019U
I034U RT8288AZSP
VCC

I016U
1 4 C030U 100nF
VIN BOOT

2 R068U 1MEG
SW_1
3
SW_2
ENABLE+5V-USB 5
EN
6 R075U 120K
GND_HS

FB +5V-USB
100nF

GND

I033U 1%
16V

C151U 100pF
C110U

RES
220K
22K
1%

1%
R073U

R098U

5 2014-02-21

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14-05-23

2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 84

10-1-14 B, AUDIO-VIDEO I/O

AUDIO-VIDEO I/O
B B
CLOSE TO SCART CLOSE TO CYPRESS
F004C R160C I046C
C073C 2.2uF AV-SCART-RIN
18K 6.3V

470pF
10nF

R152C
S047C

16V

50V
4.7K
C049C

C068C
F033C R161C I047C
C074C 2.2uF AV-SCART-LIN
18K 6.3V

470pF
10nF

R153C
S046C

16V

50V
4.7K
C050C

C067C
F038C C016C 100nF AV-SCART-B
16V

75
10pF

5%
S044C

50V
C035C

R117C
X260
1
2
3
4 F035C R159C 49.9K I006C AV-SCART-STATUS
5 1%
6

10K
100pF
7

5%
S050C
50V
8

C100C
9

R037C
10
11
12
13 F039C
14

15
16 F037C C015C 100nF AV-SCART-G
17
16V
18

C034C

75
19

5%
S051C

50V
20

10pF
21

R116C
F002C

F036C C014C 100nF AV-SCART-R


16V

C033C

75
5%
S045C

50V
10pF

R115C
F034C
R221C 100 AV-SCART-BLK
22
100pF

S049C
50V
C099C

R025C
51

I048C
S001C
R026C

L007C L008C
S014C C013C 100nF AV-SCART-CVBS
F003C 2.7uH 2.7uH
16V
75
47pF

75
5%

220pF

680pF

220pF
S048C

50V

5%
C065C

50V

50V

50V
R112C

C048C

C066C

C047C
RES

R114C
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 85

10-1-15 B, HDMI

HDMI
B X283
1
2
RX0-2+ B
3 RX0-2-
4 RX0-1+
5
RX0-1-
AIN-5V D001C
6
7 RX0-0+ AOZ8808DI-05 D002C D003C
8 AOZ8808DI-05 AOZ8808DI-05

47K

47K
9 RX0-0- RX0-2+ 1
CH1 NC1
10 RX0-2+
10 RX0-C+ RX0-2- 2 9 RX0-2- RX0-0+ 1 10 RX0-0+ SCL-0 1 10 SCL-0

R110C

R111C
CH2 NC2 CH1 NC1 CH1 NC1
11 RX0-0- 2
CH2 NC2
9 RX0-0- SDA-0 2
CH2 NC2
9 SDA-0
12 RX0-C- 3
GND1 GND2
8
13 HDMI-CEC-IN I010C 3
GND1 GND2
8 3
GND1 GND2
8
14 F007C ARC0-HDMI RX0-1+ 4
CH3 NC3
7 RX0-1+
15 F008C SCL-0 R007C 22 HDMI0-SCL HDMI0-SCL RX0-1- 5
CH4 NC4
6 RX0-1- RX0-C+ 4
CH3 NC3
7 RX0-C+ 4
CH3 NC3
7
AIN-5V AIN-5V
16 SDA-0 22 5% HDMI0-SDA HDMI0-SDA RX0-C- 5
CH4 NC4
6 RX0-C- 5
CH4 NC4
6
5% HPD0 HPD0
17 F009C R008C
F011C I009C
18 AIN-5V
19 HPD0
F138C 21 20
F010C

100nF
23 22

16V
C001C
X284
1 RX1-2+
D004C D005C D010C
2 AOZ8808DI-05 AOZ8808DI-05 AOZ8808DI-05
3 RX1-2-
4 RX1-1+ RX1-2+ 1
CH1 NC1
10 RX1-2+ RX1-0+ 1
CH1 NC1
10 RX1-0+ SCL-1 1
CH1 NC1
10 SCL-1
5 RX1-2- 2
CH2 NC2
9 RX1-2- RX1-0- 2
CH2 NC2
9 RX1-0- SDA-1 2
CH2 NC2
9 SDA-1
6 RX1-1-
BIN-5V
7 RX1-0+ 3
GND1 GND2
8 3
GND1 GND2
8 3
GND1 GND2
8
8
9 RX1-0- RX1-1+ 4 7 RX1-1+ RX1-C+ 4 7 RX1-C+ 4 7

47K

47K
CH3 NC3 CH3 NC3 BIN-5V CH3 NC3 BIN-5V
10 RX1-C+ RX1-1- 5
CH4 NC4
6 RX1-1- RX1-C- 5
CH4 NC4
6 RX1-C- 5
CH4 NC4
6
HPD1 HPD1

R108C

R109C
11
12 RX1-C-
13 HDMI-CEC-IN
14 F013C ARC1-HDMI I012C
15 F014C SCL-1 R009C 22 HDMI1-SCL HDMI1-SCL
16 SDA-1 22 5% HDMI1-SDA HDMI1-SDA
17 5%
F015C F017C R010C I011C
18 BIN-5V
19 HPD1
F137C 21 20
F016C
100nF

23 22
16V
C004C

X285
D006C D007C D011C
1 RX2-2+ AOZ8808DI-05 AOZ8808DI-05 AOZ8808DI-05
2
3 RX2-2- RX2-2+ 1
CH1 NC1
10 RX2-2+ RX2-0+ 1
CH1 NC1
10 RX2-0+ SCL-2 1
CH1 NC1
10 SCL-2
4 RX2-1+ RX2-2- 2
CH2 NC2
9 RX2-2- RX2-0- 2
CH2 NC2
9 RX2-0- SDA-2 2
CH2 NC2
9 SDA-2
5
6 RX2-1- 3
GND1 GND2
8 3
GND1 GND2
8 3
GND1 GND2
8
CIN-5V
7 RX2-0+
8 RX2-1+ 4
CH3 NC3
7 RX2-1+ RX2-C+ 4
CH3 NC3
7 RX2-C+ 4
CH3 NC3
7
CIN-5V CIN-5V
9 RX2-0- RX2-1- 5 6 RX2-1- RX2-C- 5 6 RX2-C- 5 6
47K

47K

CH4 NC4 CH4 NC4 HPD2 CH4 NC4 HPD2


10 RX2-C+
R040C

R041C

11
12 RX2-C-
13 HDMI-CEC-IN
14 F019C ARC2-HDMI I062C
15 F020C SCL-2 R011C 22 HDMI2-SCL HDMI2-SCL
16 SDA-2 22 5% HDMI2-SDA HDMI2-SDA
17 5%
F021C F023C R012C I018C
18 CIN-5V
19 HPD2
F139C 21 20
F022C
100nF

23 22
16V
C006C

X286
1 RX3-2+
D008C D009C D012C
2 AOZ8808DI-05 AOZ8808DI-05 AOZ8808DI-05
3 RX3-2-
4 RX3-1+ RX3-2+ 1
CH1 NC1
10 RX3-2+ RX3-0+ 1
CH1 NC1
10 RX3-0+ SCL-3 1
CH1 NC1
10 SCL-3
5 RX3-2- 2
CH2 NC2
9 RX3-2- RX3-0- 2
CH2 NC2
9 RX3-0- SDA-3 2
CH2 NC2
9 SDA-3
6 RX3-1-
DIN-5V
7 RX3-0+ 3
GND1 GND2
8 3
GND1 GND2
8 3
GND1 GND2
8
8
9 RX3-0- RX3-1+ 4 7 RX3-1+ RX3-C+ 4 7 RX3-C+ 4 7
47K

47K

CH3 NC3 CH3 NC3 DIN-5V CH3 NC3 DIN-5V


10 RX3-C+ RX3-1- 5
CH4 NC4
6 RX3-1- RX3-C- 5
CH4 NC4
6 RX3-C- 5
CH4 NC4
6
HPD3 HPD3
R106C

R107C

11
12 RX3-C-
13 HDMI-CEC-IN
14 F025C ARC3-HDMI I066C
15 F026C SCL-3 R013C 22 HDMI3-SCL HDMI3-SCL
16 F027C SDA-3 22 5% HDMI3-SDA HDMI3-SDA
17 5%
R014C I063C
18 F029C DIN-5V
19 HPD3
F140C 21 20 F028C
100nF

23 22
16V
C008C

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 86

10-1-16 B, ARC

ARC
B B
+3V3

U009C

5
+3V3
VCC
GND

4.7K
3

R020C

RES
U009C
L045C
ARC0-HDMI F182C ARC0
1
I022C OE I049C 30H
HDMI-ARC-BUF 4
Y L042C
A
2 ARC1-HDMI F183C ARC1

S003C
50m
10K
30H
L043C
ARC2-HDMI F184C ARC2 +5V-FE +5V-ARC

R021C

RES
30H
I024C L044C L046C I050C
S002C HDMI-ARC ARC3-HDMI F185C ARC3
50m
30H 30H

100nF
RES

1uF
ARC0

6.3V

16V
C166C

C010C

100
1%
S036C

10pF

10pF

10pF

10pF
50m

50V

50V

50V

50V
U016C

16
C012C

C163C

C164C

C165C

R053C
RES 74HC4051PW

R006C
VCC
0
11 F188C HDMI-ARC-SEL0
HDMI-CEC-IN F001C 0
- 8x
10 F187C HDMI-ARC-SEL1
100
RES HDMI-CEC 7
2
9 F186C HDMI-ARC-SEL2
I005C
BC847BW(COL) I004C
U001C 6
G8
R030C

1MEG
RES

HDMI-ARC-BUF R075C 56 F012C HDMI-ARC-IN ARC1


3

R024C
1% MDX 0
13

27K
14

180

100
1
RES 15
1

5%

1%
R015C
HDMI-ARC-IN 3
3
12
I002C 1
+3V3-STANDBY 4
5

R022C

R071C
22K 5
2
6
4

GND
VEE
7

+3V3

8
ARC2
47K

47K

47K

100
100nF

1%
16V
C009C
R031C

R032C

R033C

R073C
HDMI-SOC-IN-HPD

ARC3
3

100
1%
U010C 5
BC847BS(COL)
I020C
6

R072C
4
I019C R034C 47K
U010C 2 HDMI-HPD0
BC847BS(COL)
I067C I051C
DBG C011C 1uF DB002C
1 DBG 6.3V
DBG

100

56
1%

1%
R074C

R076C
DBG

DBG
I021C

R050C
47K HDMI-HPD1
I068C

HDMI-CYP-IN-HPD

U012C 5
BC847BS(COL)
I025C
6
4
R051C
U012C 2 HDMI-HPD2
BC847BS(COL)
I023C 47K I069C

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 87

10-1-17 B, CYPRESS SUPPLY

CYPRESS SUPPLY
B B

U017C
VMID VREFN VREFP 88DE6010
I038C L051C
6 52
I007C I029C
C080C 100nF
I032C VREFP VREFP RXVDD3P3_1 +3V3-MRV
55
RXVDD3P3_2 30H

C174C 100nF

C175C 100nF

C176C 100nF

C177C 100nF

C178C 100nF

C179C 100nF
100nF

C041C 100nF

10uF
58
16V RXVDD3P3_3
61

6.3V
16V

16V

16V
16V

16V

16V

16V

16V
RXVDD3P3_4
C106C 22uF 7 64

C223C
C040C
VMID VMID RXVDD3P3_5
67
6.3V RXVDD3P3_6

100nF

100nF

100nF
47uF

10uF

10uF
70
RXVDD3P3_7
73
6.3V

6.3V

6.3V
16V

16V

16V
RXVDD3P3_8
8 97
C107C

C082C

C079C

C094C

C095C

C081C
VREFN VREFN RXVDD3P3_9
100
RXVDD3P3_10

100nF

C181C 100nF

C182C 100nF

C183C 100nF

C184C 100nF

C185C 100nF

C186C 100nF

C187C 100nF

10uF
103
RXVDD3P3_11
106

6.3V
16V

16V

16V
16V

16V

16V

16V

16V
RXVDD3P3_12
109

C224C
C180C
RXVDD3P3_13
112
RXVDD3P3_14
115
RXVDD3P3_15
15 118
VDDA_SENSE_SIF RXVDD3P3_16
I033C I039C L048C

100nF
16 23

1uF
SIF_REF AVDD3P3_1 +3V3-MRV
35

6.3V
16V
AVDD3P3_2 30H

100nF

100nF

C189C 100nF

270pF

C233C 270pF
18

10uF
C192C

C218C

1uF
GND_SENSE_SIF
2

6.3V

6.3V
16V

16V

16V

50V

50V
AVDD1P8_1
44

C193C

C219C

C188C

C232C

C225C
AVDD1P8_2

50
VDD1P8_1
75
VDD1P8_2
95
I034C VDD1P8_3 I040C L049C
21 120
VGAFE_REF VDD1P8_4 +1V8-MRV
140
VDD1P8_5 30H

100nF
19

1uF
GND_SENSE_VGADC
1

6.3V
16V
VDD1P0_1

100nF

C191C 100nF

270pF

C235C 270pF

10uF
49

C198C

C220C
VDD1P0_2
76

6.3V
16V

16V

50V

50V
VDD1P0_3
91

C190C

C234C

C226C
VDD1P0_4
126
VDD1P0_5
133
VDD1P0_6
139
VDD1P0_7
159
VDD1P0_8 I041C L050C
166
VDD1P0_9 +1V8-MRV
30H

100nF

C195C 100nF

C196C 100nF

C197C 100nF

10uF
145
IOVDD_1
150

6.3V
16V

16V

16V

16V
VSS_1 IOVDD_2
146 157

C227C
C194C
VSS_2 IOVDD_3
152 162
VSS_3 IOVDD_4
158 167
VSS_4 IOVDD_5
163 172
VSS_5 IOVDD_6
168
173
VSS_6 +1V0-C
VDD3P3_1 84

C205C 100nF

C206C 100nF

C207C 100nF
100nF

C200C 100nF

C201C 100nF

C202C 100nF

C203C 100nF

C204C 100nF
4

22uF
U021C VDD3P3_2 89
RT9025 121

6.3V
16V

16V

16V

16V
16V

16V

16V

16V

16V
VDD3P3_3
VDD

C199C

C240C
F190C
3 6 48
+1V5-BE VIN VOUT +1V0-C 177
HS_GND OTP_VHV

R217C
10uF

22uF

2 7
1nF

+5V-FE EN ADJ
6.3V

6.3V

50V

1 I028C I042C L052C


1
C222C

C231C

C230C

56K
1uF

PGOOD +1V8-MRV
6.3V

I030C 30H

10uF

10uF
1%

C229C 100nF

C216C 100nF
100nF

C236C 100nF

C211C 100nF

C212C 100nF

C213C 100nF

C214C 100nF

C215C 100nF

1uF
5
C217C

GND_HS

NC

16V

16V

16V

16V

16V

16V

16V

16V

16V
GND

22K

R220C

C221C
C228C

C237C

C238C
6.3V

6.3V
6.3V
5%
R216C
8

L047C
+3V3-MRV

100nF
100nF

100nF
I031C I045C 30H
220K

6.3V 10uF
680K

1%

C208C

C209C

C210C

C239C
16V

16V
16V
R219C

R218C
RES

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 88

10-1-18 B, CIMAX+

CIMAX+
B B
+3V3-CIMAX

R098C

10K
U018C
I057C
CIMAX-SPI-INT I071C S038C CIMAX+
50m
I056C CONTROL
A1
RESET
3
S035C E7
INT
SYSTEM-RESETn 1 U019C 50m RES
A11
SPI_DIN
B11
SPI_DOUT
U018C 2 C11
SPI_CS
CIMAX+ D11
SPI_CLK
U018C
CIMAX+
CIMAX-SPI-MOSI C14
SPI_M_CS1 GND14
TS-PI-CLK TS-OUT1-CLK CIMAX-SPI-MISO E8
A8
TS_PI_CLK TS_TUNER TS_PO_CLK
G11
R101C
C13
SPI_M_CS2
D12
GND13
TS-PI-SYNC B8
TS_PI_STRT TS_PO_STRT
G10 TS-OUT1-SYNC CIMAX-SPI-CSn 100 B14
NC GND12
TS-PI-VALID C8 F12 TS-OUT1-VALID CIMAX-SPI-CLK B1 E1
TS_PI_VAL TS_PO_VAL R099C E5
GND11 VIO5 +3V3-CIMAX
TS-PI-DATA0 D8 F13 TS-OUT1-DATA0 100 F181C A14 J1
TS_PI_D0 TS_PO_D0 +3V3-CIMAX CFG_0 GND10 VIO4

SUPPLY
TS-PI-DATA1 E9 F10 RES R100C A13 K5 P5
TS_PI_D1 TS_PO_D1 +3V3-CIMAX CFG_1
E10
GND9 VIO3
TS-PI-DATA2 B9
TS_PI_D2 TS_PO_D2
E14 100 RES F032C GND8 VIO2
H14
TS-PI-DATA3 C9 E13 B4 K10 F14
TS_PI_D3 TS_PO_D3 F018C R105C F005C GPIO0 GND7 VIO1
TS-PI-DATA4 A10 E12 100 F006C C4 M8 A9
TS_PI_D4 TS_PO_D4 GPIO1 GND6 VIO0
TS-PI-DATA5 B10 E11 F135C A3 B7
TS_PI_D5 TS_PO_D5 GPIO2 GND5
TS-PI-DATA6 C10 D14 F189C B3 E3 P8
TS_PI_D6 TS_PO_D6 GPIO3 GND4 VCORE1 +1V2-CIMAX
TS-PI-DATA7 D10 D13 F199C A2 J4 N8
TS_PI_D7 TS_PO_D7 GPIO4 GND3 VCORE0
K7
GND2
B13 H11
DB003C F177C TMS GND1
TS-CD1-CLK K14 G14 TS-OUT2-CLK A12 F11
TS_SI2_CLK TS_SO2_CLK F178C TCLK GND0
TS-CD1-SYNC DB004C L11 H10 TS-OUT2-SYNC S042C 50m B12 D9
TS_SI2_STRT TS_SO2_STRT F179C TDI
TS-CD1-VALID DB005C K12
TS_SI2_VAL TS_SO2_VAL
G12 TS-OUT2-VALID S043C 50m
F180C C12
TDO
TS-CD1-DATA0 K13
TS_SI2_D TS_SO2_D
G13 TS-OUT2-DATA0
DB006C
USB-CIMAX-DP S039C 50m D6
DP
USB-CIMAX-DM E6
DM
TS-CD2-CLK DB010C J14 12K RES C7
TS_SI3_CLK L001C I014C REXT
TS-CD2-SYNC DB009C K11 S040C R158C I013C B6
TS_SI3_STRT +3V3-CIMAX AVDDTX
TS-CD2-VALID DB008C J12
TS_SI3_VAL
RES 50m
30H
TS-CD2-DATA0 J13
TS_SI3_D
S041C C021C 100nF C6
AVSSTX
50m 16V 10uF A7
DB007C AVDDC
C046C 6,3V
H12 D7
TS_SI4_CLK L002C I015C AVSSC
J10
TS_SI4_STRT
J11 C022C 100nF C5
TS_SI4_VAL 30H XTAL1
H13 16V 10uF D5
TS_SI4_D XTAL2
C039C 6,3V
A6
AVDD_OSC
U018C C060C 18pF B5
AGND_OSC
CIMAX+ 50V

1
2 A4
R150C AVDD_PLL

X002C
CA-A-MOCLK N7
MOCLKA TS_CI MICLKA
N4 CA-A-MICLK 4 R146C 1MEG A5
AGND_PLL
CA-A-MOSTRT 56 N11
MOSTRTA MISTRTA
J2 CA-A-MISTRT
CA-A-MOVAL M10 P3 CA-A-MIVAL

3
MOVALA MIVALA S037C
CA-A-MDO0 N12
MDOA0 MDIA0
K2 CA-A-MDI0 C061C 18pF
CA-A-MDO1 N14
MDOA1 MDIA1
L1 CA-A-MDI1 50V
L003C I016C
50m
CA-A-MDO2 M13 M1 CA-A-MDI2
MDOA2 MDIA2 +3V3-CIMAX
CA-A-MDO3 C3
MDOA3 MDIA3
N2 CA-A-MDI3 30H
C023C 100nF
CA-A-MDO4 D3 M3 CA-A-MDI4 16V 10uF +5V-FE +1V2-DVB
MDOA4 MDIA4
CA-A-MDO5 E4 L4 CA-A-MDI5 C042C 6,3V
MDOA5 MDIA5
CA-A-MDO6 F2 L5 CA-A-MDI6

47K
MDOA6 MDIA6 L004C I017C L017C
CA-A-MDO7 F5 M6 CA-A-MDI7
MDOA7 MDIA7 +1V2-CIMAX C057C 1nF
30H 30H
CA-A-RST L8
RSTA
50V C043C 10uF
CA-A-CD1n C1 C058C 2,2nF 6,3V 3

R190C
CD1A_B

RES
CA-A-CD2n L13 50V C059C 3,3nF U014C
CD2A_B
CA-A-CE1n F3 I035C 1 AO3414
CE1A_B 50V
CA-A-CE2n G3 2 RES
CE2A_B
CA-A-RDY N1 +5V-FE
RDY_IRQA_B
CA-A-WAITn P9
WAITA_B L005C
I043C F031C

100K
R151C +3V3 +3V3-CIMAX +1V2-CIMAX
CA-B-MOCLK M7
MOCLKB MICLKB
M4 CA-B-MICLK 30H

100nF

100nF

100nF

100nF

100nF

100nF

470pF

470pF
6,3V
CA-B-MOSTRT 56 CA-B-MISTRT

10uF
M11 J5

16V

16V

16V

16V

16V

16V
MOSTRTB MISTRTB

R144C
3

RES
CA-B-MOVAL L10
MOVALB MIVALB
N3 CA-B-MIVAL
CA-B-MDO0 P13 K3 CA-B-MDI0

C044C

C024C

C025C

C026C

C027C

C028C

C029C

C062C

C063C
50V
50V
MDOB0 MDIB0 I036C

100nF
CA-B-MDO1 N13
MDOB1 MDIB1
L2 CA-B-MDI1 5
U002C
CA-B-MDO2 M12 M2 CA-B-MDI2 6

16V
MDOB2 MDIB2 BC847BS(COL)
CA-B-MDO3 D1 P2 CA-B-MDI3 U002C

C108C
MDOB3 MDIB3 RES
CA-B-MDO4 CA-B-MDI4 4 BC847BS(COL) 2 R189C 47K
D4 P4

RES
MDOB4 MDIB4 RES +3V3
CA-B-MDO5 L14 M5 CA-B-MDI5 I037C RES

22K
MDOB5 MDIB5
CA-B-MDO6 L9
MDOB6 MDIB6
P6 CA-B-MDI6 +1V2-CIMAX
CA-B-MDO7 G1
MDOB7 MDIB7
L6 CA-B-MDI7 1

100nF

100nF

470pF
6,3V
10uF

16V

16V
CA-B-RST P7

R188C
RES
RSTB
CA-B-CD1n H1
C045C

C031C

C032C

C064C
50V
CD1B_B
CA-B-CD2n L12
CD2B_B
CA-B-CE1n F4
CE1B_B
CA-B-CE2n G4
CE2B_B
CA-B-RDY P1
RDY_IRQB_B
CA-B-WAITn N9
WAITB_B A0
P11 CA-AB-A00
A1
N10 CA-AB-A01
CA-AB-REGn P10
REG_B A2
K9 CA-AB-A02
CA-AB-OEn G5
OE_B A3
M9 CA-AB-A03
CA-AB-WEn L3
WE_B A4
K8 CA-AB-A04
CA-AB-IORDn H3
IORD_B A5
L7 CA-AB-A05
CA-AB-IOWRn H5
IOWR_B A6
K6 CA-AB-A06
CA-AB-D00 P12
D0 A7
N6 CA-AB-A07
CA-AB-D01 P14
D1 A8
J3 CA-AB-A08
CA-AB-D02 M14
D2 A9
H4 CA-AB-A09
CA-AB-D03 B2
D3 A10
G2 CA-AB-A10
CA-AB-D04 C2
D4 A11
H2 CA-AB-A11
CA-AB-D05 D2
D5 A12
N5 CA-AB-A12
CA-AB-D06 E2
D6 A13
K1 CA-AB-A13
CA-AB-D07 F1
D7 A14
K4 CA-AB-A14

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 89

10-1-19 B, PCMCIA SLOTS

PCMCIA SLOTS
B B

X297
X295 F040C 1
F061C 1 CA-AB-D03 F041C 2
CA-AB-D03 F062C 2 CA-AB-D04 F042C 3
CA-AB-D04 F063C 3 CA-AB-D05 F043C 4
CA-AB-D05 F064C 4 CA-AB-D06 F044C 5
CA-AB-D06 F065C 5 CA-AB-D07 F045C 6
CA-AB-D07 F066C 6 CA-B-CE1n F046C 7
CA-A-CE1n F067C 7 CA-AB-A10 F047C 8
CA-AB-A10 F068C 8 CA-AB-OEn F048C 9
CA-AB-OEn F069C 9 CA-AB-A11 F049C 10
CA-AB-A11 F070C 10 CA-AB-A09 F050C 11
CA-AB-A09 F071C 11 CA-AB-A08 F051C 12
CA-AB-A08 F072C 12 CA-AB-A13 F053C 13
CA-AB-A13 F073C 13 CA-AB-A14 F054C 14
CA-AB-A14 F074C 14 CA-AB-WEn F055C 15
CA-AB-WEn F075C 15 CA-B-RDY F056C 16
CA-A-RDY F076C 16 F057C 17
F077C +5VCA-B
17 18
+5VCA-A
18 CA-B-MIVAL F058C 19
CA-A-MIVAL F078C 19 CA-B-MICLK F059C 20
CA-A-MICLK F079C 20 CA-AB-A12 F060C 21
CA-AB-A12 F080C 21 CA-AB-A07 F121C 22
CA-AB-A07 F081C 22 CA-AB-A06 F122C 23
CA-AB-A06 F082C 23 CA-AB-A05 F123C 24
CA-AB-A05 F083C 24 CA-AB-A04 F124C 25
CA-AB-A04 F084C 25 CA-AB-A03 F125C 26
CA-AB-A03 F085C 26 CA-AB-A02 F126C 27
CA-AB-A02 F086C 27 CA-AB-A01 F127C 28
CA-AB-A01 F087C 28 CA-AB-A00 F128C 29
CA-AB-A00 F088C 29 CA-AB-D00 F129C 30
CA-AB-D00 F089C 30 CA-AB-D01 F130C 31
CA-AB-D01 F090C 31 CA-AB-D02 F131C 32
CA-AB-D02 F091C 32 CA-B-WP 33
CA-A-WP 33 34
34 35
35 CA-B-CD1n F132C 36
CA-A-CD1n F092C 36 CA-B-MDO3 F133C 37
CA-A-MDO3 F093C 37 CA-B-MDO4 F134C 38
CA-A-MDO4 F094C 38 CA-B-MDO5 F136C 39
CA-A-MDO5 F095C 39 CA-B-MDO6 F141C 40
CA-A-MDO6 F096C 40 CA-B-MDO7 F142C 41
CA-A-MDO7 F097C 41 CA-B-CE2n F143C 42
CA-A-CE2n F098C 42 CA-B-VS1n F144C 43
CA-A-VS1n F099C 43 CA-AB-IORDn F145C 44
CA-AB-IORDn F100C 44 CA-AB-IOWRn F146C 45
CA-AB-IOWRn F101C 45 CA-B-MISTRT F147C 46
CA-A-MISTRT F102C 46 CA-B-MDI0 F148C 47
CA-A-MDI0 F103C 47 CA-B-MDI1 F149C 48
CA-A-MDI1 F104C 48 CA-B-MDI2 F150C 49
CA-A-MDI2 F105C 49 CA-B-MDI3 F151C 50
CA-A-MDI3 F106C 50 51
+5VCA-B
51 52
+5VCA-A
52 CA-B-MDI4 F152C 53
CA-A-MDI4 F107C 53 CA-B-MDI5 F153C 54
CA-A-MDI5 F108C 54 CA-B-MDI6 F154C 55
CA-A-MDI6 F109C 55 CA-B-MDI7 F155C 56
CA-A-MDI7 F110C 56 CA-B-MOCLK F156C 57
CA-A-MOCLK F111C 57 CA-B-RST F157C 58
CA-A-RST F112C 58 CA-B-WAITn F158C 59
CA-A-WAITn F113C 59 CA-B-INPACKn 60
CA-A-INPACKn 60 CA-AB-REGn F160C 61
CA-AB-REGn F115C 61 CA-B-MOVAL F161C 62
CA-A-MOVAL F116C 62 CA-B-MOSTRT F162C 63
CA-A-MOSTRT F117C 63 CA-B-MDO0 F163C 64
CA-A-MDO0 F118C 64 CA-B-MDO1 F164C 65
CA-A-MDO1 F119C 65 CA-B-MDO2 F165C 66
CA-A-MDO2 F120C 66 CA-B-CD2n F159C 67
CA-A-CD2n F114C 67 68
68 71 69
71 69 72 70
72 70

R149C R148C
+5V-USB +5VCA-A +5V-USB +5VCA-B
+T 750mA +T 750mA
22uF 16V

22uF 16V
C056C

C055C
+3V3-CIMAX
+3V3-CIMAX

CA-B-CD1n RES R038C 10K


CA-A-CD1n RES R049C 10K CA-B-CD2n RES 10K
CA-A-CD2n RES 10K CA-B-VS1n RES R042C 10K R039C
CA-A-VS1n RES R079C 10K R070C CA-B-WAITn 10K
CA-A-WAITn 10K R043C
R080C
+3V3-CIMAX
+3V3-CIMAX

CA-B-RST RES R001C 100K


CA-A-RST RES R035C 100K CA-B-RDY 10K
CA-A-RDY 10K CA-B-CE2n RES R045C 10K R044C
CA-A-CE2n RES R082C 10K R081C CA-B-CE1n RES 10K
CA-A-CE1n RES 10K R046C
CA-AB-IORDn RES R084C 10K R083C
CA-AB-IOWRn RES 10K
CA-AB-OEn RES R086C 10K R085C
CA-AB-WEn RES 10K
R087C

R090C 10K CA-AB-REGn


R047C
RES CA-B-WP RES 10K
R088C
CA-A-WP RES 10K CA-B-INPACKn RES 10K
CA-A-INPACKn RES 10K
R048C
R089C

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 90

10-1-20 B, ANALOG IO

ANALOG IO
B B
X266
F175C
CLOSE TO SCART CLOSE TO CYPRESS
WHITE 1

I052C
2 F173C R162C 18K C075C 2.2uF AV-YPBPR-LIN
6.3V
RED 3

470pF
10nF

R154C
S053C
F174C

16V

50V
4

4.7K
C051C

C070C
I053C
R163C 18K C076C 2.2uF AV-YPBPR-RIN
6.3V

470pF
10nF

R155C
S052C

16V

50V
4.7K
C052C

C069C
X268 5
4
I054C
3 F168C R164C 18K C077C 2.2uF AV-DVI-RIN
6.3V
I055C
2 F167C R165C 18K C078C 2.2uF AV-DVI-LIN
1 6.3V
F166C

470pF

470pF
10nF

10nF

R156C

R157C
S027C

S028C
16V

16V

50V

50V
4.7K

4.7K
C053C

C054C

C071C

C072C
+3V3 I001C
AV-CVBS-DETECTn

10K
10K

10K

R227C
R097C

R091C

S016C AV-YPBPR-DETECTn
I008C
3
R036C 10 F172C C019C 100nF
F191C 1 U013C AV-YPBPR-S
BC847BW(COL) S017C F171C C020C 100nF

75
16V
AV-YPBPR-Y
2 RES S009C
RES L006C L009C RES

R118C
330nH 330nH

R028C

47pF
100pF

22pF
50V

50V

50V
RES

C088C

C085C

C089C
X261

RES
RES

RES
GREEN

75
1
2
F192C
3 Y

BLUE 4 C036C 10pF

F193C 50V
5 PB S018C F170C C018C 100nF AV-YPBPR-PB
50m
16V

75
RED 6 10pF C037C RES S010C
F194C 50V RES L010C L011C RES
7 PR
330nH 330nH

R119C
47pF
75

100pF
10pF C038C

22pF
50V

50V

50V
50V
C090C

C086C

C096C
S054C

S056C

S055C

R029C

RES
RES

RES
RES

F176C

S019C F169C C017C 100nF AV-YPBPR-PR


50m
16V

75
RES S011C
RES L012C L013C RES
330nH 330nH

R120C
R054C

47pF
100pF

22pF
50V

50V

50V
RES

C097C

C087C

C098C
RES
RES

RES
75

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 91

10-1-21 B, CYPRESS VIDEO & AUDIO

CYPRESS VIDEO & AUDIO


B B

U017C
88DE6010

TTL - I2S
DVIDEO-D0 R121C 33 148
TTL_D[0]
DVIDEO-D1 R122C 33 149
TTL_D[1]
DVIDEO-D2 R123C 33 153
TTL_D[2] DB001C
DVIDEO-D3 R124C 33 154
TTL_D[3] I2SOUT_MCLK
138 R137C 33
DVIDEO-D4 R125C 33 155
TTL_D[4] I2SOUT_CK
171 R138C 33 I2S-SOC-IN-BCLK
DVIDEO-D5 R126C 33 156
TTL_D[5] I2SOUT_WS
174 R139C 33 I2S-SOC-IN-LRCK
DVIDEO-D6 R127C 33 160
TTL_D[6] I2SOUT_DT0
175 R140C 33 I2S-SOC-IN-SD0
DVIDEO-D7 R128C 33 161
TTL_D[7] I2SOUT_DT1
176 R222C 33 I2S-SOC-IN-SD1
DVIDEO-D8 R129C 33 164
TTL_D[8] I2SOUT_DT2
142 R223C 33 I2S-SOC-IN-SD2
DVIDEO-D9 R130C 33 165
TTL_D[9] I2SOUT_DT3
137 R224C 1.5K I2S-SOC-IN-SD3
DVIDEO-D10 R131C 33 169
TTL_D[10]
DVIDEO-D11 R132C 33

33pF

33pF

33pF

33pF
170

50V
50V

50V

50V
1.8K
TTL_D[11]

33pF

33pF

33pF
50V

50V

50V
R027C
DVIDEO-CLK R133C 33 151 86

C168C

C169C

C170C

C171C
TTL_CLK CEC
DVIDEO-HS R134C 33 143

C241C

C242C

C243C

RES

RES

RES

RES
TTL_HS
DVIDEO-VS R135C 33 144
TTL_VS
DVIDEO-FID R136C 33 147
TTL_FLD

R147C
+3V3-MRV
I058C 27K

U017C
88DE6010

ANALOG AV
39
NC SOG0
AV-SCART-R 30
HD1_Y
AV-SCART-G 31
HD1_PB
AV-SCART-B 32
HD1_PR SPDIFIN
83 S021C SPDIF-QHDMI
50m
R145C I059C
AV-YPBPR-S 38
SOG1 SPDIFOUT
85 SPDIF-SOC-IN
AV-YPBPR-Y 33
HD2_Y 33
AV-YPBPR-PB 36
HD2_PB
S020C SPDIF-DBG
AV-YPBPR-PR 34
HD2_PR
RES 50m

33pF

33pF
50V

50V
37
NC SOG2
29

C172C

C173C
NC VGA_G

RES
27
NC VGA_B
NC 28 VGA_R

AV-SCART-CVBS 20
CV1
NC 22 CV2
AV-TUNER-CVBS C109C 100nF 24
CV3
16V NC 25 SV_Y
26
NC SV_C

NC 3 MONO
AV-TUNER-SIF C110C 100nF 17
SIF
16V
AV-YPBPR-LIN 13
STEREO_IN_L[0]

9
8
7
AV-YPBPR-RIN 14
STEREO_IN_R[0]
AV-DVI-LIN 11
STEREO_IN_L[1]
AV-DVI-RIN 12
STEREO_IN_R[1]
10 6
9 11 5
NC STEREO_IN_L[2]
10 12 4
NC STEREO_IN_R[2]
AV-SCART-LIN 4
STEREO_IN_L[3]
AV-SCART-RIN 5
STEREO_IN_R[3]
X006C
CYPRESS SHIELDING

1
2
3
AV-SCART-STATUS 40
FSW0
NC 41 FSW1
AV-SCART-BLK 42
FB

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 92

10-1-22 B, CYPRESS HDMI & CTRL

CYPRESS HDMI & CTRL


B B
C092C 8.2pF XTAL: NX3225HA EX300A - CH00142 20MHZ 8pF
50V

3
U017C

X001C
88DE6010

1MEG
R177C
4
2 MISC R179C 4.7K
47 122 F196C

1
XTAL1 JTCK +3V3-MRV
C093C 8.2pF 46 123 F195C R185C
XTAL2 JTRST
50V 124 F052C 4.7K R180C 4.7K
JTMS
SDA-CYPRESS R174C 10 130
TWSI_SDA JTDI
125 F197C R181C 4.7K
127 F198C R182C 4.7K
JTDO +3V3-MRV
SCL-CYPRESS R175C 10 131
TWSI_SCL
R183C 4.7K
136 F024C R184C 4.7K
I072C TEST
CYPRESS-RESETn I073C R176C 100 135
RESETZ F030C
45
ATEST

100nF

22pF

22pF
43
REXT
128

16V

50V

50V
GPIO[4]
129

C091C

C104C

C105C
I003C GPIO[5]
134
GPIO[6]
132 R186C 4.7K
GPIO[7] +3V3-MRV

4.99K
R187C
I061C
CYPRESS-IRQn R215C 100

I060C

100nF

16V
C030C
U017C
88DE6010
HDMI RX2-RX3
U017C HDMI-RX3-2+ 107
RX2_D2P
88DE6010 HDMI-RX3-2- 105
RX2_D2N
HDMI RX0-RX1 HDMI-RX3-1+ 104
RX2_D1P
R005C 10K C003C 100nF 141
RX_HEACP
HDMI-RX3-1- 102
RX2_D1N
16V
HDMI-RX3-0+ 101
RX2_D0P
62
RX0_D2P
HDMI-RX3-0- 99
RX2_D0N
60
RX0_D2N
HDMI-RX3-C+ 98
RX2_CKP
59
RX0_D1P
HDMI-RX3-C- 96
RX2_CKN
57
RX0_D1N
56
RX0_D0P
ATX-DDC-SCL R191C 10 88
RX2_DDC
54
RX0_D0N
ATX-DDC-SDA R192C 10 87
RX2_DDA
53 R193C 10 90
RX0_CKP +5V-FE RX2_PWR5V
51
RX0_CKN I064C
HDMI-RX2-2+ 119
RX3_D2P
78
RX0_DDC
HDMI-RX2-2- 117
RX3_D2N
77
RX0_DDA
HDMI-RX2-1+ 116
RX3_D1P
79
RX0_PWR5V
HDMI-RX2-1- 114
RX3_D1N
HDMI-RX2-0+ 113
RX3_D0P
74
RX1_D2P
HDMI-RX2-0- 111
RX3_D0N
72
RX1_D2N
HDMI-RX2-C+ 110
RX3_CKP
71
RX1_D1P
HDMI-RX2-C- 108
RX3_CKN
69
RX1_D1N
68
RX1_D0P
HDMI-CYP-SCL R093C 10 93
RX3_DDC
66
RX1_D0N
HDMI-CYP-SDA DBG R095C 10 94
RX3_DDA
65
RX1_CKP
HDMI-CYP-IN-5V R094C 10 DBG 92
RX3_PWR5V
63
RX1_CKN
DBG I065C
100nF

100nF

22pF

22pF

22pF

22pF
81
RX1_DDC
80
16V

DBG 16V

DBG 50V

DBG 50V

50V

50V
RX1_DDA
82
C135C

C160C

C005C

C007C

C083C

C084C
RX1_PWR5V

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 93

10-1-23 B, DEBUG

DEBUG
B B
X305C
DBG 1 HDMI-RX2-2+
2
3 HDMI-RX2-2-
4 HDMI-RX2-1+
5
6 HDMI-RX2-1-
7 HDMI-RX2-0+
8
9 HDMI-RX2-0-
HDMI IN (TO CYPRESS) 10 HDMI-RX2-C+
11
12 HDMI-RX2-C-
13
14
15 HDMI-CYP-SCL
16 HDMI-CYP-SDA
17
18 S026C HDMI-CYP-IN-5V
19 R016C 1K 50m
21 20

47K

47K
100nF
23 22
24

16V
C002C

R018C

R019C
R003C 10 HDMI-CYP-IN-HPD

X304C
DBG 1 HDMI-SOC-RX0-D2+
2
3 HDMI-SOC-RX0-D2-
4 HDMI-SOC-RX0-D1+
5
6 HDMI-SOC-RX0-D1-
7 HDMI-SOC-RX0-D0+
8
9 HDMI-SOC-RX0-D0-
HDMI IN (TO SOC) 10 HDMI-SOC-RX0-C+
11
12 HDMI-SOC-RX0-C-
13
14
15 HDMI-SOC-RX0-SCL
16 HDMI-SOC-RX0-SDA
17
18 S025C
R237C 1K 50m
HDMI-SOC-RX0-5V
19
21 20
47K

47K
100nF

23 22
24
16V
C245C

R229C

R230C

R002C 10 HDMI-SOC-IN-HPD
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 94

10-1-24 B, AUDIO

AUDIO
B B
PVDD +12V-AUDIO PVDD

S001D
50m

100nF

100nF
S004D

100uF 16V

100uF 16V

100uF 16V

100uF 16V

100uF 16V

100uF 16V
C022D

C021D

C007D

C006D

C004D

C003D
50m

16V

16V
S020D

C033D

C032D
50m
I007D
S021D
50m

AUDIO-HPLN 10uF C043D 10K R039D I005D

25V
47K R025D 12V PVDD Only +3V3
I029D
I019D L001D
AUDIO-HPLP 10uF C035D 10K R023D LSPK+

47K

1uF

1uF
RES
10uH

25V

25V
1uF
25V

R024D RES

C019D

C015D
25V

1uF
C031D

25V
RES
100nF
AUDIO-HPRN 10uF C044D 10K R040D I002D

10uF

10uF

C009D
1uF
25V

25V

25V

16V

1uF
25V

C026D

C025D

C016D

C017D

25V
C002D
I020D
AUDIO-HPRP 10uF C034D 10K R022D

25V

220pF

220pF
+3V3 C028D 1nF

46

32
33
44
45

26

9
+3V3 +3V3 +3V3 50V U002D

50V

50V
L002D
R035D 8.2K TAS5760LD LSPK-

C008D

C005D

AVDD

PVDD_1
PVDD_2
PVDD_3
PVDD_4

DRVDD

DVDD
10uH
C037D 220nF 10V

10nF

10nF
1 43

1uF
SFT_CLIP BSTRPA+
42
4.7K

4.7K

8.2K

5.6K

8.2K

5.6K

25V

50V

50V
RES
SPK_OUTA+ F003D
19 40

C010D

C071D

C072D
DR_INA+ SPK_OUTA-
C042D 1nF 18 39 C038D 220nF 10V TYPE
RES

RES

10K

10K

10K
DR_INA- BSTRPA-
50V TYPE

R031D

R033D

R030D

R032D
R036D 8.2K 30 34 C039D 220nF 10V F008D 6 5
R037D

R038D

DR_INB+ BSTRPB+
31 35 F009D 4 4
DR_INB- SPK_OUTB+
37 3 3 DBG

R002D

R005D

R001D
SPK_OUTB-
PQ-I2S-MCLK 13 38 C040D 220nF 10V F010D 2 2
MCLK BSTRPB- L003D
PQ-I2S-BCLK 14
SCLK
RSPK+ F011D
1 1
PQ-I2S-LRCK 16
LRCK DR_OUTA
20 10uH X070 BAS X002D
PQ-I2S-SDO TYPE

10nF
15 29

RES

1uF
SDIN DR_OUTB
TYPE

10nF
25V

50V
R034D
SDA-FE R003D 47 7 5 6 5

C023D

C069D
50V
1uF
FREQ/SDA SPK_FAULT
SCL-FE R004D 47 4 4

1K
8 6

C067D
25V
PBTL/SCL SPK_SD
3 3 DBG

10nF

10nF
C020D
2 2

I009D
22 4

50V

50V
I028D DR_MUTE ANA_REF
+3V3 R028D 39K R027D 22K I018D 1 1
+3V3

28 3

C068D

C070D
6,3V DR_UVE VCOM
X073 X003D

I008D
24 2
RES I024D DR_CN ANA_REG
I027D
I025D
PVDD

I026D

R014D 150K 1uF C030D 25 I010D


DR_CP
I016D

25V

25V
R029D L004D
C012D 470pF 3.9K 10 RSPK-
10K

SPK_GAIN0

GVDD_REG
50V 10uH

DRGND_1
DRGND_2
11
RES

1uF

1uF
SPK_GAIN1

PGND_1
PGND_2

DR_VSS

HS_PAD
GGND

DGND
12
RES
RES

1uF
SPK_SLEEP/ADR

C013D

C014D

25V
10K
R010D

C024D
10K

10K

48

47

17

36
41

23

21
27

49
I023D
R020D
R009D

R006D

25V

25V
RES

1uF

1uF
1uF

C029D

C018D
25V

C027D

S011D R007D 33
1 8
+3V3 I015D C063D F015D
RES R007D 33
2 7 2
4V 100uF I014D
3
C064D I013D F013D

1K

5% 1K
7

8
RES R007D 33 1 X274

22nF

22nF
F014D

5%
2 3 6

S014D

S013D

16V

16V
4V 100uF

1K

5% 1K
6

C065D

C066D
I004D I017D

5%
S003D

DETECT12V R011D 10K BC857BW(COL) +3V3 S012D R007D 33

R008D

R008D
10K

1
1 U001D 4 5

R008D

R008D
3

4
I003D
3
I012D

10K
R017D

R021D
I006D
SYSTEM-RESETn R012D 10K BC857BW(COL) S006D
1 U003D 50m
F002D
+3V3
3
10K

100nF
R019D

16V
RES

C036D
S008D I011D
AUDIO-RESETn R013D 10K BC857BW(COL)
50m 1 U004D

3 3 +3V3
R016D
10K 1 U005D
S005D
BC847BW(COL)

1
10K

I021D
50m SPDIF-OUT
10nF
R015D

2
16V

X273
C041D

R026D
X072 X001D
1 1 I001D 2
VS
F012D 2 2
DBG F001D
3 3 SPDIF-OUT 1
IN
50m RES R018D 10 5 4

100nF
TYPE SPDIF-DBG S002D

10pF
3
S007D GND
RES

S015D
S010D TYPE 50m RES

50V

16V
50m MT1 MT2

C011D

C001D
AUDIO-RESETn

5
4
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 95

10-1-25 B, LVDS OUTPUT

LVDS OUTPUT
B B

F204B

F201B
F200B
F199B
F198B
F197B
F196B
F194B
F195B
F193B
F192B
F081B
F086B
F088B
F089B F087B

F013B F014B
F090B

F015B
F102B

F103B
F091B
F104B
F105B
F106B
F025B

F107B F205B F009B


F108B
F109B F207B
F110B F017B
F111B
F112B
F211B
F113B
F114B F213B

F115B
F116B
F117B
F118B

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 96

10-1-26 B, MASTER - I/O , FLASH

MASTER - I/O , FLASH


B B

+3V3

16V
C277B

100nF
RES
1
U010B
NX3L4684TK
RES DBG
VCC
SOC-AMBI-SPI-CLK 5
1Y0 2Y0
7 SOC-AMBI-SPI-MOSI X325B
SCL-BE R130B 1 SCL-DISP SCL-DISP F146B 1
AMBI-SPI-SWITCH I076B 4
1S 2S
8 AMBI-SPI-SWITCH F145B 2
SDA-BE R131B 1 SDA-DISP SDA-DISP F144B 3
SW-AMBI-SPI-CLK 3
1Z 2Z
9 SW-AMBI-SPI-MOSI 5 4

NT-AMBI-SPI-CLK 2
1Y1 2Y1
10 NT-AMBI-SPI-MOSI TYPE
GND

GND_HS
1K

+3V3 +3V3 +3V3


11
6
R122B

F149B
RES

100nF
4.7K

4.7K
10K
10K

10K
10K
16V
C182B
RES

RES
+3V3

14
U022B

R127B

R128B
R186B
R126B

R187B
R125B
RES
PCA9543APWR

VCC
SDA-DISP R177B 4.7K
SCL-BE 12
SCL SD0
5 SDA-DISP RES
SDA-BE 13
SDA SC0
6 SCL-DISP SCL-DISP R178B 4.7K

INT0
4 RES
11
INT
R185B 9
SD1
BE-RESETn 10 3
RESET SC1
10
8
F209B INT1
1
I078B A0
2
A1

GND
7
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 97

10-1-27 B, VDISP - QFHD

VDISP - QFHD
B B

1 S018B 8
50m RES
2 S018B 7
50m RES
3 S018B 6
50m RES

4 S018B 5
50m RES

1 S017B 8
50m RES
2 S017B 7
50m RES
3 S017B 6
50m RES

4 S017B 5
50m RES

RES
SI4835DDY-GE3

5 6 7 8
1 2 3

U018B
+12V

F073B

1 2 5 6
SI3443CDV
!

U019B
4
X016B I005B
+3V3 F072B
+VDISP

4
T 4A 32V

R198B

C197B 100nF
4

1uF

47

100nF
RES C296B 22nF

22uF
4.7K

16V

16V

R199B
PUMD12

C227B

16V

16V
RES
3
16V
5 U020B

47K

C297B

C298B
RES

RES
100K

I001B
3 I002B C295B 100nF
R315B

I003B
16V

22K
R026B

22K

47K
6

R294B
I004B I070B DBG DBG
NT-LCD-PWR-ON R027B 1K 2 U020B

RES
R219B D006B
PUMD12 I044B
R295B

R055B

RES
10K

4,7K GREEN
1

I006B
R058B

NT-LCD-PWR-ON 1 U008B
PDTC144EU
RES
2

NT-LCD-PWR-ON 1 U012B
PDTC144EU

5 2014-02-21

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10-1-28

+3V3
B, FPGA - POWER

C210B

100uF 16V

C207B 10uF

6,3V
FPGA - POWER

8
2
1

EN
VIN2
6 VIN1

GND
U021B
RT9187GSP

GND_HS
BP|ADJ
NC
VOUT2
VOUT1

5
7
4
3
Circuit Diagrams and PWB Layouts

F153B

C208B 10uF

6,3V
I073B

R093B 22K R094B 47K


1% 1%
QV14.1E LA

RES RES
R091B 1MEG R090B 1MEG
10.

RES RES
C209B 10nF R092B 22K

16V
I072B
F152B
EN 98

2014-Oct-22 back to
div.table
+2V5-BE
+2V5-BE

+1V5-BEDDRB
+1V5-BEDDRA

+2V5-BE
+2V5-BE

+3V3
+3V3
+1V2

C201B

100uF 16V
RES
30H
30H
30H
30H
30H

L008B
L007B
L018B
L017B
L002B

X004B

RES

C193B 10uF C188B 10uF C185B 10uF C183B 10uF


I024B
I023B
I022B
I021B
I020B

6,3V 6,3V 6,3V 6,3V

C194B 10uF C187B 10uF C189B 10uF C190B 10uF C186B 10uF C184B 10uF
RES 6,3V 6,3V
RES 6,3V 6,3V 6,3V
RES 6,3V

C192B 10uF C191B 10uF


RES 6,3V
RES 6,3V

C066B 1uF C060B 1uF C055B 1uF


C167B 1uF
6.3V 6.3V 6.3V
C195B 1uF
6.3V
C069B 1uF C074B 1uF C061B 1uF C056B 1uF
6.3V
C168B 1uF
6.3V 6.3V 6.3V 6.3V
C196B 1uF
6.3V
C070B 1uF C165B 1uF C062B 1uF C057B 1uF
6.3V
C169B 1uF
6.3V 6.3V 6.3V 6.3V
C198B 1uF
6.3V
C073B 1uF C166B 1uF C065B 1uF C058B 1uF
6.3V
C170B 1uF RES RES RES
6.3V 6.3V 6.3V 6.3V
RES C199B 1uF
BG2-QTV FHD 2K14

6.3V
C059B 1uF
6.3V
RES 6.3V
C200B 1uF
RES 6.3V
+VAUX

+VCCO2
+VCCO0
+VCCINT

715RLPCB000000005
B

5
2014-02-21

14-05-23
19570_047_140523.eps
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 99

10-1-29 B, FPGA - IO BANKS - LVDS & GPIO

FPGA - IO BANKS 0 and 2 - LVDS & GPIO


B I050B
B

1uF

6.3V
C226B
U023B

R129B
RES

RES
XC6SLX75

HSWAPEN A3
IO_L1P_HSWAPEN_0
BANK 0 IO_L38P_0
C13 PQ-TX2-0P
PQ-RESETN A4
IO_L1N_VREF_0 IO_L38N_VREF_0
A13 PQ-TX2-0N
PQ-TX0-0P C5
IO_L2P_0 IO_L43P_0
E12 PQ-TX3-0P
PQ-TX0-0N A5
IO_L2N_0 IO_L43N_0
D12 PQ-TX3-0N
PQ-TX0-1P D6
IO_L3P_0 IO_L45P_0
F13 PQ-TX3-2P
PQ-TX0-1N C6
IO_L3N_0 IO_L45N_0
D13 PQ-TX3-2N
PQ-TX0-2P B6
IO_L4P_0 IO_L46P_0
H13 PQ-TX3-1P
PQ-TX0-2N A6 LX75 ONLY G13 PQ-TX3-1N
IO_L4N_0 IO_L46N_0
PQ-TX0-CLKP C7
IO_L5P_0 IO_L47P_0
E14 PQ-TX3-CLKP
PQ-TX0-CLKN A7
IO_L5N_0 IO_L47N_0
F15 PQ-TX3-CLKN
PQ-TX0-4P B8
IO_L6P_0 IO_L48P_0
F14 PQ-TX3-4P
PQ-TX0-4N A8
IO_L6N_0 IO_L48N_0
H14 PQ-TX3-4N
PQ-TX1-0P D9
IO_L7P_0 IO_L49P_0
D14 PQ-TX3-3P
PQ-TX1-0N C8
IO_L7N_0 IO_L49N_0
C14 PQ-TX3-3N
PQ-TX1-2P C9
IO_L8P_0 IO_L50P_0
B14 PQ-TX2-1P
PQ-TX1-2N A9
IO_L8N_VREF_0 IO_L50N_0
A14 PQ-TX2-1N
PQ-TX0-3P D7
IO_L32P_0 IO_L51P_0
C15 PQ-TX2-2P
PQ-TX0-3N D8
IO_L32N_0 IO_L51N_0
A15 PQ-TX2-2N
PQ-TX1-1P D10
IO_L33P_0 IO_L62P_0
D15 PQ-LED0
PQ-TX1-1N C10
IO_L33N_0 IO_L62N_VREF_0
C16 PQ-LED1
PQ-TX1-CLKP B10
IO_L34P_GCLK19_0 IO_L63P_SCP7_0
B16 PQ-TX2-CLKP
PQ-TX1-CLKN A10
IO_L34N_GCLK18_0 IO_L63N_SCP6_0
A16 PQ-TX2-CLKN
PQ-TX1-4P C11
IO_L35P_GCLK17_0 IO_L64P_SCP5_0
C17 PQ-TX2-3P
PQ-TX1-4N A11
IO_L35N_GCLK16_0 IO_L64N_SCP4_0
A17 PQ-TX2-3N
PQ-TX1-3P D11
IO_L36P_GCLK15_0 IO_L65P_SCP3_0
B18 PQ-TX2-4P
PQ-TX1-3N C12
IO_L36N_GCLK14_0 IO_L65N_SCP2_0
A18 PQ-TX2-4N
PQ-CLK R025B 10 RES B12
IO_L37P_GCLK13_0 IO_L66P_SCP1_0
E16 PQ-LED2
A12
IO_L37N_GCLK12_0 IO_L66N_SCP0_0
D17 PQ-LED3

U023B
XC6SLX75

CCLK R004B 10 Y21


IO_L1P_CCLK_2 BANK 2 IO_L30P_GCLK1_D13_2
Y13 DB022B SOC-TX0-CLKP
M0 F154B AA22
IO_L1N_M0_CMPMISO_2 IO_L30N_GCLK0_USERCCLK_2
AB13 DB023B SOC-TX0-CLKN
SOC-TX0-0P DB004B AA21
IO_L2P_CMPCLK_2 IO_L31P_GCLK31_D14_2
AA12 DB024B SOC-TX1-2P
SOC-TX0-0N DB005B AB21
IO_L2N_CMPMOSI_2 IO_L31N_GCLK30_D15_2
AB12 DB025B SOC-TX1-2N
MISO AA20
IO_L3P_D0_DIN_MISO_MISO1_2 IO_L32P_GCLK29_2
Y11 DB026B SOC-TX1-CLKP
MOSI R012B 10 AB20
IO_L3N_MOSI_CSI_B_MISO0_2 IO_L32N_GCLK28_2
AB11 DB027B SOC-TX1-CLKN
NT-AMBI-SPI-CLK R060B 1 T18
IO_L4P_2 IO_L40P_2
R11
NT-AMBI-SPI-MOSI R059B 1 T17
IO_L4N_VREF_2
LX45 ONLY IO_L40N_2
T11
SOC-TX0-1P DB006B Y19
IO_L5P_2 IO_L41P_2
AA10 DB021B SOC-TX1-3P
SOC-TX0-1N DB007B AB19
IO_L5N_2 IO_L41N_VREF_2
AB10 DB020B SOC-TX1-3N
W18
IO_L6P_2 IO_L42P_2
V11 R065B 1 SW-AMBI-SPI-CLK
Y18
IO_L6N_2 IO_L42N_2
W11 R066B 1 SW-AMBI-SPI-MOSI
I052B T16
IO_L7P_2 IO_L43P_2
Y9 DB018B SOC-TX1-4P
T15
IO_L7N_2 IO_L43N_2
AB9 DB019B SOC-TX1-4N
U17 W10
IO_L8P_2 IO_L44P_2
LX45 ONLY
1

U16 Y10
IO_L8N_2 IO_L44N_2
V19
IO_L9P_2 LX45 ONLY IO_L45P_2
AA8 R028B 100 PQ-3D-LR
V18
IO_L9N_2 IO_L45N_2
AB8 SOC-3D-LR
R16 W8
R064B

IO_L10P_2 IO_L46P_2
R15 V7
IO_L10N_2 IO_L46N_2
V17
IO_L11P_2
LX45 ONLY IO_L47P_2
W9
W17 Y8
IO_L11N_2 IO_L47N_2
SOC-AMBI-SPI-CLK R063B 1 U14
IO_L12P_D1_MISO2_2 IO_L48P_D7_2
Y7 R067B 1 AMBI-SPI-MOSI
SOC-AMBI-SPI-MOSI R062B 1 U13
IO_L12N_D2_MISO3_2 IO_L48N_RDWR_B_VREF_2
AB7 R070B 1 AMBI-SPI-CLK
M1 U15
IO_L13P_M1_2 IO_L49P_D3_2
AA6 R022B 10 SDA-BE
AMBI-SPI-SWITCH R061B 1 V15
IO_L13N_D10_2 IO_L49N_D4_2
AB6 R023B 10 SCL-BE
SOC-TX0-2P DB008B AA18
IO_L14P_D11_2 IO_L50P_2
U9
SOC-TX0-2N DB009B AB18
IO_L14N_D12_2 IO_L50N_2
V9
SOC-TX0-3P DB010B Y17
IO_L15P_2 IO_L51P_2
T8
SOC-TX0-3N DB011B AB17
IO_L15N_2 IO_L51N_2
U8
SOC-TX1-1P DB012B AA14
IO_L16P_2 IO_L52P_2
T10
SOC-TX1-1N DB013B AB14
IO_L16N_VREF_2
LX45 ONLY IO_L52N_2
U10
Y16 W6
IO_L17P_2 IO_L53P_2
W15 Y6
IO_L17N_2 IO_L53N_2
V13 LX45 ONLY Y5
IO_L18P_2 IO_L54P_2
W13 AB5
IO_L18N_2 IO_L54N_2
SOC-TX0-4P DB014B AA16
IO_L19P_2 IO_L57P_2
AA4 SOC-I2S-MCLK
SOC-TX0-4N DB015B AB16
IO_L19N_2 IO_L57N_2
AB4 SOC-I2S-SDO
W14
IO_L20P_2 IO_L58P_2
Y3 PQ-I2S-LRCK
Y14 LX45 ONLY AB3 PQ-I2S-SDO
IO_L20N_2 IO_L58N_2
SOC-TX1-0P DB016B Y15
IO_L21P_2 IO_L59P_2
R9
SOC-TX1-0N DB017B AB15
IO_L21N_2 IO_L59N_2
R8
T12 LX45 ONLY T7
IO_L22P_2 IO_L60P_2
U12 R7
IO_L22N_2 IO_L60N_2
T14
IO_L23P_2
LX45 ONLY IO_L62P_D5_2
W4 SOC-I2S-BCLK
R13
IO_L23N_2 IO_L62N_D6_2
Y4 SOC-I2S-LRCK
PQ-CLK R013B 10 W12
IO_L29P_GCLK3_2 IO_L63P_2
U6
SOC-AMBI-SPI-MISO R046B 1 Y12
IO_L29N_GCLK2_2
LX45 ONLY IO_L63N_2
V5
IO_L64P_D8_2
AA2 PQ-I2S-BCLK
IO_L64N_D9_2
AB2 PQ-I2S-MCLK
IO_L65P_INIT_B_2
T6 F160B INIT-B
IO_L65N_CSO_B_2
T5 R024B 10 CSO-B
PROGRAM_B_2
AA1 F008B PROG-B
Y20
CMPCS_B_2
DONE_2
Y22 F011B DONE

R132B 1K
+VCCO2

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 100

10-1-30 B, FPGA - IO BANKS - DDR

FPGA - IO BANKS 1 and 3 - DDR


B B
U023B
XC6SLX75

R057B 100 1%
I080B
BEDDRA-RZQ BEDDRA-RZQ C19 BANK 1 K20 BEDDRA-MA5
IO_L1P_A25_1 IO_L40P_GCLK11_M1A5_1
B20 K19 BEDDRA-MA6
+BEDDRA-VREF IO_L1N_A24_VREF_1 IO_L40N_GCLK10_M1A6_1
C053B 100nF G16
IO_L9P_1 IO_L41P_GCLK9_IRDY1_M1RASN_1
H21 BEDDRA-RASn
16V G17 H22 BEDDRA-CASn
IO_L9N_1 IO_L41N_GCLK8_M1CASN_1
F16
IO_L10P_1 IO_L42P_GCLK7_M1UDM_1
M20 BEDDRA-DML
F17
IO_L10N_1 IO_L42N_GCLK6_TRDY1_M1LDM_1
L19 BEDDRA-DMU
B21
IO_L19P_1 IO_L43P_GCLK5_M1DQ4_1
J20 BEDDRA-DQU6
B22
IO_L19N_1 IO_L43N_GCLK4_M1DQ5_1
J22 BEDDRA-DQU2
A20
IO_L20P_1 IO_L44P_A3_M1DQ6_1
K21 BEDDRA-DQU4
A21
IO_L20N_1 IO_L44N_A2_M1DQ7_1
K22 BEDDRA-DQU0
K16
IO_L21P_1 IO_L45P_A1_M1LDQS_1
L20 BEDDRA-DQSU-P
J16
IO_L21N_1 IO_L45N_A0_M1LDQSN_1
L22 BEDDRA-DQSU-N
C052B 100nF H16
IO_L28P_1 IO_L46P_FCS_B_M1DQ2_1
M21 BEDDRA-DQU3
16V H17 M22 BEDDRA-DQU1
+BEDDRA-VREF IO_L28N_VREF_1 IO_L46N_FOE_B_M1DQ3_1
BEDDRA-MA13 D19
IO_L29P_A23_M1A13_1 IO_L47P_FWE_B_M1DQ0_1 N20 BEDDRA-DQU5
I057B
D20
IO_L29N_A22_M1A14_1 IO_L47N_LDC_M1DQ1_1 N22 BEDDRA-DQU7
R035B 4.7K BEDDRA-RSTn BEDDRA-RSTn F18
IO_L30P_A21_M1RESET_1 IO_L48P_HDC_M1DQ8_1 P21 BEDDRA-DQL3
BEDDRA-MA11 F19
IO_L30N_A20_M1A11_1 IO_L48N_M1DQ9_1
P22 BEDDRA-DQL1
R034B 4.7K BEDDRA-CKE BEDDRA-CKE D21
IO_L31P_A19_M1CKE_1 IO_L49P_M1DQ10_1 R20 BEDDRA-DQL5
I091B
BEDDRA-MA12 D22
IO_L31N_A18_M1A12_1 IO_L49N_M1DQ11_1 R22 BEDDRA-DQL7
BEDDRA-MA8 C20
IO_L32P_A17_M1A8_1 IO_L50P_M1UDQS_1 T21 BEDDRA-DQSL-P
BEDDRA-MA9 C22
IO_L32N_A16_M1A9_1 IO_L50N_M1UDQSN_1 T22 BEDDRA-DQSL-N
BEDDRA-MA10 G19
IO_L33P_A15_M1A10_1 IO_L51P_M1DQ12_1 U20 BEDDRA-DQL4
BEDDRA-MA4 F20
IO_L33N_A14_M1A4_1 IO_L51N_M1DQ13_1 U22 BEDDRA-DQL0
BEDDRA-WEn H19
IO_L34P_A13_M1WE_1 IO_L52P_M1DQ14_1 V21 BEDDRA-DQL6
BEDDRA-BA2 H18
IO_L34N_A12_M1BA2_1 IO_L52N_M1DQ15_1 V22 BEDDRA-DQL2
BEDDRA-MA7 E20
IO_L35P_A11_M1A7_1 IO_L53P_1 M19 BEDDRA-ZIO
BEDDRA-MA2 E22 N19
IO_L35N_A10_M1A2_1 IO_L53N_VREF_1 +BEDDRA-VREF I062B
BEDDRA-BA0 J17
IO_L36P_A9_M1BA0_1 IO_L58P_1 M16 C054B 100nF
BEDDRA-BA1 K17
IO_L36N_A8_M1BA1_1 IO_L58N_1 L15 16V BEDDRA-CSn BEDDRA-CSn R053B 4.7K
BEDDRA-MA0 F21
IO_L37P_A7_M1A0_1 IO_L59P_1 P19
BEDDRA-MA1 F22
IO_L37N_A6_M1A1_1 IO_L59N_1 P20
BEDDRA-CLKB-P H20
IO_L38P_A5_M1CLK_1 IO_L60P_1 W20
BEDDRA-CLKB-N J19
IO_L38N_A4_M1CLKN_1 IO_L60N_1 W22
BEDDRA-MA3 G20
IO_L39P_M1A3_1 IO_L61P_1 L17
BEDDRA-ODT G22
IO_L39N_M1ODT_1 IO_L61N_1 K18
IO_L70P_1 U19
IO_L70N_1 V20
IO_L71P_1 M17
IO_L71N_1 M18
IO_L72P_1 P17
IO_L72N_1 N16
IO_L73P_1 P18
IO_L73N_1 R19
IO_L74P_AWAKE_1 T19
IO_L74N_DOUT_BUSY_1 T20

I086B
U023B
R056B 100 1% BEDDRB-RZQ BEDDRB-RZQ XC6SLX75

C051B 100nF Y2
IO_L1P_3
BANK 3 IO_L42P_GCLK25_TRDY2_M3UDM_3
M3 BEDDRB-DMU
16V Y1 L4 BEDDRB-DML
+BEDDRB-VREF IO_L1N_VREF_3 IO_L42N_GCLK24_M3LDM_3
BEDDRB-ZIO W3
IO_L2P_3 IO_L43P_GCLK23_M3RASN_3
K5 BEDDRB-RASn
W1
IO_L2N_3 IO_L43N_GCLK22_IRDY2_M3CASN_3
K4 BEDDRB-CASn
P8
IO_L7P_3 IO_L44P_GCLK21_M3A5_3
K3 BEDDRB-MA5
P7
IO_L7N_3 IO_L44N_GCLK20_M3A6_3
J4 BEDDRB-MA6
P6
IO_L8P_3 IO_L45P_M3A3_3
K6 BEDDRB-MA3
P5
IO_L8N_3 IO_L45N_M3ODT_3
J6 BEDDRB-ODT
T4
IO_L9P_3 IO_L46P_M3CLK_3
H4 BEDDRB-CLKB-P
T3
IO_L9N_3 IO_L46N_M3CLKN_3
H3 BEDDRB-CLKB-N
U4
IO_L10P_3 IO_L47P_M3A0_3
H2 BEDDRB-MA0
V3
IO_L10N_3 IO_L47N_M3A1_3
H1 BEDDRB-MA1
N6
IO_L11P_3 IO_L48P_M3BA0_3
G3 BEDDRB-BA0
N7
IO_L11N_3 IO_L48N_M3BA1_3
G1 BEDDRB-BA1
M7
IO_L23P_3 IO_L49P_M3A7_3
H6 BEDDRB-MA7
R054B 4.7K I058B BEDDRB-CSn BEDDRB-CSn M8
IO_L23N_3 IO_L49N_M3A2_3
H5 BEDDRB-MA2
R4
IO_L24P_3 IO_L50P_M3WE_3
F2 BEDDRB-WEn
P4
IO_L24N_3 IO_L50N_M3BA2_3
F1 BEDDRB-BA2
M6
IO_L25P_3 IO_L51P_M3A10_3
G4 BEDDRB-MA10
L6
IO_L25N_3 IO_L51N_M3A4_3
F3 BEDDRB-MA4
P3
IO_L26P_3 IO_L52P_M3A8_3
E3 BEDDRB-MA8 I093B
N4
IO_L26N_3 IO_L52N_M3A9_3
E1 BEDDRB-MA9
C050B 100nF M5
IO_L31P_3 IO_L53P_M3CKE_3
D2 BEDDRB-CKE BEDDRB-CKE R036B 4.7K
16V M4 D1 BEDDRB-MA12
+BEDDRB-VREF IO_L31N_VREF_3 IO_L53N_M3A12_3
BEDDRB-DQU6 V2
IO_L32P_M3DQ14_3 IO_L54P_M3RESET_3
C3 BEDDRB-RSTn BEDDRB-RSTn R037B 4.7K
BEDDRB-DQU7 V1
IO_L32N_M3DQ15_3 IO_L54N_M3A11_3
C1 BEDDRB-MA11
BEDDRB-DQU4 U3
IO_L33P_M3DQ12_3 IO_L55P_M3A13_3
G6 BEDDRB-MA13
BEDDRB-DQU5 U1
IO_L33N_M3DQ13_3 IO_L55N_M3A14_3
F5 I095B
BEDDRB-DQSU-P T2
IO_L34P_M3UDQS_3 IO_L57P_3
K7
BEDDRB-DQSU-N T1 K8
IO_L34N_M3UDQSN_3 IO_L57N_VREF_3 +BEDDRB-VREF
BEDDRB-DQU2 R3
IO_L35P_M3DQ10_3 IO_L58P_3
D5 C049B 100nF
BEDDRB-DQU3 R1
IO_L35N_M3DQ11_3 IO_L58N_3
E4
16V
BEDDRB-DQU0 P2
IO_L36P_M3DQ8_3 IO_L59P_3
J7
BEDDRB-DQU1 P1
IO_L36N_M3DQ9_3 IO_L59N_3
H8
BEDDRB-DQL0 N3
IO_L37P_M3DQ0_3 IO_L60P_3
B2
BEDDRB-DQL1 N1
IO_L37N_M3DQ1_3 IO_L60N_3
B1
BEDDRB-DQL2 M2
IO_L38P_M3DQ2_3 IO_L80P_3
G7
BEDDRB-DQL3 M1
IO_L38N_M3DQ3_3 IO_L80N_3
F7
BEDDRB-DQSL-P L3
IO_L39P_M3LDQS_3 IO_L81P_3
D3
BEDDRB-DQSL-N L1
IO_L39N_M3LDQSN_3 IO_L81N_3
C4
BEDDRB-DQL6 K2
IO_L40P_M3DQ6_3 IO_L82P_3
E5
BEDDRB-DQL7 K1
IO_L40N_M3DQ7_3 IO_L82N_3
E6
BEDDRB-DQL4 J3
IO_L41P_GCLK27_M3DQ4_3 IO_L83P_3
A2
BEDDRB-DQL5 J1 B3
IO_L41N_GCLK26_M3DQ5_3 IO_L83N_VREF_3
C048B 100nF
+BEDDRB-VREF
16V

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 101

10-1-31 B, FPGA - CONFIGURATION

FPGA - CONFIGURATION
B B
D072B U023B
R124B 470 +3V3
DBG DBG POWER
X344B GREEN D16 A1
3 +VAUX VCCAUX_1 GND_1
1 CCLK F11
VCCAUX_2 GND_2
A22
2 CSO-B DBG G12
VCCAUX_3 GND_3
AA5
3 MOSI DONE 1 U027B H9
VCCAUX_4 GND_4
AA9
4 MISO PDTC114EU H15 AA13
F124B VCCAUX_5 GND_5
5 PROG-B K15
VCCAUX_6 GND_6
AA17
6 2 L8 AB1
F123B VCCAUX_7 GND_7
7 8 M15 AB22
VCCAUX_8 GND_8
+3V3 N8 B5
VCCAUX_9 GND_9
TYPE R6 B9
VCCAUX_10 GND_10
R10 B13
I025B VCCAUX_11 GND_11
MISO R097B 10 R12
VCCAUX_12 GND_12
B17
+3V3 U11 D4
VCCAUX_13 GND_13
C220B 100nF V6 D18

2.2K
VCCAUX_14 GND_14
J8 E2
16V +VCCINT VCCINT_1 GND_15
J10 E7
VCCINT_2 GND_16
U033B

R146B

8
X014B J12 E11
VCCINT_3 GND_17
3225 RES MX25L2006EM1I-12G J14
VCCINT_4 GND_18
E15
TS
VCC MOSI 5
D
VCC
Q 2 K9
VCCINT_5 GND_19
E21
1
OE OUT
3 R151B 47 PQ-CLK FLASH K11
VCCINT_6 GND_20
G5
+3V3 RES CCLK 6 K13 G18
ST C VCCINT_7 GND_21

100nF
GND L10 H7
VCCINT_8 GND_22
CSO-B 1 L12 J2

16V
S VCCINT_9 GND_23
L14 J9

C222B

2
VCCINT_10 GND_24
100nF

3 BOOT M9 J11

RES
W VCCINT_11 GND_25
M11 J13
16V

VCCINT_12 GND_26
7 Single Dual M13 J15
C171B

HOLD VCCINT_13 GND_27


VSS N10 J21
VCCINT_14 GND_28
U007B N12
VCCINT_15 GND_29
K10
U007B U007B
5

XC6SLX45 16Mb 32Mb N14 K12

4
VCCINT_16 GND_30
VCC P9 K14
VCCINT_17 GND_31
GND 3
A
1 Y
4 1
A
1 Y
6 R150B 47 P11
VCCINT_18 GND_32
L5
XC6SLX75 32Mb 64Mb P13 L9
2

I031B VCCINT_19 GND_33


+3V3 R14 L11
VCCINT_20 GND_34
R145B 1MEG R149B 47 PQ-CLK +VCCO0 B4
VCCO_0_1 GND_35
L13
I039B I030B
RES I027B
B7
VCCO_0_2 GND_36
L18
1K

MISO R111B 10 B11


VCCO_0_3 GND_37
M10
B15 M12
F125B VCCO_0_4 GND_38
C221B 100nF B19 M14

2.2K
VCCO_0_5 GND_39
E9 N2
R148B

16V VCCO_0_6 GND_40


X018B E13 N9
VCCO_0_7 GND_41
U032B

8
1 3

R147B
E17 N11
I029B VCCO_0_8 GND_42
W25Q64FVSSIG G10 N13
F126B VCCO_0_9 GND_43
MOSI VCC
10pF

10pF

5 2 G14 N17
2
4

D Q VCCO_0_10 GND_44
C21 N21
50V

50V

F127B FLASH +1V5-BEDDRA VCCO_1_1 GND_45


CCLK 6 E19 P10
C243B

C244B

C VCCO_1_2 GND_46
G21 P12
F128B VCCO_1_3 GND_47
CSO-B 1
S
J18
VCCO_1_4 GND_48
P14
L16 R5
VCCO_1_5 GND_49
3 L21 R18
W VCCO_1_6 GND_50
N18 U2
VCCO_1_7 GND_51
+VCCO0 7
HOLD
R21
VCCO_1_8 GND_52
U7
VSS U18 U21
VCCO_1_9 GND_53
SOC-I2S-LRCK R071B 1 PQ-I2S-LRCK W21
VCCO_1_10 GND_54
V4
RES AA3 V10

4
10K

+VCCO2 VCCO_2_1 GND_55


SOC-I2S-BCLK R083B 1 PQ-I2S-BCLK F135B
AA7
VCCO_2_2 GND_56
V14
R102B

RES AA11
VCCO_2_3 GND_57
W7
SOC-I2S-SDO R084B 1 PQ-I2S-SDO AA15
VCCO_2_4 GND_58
W16
RES D073B AA19 W19
I028B +3V3 VCCO_2_5 GND_59
SOC-I2S-MCLK R085B 1 PQ-I2S-MCLK R115B 10 PQ-RESETN PQ-LED0 R161B 470 T9
VCCO_2_6
RES F129B
T13
VCCO_2_7
SW-AMBI-SPI-CLK R098B 1 AMBI-SPI-CLK GREEN V8
VCCO_2_8
RES V12
VCCO_2_9
3
4

SW-AMBI-SPI-MOSI R099B 1 AMBI-SPI-MOSI D074B V16


+3V3 VCCO_2_10
RES PQ-LED1 R162B 470 W5
VCCO_2_11
X011B

BE-RESETn R116B 100 PROG-B


SKHU

C2
+1V5-BEDDRB VCCO_3_1
RES GREEN F4
VCCO_3_2
BE-RESETn R144B 100 PQ-RESETN F6
VCCO_3_3
RES D075B G2
+3V3
1
2

VCCO_3_4
PQ-LED2 R163B 470 J5
VCCO_3_5
L2
VCCO_3_6
GREEN L7
VCCO_3_7
N5
VCCO_3_8
D076B R2
+3V3 VCCO_3_9
PQ-LED3 R164B 470 U5
VCCO_3_10
W2
VCCO_3_11
GREEN
+VAUX

+VAUX
10K

10K

U023B DBG U023B


R095B

R096B

X308B
1 F134B
NC JTAG - MISC
E8 G8 2 F130B G15 P15
NC_1 NC_7 TCK VFS
E10 G9 3 F133B E18 LX75 P16
NC_2 NC_8 TDI RFUSE
F8 G11 4 F132B C18 ONLY R17
NC_3 NC_9 TMS VBATT
F9 H10 5 F131B A19
NC_4 NC_10 TDO
F10 H11 6 N15
NC_5 NC_11 +VAUX SUSPEND
F12 H12 8 7
NC_6 NC_12
100nF

TYPE
16V
C219B
DBG

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 102

10-1-32 B, FPGA - DDR

FPGA - DDR
B B

X005B X006B
+1V5-BE +1V5-BEDDRA +1V5-BE +1V5-BEDDRB

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
10uF

10nF

10nF

10nF

10nF

10uF

10nF

10nF

10nF

10nF
6.3V

6.3V
16V

16V

16V

16V

16V

16V

16V

16V
C172B

C019B

C020B

C021B

C022B

C023B

C024B

C174B

C175B

C176B

C177B

C173B

C025B

C026B

C027B

C028B

C046B

C047B

C178B

C179B

C180B

C181B
RES

RES

RES

RES

RES

RES

RES

RES
+1V5-BEDDRA +1V5-BEDDRB
H9
H2
F1
E9
D2
C9
C1
A8
A1

R9
R1
N9
N1
K8
K2
G7
D9
B2

R9
R1
N9
N1
K8
K2
G7
D9
B2
H9
H2
F1
E9
D2
C9
C1
A8
A1
U030B U031B
H5TQ1G63BFR-H9C H5TQ1G63BFR-H9C

D012B VDDQ VDD VDDQ VDD


BEDDRA-DQU0 D7
0 0
N3 BEDDRA-MA0 BEDDRB-DQU5 D7
0 0
N3 BEDDRB-MA0
BEDDRA-DQU1 C3
1 1
P7 BEDDRA-MA1 BEDDRB-DQU3 C3
1 1
P7 BEDDRB-MA1
BEDDRA-DQU2 C8
2 2
P3 BEDDRA-MA2 BEDDRB-DQU7 C8
2 2
P3 BEDDRB-MA2
BEDDRA-DQU3 C2
3 3
N2 BEDDRA-MA3 BEDDRB-DQU2 C2
3 3
N2 BEDDRB-MA3
BEDDRA-DQU4 A7
4
DQU
4
P8 BEDDRA-MA4 BEDDRB-DQU4 A7
4
DQU
4
P8 BEDDRB-MA4
BEDDRA-DQU5 A2
5 5
P2 BEDDRA-MA5 BEDDRB-DQU0 A2
5 5
P2 BEDDRB-MA5
BEDDRA-DQU6 B8
6 6
R8 BEDDRA-MA6 BEDDRB-DQU6 B8
6 6
R8 BEDDRB-MA6
BEDDRA-DQU7 A3
7 A 7
R2 BEDDRA-MA7 BEDDRB-DQU1 A3
7 A 7
R2 BEDDRB-MA7
8
T8 BEDDRA-MA8 8
T8 BEDDRB-MA8
BEDDRA-DQSU-N B7
DQSU1 9
R3 BEDDRA-MA9 BEDDRB-DQSU-N D024B B7
DQSU1 9
R3 BEDDRB-MA9
BEDDRA-DQSU-P C7
DQSU2 10
L7 BEDDRA-MA10 BEDDRB-DQSU-P D025B C7
DQSU2 10
L7 BEDDRB-MA10
11
R7 BEDDRA-MA11 11
R7 BEDDRB-MA11
BEDDRA-DQSL-P F3
DQSL
N7 BEDDRA-MA12 BEDDRB-DQSL-P F3
DQSL
N7 BEDDRB-MA12
12 12
BEDDRA-DQSL-N G3
DQSL
T3 BEDDRA-MA13 BEDDRB-DQSL-N G3
DQSL
T3 BEDDRB-MA13
13 13
M7 M7
14 +BEDDRA-VREF 14 +BEDDRB-VREF
BEDDRA-DQL0 E3
0 BC
BEDDRB-DQL7 E3
0 BC
100nF

100nF

100nF

100nF
BEDDRA-DQL1 BEDDRB-DQL1 +1V5-BEDDRB

50V
F7 +1V5-BEDDRA F7
16V

16V
1nF

1nF
1 AP 1 AP F161B

1%
BEDDRA-DQL2 F2
2 F162B
BEDDRB-DQL5 F2
2

1%
BEDDRA-DQL3 BEDDRB-DQL0

R154B

R158B
F8 H1 F8 H1
C223B

C225B

C245B

C224B

C018B

C246B
3 VREFDQ 1% 3 VREFDQ R155B
BEDDRA-DQL4 H3 DQL M8 BEDDRB-DQL6 H3 DQL M8

1K

1K
4 VREFCA 4 VREFCA
BEDDRA-DQL5 H8
5
1K
1%
R152B BEDDRB-DQL3 H8
5 I054B
1K
R160B
1%
BEDDRA-DQL6 G2
6 ZQ
L8 240 BEDDRB-DQL4 G2
6 ZQ
L8
BEDDRA-DQL7 H7
7 I053B R159B
BEDDRB-DQL2 H7
7
240 1%

0
M2 BEDDRA-BA0 0
M2 BEDDRB-BA0
J1
BA 1
N8 BEDDRA-BA1 J1
BA 1
N8 BEDDRB-BA1
J9
2
M3 BEDDRA-BA2 J9
2
M3 BEDDRB-BA2
L1 L1
NC NC
L9
RAS
J3 BEDDRA-RASn L9
RAS
J3 BEDDRB-RASn
T7
ODT
K1 BEDDRA-ODT T7
ODT
K1 BEDDRB-ODT
CAS
K3 D005B BEDDRA-CASn CAS
K3 BEDDRB-CASn
CK
J7 BEDDRA-CLKB-P CK
J7 BEDDRB-CLKB-P
CK
K7 BEDDRA-CLKB-N CK
K7 BEDDRB-CLKB-N
CKE
K9 BEDDRA-CKE CKE
K9 D063B BEDDRB-CKE
CS
L2 BEDDRA-CSn CS
L2 BEDDRB-CSn
WE
L3 BEDDRA-WEn WE
L3 BEDDRB-WEn
RESET
T2 BEDDRA-RSTn RESET
T2 BEDDRB-RSTn

DML
E7 BEDDRA-DML DML
E7 BEDDRB-DML
DMU
D3 BEDDRA-DMU DMU
D3 BEDDRB-DMU
VSSQ VSS VSSQ VSS

100 R133B BEDDRA-CLKB-P 100 R134B BEDDRB-CLKB-P


M9
M1

M9
M1
G9
G1

G8

G8
G9
G1
D8
D1

D8
D1
E8
E2

B9
B1

P9
P1

E1
B3
A9

E1
B3
A9
E8
E2

B9
B1

P9
P1
F9

T9
T1

F9

T9
T1
J8
J2

J8
J2
1% 1%
GND BEDDRA-CLKB-N BEDDRB-CLKB-N

D014B D013B

GND GND

5 2014-02-21

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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 103

10-1-33 B, FPGA - LVDS OUT DEBUG

FPGA - LVDS OUT DEBUG


B B

X331B

DBG TYPE

60 61
58 59
56 57
54 55
52 53
51
50
49
48
47
46
45
44
43
42
PQ-TX2-0N 41
PQ-TX2-0P 40
PQ-TX2-1N 39
PQ-TX2-1P 38
PQ-TX2-2N 37
PQ-TX2-2P 36
35
PQ-TX2-CLKN 34
PQ-TX2-CLKP 33
32
PQ-TX2-3N 31
PQ-TX2-3P 30
PQ-TX2-4N 29
PQ-TX2-4P 28
27
26
PQ-TX3-0N 25
PQ-TX3-0P 24
PQ-TX3-1N 23
PQ-TX3-1P 22
PQ-TX3-2N 21
PQ-TX3-2P 20
19
PQ-TX3-CLKN 18
PQ-TX3-CLKP 17
16
PQ-TX3-3N 15
PQ-TX3-3P 14
PQ-TX3-4N 13
PQ-TX3-4P 12
11
10
9
8
7
6
5
4
+VDISP 3
2
1

5 2014-02-21

BG2-QTV FHD 2K14 715RLPCB000000005

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14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 104

10-1-34 B, MASTER - LVDS RX

MASTER - LVDS RX
B B

U001B
NT72314

LVDS_RX
AK28 K30
CRE0_N ARE0_N
AJ28 J28
CRE0_P ARE0_P
AH29 J30
CRE1_N ARE1_N
AJ29 J29
CRE1_P ARE1_P
AH30 H28
CRE2_N ARE2_N
AJ30 H29
CRE2_P ARE2_P
AG29 G30
CRE3_N ARE3_N
AF28 F28
CRE3_P ARE3_P
AF29 F30
CRE4_N ARE4_N
AE28 F29
CRE4_P ARE4_P
AG28 G28
CRECLK_N ARECLK_N
AG30 G29
CRECLK_P ARECLK_P
AH24 P28
CRO0_N ARO0_N
AJ24 P29
CRO0_P ARO0_P
AK24 N28
CRO1_N ARO1_N
AH25 N29
CRO1_P ARO1_P
AK25 N30
CRO2_N ARO2_N
AJ25 M28
CRO2_P ARO2_P
AH27 L28
CRO3_N ARO3_N
AJ27 L29
CRO3_P ARO3_P
AK27 K28
CRO4_N ARO4_N
AH28 K29
CRO4_P ARO4_P
AH26 M30
CROCLK_N AROCLK_N
AJ26 M29
CROCLK_P AROCLK_P

R029B 100 PQ-TX1-0N PQ-TX1-0N AK18


DRE0_N BRE0_N
Y30
PQ-TX1-0P PQ-TX1-0P AJ18
DRE0_P BRE0_P
W28
R072B 100 PQ-TX1-1N PQ-TX1-1N AH19
DRE1_N BRE1_N
W30
PQ-TX1-1P PQ-TX1-1P AJ19
DRE1_P BRE1_P
W29
R073B 100 PQ-TX1-2N PQ-TX1-2N AH20
DRE2_N BRE2_N
V28
PQ-TX1-2P PQ-TX1-2P AJ20
DRE2_P BRE2_P
V29
R074B 100 PQ-TX1-3N PQ-TX1-3N AK21
DRE3_N BRE3_N
U30
PQ-TX1-3P PQ-TX1-3P AJ21
DRE3_P BRE3_P
T28
R075B 100 PQ-TX1-4N PQ-TX1-4N AH22
DRE4_N BRE4_N
T30
PQ-TX1-4P PQ-TX1-4P AJ22
DRE4_P BRE4_P
T29
R076B 100 PQ-TX1-CLKN PQ-TX1-CLKN AK20
DRECLK_N BRECLK_N
U28
PQ-TX1-CLKP PQ-TX1-CLKP AH21
DRECLK_P BRECLK_P
U29
R077B 100 PQ-TX0-0N PQ-TX0-0N AH14
DRO0_N BRO0_N
AD28
PQ-TX0-0P PQ-TX0-0P AJ14
DRO0_P BRO0_P
AD29
R078B 100 PQ-TX0-1N PQ-TX0-1N AK14
DRO1_N BRO1_N
AC28
PQ-TX0-1P PQ-TX0-1P AH15
DRO1_P BRO1_P
AC29
R079B 100 PQ-TX0-2N PQ-TX0-2N AK15
DRO2_N BRO2_N
AC30
PQ-TX0-2P PQ-TX0-2P AJ15
DRO2_P BRO2_P
AB28
R080B 100 PQ-TX0-3N PQ-TX0-3N AH17
DRO3_N BRO3_N
AA28
PQ-TX0-3P PQ-TX0-3P AJ17
DRO3_P BRO3_P
AA29
R081B 100 PQ-TX0-4N PQ-TX0-4N AK17
DRO4_N BRO4_N
Y28
PQ-TX0-4P PQ-TX0-4P AH18
DRO4_P BRO4_P
Y29
R082B 100 PQ-TX0-CLKN PQ-TX0-CLKN AH16
DROCLK_N BROCLK_N
AB30
PQ-TX0-CLKP PQ-TX0-CLKP AJ16
DROCLK_P BROCLK_P
AB29

MASTER

5 2014-02-21

BG2-QTV FHD 2K14 715RLPCB000000005

19570_053_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 105

10-1-35 B, MASTER - VX1 OUTPUT

MASTER - VX1 OUTPUT


B B

U001B
C328B
C329B
C326B
C327B
C325B

C324B

C323B

TYPE +3V3-NVT
SYS_LVDS_VX1
VB1-TX0N C029B 100nF AJ9 AC2 NTTX-AE0N
10pF
10pF
100nF
100nF
100nF

100nF

100nF

TX0N ATE0_N
VB1-TX0P C030B 100nF 16V AK9
TX0P ATE0_P
AC3 NTTX-AE0P

GREEN
D008B
VB1-TX1N 16V C031B 100nF AJ8 AB2 NTTX-AE1N

DBG
TX1N ATE1_N
RES
RES
RES
RES
RES

RES

RES

VB1-TX1P C032B 100nF 16V AK8


TX1P ATE1_P
AB3 NTTX-AE1P
VB1-TX2N 16V C033B 100nF AJ7
TX2N ATE2_N
AA2 NTTX-AE2N
VB1-TX2P C034B 100nF 16V AK7
TX2P ATE2_P
AA1 NTTX-AE2P
1 VB1-TX3N 16V C035B 100nF AJ6 Y2 NTTX-AE3N 2
TX3N ATE3_N
2 VB1-TX3P C036B 100nF 16V AK6
TX3P ATE3_P
Y3 NTTX-AE3P R289B
3 R009B F221B NT-CTRL-DISP2 VB1-TX4N 16V C037B 100nF AJ5 W2 NTTX-AE4N BC857BW(COL) 1K LOCKn
TX4N ATE4_N
4 I037B R008B 100 NT-CTRL-DISP1 VB1-TX4P C038B 100nF 16V AK5 W3 NTTX-AE4P U024B 1
TX4P ATE4_P
5 I038B
100 VB1-TX5N 16V C039B 100nF AJ4 AA3 NTTX-AECLKN DBG DBG
F026B TX5N ATECLK_N
6 R007B NT-CTRL-DISP4 VB1-TX5P C040B 100nF 16V AK4 Y1 NTTX-AECLKP 3
TX5P ATECLK_P
7 I036B R006B 100 F019B NT-CTRL-DISP3 VB1-TX6N 16V C041B 100nF AJ3 AG2 NTTX-AO0N
TX6N ATO0_N
8 I035B RES R005B 100 NT-CTRL-DISP1 VB1-TX6P C042B 100nF 16V AK3 AG1 NTTX-AO0P

470
TX6P ATO0_P
9 I034B RES R011B 100 F027B SDA-DISP VB1-TX7N 16V C043B 100nF AJ2 AG3 NTTX-AO1N
TX7N ATO1_N
10 I033B RES R010B 47 SCL-DISP VB1-TX7P C044B 100nF 16V AK2 AF1 NTTX-AO1P

DBG
TX7P ATO1_P
11 I032B 47 16V AF2 NTTX-AO2N
F020B ATO2_N
12 X025B VB1-TX7P HTPDn R108B AJ11 AF3 NTTX-AO2P

R312B
HTPDN ATO2_P
13 X026B VB1-TX7N LOCKn R107B 100 F010B AK10 AD2 NTTX-AO3N
LOCKN ATO3_N
14
100 I018B ATO3_P
AD1 NTTX-AO3P
15 R313B 1MEG R234B 12K AJ10
EXT_SWING ATO4_N
AD3 NTTX-AO4N
16 X027B VB1-TX6P X019B AC1 NTTX-AO4P
ATO4_P
17 X028B VB1-TX6N 1 3 AE2 NTTX-AOCLKN
ATOCLK_N
18 AE3 NTTX-AOCLKP

12K

12K
ATOCLK_P

10K

10K

22pF

22pF
19

2
4
R254B

R253B
X029B VB1-TX5P NTTX-BE0N

R204B

R205B
20 N2

50V

50V
12MEGHz R286B BTE0_N
21 X030B VB1-TX5N 100 G1 N3 NTTX-BE0P

C279B

C278B
OSCI BTE0_P
22
BTE1_N
M2 NTTX-BE1N
23 R287B 100 G2
OSCO BTE1_P
M3 NTTX-BE1P
24 X031B VB1-TX4P L2 NTTX-BE2N
BTE2_N
25 X032B VB1-TX4N +3V3-NVT +3V3-NVT L1 NTTX-BE2P
BTE2_P
26 F1
XTAL_BUF_OUT_N BTE3_N
K2 NTTX-BE3N
27 F2
XTAL_BUF_OUT_P BTE3_P
K3 NTTX-BE3P
28 X033B VB1-TX3P J2 NTTX-BE4N
BTE4_N
29 X034B VB1-TX3N BE-RESETn AF11 J3 NTTX-BE4P
SYS_RESET BTE4_P
30
BTECLK_N
L3 NTTX-BECLKN
31
F250B
J4
TEST BTECLK_P
K1 NTTX-BECLKP
32 X035B VB1-TX2P F5 U2 NTTX-BO0N
F002B TEST_MPLL BTO0_N
33 X036B VB1-TX2N V26 U1 NTTX-BO0P
F003B TEST_RX BTO0_P
34
BTO1_N
U3 NTTX-BO1N
35
BTO1_P
T1 NTTX-BO1P
36 X037B VB1-TX1P T2 NTTX-BO2N
BTO2_N
VB1-TX1N

S001B
37 X038B T3 NTTX-BO2P

50m
BTO2_P
38
BTO3_N
P2 NTTX-BO3N
39
BTO3_P
P1 NTTX-BO3P
40 X039B VB1-TX0P P3 NTTX-BO4N
BTO4_N
41 X040B VB1-TX0N BTO4_P
N1 NTTX-BO4P
42
F226B X041B BTOCLK_N
R2 NTTX-BOCLKN
43 LOCKn +3V3-NVT BTOCLK_P
R3 NTTX-BOCLKP
44 X042B HTPDn
45
+3V3-NVT
46
R222B

47
MASTER
4.7K

48
49

470
50
+VDISP
BE-RESETn
51

DBG
53 52
100nF

55 54
R292B
1
2

57 56
16V

59 58
C045B
SKHU
X013B

61 60
DBG

GREEN

+3V3-NVT
D001B

DBG

TYPE
X001B
X055 C271B 100nF
3
4

16V
U013B 3
3

VDD 3

2
2 1 U011B
RESET|RESET
PDTC144EU
DBG
GND 2
1

5 2014-02-21

BG2-QTV FHD 2K14 715RLPCB000000005

19570_054_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 106

10-1-36 B, MASTER - I/O , FLASH

MASTER - I/O , FLASH


B B
U001B
TYPE

BL-I-CTRL AF22
GPIOC_15|PWM_OUT GPIO GPIOA_0|I2C_SLAVE_SCL|MULTI_LVSYNC_OUT|MULTI_IVSYNC_IN
N4
NT-CTRL-DISP1 L27
GPIOC_14|PWM_IN GPIOA_1|I2C_SLAVE_SDA|MULTI_PVSYNC_OUT|MULTI_PVSYNC_IN
N5
MBS8 F26
GPIOC_13|BS8 GPIOA_2|BS0
K26 BS0
MBS7 G27
GPIOC_12|BS7 GPIOA_3|BS1
K27 MBS1
MBS6 G26
GPIOC_11|BS6 GPIOA_4|BS2
J26 MBS2
DB001B L26
GPIOC_10|I2C_M_4_SDA GPIOA_5|3D_LR_IN
V27 PQ-3D-LR
DB002B M27
GPIOC_09|I2C_M_4_SCK GPIOA_6|3D_IR_OUT_0
U26 R212B 22 3D-GOGGLES
SPI0-WP R181B 22 N26
GPIOC_08|SPI_0_WS GPIOA_7|BS3
J27 MBS3
SPI0-HOLD R182B 22 P27
GPIOC_07|SPI_0_HOLD GPIOA_8|3D_IR_OUT_1
U27 NT-CTRL-DISP3
MBS9 M5
GPIOC_06|SPI_1_CS_7|BS9 GPIOA_9|3D_IR_OUT_2
T26 NT-CTRL-DISP4
PQ-3D-LR RES R167B 22 M4
GPIOC_05|SPI_1_CS_6 GPIOA_10|BS4
H26 MBS4
NT-CTRL-DISP2 L5
GPIOC_04|SPI_1_CS_5 GPIOA_11|BS5
H27 MBS5
SPLASH-ON L4
GPIOC_03|SPI_1_CS_4 GPIOA_12|I2C_M2_SCK|LED_SPI_CS3|AMBI_LIGHT
AG16 DB028B
DB003B K5
GPIOC_02|SPI_1_CS_3 GPIOA_13|I2C_M2_SDA|LED_SPI_CK3|AMBI_LIGHT
AF17 R156B 22 NT-AMBI-SPI-CLK
K4 AG17 DB029B
GPIOC_01|SPI_1_CS_2 GPIOA_14|I2C_M3_SCK|LED_SPI_DI3|AMBI_LIGHT
J5
GPIOC_00|SPI_1_CS_1 GPIOA_15|I2C_M3_SDA|LED_SPI_DO3|AMBI_LIGHT
AF18 R157B 22 NT-AMBI-SPI-MOSI
V5
GPIOA_16|MASTER_READY_0
AF16 W4
GPIOB_31|SPI_SLAVER_DO|HSYNC_3 GPIOA_17|MASTER_READY_1
AG15 W5
GPIOB_30|SPI_SLAVER_DI|VSYNC_3 GPIOA_18|MASTER_READY_2
AF15 Y4
GPIOB_29|SPI_SLAVER_CK|VDE_3 GPIOA_19|MASTER_READY_3
AG14 Y5
GPIOB_28|SPI_SLAVER_CS|H_OUT_3 GPIOA_20|SLAVE_SYNC_1
AF14
GPIOB_27|LED_SPI_DO1|HSYNC_2 GPIOA_21|SLAVE_SYNC_2
AA4 NT-LCD-PWR-ON
AG13 AA5
GPIOB_26|LED_SPI_DI1|LED_YDIO1|VSYNC_2 GPIOA_22|SLAVE_SYNC_3
AF13 AB4
GPIOB_25|LED_SPI_CK1|LED_I2C_SDA1|VDE_2 GPIOA_23|SLAVE_SYNC_4
AG12 AB5
GPIOB_24|LED_SPI_CS1|LED_I2C_SCL1|H_OUT_2 GPIOA_24|SLAVE_SYNC_5
BL-DIM8 AG22
GPIOB_23|PWM_7|LED_SPI_DO2|HSYNC_1 GPIOA_25|SLAVE_SYNC_6
AC4
BL-DIM7 AG21
GPIOB_22|PWM_6|LED_SPI_DI2|YDIO0|VSYNC_1 GPIOA_26|SLAVE_SYNC_7
AC5
BL-DIM6 AF21
GPIOB_21|PWM_5|LED_SPI_CK2|LED_I2C_SDA0|VDE_1 GPIOA_27|MULTI_CFG0|PHSYNC_OUT|MULTI_PHSYNC_IN
P4
BL-DIM5 AG20
GPIOB_20|PWM_4|LED_SPI_CS2|LED_I2C_SCL0|H_OUT_1 GPIOA_28|MULTI_CHIP_CFG1
P5 AMBI-SPI-SWITCH
BL-DIM4 AF20
GPIOB_19|PWM_3|LED_SPI_DO0|HSYNC_0 GPIOA_29|MULTI_CHIP_CFG2
R4 R244B 10K BL-ON
BL-DIM3 AG19
GPIOB_18|PWM_2|LED_SPI_DI0|VSYNC_0 GPIOA_30|MULTI_CHIP_CFG3
R5 F206B SWDBG
BL-DIM2 AF19
GPIOB_17|PWM_1|LED_SPI_CK0|VDE_0 GPIOA_31|SLAVE_RESET
T4
BL-DIM1 AG18
GPIOB_16|PWM_0|LED_SPI_CS0|H_OUT_0
R002B 4.7K
V4
GPIOB_15|SPI_1_CS0|MULTI_CHIP GPIOB_0|SPI_0_DI
T27 SPI0-DI
U5
GPIOB_14|SPI_1_CK|MULTI_CHIP GPIOB_1|SPI_0_DO
R26 R170B 22 SPI0-DO
U4
GPIOB_13|SPI_1_DO|MULTI_CHIP GPIOB_2|SPI_0_CK
R27 R171B 22 SPI0-CLK
T5
GPIOB_12|SPI_1_DI|MULTI_CHIP GPIOB_3|SPI_0_CS
P26 R172B 22 SPI0-CS
SDA-BE R201B 47 M26
GPIOB_11|SDA_SLAVER|MAIL_BOX GPIOB_4|ICE_DSU_TX
AD4 R173B 22 M-DSU-TX
SCL-BE R200B 47 N27
GPIOB_10|SCK_SLAVER|MAIL_BOX GPIOB_5|ICE_DSU_RX
AD5 R174B 22 M-DSU-RX
GPIOB_6|UART_RX1
AE4 R175B 22 M-UART-RX
GPIOB_7|UART_TX1
AE5 R176B 22 M-UART-TX
AG11
GPIOB_8|SCK_MASTER
AF12
GPIOB_9|SDA_MASTER

+3V3-NVT

100nF
+3V3-NVT

10K
3

16V
10K

10K

5%

C275B
U009B 1 CTRL-DISP1
PDTC144EU

R206B
U003B
DBG

8
R208B

R300B

10K

10K
M25P16-VMN6P
X312B 2
M-DSU-TX 1 SPI0-DO F212B 5
D
VCC
Q 2
2 FLASH
M-DSU-RX 3 SPI0-CLK F210B 6

R236B

R239B
C
5 4
SPI0-CS F208B 1
S
F229B BS0
TYPE MBS1

22
X313B SPI0-WP F214B 3
W
M-UART-TX 1 MBS2
2 SPI0-HOLD F217B 7
HOLD
M-UART-RX 3 VSS MBS3
5 4

1
2
MBS4

R207B
4
TYPE

DBG
X015B
DBG MBS5

SKHU
X342B MBS6
SPI0-CLK 1 SPI0-DI F219B

3
4
SPI0-CS 2 MBS7
SPI0-DO 3
SPI0-DI 4 MBS8
BE-RESETn 5
6 MBS9
8 7

TYPE
+3V3-NVT DBG

10K

10K

10K

10K

10K

10K

10K

10K
4.7K

4.7K

4.7K

4.7K
5%

5%

5%

5%

R259B

R260B

R262B

R263B

R264B

R265B

R266B

R267B
R224B

R225B

R226B

R227B

DBG
X314B
F238B 1
2
3
M-DSU-RX F240B 4
M-DSU-TX F244B 5
M-UART-RX F246B 7 6
M-UART-TX F248B
TYPE

5 2014-02-21

BG2-QTV FHD 2K14 715RLPCB000000005

19570_050_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 107

10-1-37 B, MASTER - DDR

MASTER - DDR
B B

DDR1V5-M DDR1V5-M

U001B
U004B U005B

H9
H2
F1
E9
D2
C9
C1
A8
A1

R9
R1
N9
N1
K8
K2
G7
D9
B2

H9
H2
F1
E9
D2
C9
C1
A8
A1

R9
R1
N9
N1
K8
K2
G7
D9
B2
DDR3_32BIT
MA0 B15
MA0 DDR1_DQL0
B9 DDRA-DQL0 H5TQ1G63BFR-H9C H5TQ1G63BFR-H9C
MA1 C18
MA1 DDR1_DQL1
A3 DDRA-DQL1
MA2 C14
MA2 DDR1_DQL2
A9 DDRA-DQL2 VDDQ VDD VDDQ VDD
MA3 A12
MA3 DDR1_DQL3
B3 DDRA-DQL3 DDRA-DQU0 D7
0 0
N3 D046B DDR-MA0 DDRB-DQU0 D7
0 0
N3 D061B DDR-MA0
MA4 C19
MA4 DDR1_DQL4
A10 DDRA-DQL4 DDRA-DQU1 C3
1 1
P7 DDR-MA1 DDRB-DQU1 C3
1 1
P7 DDR-MA1
MA5 C12
MA5 DDR1_DQL5
B2 DDRA-DQL5 DDRA-DQU2 D038B C8
2 2
P3 DDR-MA2 DDRB-DQU2 D055B C8
2 2
P3 DDR-MA2
MA6 B19
MA6 DDR1_DQL6
C9 DDRA-DQL6 DDRA-DQU3 D039B C2
3 3
N2 DDR-MA3 DDRB-DQU3 C2
3 3
N2 DDR-MA3
MA7 A13
MA7 DDR1_DQL7
C2 DDRA-DQL7 DDRA-DQU4 A7
4
DQU
4
P8 D047B DDR-MA4 DDRB-DQU4 A7
4
DQU
4
P8 D062B DDR-MA4
MA8 A19
MA8
DDRA-DQU5 A2
5 5
P2 DDR-MA5 DDRB-DQU5 A2
5 5
P2 DDR-MA5
MA9 B14
MA9 DDR1_DQU0
B4 DDRA-DQU0 DDRA-DQU6 B8
6 6
R8 DDR-MA6 DDRB-DQU6 B8
6 6
R8 DDR-MA6
MA10 B21
MA10 DDR1_DQU1
C7 DDRA-DQU1 DDRA-DQU7 A3
7 A 7
R2 DDR-MA7 DDRB-DQU7 A3
7 A 7
R2 DDR-MA7
MA11 A18
MA11 DDR1_DQU2
A4 DDRA-DQU2 8
T8 DDR-MA8 8
T8 DDR-MA8
MA12 B20
MA12 DDR1_DQU3
B8 DDRA-DQU3 DDRA-DQSU-N D040B B7
DQSU1 9
R3 DDR-MA9 DDRB-DQSU-N D056B B7
DQSU1 9
R3 DDR-MA9
MA13 C13
MA13 DDR1_DQU4
B5 DDRA-DQU4 DDRA-DQSU-P D041B C7
DQSU2 10
L7 D048B DDR-MA10 DDRB-DQSU-P D057B C7
DQSU2 10
L7 DDR-MA10
DDR1_DQU5
B7 DDRA-DQU5 11
R7 DDR-MA11 11
R7 DDR-MA11
MBA0 C11
MBA0 DDR1_DQU6
C4 DDRA-DQU6 DDRA-DQSL-P D042B F3
DQSL
N7 DDR-MA12 DDRB-DQSL-P D058B F3
DQSL
N7 DDR-MA12
12 12
MBA1 C20
MBA1 DDR1_DQU7
A7 DDRA-DQU7 DDRA-DQSL-N D043B G3
DQSL
T3 DDR-MA13 DDRB-DQSL-N D059B G3
DQSL
T3 DDR-MA13
13 13
MBA2 B12
MBA2
M7 M7
14 14

R019B

R021B
DDR1_DQSL_P
C6 DDRA-DQSL-P DDRA-DQL0 D044B E3
0 BC
DDRB-DQL0 E3
0 BC

100nF

100nF
MWEn A15 A6 DDRA-DQSL-N DDRA-DQL1 F7 F215B DDR1V5-M DDRB-DQL1 F7 DDR1V5-M

1nF

1nF
MWE DDR1_DQSL_N 1 AP 1 AP F235B
MCASn C15 DDRA-DQL2 F2 DDRB-DQL2 F2

16V

50V

16V

50V
MCAS 2 2
MRASn DDRA-DQSU-P DDRA-DQL3 DDRB-DQL3

1%
A16 B6 F8 H1 F8 H1

C067B

C071B

C068B

C072B
MRAS DDR1_DQSU_P 3 VREFDQ 1% 3 VREFDQ R020B
C5 DDRA-DQSU-N DDRA-DQL4 H3 DQL M8 DDRB-DQL4 D060B H3 DQL M8

1K

1K
DDR1_DQSU_N 4 VREFCA 4 VREFCA
MCKE A21
DDR_MCKE
DDRA-DQL5 H8
5
1K
1%
R018B DDRB-DQL5 H8
5
1K
R246B
1%
MODT B10
DDR_ODT DDR1_DML
C3 DDRA-DML DDRA-DQL6 G2
6 ZQ
L8 240 DDRB-DQL6 G2
6 ZQ
L8
MRSTn B13
DDR_MRST DDR1_DMU
C8 DDRA-DMU DDRA-DQL7 D045B H7
7
R245B DDRB-DQL7 H7
7
240 1%

0
M2 DDRM-BA0 0
M2 DDRM-BA0
MCS0n C10
DDR_CS0 DDR2_DQL0
B28 DDRB-DQL0 J1
BA 1
N8 D049B DDRM-BA1 J1
BA 1
N8 D064B DDRM-BA1
MCS1n B11
DDR_CS1 DDR2_DQL1
C22 DDRB-DQL1 J9
2
M3 DDRM-BA2 J9
2
M3 DDRM-BA2
DDR2_DQL2
C28 DDRB-DQL2 L1
NC
L1
NC
MCLKA-P C16
DDR1_MCLK0_P DDR2_DQL3
B22 DDRB-DQL3 L9
RAS
J3 DDR-MRASn L9
RAS
J3 DDR-MRASn
MCLKA-N B17
DDR1_MCLK0_N DDR2_DQL4
C29 DDRB-DQL4 T7
ODT
K1 DDR-MODT T7
ODT
K1 DDR-MODT
DDR2_DQL5
C21 DDRB-DQL5 CAS
K3 DDR-MCASn CAS
K3 DDR-MCASn
MCLKB-P C17
DDR2_MCLK0_P DDR2_DQL6
B29 DDRB-DQL6 CK
J7 D050B DDR-MCLKA-P CK
J7 D065B DDR-MCLKB-P
MCLKB-N B18
DDR2_MCLK0_N DDR2_DQL7
A22 DDRB-DQL7 CK
K7 D051B DDR-MCLKA-N CK
K7 D066B DDR-MCLKB-N
CKE
K9 D052B DDR-MCKE CKE
K9 D067B DDR-MCKE
DDR1V5-M R015B 1K B16
BYPASS_TEST0 DDR2_DQU0
B24 DDRB-DQU0 CS
L2 D053B DDR-MCS0n CS
L2 D068B DDR-MCS1n DDR-MCS1n
RES DDR2_DQU1
A27 DDRB-DQU1 WE
L3 DDR-MWEn DDR-MCS0n WE
L3 DDR-MWEn
R016B 1K H15
DDR_VREF DDR2_DQU2
C23 DDRB-DQU2 RESET
T2 DDR-MRSTn RESET
T2 DDR-MRSTn

1K
1% DDR2_DQU3
C27 DDRB-DQU3

1K
C24 DDRB-DQU4 E7 DDRA-DML E7 D069B DDRB-DML

RES

RES
DDR2_DQU4 DML DML
F232B DDR2_DQU5
B27 DDRB-DQU5 DMU
D3 D054B DDRA-DMU DMU
D3 DDRB-DMU
1K

100nF

DDRB-DQU6
10nF

A24

R215B
DDR2_DQU6 VSSQ VSS VSSQ VSS
1%

C26 DDRB-DQU7

R214B
16V

16V

DDR2_DQU7
C001B

C003B

B26 DDRB-DQSL-P
R017B

DDR2_DQSL_P
DDRB-DQSL-N

M9
M1

M9
M1
G8
G9
G1

G9
G1

G8
D8
D1

D8
D1
P9
P1

E1
B3
A9
E8
E2

B9
B1

E8
E2

B9
B1

P9
P1

E1
B3
A9
F9

T9
T1

F9

T9
T1
C25

J8
J2

J8
J2
DDR2_DQSL_N

DDR2_DQSU_P
B25 DDRB-DQSU-P
DDR2_DQSU_N
A25 DDRB-DQSU-N

DDR2_DML
B23 DDRB-DML
DDR2_DMU
A28 DDRB-DMU

MBA1 R030B 22 DDRM-BA1 DDR-MA0 R038B 22 MA0


4 5
1%
MA12 R030B 22 DDR-MA12 DDR-MCKE R039B 22 MCKE
3 6
1%

MA4 R030B 22 DDR-MA4 DDR-MA10 R040B 22 MA10


2 7
1%
MA6 R030B 22 DDR-MA6 DDR-MRASn R041B 22 MRASn
1 8
1%
DDR-MCASn R042B 22 MCASn
1%
DDR-MWEn R043B 22 MWEn
MA8 R031B 22 DDR-MA8 1%
4 5 DDR-MA7 R316B 22 MA7
MA1 R031B 22 DDR-MA1 1%
3 6 DDR-MCS0n R045B 22 MCS0n
1% D031B D032B D033B D028B
MA11 R031B 22 DDR-MA11 DDR-MCS1n R318B 22 MCS1n
2 7
1%
DDR-MCLKA-N R047B 1 MCLKA-N

DDR-MCLKA-P R048B 1 MCLKA-P

MA2 R032B 22 DDR-MA2 DDR-MCLKB-N R049B 1 MCLKB-N


4 5
MA9 R032B 22 DDR-MA9 DDR-MCLKB-P R050B 1 MCLKB-P
3 6 DDR1V5-M

MA13 R032B 22 DDR-MA13 R052B 1K


2 7
1%
MRSTn R032B 22 DDR-MRSTn DDR-MODT R051B 22 MODT
1 8
1%

100
MA5 R033B 22 DDR-MA5 DDR-MCLKA-P R068B
4 5
1%
MA3 R033B 22 DDR-MA3 DDR-MCLKA-N DDR1V5-M
3 6
L001B I026B
DDR-MCLKB-P R069B 100
+1V5-M
MBA2 R033B 22 DDRM-BA2 1% 30H
2 7 DDR-MCLKB-N

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
MBA0 R033B 22 DDRM-BA0

10uF

10uF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF
1 8

6,3V

6,3V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V
RES

RES

RES

RES

RES

RES

RES

RES
C063B

C064B

C004B

C005B

C006B

C007B

C008B

C318B
C009B

C010B

C011B

C012B

C311B

C312B

C314B

C315B

C316B

C317B
C013B

C014B

C015B

C313B
X017B X065B
1 1

5 2014-02-21

BG2-QTV FHD 2K14 715RLPCB000000005

19570_056_140523.eps
14-05-23

2014-Oct-22 back to
div.table
10-1-38

+2V5-M
+2V5-M
+1V0-M
B, MASTER - POWER

220H
220H

L012B
L011B
C258B 10uF C257B 10uF

6,3V 6,3V

J9

L9

P8
K9

N9
N8
H9

M9
J24
J23
J22
J21
J20
J11
J10

L22
F24
F23

P22
K22
E30
E29
E28
E27
E26
E25
E24
E23
B30

R22
N22
H24
H23
H22
H21
H20
H11
H10
D30
D29
D28
D27
D26
D25
D24
D23
C30

G24
G23

M22

I015B
I014B
TYPE
U001B
MASTER - POWER

C146B 100nF C141B 100nF


CORE_1.0V_9
CORE_1.0V_8
CORE_1.0V_7
CORE_1.0V_6
CORE_1.0V_5
CORE_1.0V_4
CORE_1.0V_3
CORE_1.0V_2
CORE_1.0V_1

CORE_1.0V_50
CORE_1.0V_49
CORE_1.0V_48
CORE_1.0V_47
CORE_1.0V_46
CORE_1.0V_45
CORE_1.0V_44
CORE_1.0V_43
CORE_1.0V_42
CORE_1.0V_41
CORE_1.0V_40
CORE_1.0V_39
CORE_1.0V_38
CORE_1.0V_37
CORE_1.0V_36
CORE_1.0V_35
CORE_1.0V_34
CORE_1.0V_33
CORE_1.0V_32
CORE_1.0V_31
CORE_1.0V_30
CORE_1.0V_29
CORE_1.0V_28
CORE_1.0V_27
CORE_1.0V_26
CORE_1.0V_25
CORE_1.0V_24
CORE_1.0V_23
CORE_1.0V_22
CORE_1.0V_21
CORE_1.0V_20
CORE_1.0V_19
CORE_1.0V_18
CORE_1.0V_17
CORE_1.0V_16
CORE_1.0V_15
CORE_1.0V_14
CORE_1.0V_13
CORE_1.0V_12
CORE_1.0V_11
CORE_1.0V_10

16V 16V

C147B 100nF C142B 100nF D13


CORE_1.0V_51 DDR_MMU_1.5V_1
RES 16V R8 D14
16V CORE_1.0V_52 DDR_MMU_1.5V_2
T22 E13
CORE_1.0V_53 DDR_MMU_1.5V_3
C148B 100nF C143B 100nF T8 E14
CORE_1.0V_54 DDR_MMU_1.5V_4
U22 F13
16V 16V CORE_1.0V_55 DDR_MMU_1.5V_5
U8 F14
CORE_1.0V_56 DDR_MMU_1.5V_6
V22 G13
CORE_1.0V_57 DDR_MMU_1.5V_7
C149B 100nF C144B 100nF V8 G14
CORE_1.0V_58 DDR_MMU_1.5V_8
RES 16V W22 H13
16V CORE_1.0V_59 DDR_MMU_1.5V_9
W8 H14
CORE_1.0V_60 DDR_MMU_1.5V_10
C150B 100nF C145B 100nF Y22 H17
CORE_1.0V_61 DDR_MMU_1.5V_11
Y8 H18
16V 16V CORE_1.0V_62 DDR_MMU_1.5V_12

TX-2.5V-M
RX-2.5V-M
Y9 J13
CORE_1.0V_63 DDR_MMU_1.5V_13
AA14 J14
CORE_1.0V_64 DDR_MMU_1.5V_14
AA15 J17
MMU-1.5V-M

CORE_1.0V_65 DDR_MMU_1.5V_15
AA16 J18
CORE_1.0V_66 DDR_MMU_1.5V_16
AA17 K13
CORE_1.0V_67 DDR_MMU_1.5V_17
Circuit Diagrams and PWB Layouts

AA18

+2V5-M
+2V5-M
CORE_1.0V_68 DDR_MMU_1.5V_18 K14
POWER

AA19 K16
CORE_1.0V_69 DDR_MMU_1.5V_19
AA20 K17
CORE_1.0V_70 DDR_MMU_1.5V_20
AA21 K18
CORE_1.0V_71 DDR_MMU_1.5V_21
AA22 K19
CORE_1.0V_72 DDR_MMU_1.5V_22
AA8
CORE_1.0V_73

220H
220H

L014B
L013B
AA9 P9
CORE_1.0V_74 TX_2.5_1
AB10 R9
CORE_1.0V_75 TX_2.5_2
TX-2.5V-M

C260B 10uF C259B 10uF AB11 T9


CORE_1.0V_76 TX_2.5_3
AB12 U9
6,3V 6,3V CORE_1.0V_77 TX_2.5_4
AB13 V9
CORE_1.0V_78 TX_2.5_5
AB14 W9
CORE_1.0V_79 TX_2.5_6
AB15
CORE_1.0V_80

I013B
QV14.1E LA

AB16 AC9
CORE_1.0V_81 VX1_2.5V_1

I012B
AB9 AC10
VX1_2.5V_2
MPLL_2.5V_1 VX1_2.5V_3 AC11
C156B 100nF C151B 100nF F3 AC12
MPLL_2.5V_2 VX1_2.5V_4
F4 AC13
16V 16V VX1_2.5V_5
VX-2.5V-M

C157B 100nF C152B 100nF


IO_3.3V_15
IO_3.3V_14
IO_3.3V_13
IO_3.3V_12
IO_3.3V_11
IO_3.3V_10

RX_2.5V_15
RX_2.5V_14
RX_2.5V_13
RX_2.5V_12
RX_2.5V_11
RX_2.5V_10
RX_2.5V_9
RX_2.5V_8
RX_2.5V_7
RX_2.5V_6
RX_2.5V_5
RX_2.5V_4
RX_2.5V_3
RX_2.5V_2
RX_2.5V_1
IO_3.3V_9
IO_3.3V_8
IO_3.3V_7
IO_3.3V_6
IO_3.3V_5
IO_3.3V_4
IO_3.3V_2
IO_3.3V_1

DDR_VCCAD_1.0V_4
DDR_VCCAD_1.0V_3
DDR_VCCAD_1.0V_2
DDR_VCCAD_1.0V_1
DDR_CLK_1.5V_2
DDR_CLK_1.5V_1
DDR_DLL_2.5V_2
DDR_DLL_2.5V_1
10.

16V 16V

MPLL-2.5V-M
C153B 100nF

MPLL-2.5V-M
J19
J12
H19
H12
E15
D15
K15
J15
AB23
AB22
AB21
AB20
AB19
AB18
AB17
AA23
Y23
W23
V23
U23
T23
R23
P23
AC23
AC22
AC21
AC16
AC15
AC14
N23
M8
M23
L8
L23
K23
K8
J8

RES 16V

C154B 100nF

16V
EN 108

I/O-3.3V-M

C155B 100nF

16V

VX-2.5V-M

2014-Oct-22 back to
div.table
RX-2.5V-M

DLL-2.5V-M

DDR-AD1.0V-M
DDRCLK-1.5V-M

+2V5-M

L005B

220H
+1V0-M

220H
L015B

C261B 10uF

6,3V
SENSE+1V0M

I011B
DDR1V5-M
DDR-AD1.0V-M
X007B

I007B

220H
L003B

C158B 100nF

16V
C256B 10uF C255B 10uF
C159B 100nF C319B 10uF
6,3V 6,3V
16V 6.3V
DLL-2.5V-M
I009B

C116B 100nF C112B 100nF C099B 100nF


F034B

16V RES 16V RES 16V


C130B 100nF C119B 100nF C113B 100nF C100B 100nF C087B 100nF C075B 100nF

16V 16V RES 16V 16V RES 16V 16V

C131B 100nF C120B 100nF C114B 100nF C101B 100nF C088B 100nF C076B 100nF

16V 16V 16V 16V RES 16V 16V

C132B 100nF C121B 100nF C115B 100nF C102B 100nF C089B 100nF C077B 100nF

16V 16V 16V 16V 16V 16V


+3V3-NVT

C133B 100nF C122B 100nF C103B 100nF C090B 100nF C078B 100nF
RES 16V 16V 16V 16V RES 16V
220H
L016B

C134B 100nF C123B 100nF C104B 100nF C091B 100nF C079B 100nF

16V 16V 16V 16V 16V


+1V5-M

C262B 10uF
C135B 100nF C124B 100nF C105B 100nF C092B 100nF C080B 100nF
6,3V
16V 16V 16V RES 16V 16V
220H
L004B

C160B 100nF C136B 100nF C125B 100nF C106B 100nF C093B 100nF C081B 100nF

16V RES 16V RES 16V 16V 16V 16V


I008B

C161B 100nF C137B 100nF C126B 100nF C107B 100nF C094B 100nF C082B 100nF
RES 16V 16V 16V 16V RES 16V 16V
C320B 10uF
C162B 100nF C138B 100nF C127B 100nF C108B 100nF C095B 100nF C083B 100nF
6.3V
16V RES 16V RES 16V 16V RES 16V 16V
C117B 100nF
BG2-QTV FHD 2K14

16V
C163B 100nF C139B 100nF C128B 100nF C109B 100nF C096B 100nF C084B 100nF
RES C118B 100nF
16V 16V RES 16V 16V 16V 16V
16V
C164B 100nF C140B 100nF C129B 100nF C110B 100nF C097B 100nF C085B 100nF
DDRCLK-1.5V-M

RES 16V 16V 16V RES 16V RES 16V 16V


I/O-3.3V-M
I010B
MMU-1.5V-M

C111B 100nF C098B 100nF C086B 100nF

16V 16V 16V


I/O-3.3V-M

715RLPCB000000005
B

5
2014-02-21

14-05-23
19570_057_140523.eps
10-1-39

B
B, MASTER - GND

E9
E8
E7
E6
E5
E4
E3
B1

D9
D8
D7
D6
D5
D4
D3
D2
D1
C1

G4
G3
F11

E17
E22
E21
E20
E19
E18
E12
E11
E10

D17
D22
D21
D20
D19
D18
D12
D11
D10
TYPE
MASTER - GND

U001B

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
VX_GND_1

MPLL_GND_2
MPLL_GND_1
Y10 F12
VX_GND_2 GND_36
Y11 F18

DDR_APLL_GND_2
DDR_APLL_GND_1
VX_GND_3 GND_37
Y12 F19
VX_GND_4 GND_38
Y13 F20
VX_GND_5 GND_39
AA10 F21
VX_GND_6 GND_40
AA11 F22
VX_GND_7 GND_41
AA12 G11
VX_GND_8 GND_42
AA13 G12
VX_GND_9 GND_43
AG10 G18
VX_GND_10 GND_44
AG4 G19
VX_GND_11 GND_45
AG5 G20
VX_GND_12 GND_46
AG6 G21
VX_GND_13 GND_47
AG7 G22
VX_GND_14 GND_48
AG8 K10
VX_GND_15 GND_49
AG9 K11
VX_GND_16 GND_50
AH1 K12
VX_GND_17 GND_51
AH10 K20
VX_GND_18 GND_52
AH11 K21
VX_GND_19 GND_53
Circuit Diagrams and PWB Layouts

AH12 L10
VX_GND_20 GND_54
AH2 L11
VX_GND_21 GND_55
AH3 L12
VX_GND_22 GND_56
AH4 L13
VX_GND_23 GND_57
AH5 L14
VX_GND_24 GND_58
AH6 L15
VX_GND_25 GND_59
AH7 L16
VX_GND_26 GND_60
AH8 L17
VX_GND_27 GND_61
AH9 L18
VX_GND_28 GND_62
AJ1 L19
VX_GND_29 GND_63
AJ12 L20
VX_GND_30 GND_64
AK12 L21
QV14.1E LA

GND_65
LVDS_TX_GND_1 GND_66 M10
H2 M11
LVDS_TX_GND_2 GND_67
H3 M12
LVDS_TX_GND_3 GND_68
H4 M13
LVDS_TX_GND_4 GND_69
N6 M14
LVDS_TX_GND_5 GND_70
P6 M15
LVDS_TX_GND_6 GND_71
10.

R6 M16
LVDS_TX_GND_7 GND_72
T6 M17
LVDS_TX_GND_8 GND_73
U6 M18
LVDS_TX_GND_9 GND_74
V2 M19
LVDS_TX_GND_10 GND_75
V3 M20
LVDS_TX_GND_11 GND_76
V6 M21
LVDS_TX_GND_12 GND_77
W6 N10
LVDS_TX_GND_13 GND_78
EN 109

Y6 N11
LVDS_TX_GND_14 GND_79
AF4 N12
GND

LVDS_TX_GND_15 GND_80
AF5 N13
GND_81
LVDS_RX_GND_1 GND_82 N14
R28 N15

2014-Oct-22 back to
div.table
LVDS_RX_GND_2 GND_83
R29 N16
LVDS_RX_GND_3 GND_84
W26 N17
LVDS_RX_GND_4 GND_85
W27 N18
LVDS_RX_GND_5 GND_86
Y26 N19
LVDS_RX_GND_6 GND_87
Y27 N20
LVDS_RX_GND_7 GND_88
AA26 N21
LVDS_RX_GND_8 GND_89
AA27 P10
LVDS_RX_GND_9 GND_90
AB26 P11
LVDS_RX_GND_10 GND_91
AB27 P12
LVDS_RX_GND_11 GND_92
AC26 P13
LVDS_RX_GND_12 GND_93
AC27 P14
LVDS_RX_GND_13 GND_94
AD26 P15
LVDS_RX_GND_14 GND_95
AD27 P16
LVDS_RX_GND_15 GND_96
AE23 P17
LVDS_RX_GND_16 GND_97
AE24 P18
LVDS_RX_GND_17 GND_98
AE25 P19
LVDS_RX_GND_18 GND_99
AE26 P20
LVDS_RX_GND_19 GND_100
AE27 P21
LVDS_RX_GND_20 GND_101
AE29 R10
LVDS_RX_GND_21 GND_102
AE30 R11
LVDS_RX_GND_22 GND_103
AF23 R12
LVDS_RX_GND_23 GND_104
AF24 R13
LVDS_RX_GND_24 GND_105
AF25 R14
LVDS_RX_GND_25 GND_106
AF26 R15
LVDS_RX_GND_26 GND_107
AF27 R16
LVDS_RX_GND_27 GND_108
AG23 R17
LVDS_RX_GND_28 GND_109
AG24 R18
LVDS_RX_GND_29 GND_110
AG25 R19
LVDS_RX_GND_30 GND_111
AG26 R20
LVDS_RX_GND_31 GND_112
AG27 R21
LVDS_RX_GND_32 GND_113
AH13 T10
LVDS_RX_GND_33 GND_114
AH23 T11
LVDS_RX_GND_34 GND_115
AJ13 T12
LVDS_RX_GND_35 GND_116
AJ23 T13
GND_117
DDR_CLK_GND1 GND_118 T14
D16 T15
DDR_CLK_GND2 GND_119
E16
GND_169
GND_168
GND_167
GND_166
GND_165
GND_164
GND_163
GND_162
GND_161
GND_160
GND_159
GND_158
GND_157
GND_156
GND_155
GND_154
GND_153
GND_152
GND_151
GND_150
GND_149
GND_148
GND_147
GND_146
GND_145
GND_144
GND_143
GND_142
GND_141
GND_140
GND_139
GND_138
GND_137
GND_136
GND_135
GND_134
GND_133
GND_132
GND_131
GND_130
GND_129
GND_128
GND_127
GND_126
GND_125
GND_124
GND_123
GND_122
GND_121
GND_120

Y21
Y20
Y19
Y18
Y17
Y16
Y15
Y14
W21
W20
W19
W18
W17
W16
W15
W14
W13
W12
W11
W10
V21
V20
V19
V18
V17
V16
V15
V14
V13
V12
V11
V10
U21
U20
U19
U18
U17
U16
U15
U14
U13
U12
U11
U10
T21
T20
T19
T18
T17
T16

BG2-QTV FHD 2K14


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5
2014-02-21

14-05-23
19570_058_140523.eps
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 110

10-1-40 B, NOVATEK SUPPLY

NOVATEK SUPPLY
B B
L022B
RES
30H
L010B I097B
+12V
30H

100nF
10uF

10uF

100nF
16V 10uF
16V

16V

16V

C345B

C299B
C343B

C344B

C292B

16V
RES
U028B
TPS54494PWP

1 16
VIN1 VIN2
L027B L028B F021B
100nF C293B I090B 2 15 C294B 100nF
+1V0-M 1.5uH
VBST1 VBST2
1.5uH
+1V5-M
16V I075B 16V
22uF

22uF

22uF

22uF

22uF

22uF
3 14
SW1 SW2
6,3V

6,3V

6,3V

6,3V

6,3V

6,3V
RES

10 R196B 4 13
C369B

C368B

C367B

C370B

C371B

C372B
PGND1 PGND2
5 4

RES
I065B
5
EN1 EN2
12 ENABLE+1V5+2V5
10 R196B
D004B I077B
6 3 6 11 R233B 470

1nF
PG1 PG2 +3V3

50V
LTST-C190 RED 5%
10 R196B 7 10

C357B
1nF
VFB1 VFB2
7 2 R197B 10

50V
I082B 9 I079B 4 5

C352B

GND_HS
VREG5
F031B C354B 1nF C353B 10 R196B

GND
8 1 R197B 10 C355B 1nF C356B 1nF
50V 1nF 50V I085B
R184B 10K GND-D3 3 6

1uF
+3V3 I096B 50V 50V

17

16V
8
RES GND-D3 R197B 10

C381B
DETECT12V S010B 2 7
BE-ENABLE RES I092B
GND-D3
R197B 10
ENABLE+3V3-NVT 1 8
+3V3-NVT I094B
X003B 22K R120B +1V5-M
C386B 1uF R238B 8.2K I074B
+1V0-M 1%
6.3V 1%
+5V-FE R250B
GND-D3 RES C378B
22K

SENSE+1V0M 10 C377B RES

220K
22pF 50V
R088B

470K

22K
50V 22pF

5%
F012B I069B

22K

1%
R112B
ENABLE+1V5+2V5

1%
22K

I049B

R153B
RES
R087B

R119B
+5V-FE +3V3 +3V3

R118B

RES
I047B 2 U017B
BC847BS(COL)
3
GND-D3 GND-D3

1
1
R089B

R109B

R110B
47K I048B 5 U017B GND-D3 GND-D3
+3V3-NVT BC847BS(COL)
22K

RES
L023B
4

RES
30H
R086B

3
I066B U025B
1 AO3414
2
U002B I042B

22K
BC857BW(COL)
2

RES 10K
F022B

10
+3V3-NVT

RES
R003B
1

R106B
2

R014B
3 C017B 100nF
ENABLE+3V3-NVT R105B 22K C016B 100nF RES 16V
10uF

U026B 1
I043B
I016B RES 16V
6,3V

I019B
RT9187GSP
C337B

3 +3V3 U029B
U006B RT9715EGB
1 3 F223B
VIN1 VOUT1 BC857BW(COL)
F024B 5 1
F023B VIN VOUT
2 4 +2V5-M
+3V3 VIN2 VOUT2 I017B
4 3
EN|EN NC
1MEG

7
47K

22K

10K

22K
NC

100nF
GND

10uF

10uF
1%

ENABLE+1V5+2V5 8 5

6,3V

6,3V
16V
RES

RES

EN BP|ADJ

C338B
C002B

C302B
2
GND GND_HS
R240B

R113B

R123B

R104B

R103B
I068B
10uF

I067B
100uF 16V
C339B

6,3V

1MEG
C303B

22K

10nF
RES

1%

16V
RES

RES
C358B
R121B

R114B

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 111

10-1-41 B, SCALER POWER

SCALER POWER
B B

F004B

F005B

F007B

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 112

10-1-42 B, LVDS OUTPUT

LVDS OUTPUT
B B
X050

TYPE
50 51
48 49 +3V3-NVT
46 47
44 45

1K
42 43

10pF
10pF
10pF
10pF
1nF
1nF
1nF
1nF
1nF

1nF
F203B
41

RES
40

C214B
C215B
C205B
C206B
C213B
C216B
C217B
C211B
C212B
C218B
X051
39

R143B
38 TYPE
F202B
37 60 61

RES
RES
RES
RES
RES
RES
RES
RES
RES
RES
36 58 59
35 56 57
34 NT-CTRL-DISP1 R319B 100 RES 54 55
33 52 53
NTTX-BO0N F168B 32 NT-CTRL-DISP3 R135B 100 I059B 51
NTTX-BO0P F169B 31 SDA-DISP R001B 10 RES I056B 50
NTTX-BO1N F170B 30 SCL-DISP R044B 10 RES I055B 49
NTTX-BO1P F171B 29 SDA-DISP R165B 47 RES I051B 48
NTTX-BO2N F172B 28 SCL-DISP R166B 47 RES I046B 47
NTTX-BO2P F173B 27 NT-CTRL-DISP4 R139B 100 RES I045B 46
26 45
NTTX-BOCLKN F174B 25 NT-CTRL-DISP1 R140B 100 I041B 44
NTTX-BOCLKP F175B 24 NT-CTRL-DISP2 R136B 100 F070B 43
23 NT-CTRL-DISP3 R137B 100 RES I040B 42
NTTX-BO3N F176B 22 41
NTTX-BO3P F177B 21 NTTX-AO0N F119B 40
NTTX-BO4N F178B 20 NTTX-AO0P F122B 39
NTTX-BO4P F179B 19 NTTX-AO1N F136B 38
18 NTTX-AO1P F137B 37
17 NTTX-AO2N F138B 36
NTTX-BE0N F180B 16 NTTX-AO2P F139B 35
NTTX-BE0P F181B 15 34
NTTX-BE1N F182B 14 NTTX-AOCLKN F140B 33
NTTX-BE1P F183B 13 NTTX-AOCLKP F141B 32
NTTX-BE2N F184B 12 31
NTTX-BE2P F185B 11 NTTX-AO3N F142B 30
10 NTTX-AO3P F143B 29
NTTX-BECLKN F186B 9 NTTX-AO4N F147B 28
NTTX-BECLKP F187B 8 NTTX-AO4P F148B 27
7 NT-CTRL-DISP3 RES R141B 100 I060B 26
NTTX-BE3N F189B 6 C204B 10pF RES I061B 25
NTTX-BE3P F188B 5 NTTX-AE0N F150B 24
NTTX-BE4N F190B 4 NTTX-AE0P F151B 23
NTTX-BE4P F191B 3 NTTX-AE1N F155B 22
2 NTTX-AE1P F156B 21
1 NTTX-AE2N F157B 20
NTTX-AE2P F158B 19
18
NTTX-AECLKN F159B 17
NTTX-AECLKP F163B 16
15
NTTX-AE3N F164B 14
NTTX-AE3P F165B 13
NTTX-AE4N F166B 12
NTTX-AE4P F167B 11
4 S003B 5 I063B 10
3 S003B 6 I064B 9
2 S003B 7

10pF
8
1 S003B 8 7
6

C203B
5
4
3

RES
+VDISP
2
1

100nF

16V
C202B
5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 113

10-1-43 B, RF4CE

RF4CE
B B
+3V3-STANDBY

L001E

30H
I007E
X004E
1 3

100nF

220pF

100nF

100nF

100nF

100nF
10uF
1uF
15pF

15pF

6.3V

6.3V
16V

50V

16V

16V

16V

16V
2
4
I010E

C002E

C012E

C003E

C004E

C010E

C016E

C005E

C006E
50V

50V
C008E

C009E

1uF
U003E

28
27
24
29
21
31

40
39
10
+3V3-STANDBY

6.3V
+3V3-STANDBY CC2533F96RHA

C011E
X003E

AVDD1
AVDD2
AVDD3
AVDD4
AVDD5
AVDD6

DCOUPL
DVDD1
DVDD2
U004E GND
U001E

10K
LFB18
100nF

22 FEED
RT9818C-29GVL XOSC_Q1 I004E

5%
3
16V

3
BAL1 I006E L002E

R002E
VDD RES 23 1
C007E

RES
XOSC_Q2 I005E UNBAL
25 4 4.7nH
RES

F004E RF_P BAL2 GND

C014E
20 26
RESET|RESET RESET_N RF_N

50V
10nF
19 36

470fF
2
5
6
P0_0 P2_0
GND 18 35
16V
P0_1 P2_1
17 34
C001E

P0_2 P2_2
16 33
RES

P0_3 P2_3|XOSC32K_Q2
15 32
P0_4 P2_4|XOSC32K_Q1 F010E F006E
14
P0_5
RF4CE-DD
13
P0_6 I003E
RF4CE-DC
RF4CE-RESETn 12
P0_7 RBIAS
30
F007E

10pF
56K
F003E
SOC-TXD-RF4CE R004E 10 11 2

50V
P1_0 SCL

5%
9

C015E
F002E 5% P1_1
SOC-RXD-RF4CE R005E 10 8
P1_2 SDA
3
7

R006E
5% F009E P1_3
6 4
P1_4 NC2
+3V3-STANDBY 5
P1_5 NC1
1
38
P1_6
37
P1_7
GND_HS DBG
100K

X303
5%

41
R003E

2
RES

F005E +3V3-STANDBY
F001E
RF4CE-DC 3
RC RF4CE-DD 4
5
3 6
I002E R001E I001E
RF4CE-RESETn 7
U002E 1 10K 8
BC847BW(COL) S001E 9
5% +3V3-STANDBY 50m 10
2
FTSH
R011E
10K
+3V3
RES 5%
X027

R009E
RF4CE-RESETn 1
10K SOC-TXD-RF4CE SOC-TXD-RF4CE 2
+3V3-STANDBY
5% 3
R010E
X001E 10K SOC-RXD-RF4CE SOC-RXD-RF4CE 4
TSOP75236 +3V3-STANDBY
5% 5
I008E
R007E 100 2
VS R012E
RC 6
+3V3-STANDBY 10K
DBG I009E +3V3
7
RC R008E 10 3
OUT
RES 5% 8
+3V3-STANDBY
DBG 9 10
100nF

10pF

1
1uF

GND1
4 FH52
6.3V

16V

50V

GND2
C017E

C019E

C018E

DBG DBG
DBG

DBG
DBG

F008E
X311
1
2
3
5 4

TYPE

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 114

10-1-44 B, MARVELL - AmbiLight + DIAGNOSTIC SERIAL FLASH + EMMC

MARVELL - AMBILIGHT + DIAGNOSTIC SERIAL FLASH + EMMC


B B
+3V3-MRV

RES

RES
RES

RES
RES

RES
10K

10K

10K

10K

10K

10K

10K
U001T

R214T

R217T

R219T

R220T

R221T

R222T

R247T
88DE3100

SOC_SPI1
SPI1_SS0N
BC26 R198T 10 SOC-SF-SPI-CSn
SPI1_SS1N
BG26 D006T SOC-AMBI-SPI-CSn
SPI1_SS2N
BA26 R073T 33 I055T SOC-I2S-MCLK
BG28
SPI1_SS3N
SPI1_SCLK
BJ29 R201T 47 SOC-SF-SPI-CLK
SPI1_SDO
BE28 R202T 47 SOC-AMBI-SPI-CLK
SPI1_SDI
BJ28 R203T 47 SOC-SF-SPI-MOSI
R204T 47 SOC-AMBI-SPI-MOSI
R205T 47 SOC-SF-SPI-MISO
R035T 47 SOC-AMBI-SPI-MISO
I042T I054T

RES

RES

RES
RES
RES

RES
10K

10K

10K

10K

10K

10K

10K

33pF
C231T
R215T

R224T

R226T

R227T

R228T

R229T

R234T
U007T

AH11
AH9
AH6
AH4
AG13
AG2
AE14
AE1
AA14
AA13
AA12
AA11
AA9
AA8
AA2
AA1
Y14
Y13
Y12
Y11
Y10
Y9
Y8
Y7
Y6
Y3
Y1
W14
W13
W12
W11
W10
W9
W8
W7
W3
TYPE
+3V3

NC122
NC121
NC120
NC119
NC118
NC117
NC116
NC115
NC114
NC113
NC112
NC111
NC110
NC109
NC108
NC107
NC106
NC105
NC104
NC103
NC102
NC101
NC100
NC99
NC98
NC97
NC96
NC95
NC94
NC93
NC92
NC91
NC90
NC89
NC88
NC87
H6 W2
RFU1 NC86
H7 W1
RFU2 NC85

100nF

10uF

10uF
K5 V14
RFU3 NC84
M5 V13

6.3V

6.3V
16V
RFU4 NC83
M8 V12

C082T
C013T

C083T
RFU5 NC82
M9 V3
RFU6 NC81
M10 V2
RFU7 NC80 +3V3
N10 V1
RFU8 NC79
+3V3-MRV P3
RFU9 NC78
U14
STRAPS P10
RFU10 NC77
U13
R5 U12
RFU11 NC76

100nF

100nF

100nF
T5 U3

RES
RES

RES
RES
RES
RFU12 NC75
U6 U2

16V

16V

16V
RFU13 NC74
U7 U1

C014T

C015T

C016T
10K
10K
10K

10K
10K
10K
10K
10K
10K
RFU14 NC73
U10 T14
RFU15 NC72
AA7 T13
RFU16 NC71
AA10 T12
RFU17 NC70
U001T T3

R251T
R252T
R253T

R303T
R304T
R305T
R306T
R309T
R310T
NC NC69
88DE3100 A4 T2
NC1 NC68
A6 T1
SOC_NAND NC2 NC67
R199T 10 EMMC-RESETn

10uF

10uF

10uF
BC32 A9 R14
NAND_CEN NC3 NC66
BE32 EMMC-CMD A11 R13

6.3V

6.3V

6.3V
NAND_RDY NC4 NC65
BH32 I002T BOOT-SRC0 B2 R12

C084T

C085T

C086T
NAND_ALE NC5 NC64
NAND_CLE
BH31 I001T BOOT-SRC1 B13
NC6 NC63
R3
NAND_WEN
BK32 I008T EMMC-VSELECT D1
NC7 NC62
R2
NAND_REN
BH34 I011T CPU-BYPASS D14
NC8 NC61
R1
NAND_WPN
BH33 R312T 22 EMMC-CLK H1
NC9 NC60
P14
H2 P13
NC10 NC59
NAND_IO[0]
BC28 EMMC-D0 H8
NC11 NC58
P12

100nF

100nF

100nF
NAND_IO[1]
BA30 EMMC-D1 H9
NC12 NC57
P2
BH29 EMMC-D2 H10 P1

16V

16V

16V
NAND_IO[2] NC13 NC56
BC30 EMMC-D3 H11 N14

C017T

C018T

C019T
NAND_IO[3] NC14 NC55
NAND_IO[4]
BE30 EMMC-D4 H12
NC15 NC54
N13
NAND_IO[5]
BJ31 EMMC-D5 H13
NC16 NC53
N12
NAND_IO[6]
BG31 EMMC-D6 NC52
N3
NAND_IO[7]
BK29 EMMC-D7

NC17
NC18
NC19
NC20
NC21
NC22
NC23
NC24
NC25
NC26
NC27
NC28
NC29
NC30
NC31
NC32
NC33
NC34
NC35
NC36
NC37
NC38
NC39
NC40
NC41
NC42
NC43
NC44
NC45
NC46
NC47
NC48
NC49
NC50
NC51
NAND_GPIO[0]
BG32 R233T 10 SOC-3D-LR
NAND_GPIO[1]
BJ32 R232T 10 HDMI-MUX-IRQn

M12
M13
M14
H14

K10
K11
K12
K13
K14

L12
L13
L14
J10
J11
J12
J13
J14

M1
M2
M3

N1
N2
K1
K3
K7
K8
K9

L1
L2
L3
L4
J1
J7
J8
J9
RES
RES
RES

RES
10K
10K
10K

10K
10K
10K
10K
10K
10K
+3V3 +3V3 +3V3
R254T
R240T
R243T

R244T
R245T
R246T
R248T
R297T
R298T

10K

10K

10K

10K

10K

10K

10K

10K

10K
U007T

RES

M6
N5
T10
U9

K6
W4
Y4
AA3
AA5
TYPE

R036T

R037T

R038T

R039T

R040T

R041T

R042T

R043T

R044T
RES

VCC_1
VCC_2
VCC_3
VCC_4

VCCQ_1
VCCQ_2
VCCQ_3
VCCQ_4
VCCQ_5
X307T
F037T
SOC-SF-SPI-CSn I064T 1 DBG
X340 EMMC-CMD R200T 10 W5
CMD DAT0
H3 R027T 10 EMMC-D0
SOC-SF-SPI-MISO I065T 2 DBG 1 S016T EMMC-D3 DAT1
H4 R028T 10 F018T EMMC-D1
3 2 50m EMMC-CLK F038T W6 H5 R029T 10 F019T EMMC-D2
+3V3-MRV CLK DAT2
SOC-SF-SPI-CLK 4 3 S015T EMMC-D4 J2 R030T 10 F020T EMMC-D3

10K
+3V3 MAIN DAT3
5 4 50m U5
RST DAT4
J3 R031T 10 F021T EMMC-D4
+3V3-MRV SOC-SF-SPI-MOSI I066T 6 5 S006T EMMC-D0 DAT5
J4 R032T 10 F022T EMMC-D5
BOOT-SRC0 7 6 50m F045T K2 J5 R033T 10 F031T EMMC-D6

4.7K
VDDI DAT6
BOOT-SRC1 8 7 S005T EMMC-D1 J6 R034T 10 F032T EMMC-D7

R045T

VSSQ_1
VSSQ_2
VSSQ_3
VSSQ_4
VSSQ_5
DAT7

100nF

VSS_1
VSS_2
VSS_3
VSS_4
8 50m F034T

RES
TYPE 9 S017T EMMC-D2

16V
R047T 10K 10 50m

R053T

C020T
I052T

AA4
AA6
R10
EMMC-D6

M7

U8
P5

K4
Y2
Y5
11 S008T
3

12 50m EMMC-RESETn
U006T 13 S007T EMMC-D7 F036T F035T

100nF
VCC 14 50m S004T

2 SOC-RESET-INn 15 S010T EMMC-D5

16V
RESET
F046T 16 50m

C087T
GND S014T EMMC-CMD

RES
17
RES

18 50m
19 S009T EMMC-CLK
100
1

20 50m
+3V3
21 22
100nF

TYPE
R052T

X301T
16V
C178T

3 1
4 2

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 115

10-1-45 B, ETHERNET

ETHERNET
B B

+3V3-STANDBY

+1V8-STANDBY
49.9
49.9

49.9
49.9

10K

10K

10K
10nF

10nF

RES C036T 10nF


16V

16V
C317T

C318T

16V
U001T X296
R294T
R302T

R272T
R290T

R209T

R210T

R211T

I009T
88DE3100 C022T 100nF 1
ETHERNET-TXP ETHERNET-TXP F053T 16V 2
ETHERNET-TXN ETHERNET-TXN F052T 3
SM_FE
FE_TXP
AT1 ETHERNET-RXP ETHERNET-RXP F051T 4
FE_TXN
AT2 ETHERNET-RXN ETHERNET-RXN F050T 5
RES C037T 10nF 6
D001T F049T

15pF

15pF

15pF

15pF
AU2 I010T 7 8
FE_RXP TYPE 16V
AV2 RES

50V

50V

50V

50V
FE_RXN
C023T 100nF

C035T

C034T

C033T

C032T
BF8 I003T R206T 10 RF4CE-RESETn 1 2

RES

RES

RES

RES
SM_FE_LED[0] TMDS_CH1- TMDS_CH1+ 16V CHASSIS-GND CHASSIS-GND
SM_FE_LED[1]
BH7
I004T
R207T 10 WOLAN-ENABLE
SM_FE_LED[2]
BJ4
I006T
R208T 10 BE-ENABLE 3
GND1
8
I053T GND2
AT4 R048T 4.99K 4 +1V8-STANDBY
10K

10K

10K

FE_RSET TMDS_CH2-
1% 5 S021T
TMDS_CH2+
RES

RES
RES

NC4
NC3
NC2
NC1
CHASSIS-GND
R212T

R230T

R213T

10
9
7
6

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 116

10-1-46 B, MARVELL - USB

MARVELL - USB
B B

X030
+3V3 1
2
+3V3 3
4
! 5

100uF 16V
X002T

C235T
I019T 6
+12V
T 2A 63V 7
+3V3-STANDBY

100nF

100nF

100nF

100nF

100nF
I018T 8
10 9

16V

16V

16V

16V

16V
100nF

100nF

100nF
C021T

C024T

C043T

C044T

C045T

16V

16V
TYPE

16V
100nF C005T

C046T

C008T

C009T
16V

X029
U008T

27

21

5
9
14
F009T 1
GL850G-OHGXX +5V-USB
USB-SKYPE-DM F010T 2
USB-SKYPE-DP

VCC_A1
VCC_A2
VCC_A3
VCC

VCC_D
F011T 3
DDP_1
4 USB-EXT1-DP LED2 L007T F013T 4
3

28
VREG DDN_1
3 USB-EXT1-DM 30H
5
+3V3

100nF
X005T

7 6
F012T
4 10 25 R070T 10K

16V
XIN OVR_1 +3V3
2 TYPE

C065T
1

DDP_2
7 USB-EXT2-DP
USB-EXT2-DM
18pF

18pF

11 6
XOUT DDN_2
50V

50V

SYSTEM-RESETn 17 24 R069T 10K


C047T

C048T

RESET OVR_2 +3V3 R061T

R071T 10K
I007T +5V-USB X280
22 +T 750mA
+3V3 SELFPWR
100nF

I021T DDP_3
13 USB-EXT3-DP 6V F001T 1
R066T 100K 23 12 USB-EXT3-DM USB-EXT2-DM F008T 2
16V

GANG DDN_3
USB-EXT2-DP F006T 3
C316T

I032T
R072T 680 8 20 R068T 10K 4
RREF OVR_3 +3V3

100nF
5 6
F077T
18

16V
TEST|I2C_SCL
26 16 USB-CIMAX-DP

C006T
PWR|I2C_SDA DDP_4
DDN_4
15 USB-CIMAX-DM
USB-HUB-DM 1
DN
USB-HUB-DP 2
DP OVR_4
19 R067T 10K
+3V3
GND_HS
R062T
+5V-USB X281
29

+T 750mA
6V F002T 1
USB-EXT3-DM F004T 2
USB-EXT3-DP F005T 3
4

100nF
5 6

16V
F003T

C007T
R063T
+5V-USB X282
U001T +T 750mA
88DE3100 6V F014T 1
USB-EXT1-DM F016T 2
SOC_USB
USB3_DP
BJ24 USB-WIFI-DP USB-EXT1-DP F017T 3
USB3_DN
BJ23 USB-WIFI-DM 4

100nF
BJ22 5 6
USB3_TP
BK22

16V
USB3_TN +5V-USB F015T
BJ25

C010T
USB3_RP
BK25
USB3_RN

USB2_0_DP
AN4 USB-HUB-DP
USB2_0_DN
AN6 USB-HUB-DM

100uF 16V
C234T
USB2_1_DP
AN10 USB-SKYPE-DP
USB2_1_DN
AN8 USB-SKYPE-DM

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 117

10-1-47 B, SENSOR BOARD CONNECTION

SENSOR BOARD CONNECTION


B B

RES X026
TYPE
F023T
X025 41
13 12 1 42 40 F024T R025T 10 SDA-SRF
11 2 39
10 3 38 F025T R026T 10 SCL-SRF
9 4 37 I013T R064T
8 36 +5V-FE
5 F026T +T 750mA R132T 10 RC
7 6 35
6 34 +3V3-STANDBY
7 F027T R133T 10 KEYBOARD KEYBOARD R216T 100K
5 33 F071T
+3V3-STANDBY
8 R134T 100 LED2 RES
4 9 32 F028T R130T 100 LED1
3 10 31 F029T R131T 1K 3D-GOGGLES
2 11 30 RES S002T
1 29 I020T
AMBI-POWER
12 R102T
28 F030T
+3V3
X020 13 +T 750mA R128T 47 AMBI-SPI-MOSI
RES 14 27
26 GND-AL F033T R129T 47 AMBI-SPI-CLK
15
16 25
24 GND-AL F007T R051T 100I033T
17
23
AMBI-TEMP
18
GND-AL

100pF

100pF

100pF

100pF

100pF

100pF

100pF
22

10pF

10pF

10pF

10uF
19
AMBI-POWER

1uF

1uF

1uF

1uF
20 21

16V

50V

50V
21 20

C042T

C028T

C031T

C030T

C026T

C029T

C027T

C038T

C041T

C039T

C040T

C232T

C025T

C147T

C148T
22 19

RES
23 18
24 17
25 16 GND-AL
26 15
28 27 14
13
AMBI-POWER
F039T

100nF
TYPE 12

10uF
11

16V
10 +3V3-STANDBY
C011T

C164T
9

RES

RES
8
7
6
5 I005T C012T 100nF

2.7K
4 GND-AL GND-AL
RES
3

RES
2 GND-AL
1 GND-AL

R168T
2
GND-AL I070T
BC857BW(COL) I073T R059T 3.3K
U014T 1
RES
RES 2
3
BC857BW(COL) I074T R058T 1K RC

1uF
U015T 1

RES 6.3V
RES RES

C370T
3 3
I072T
I071T R046T
U012T 1 I062T R057T 100
BC847BW(COL) 100K
RES RES RES
2

1uF
RES 6.3V

10K
C369T

RES
R056T
+3V3 +3V3 +3V3

+3V3

S042T

S043T

S044T
C264T 100nF

50m

50m

50m
RES

RES
U013T 16V

8
X071
TMP75AIDGKR

V+
1 F048T 10 R278T F043T SCL-SRF
2 F056T SCL-HDMI R343T 47 2
SCL A0
7 I017T
3 F054T 10 R277T F047T SDA-SRF SDA-HDMI R344T 47 1
SDA A1
6 I015T
4 5 I016T
A2
10pF

10pF

5 6 3

GND
GND ALERT
50V

50V

TYPE
C267T

C266T

S045T

S046T

S047T
50m

50m

50m
RES
L005T
F055T +3V3
30H
1uF
6.3V

C265T

5 2014-02-21

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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 118

10-1-48 B, MARVELL - DDR3

MARVELL - DDR3 (U002T and U003T)


B B
+1V5-MRV

+1V5-MRV

U001T U001T

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9
C323T 100nF

SOC_SDRAM0 SOC_SDRAM0 U002T 16V


F34 M0-RESETN L49 M0-DQS0P C324T 100nF
M0_RSTN M0_DQSP[0]
H38 M0-CSN L50 M0-DQS0N 16V
M0_CSN M0_DQSN[0] VDD VDDQ
C40 M0-CKE K49 M0-DQM0 M0-MA0 N3 C325T 100nF
M0_CKE M0_DM[0] 0
F42 M0-RASN M49 D010T M0-MD0 M0-MA1 P7 D7 M0-MD9 16V
M0_RASN M0_DQ[0] 1 0
D38 M0-CASN J48 M0-MD1 M0-MA2 P3 C3 M0-MD10 C326T 100nF
M0_CASN M0_DQ[1] 2 1
F40 M0-WEN K48 M0-MD2 M0-MA3 N2 C8 D007T M0-MD13 16V
M0_WEN M0_DQ[2] 3 2
H40 M0-ODT M0-MCLK0N G49 M0-MD3 M0-MA4 P8 C2 M0-MD8 C327T 100nF
M0_ODT M0_DQ[3] 4 3
L45 M0-MD4 M0-MA5 P2 DQU A7 M0-MD12 16V
M0_DQ[4] 5 4

2.2pF
A41 M0-MCLK0P H49 M0-MD5 M0-MA6 R8 A2 M0-MD14 C328T 100nF
M0_CKP M0_DQ[5] 6 5
B41 M0-MCLK0N L47 M0-MD6 M0-MA7 R2 B8 M0-MD15 16V

50V
M0_CKN M0_DQ[6] 7 A 6
H50 M0-MD7 M0-MA8 T8 A3 M0-MD11 C329T 100nF

C367T
M0_DQ[7] 8 7
C39 M0-BA0 M0-MA9 R3 16V
M0_BA[0] 9
B40 M0-BA1 M0-MCLK0P E49 M0-DQS1P M0-MA10 L7 B7 M0-DQS1N C330T 100nF
M0_BA[1] M0_DQSP[1] 10 DQSU
H36 M0-BA2 E50 M0-DQS1N M0-MA11 R7 C7 M0-DQS1P 16V
M0_BA[2] M0_DQSN[1] 11 DQSU
G47 M0-DQM1 M0-MA12 N7 C331T 100nF
M0_DM[1] 12
F38 M0-MA0 G48 M0-MD8 M0-MA13 T3 F3 M0-DQS0P 16V
M0_A[0] M0_DQ[8] 13 DQSL
A38 M0-MA1 F49 M0-MD9 M0-MA14 T7 G3 M0-DQS0N C332T 100nF
M0_A[1] M0_DQ[9] 14 DQSL
B38 M0-MA2 J47 M0-MD10 M7 16V
M0_A[2] M0_DQ[10] 15
C38 M0-MA3 J45 M0-MD11 E3 M0-MD0 C333T 100nF
M0_A[3] M0_DQ[11] BC 0
B37 M0-MA4 D50 M0-MD12 F7 M0-MD7 16V
M0_A[4] M0_DQ[12] AP 1
B35 M0-MA5 C49 M0-MD13 F2 M0-MD2 C334T 100nF
M0_A[5] M0_DQ[13] 2
C37 M0-MA6 E48 M0-MD14 H1 F8 M0-MD3 16V
M0_A[6] M0_DQ[14] DDR-MVREF01 VREFDQ 3
C34 M0-MA7 D49 M0-MD15 M8 DQL H3 M0-MD4 C335T 100nF
M0_A[7] M0_DQ[15] VREFCA 4
B34 M0-MA8 H8 M0-MD5 16V
M0_A[8] 5
C36 M0-MA9 B49 M0-DQS2P R001T 240 I045T L8 G2 M0-MD6 C336T 100nF
M0_A[9] M0_DQSP[2] ZQ 6
A35 M0-MA10 A49 M0-DQS2N H7 M0-MD1 16V
M0_A[10] M0_DQSN[2] 7
F36 M0-MA11 C48 M0-DQM2 M0-BA0 M2 C337T 100nF
M0_A[11] M0_DM[2] 0
C33 M0-MA12 D46 M0-MD16 M0-BA1 N8 J1 16V
M0_A[12] M0_DQ[16] 1 BA
D34 M0-MA13 G45 M0-MD17 M0-BA2 M3 J9 C338T 100nF
M0_A[13] M0_DQ[17] 2 NC
H32 M0-MA14 B50 M0-MD18 L1 16V
M0_A[14] M0_DQ[18]
E47 M0-MD19 M0-RASN J3 L9 C339T 100nF
M0_DQ[19] RAS
F32 D48 M0-MD20 M0-ODT K1 16V
M0_VREF M0_DQ[20] ODT
A47 M0-MD21 M0-CASN K3 C340T 100nF
M0_DQ[21] CAS
F30 I046T 240 R003T B47 D017T M0-MD22 M0-MCLK0P J7 16V
M0_CAL M0_DQ[22] CK
B46 M0-MD23 M0-MCLK0N K7
M0_DQ[23] CK
+1V5-MRV M0-CKE K9 C372T 1uF
CKE
A44 M0-DQS3P M0-CSN L2
M0_DQSP[3] CS
B44 M0-DQS3N M0-WEN L3 C373T 1uF
M0_DQSN[3] WE
1K

D42 M0-DQM3 M0-RESETN T2


M0_DM[3] RESET
J43 M0-MD24
M0_DQ[24]
D44 M0-MD25 M0-DQM0 E7 C380T 10uF
F087T M0_DQ[25] DML
F44 M0-MD26 M0-DQM1 D3
R078T

M0_DQ[26] DMU 6.3V


C45 M0-MD27
M0_DQ[27] VSS VSSQ
B43 M0-MD28
M0_DQ[28]
1K

100nF

C44 M0-MD29
M0_DQ[29]
C42 M0-MD30
16V

M0_DQ[30]

M1
M9
G8

G1
G9
D1
D8
A9
B3
E1

P1
P9

B1
B9

E2
E8
T1
T9

F9
C41 M0-MD31
C276T

J2
J8
M0_DQ[31]
R079T

+1V5-MRV

+1V5-MRV
1K

+VTT
C363T
+1V5-MRV
M0-MCLK0P R322T 240 M0-DQS0P +1V5-MRV
R321T

16V 100uF
R329T 240 M0-DQS0N
75

R010T 47 M0-MA0 R323T 240 M0-DQS1P C361T 10uF


1nF
5%

1 8 R006T 47 M0-MA1 R347T 240 M0-DQS1N


50V
RES

6.3V
R010T 47 3 6 M0-MA2 R327T 240 M0-DQS2P
C001T

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9
3 6 R010T 47 M0-MA3 R348T 240 M0-DQS2N C365T 1uF
R013T

R006T 47 2 7 M0-MA4 I047T


R328T 240 M0-DQS3P U003T 10V
4 5 R010T 47 M0-MA5 R349T 240 M0-DQS3N
R008T 47 4 5 M0-MA6 VDD VDDQ
75

2 7 R012T 47 M0-MA7 M0-MA0 N3 C341T 100nF


1nF

0
5%

R008T 47 2 7 M0-MA8 M0-MA1 P7 D7 M0-MD29 16V


50V

1 0
4 5 R012T 47 M0-MA9 M0-MA2 P3 C3 M0-MD24 C342T 100nF
C002T

2 1
R011T 47 1 8 M0-MA10 +1V5-MRV M0-MA3 N2 C8 D020T M0-MD31 16V
R014T

3 2
R008T 47 M0-MA11 M0-MCLK0N M0-MA4 P8 C2 M0-MD27 C343T 100nF
4 3
R006T 47 1 8 M0-MA12 M0-MA5 P2 DQU A7 M0-MD28 16V
5 4
1 8 R012T 47 M0-MA13 M0-MA6 R8 A2 M0-MD26 C344T 100nF
6 5
R008T 47 4 5 M0-MA14 M0-MA7 R2 B8 M0-MD30 16V
7 A 6
3 6 M0-MA8 D019T T8 A3 M0-MD25 C345T 100nF
8 7
R009T 47 M0-BA0 M0-MA9 R3 16V
9
4 5 R007T 47 M0-BA2 M0-MA10 L7 B7 M0-DQS3N C346T 100nF
10 DQSU
R006T 47 1 8 M0-BA1 M0-MA11 R7 C7 M0-DQS3P 16V
11 DQSU
2 7 R009T 47 M0-CKE M0-MA12 D018T N7 C347T 100nF
2 7 12
R007T 47 M0-CASN M0-MA13 T3 F3 D021T M0-DQS2P 16V
13 DQSL
3 6 R009T 47 M0-ODT M0-MA14 T7 G3 D022T M0-DQS2N C348T 100nF
14 DQSL
R009T 47 1 8 M0-CSN M7 16V
15
3 6 R012T 47 M0-RESETN E3 M0-MD17 C349T 100nF
BC 0
R007T 47 3 6 M0-RASN F7 M0-MD22 16V
AP 1
4 5 R007T 47 M0-WEN F2 M0-MD18 C350T 100nF
2
2 7 H1 F8 M0-MD23 16V
DDR-MVREF02 VREFDQ 3
M8 DQL H3 D023T M0-MD19 C351T 100nF
VREFCA 4
1K

H8 M0-MD21 16V
5
R002T 240 I048T L8 G2 M0-MD16 C352T 100nF
ZQ 6
H7 M0-MD20 16V
7
M0-BA0 M2 C353T 100nF
R320T

0
M0-BA1 N8 J1 16V
1 BA
M0-BA2 M3 J9 C354T 100nF
2 NC
L1 16V
M0-RASN J3 L9 C355T 100nF
RAS
+1V5-MRV +1V5-MRV M0-ODT K1 16V
ODT
M0-CASN K3 C356T 100nF
CAS
M0-MCLK0P J7 16V
CK
M0-MCLK0N K7 C357T 100nF
CK
1K

1K

M0-CKE K9 16V
CKE
R313T

R315T

M0-CSN L2 C358T 100nF


CS
M0-WEN L3 16V
WE
M0-RESETN T2
RESET
F088T F089T C374T 1uF
DDR-MVREF01 DDR-MVREF02
M0-DQM2 E7
DML
1K

1K
100nF

100nF

100nF

100nF

M0-DQM3 D3
DMU
R314T

R316T
16V

16V

16V

16V

VSS VSSQ
C319T

C320T

C321T

C322T

M1
M9

G1
G9
G8

D1
D8
A9
B3
E1

P1
P9

B1
B9

E2
E8
T1
T9

F9
J2
J8
+VTT
10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10uF

10uF
1uF

1nF

1nF

1nF

1nF

1nF

6.3V

6.3V
C375T

C382T

C383T

C384T

C385T

C386T

C387T

C388T

C389T

C390T

C391T

C392T

C404T

C405T

C406T

C407T

C408T

C050T

C051T

D037T D038T D039T D033T D034T D035T D036T


5 2014-02-21

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19570_067_140523.eps
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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 119

10-1-49 B, MARVELL - DDR3

MARVELL - DDR3 (U004T and U005T)


B B
+1V5-MRV

U001T U001T

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9
SOC_SDRAM1 SOC_SDRAM1
U004T
C32 M1-RESETN B10 M1-DQS0P +1V5-MRV
M1_RSTN M1_DQSP[0]
F26 M1-CSN A10 M1-DQS0N VDD VDDQ
M1_CSN M1_DQSN[0]
D25 M1-CKE C7 M1-DQM0 M1-MA0 N3
M1_CKE M1_DM[0] 0
F23 M1-RASN D7 M1-MD0 M1-MA1 P7 D7 M1-MD2 C282T 100nF
M1_RASN M1_DQ[0] 1 0
D23 M1-CASN C8 M1-MD1 M1-MA2 P3 C3 M1-MD0 16V
M1_CASN M1_DQ[1] 2 1
D26 M1-WEN M1-MCLK0N A7 M1-MD2 M1-MA3 N2 C8 M1-MD3 C283T 100nF
M1_WEN M1_DQ[2] 3 2
F25 M1-ODT B7 M1-MD3 M1-MA4 P8 C2 M1-MD1 16V
M1_ODT M1_DQ[3] 4 3

2.2pF
C9 M1-MD4 M1-MA5 P2 DQU A7 M1-MD4 C284T 100nF
M1_DQ[4] 5 4
B25 M1-MCLK0P G10 M1-MD5 M1-MA6 R8 A2 M1-MD7 16V

50V
M1_CKP M1_DQ[5] 6 5
A25 M1-MCLK0N B8 M1-MD6 M1-MA7 R2 B8 D024T M1-MD6 C285T 100nF

C277T
M1_CKN M1_DQ[6] 7 A 6
F9 M1-MD7 M1-MA8 T8 A3 M1-MD5 16V
M1_DQ[7] 8 7
H26 M1-BA0 M1-MCLK0P M1-MA9 R3 C286T 100nF
M1_BA[0] 9
F28 M1-BA1 B13 M1-DQS1P M1-MA10 L7 B7 M1-DQS0N 16V
M1_BA[1] M1_DQSP[1] 10 DQSU
D28 M1-BA2 A13 M1-DQS1N M1-MA11 R7 C7 M1-DQS0P C287T 100nF
M1_BA[2] M1_DQSN[1] 11 DQSU
B11 M1-DQM1 M1-MA12 N7 16V
M1_DM[1] 12
C25 M1-MA0 F11 M1-MD8 M1-MA13 T3 F3 M1-DQS1P C288T 100nF
M1_A[0] M1_DQ[8] 13 DQSL
C26 M1-MA1 D11 M1-MD9 M1-MA14 T7 G3 M1-DQS1N 16V
M1_A[1] M1_DQ[9] 14 DQSL
A26 M1-MA2 F13 M1-MD10 M7 C289T 100nF
M1_A[2] M1_DQ[10] 15
D31 M1-MA3 C11 M1-MD11 E3 M1-MD8 16V
M1_A[3] M1_DQ[11] BC 0
B28 M1-MA4 C14 M1-MD12 F7 M1-MD10 C290T 100nF
M1_A[4] M1_DQ[12] AP 1
B26 M1-MA5 C12 M1-MD13 F2 M1-MD11 16V
M1_A[5] M1_DQ[13] 2
C29 M1-MA6 C13 M1-MD14 H1 F8 M1-MD9 C291T 100nF
M1_A[6] M1_DQ[14] DDR-MVREF11 VREFDQ 3
B29 M1-MA7 B14 M1-MD15 M8 DQL H3 M1-MD12 16V
M1_A[7] M1_DQ[15] VREFCA 4
A32 M1-MA8 H8 M1-MD13 C292T 100nF
M1_A[8] 5
C31 M1-MA9 A18 M1-DQS2P R004T 240 I050T L8 G2 D025T M1-MD15 16V
M1_A[9] M1_DQSP[2] ZQ 6
H25 M1-MA10 B18 M1-DQS2N H7 M1-MD14 C293T 100nF
M1_A[10] M1_DQSN[2] 7
A29 M1-MA11 C17 M1-DQM2 M1-BA0 M2 16V
M1_A[11] M1_DM[2] 0
H28 M1-MA12 F15 M1-MD16 M1-BA1 N8 J1 C294T 100nF
M1_A[12] M1_DQ[16] 1 BA
B31 M1-MA13 D15 M1-MD17 M1-BA2 M3 J9 16V
M1_A[13] M1_DQ[17] 2 NC
B32 M1-MA14 C15 M1-MD18 L1 C295T 100nF
M1_A[14] M1_DQ[18]
F17 M1-MD19 M1-RASN J3 L9 16V
M1_DQ[19] RAS
B16 M1-MD20 M1-ODT K1 C296T 100nF
M1_DQ[20] ODT
F19 M1-MD21 M1-CASN K3 16V
M1_DQ[21] CAS
A16 M1-MD22 M1-MCLK0P J7 C297T 100nF
M1_DQ[22] CK
H19 M1-MD23 M1-MCLK0N K7 16V
M1_DQ[23] CK
M1-CKE K9 C298T 100nF
CKE
R080T 240 M1-DQS0P B22 M1-DQS3P M1-CSN L2 16V
M1_DQSP[3] CS
R084T 240 M1-DQS0N A22 M1-DQS3N M1-WEN L3 C299T 100nF
M1_DQSN[3] WE
R081T 240 M1-DQS1P A19 M1-DQM3 M1-RESETN T2 16V
M1_DM[3] RESET
R085T 240 M1-DQS1N F21 M1-MD24
M1_DQ[24]
R082T 240 M1-DQS2P D19 M1-MD25 M1-DQM1 E7 C378T 1uF
M1_DQ[25] DML
R086T 240 M1-DQS2N B19 M1-MD26 M1-DQM0 D3
M1_DQ[26] DMU
R083T 240 M1-DQS3P D20 M1-MD27 C379T 1uF
M1_DQ[27] VSS VSSQ
R087T 240 M1-DQS3N C20 M1-MD28
M1_DQ[28]
B20 M1-MD29
M1_DQ[29]
C22 M1-MD30 C381T 10uF
M1_DQ[30]

M1
M9
G8

G1
G9
D1
D8
A9
B3
E1

P1
P9

B1
B9

E2
E8
T1
T9

F9
B23 M1-MD31

J2
J8
M1_DQ[31] 6.3V

+1V5-MRV

+1V5-MRV +1V5-MRV

+1V5-MRV

C364T
1K

B2
D9
G7
K2
K8
N1
N9
R1
R9

A1
A8
C1
C9
D2
E9
F1
H2
H9
+VTT U005T 16V 100uF

C362T 10uF
R295T

VDD VDDQ
+1V5-MRV M1-MA0 N3
0 6.3V
R018T 47 M1-MA0 M1-MCLK0P M1-MA1 P7 D7 M1-MD16
1 0
3 6 R016T 47 M1-MA1 M1-MA2 P3 C3 M1-MD18 C366T 1uF
2 1
75

R018T 47 2 7 M1-MA2 M1-MA3 N2 C8 M1-MD19


1nF

3 2 10V
5%

1 8 R018T 47 M1-MA3 M1-MA4 P8 C2 M1-MD21


50V
RES

4 3
R016T 47 4 5 M1-MA4 M1-MA5 P2 DQU A7 D029T M1-MD22 C300T 100nF
C003T

5 4
1 8 R018T 47 M1-MA5 M1-MA6 R8 A2 M1-MD23 16V
R022T

6 5
R017T 47 2 7 M1-MA6 M1-MA7 R2 B8 M1-MD20 C301T 100nF
I049T 7 A 6
3 6 R019T 47 M1-MA7 M1-MA8 D027T T8 A3 M1-MD17 16V
8 7
R017T 47 4 5 M1-MA8 M1-MA9 R3 C302T 100nF
9
75

1 8 R019T 47 M1-MA9 M1-MA10 D028T L7 B7 M1-DQS2N 16V


1nF

10 DQSU
5%

R021T 47 3 6 M1-MA10 M1-MA11 R7 C7 M1-DQS2P C303T 100nF


50V

11 DQSU
R017T 47 M1-MA11 M1-MA12 N7 16V
C004T

4 5 12
R016T 47 M1-MA12 M1-MA13 T3 F3 D030T M1-DQS3P C304T 100nF
R023T

13 DQSL
4 5 R019T 47 M1-MA13 M1-MCLK0N M1-MA14 T7 G3 D031T M1-DQS3N 16V
14 DQSL
R017T 47 1 8 M1-MA14 M7 C305T 100nF
15
2 7 E3 D032T M1-MD31 16V
BC 0
R015T 47 M1-BA0 F7 M1-MD27 C306T 100nF
AP 1
2 7 R015T 47 M1-BA2 F2 M1-MD30 16V
2
R016T 47 1 8 M1-BA1 H1 F8 M1-MD25 C307T 100nF
3 6
DDR-MVREF12 VREFDQ 3
R020T 47 M1-CKE M8 DQL H3 M1-MD28 16V
VREFCA 4
R020T 47 1 8 M1-CASN H8 M1-MD26 C308T 100nF
5
3 6 R020T 47 M1-ODT R005T 240 I051T L8 G2 M1-MD29 16V
ZQ 6
R015T 47 2 7 M1-CSN H7 M1-MD24 C309T 100nF
7
4 5 R019T 47 M1-RESETN M1-BA0 M2 16V
0
R020T 47 2 7 M1-RASN M1-BA1 N8 J1 C310T 100nF
1 BA
4 5 R015T 47 M1-WEN M1-BA2 M3 J9 16V
2 NC
3 6 L1 C311T 100nF
M1-RASN J3 L9 16V
RAS
1K

M1-ODT K1 C312T 100nF


ODT
M1-CASN K3 16V
CAS
M1-MCLK0P J7 C313T 100nF
CK
M1-MCLK0N K7 16V
R296T

CK
M1-CKE K9 C314T 100nF
CKE
M1-CSN L2 16V
CS
M1-WEN L3 C315T 100nF
WE
M1-RESETN T2 16V
RESET
C359T 100nF
+VTT +1V5-MRV +1V5-MRV M1-DQM3 E7 16V
DML
M1-DQM2 D3 C360T 100nF
DMU
16V
VSS VSSQ
1K

1K

C377T 1uF
R088T

R156T
10uF

C052T 10uF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF

10nF
1uF

1nF

1nF

1nF

1nF

1nF

M1
M9
G8

G1
G9
D1
D8
A9
B3
E1

P1
P9

B1
B9

E2
E8
T1
T9

F9
J2
J8
6.3V
6.3V
C064T

C393T

C394T

C395T

C396T

C397T

C398T

C399T

C400T

C401T

C402T

C403T

C409T

C410T

C411T

C412T

C413T
C376T

F090T F091T
DDR-MVREF11 DDR-MVREF12
1K

1K
100nF

100nF

100nF

100nF
R089T

R157T
16V

16V

16V

16V
C279T
C278T

C280T

C281T

D040T D041T D042T

5 2014-02-21

D044T D046T D047T D043T


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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 120

10-1-50 B, MARVELL - DVIDEO - CONTROL - LVDS

MARVELL - DVIDEO - CONTROL - LVDS


B B

+3V3-MRV

RES

RES
RES
10K

10K

10K

10K

10K
U001T U001T

R317T

R319T

R287T

R324T

R325T
88DE3100 88DE3100

SOC_SDIO SOC_AV_IN
U001T SD0_CLK
BK19 R268T 10 STRAP AN49
88DE3100 BA21 R269T 10 I061T CTRL-DISP1 SOG0
SD0_DAT0 AV43
BC21 D016T HD1_Y
SD0_DAT1 AV45
BJ19 HD1_PB
SOC_VIDEO SD0_DAT2
HD1_PR
AV48
DVIO[0]
A2 DVIDEO-D0 BH19
SD0_DAT3
DVIO[1]
A4 DVIDEO-D1 BE21 R273T 10 AV-YPBPR-DETECTn
SD0_CDN AP43
E3 DVIDEO-D10 BC23 R274T 10 AV-CVBS-DETECTn SOG1
DVIO[10] SD0_CMD AY47
D3 DVIDEO-D11 BC25 R275T 10 HDMI2LVDS-IRQn HD2_Y
DVIO[11] SD0_WP AY49
B5 DVIDEO-D2 HD2_PB
DVIO[2] AT43
C5 DVIDEO-D3 HD2_PR
DVIO[3]
DVIDEO-D4

RES

RES

RES
RES
B4
DVIO[4] AP45
G7 DVIDEO-D5 SOG2
DVIO[5] AV41
G6 DVIDEO-D6 VGA_R

10K

10K

10K

10K

10K
DVIO[6] AT41
B2 DVIDEO-D7 VGA_G
DVIO[7] AW49
B1 DVIDEO-D8 VGA_B
DVIO[8]
DVIO[9]
C3 DVIDEO-D9
AU49
SV_Y

R318T

R326T

R330T

R331T

R332T
AR50
G4 DVIDEO-CLK SV_C
DV0_CLK
DV0_HS
E2 DVIDEO-HS
AT45
D2 DVIDEO-VS CVBS1
DV0_VS AU48
F3 DVIDEO-FID CVBS2
DV0_FID
AL48
AUDIO_IN_R0
AM50
U001T AUDIO_IN_L0
88DE3100
AM45
AUDIO_IN_R1
AM47
AUDIO_IN_L1
SOC_LVDS
LVDS0_TCK_P
AA1 SOC-TX0-CLKP
SOC-TX0-CLKN AJ43
AA2 AUDIO_IN_R2
LVDS0_TCK_N AK41
AUDIO_IN_L2
LVDS0_TD0_P
V1 SOC-TX0-0P
SOC-TX0-0N AJ45
U001T V2 AUDIO_IN_R3
LVDS0_TD0_N AK48
88DE3100 AUDIO_IN_L3
C165T 10nF LVDS0_TD1_P
V6 SOC-TX0-1P
SOC-TX0-1N AM43
V4 AUDIO_IN_R4
SOC_PEX LVDS0_TD1_N
100

16V AM41
AP2 AUDIO_L4
PEX_CLK_P
AR2 LVDS0_TD2_P
Y2 SOC-TX0-2P
PEX_CLK_N BB49
LVDS0_TD2_N
W2 SOC-TX0-2N SIF
R235T

C275T 10nF LVDS0_TD3_P


V10 SOC-TX0-3P
SOC-TX0-3N BA49
V8 SIF_REF
16V LVDS0_TD3_N AY50
VGAFE_REF
SOC-TX0-4P AK49
Y6 AUDIO_VMID
LVDS0_TD4_P AJ50
LVDS0_TD4_N
Y8 SOC-TX0-4N AUDIO_VREF_P
AJ49
AUDIO_VREF_N
LVDS1_TCK_P
AE2 SOC-TX1-CLKP
SOC-TX1-CLKN AR49
U001T AF2 MONOUT
LVDS1_TCK_N AP49
88DE3100 FSW0
SOC-TX1-0P AP47
AB2 FSW1
LVDS1_TD0_P AP41
LVDS1_TD0_N
AC2 SOC-TX1-0N FB
SOC_SATA
AN2 I063T
SATA0_TP AM49
AN1 LVDS1_TD1_P
AB6 SOC-TX1-1P ATEST
SATA0_TN
LVDS1_TD1_N
AB4 SOC-TX1-1N

4.99K
AL2
SATA0_RP
AM2 LVDS1_TD2_P
AD1 SOC-TX1-2P
SATA0_RN
LVDS1_TD2_N
AD2 SOC-TX1-2N

R345T
LVDS1_TD3_P
AB10 SOC-TX1-3P
LVDS1_TD3_N
AB8 SOC-TX1-3N

LVDS1_TD4_P
AE6 SOC-TX1-4P
LVDS1_TD4_N
AE8 SOC-TX1-4N

5 2014-02-21

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2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 121

10-1-51 B, MARVELL - AUDIO

MARVELL - AUDIO
B B
+3V3-MRV STRAP

RES

RES
RES
10K

10K

10K

10K

10K
U001T
88DE3100

R236T

R241T

R242T

R218T

R223T
SOC_AUDIO
I2S0_LRCK
M8 R054T 33 SOC-I2S-LRCK
I2S0_BCLK
K3 R055T 33 SOC-I2S-BCLK
I2S0_DO[0]
L3 R060T 33 I038T SOC-I2S-SDO
I2S0_DO[1]
L10 CYPRESS-RESETn
I2S0_DO[2]
M10 CYPRESS-IRQn
I2S0_DO[3]
L8 R280T 33 AUDIO-RESETn

I2S1_LRCK
J6 I2S-SOC-IN-SD1
I2S1_BCLK
J8 I2S-SOC-IN-SD2
I2S1_DO
G1 I2S-SOC-IN-SD3

I2S2_LRCK
H2 I2S-SOC-IN-LRCK
I2S2_BCLK
G2 I2S-SOC-IN-BCLK
I2S2_DI_0
J3 I2S-SOC-IN-SD0
R372T
SPDIFO
L2 R090T 33 100 SPDIF-OUT
SPDIFI
K2 R024T 100 HDMI-ARC

SPDIF-SOC-IN

RES

10K

10K
33pF

33pF

33pF

33pF

10K

10K

10K
C230T

C229T

C228T

C227T

R225T

R258T
RES
R237T

R238T

R239T
U001T
88DE3100

SOC_AV_DAC I022T
ADAC_AOUTL_P
U3 R103T 100 AUDIO-HPLP
ADAC_AOUTL_N
U4 R049T 100 I075T AUDIO-HPLN
I024T
I023T
ADAC_AOUTR_P
R4 R104T 100 AUDIO-HPRP
ADAC_AOUTR_N
T4 R050T 100 I076T AUDIO-HPRN
I025T
T1 C049T 100nF
ADAC_VCOM +1V8-AVDD
330pF

330pF

330pF

330pF
I026T
16V
R1
VDAC1P
P2
C226T

C233T

C071T

C072T

VDAC2P
R2
VDAC3P
N1
VDAC4P

M3
VDAC_REXT

5 2014-02-21

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2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 122

10-1-52 B, MARVELL - POWER

MARVELL - POWER
B F076T L004T
B
+1V8-STANDBY
30H +VCORE

100nF

100nF

100nF

100nF

100nF
2.2uF

2.2uF
U001T U001T U001T

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
10uF

10uF

22uF

C208T 10uF
C254T

C236T

C255T

C237T

C238T

C239T

C240T
88DE3100 88DE3100 88DE3100

6.3V
GND POWER1 POWER2

C205T

C206T

C207T

C053T

C054T

C055T

C056T

C057T

C058T

C059T

C060T

C061T

C062T

C063T

C066T

C067T

C068T

C069T

C070T
AA15 AT21 BD4 AA19

RES
VSS_1 VSS_57 VDD_SMCORE VDD_1 +VCORE
AA17 AT25 AW3 AA21
VSS_2 VSS_58 AVDD_SM_1P8 VDD_2
AA30 AT26 AT10 AA23
VSS_3 VSS_59 AVDD_SM_3P3 +3V3-STANDBY VDD_3
AA32 AT30 AT8 AA25
VSS_4 VSS_60 AVDD_FE_1P8 VDD_4
AA34 AT6 AY6 AA26
VSS_5 VSS_61 AVDD_LDO_1P8 VDD_5
AA36 AV10 AC19
VSS_6 VSS_62 VDD_6
AA38 AV15 H11 AE17
VSS_7 VSS_63 AVDD_MPLL_1P8 +1V8-AVDD VDD_7
AC17 AV19 BC3 AE21
VSS_8 VSS_64 AVDD_PLL_1P8 VDD_8 +VCPU
AC21 AV26 BE23 AE25
VSS_9 VSS_65 AVDD_CLK_3P3 +3V3-AVDD VDD_9
AC23 AV30 AE28
VSS_10 VSS_66 VDD_10

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
10uF

10uF

22uF
AC25 AW5 AM12 AF17

1uF

1uF
VSS_11 VSS_67 AVHV_OTP_1P8 +1V8-OTP VDD_11
AC26 B3 AL10 AF21

6.3V
VSS_12 VSS_68 AVHV_OTP_3P3 +3V3-AVDD VDD_12
AC38 BA17 AF25

C210T

C211T

C212T

C195T

C197T

C104T

C105T

C106T

C107T

C108T

C109T

C110T

C111T

C112T

C113T

C115T
VSS_13 VSS_69 VDD_13
AE15 BD8 AL4 AF28

RES
VSS_14 VSS_70 AVDD_SATA0_1P8_1 +1V8-AVDD VDD_14
AE19 BF4 AL6 AH28
VSS_15 VSS_71 AVDD_SATA0_1P8_2 VDD_15
AE23 BG23 AH30
VSS_16 VSS_72 VDD_16
AE26 D1 BG25 AH32
VSS_17 VSS_73 AVDD_USB3_1P8 +1V8-AVDD VDD_17
AE30 J4 BH21 AK17
VSS_18 VSS_74 AVDD_USB3_3P3_1 +3V3-AVDD VDD_18
AE38 K15 AP12 AK19
VSS_19 VSS_75 AVDD_USB3_3P3_2 VDD_19
AF15 K17 AK21
VSS_20 VSS_76 VDD_20
AF19 K21 AE12 AK23
VSS_21 VSS_77 AVDD_HDMI_1P8_1 +1V8-AVDD VDD_21 +1V5-MRV
AF23 K23 AF12 AK25
VSS_22 VSS_78 AVDD_HDMI_1P8_2 VDD_22
AF26 K30 AG10 AK26
VSS_23 VSS_79 AVDD_HDMI_3P3_1 +3V3-AVDD VDD_23

100nF

100nF

C125T 100nF

C126T 100nF

C127T 100nF

C128T 100nF

C129T 100nF

C130T 100nF

C131T 100nF

C133T 100nF

C134T 100nF

C135T 100nF

C136T 100nF

C137T 100nF

C138T 100nF
C132T 2.2uF
10uF

10uF

10uF

10uF

C139T 10nF

10nF
AF30 K34 AG8 AK28

C199T 1uF
VSS_24 VSS_80 AVDD_HDMI_3P3_2 VDD_24
AF32 L12 AH12 AK32

6.3V
16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V

16V
VSS_25 VSS_81 AVDD_HDMI_3P3_3 VDD_25
AF36 L43 AM17

C213T

C214T

C215T

C216T

C198T

C124T

C140T
VSS_26 VSS_82 VDD_26
AF38 L6 AB41 AP17
VSS_27 VSS_83 AVDD_HDMI_RX_3P3_1 VDD_27
AH15 N15 AF41 AP19
VSS_28 VSS_84 AVDD_HDMI_RX_3P3_2 VDD_28
AH17 N25 AH41 AP21
VSS_29 VSS_85 AVDD_HDMI_RX_3P3_3 VDD_29
AH19 N26 Y41 AP23
VSS_30 VSS_86 AVDD_HDMI_RX_3P3_4 VDD_30
AH21 N28 R41 AP25
VSS_31 VSS_87 AVDD_HDMI_RX_1P8_1 +1V8-AVDD VDD_31
AH23 N32 R43 AP28
VSS_32 VSS_88 AVDD_HDMI_RX_1P8_2 VDD_32
AH25 N36 U41 AP30
VSS_33 VSS_89 AVDD_HDMI_RX_1P8_3 VDD_33
AH26 N38 Y43 AT19
VSS_34 VSS_90 AVDD_HDMI_RX_1P8_4 VDD_34 +3V3-MRV
AH38 N43 AT23
VSS_35 VSS_91 VDD_35
AJ10 N45 AA12 N17
VSS_36 VSS_92 AVDD_LVDS_1 VDD_36

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
2.2uF

2.2uF
AJ8 N47 AC12 N19

1uF

1uF

1uF
VSS_37 VSS_93 AVDD_LVDS_2 VDD_37
AK12 N49 AC15 N21
VSS_38 VSS_94 AVDD_LVDS_3 VDD_38
AK15 R15 U12 N23

C220T

C219T

C202T

C200T

C201T

C142T

C143T

C144T

C145T

C146T

C149T

C150T

C151T

C152T

C153T

C154T

C155T

C156T

C157T

C158T

C159T

C160T

C141T
VSS_39 VSS_95 AVDD_LVDS_4 VDD_39
AK30 R19 W12 R17
VSS_40 VSS_96 AVDD_LVDS_5 VDD_40
AK34 R21 U17
VSS_41 VSS_97 VDD_41
AK38 R23 U10 U19
VSS_42 VSS_98 AVDD_ADAC_1P8 VDD_42
AL8 R25 N2 U21
VSS_43 VSS_99 AVDD_VDAC_1P8_1 VDD_43
AM15 R26 N3 U25
VSS_44 VSS_100 AVDD_VDAC_1P8_2 VDD_44
AM19 R38 N6 U26
VSS_45 VSS_101 AVDD_VDAC_1P8_3 VDD_45
AM21 U15 U6 W25
VSS_46 VSS_102 AVDD_VDAC_1P8_4 VDD_46
AM23 U23 W26
VSS_47 VSS_103 VDD_47
AM25
VSS_48 VSS_104
U28
AVDD33_VGAFE_T0
AV47
VDD_CORE_FB
BJ20 SENSE-VCORE L001T
+3V3-VGAFE I027T
AM26 U30 AU50 S013T
VSS_49 VSS_105 AVDD33_VGAFE_T1 +1V8-MRV +1V8-AVIF 50m
+1V8-OTP
AM28 U32 AT47 AA28
VSS_50 VSS_106 AVDD33_VGAFE_T2 VDD_CPU_1 +VCPU 30H
AM30
VSS_51 VSS_107
U34
AVDD33_VGAFE_T3
AM48
VDD_CPU_2
AC28 RES

100nF

100nF

100nF

100nF

100nF
2.2uF

2.2uF
AP15 U38 AC30

1uF
VSS_52 VSS_108 VDD_CPU_3
AP26 W15 AM38 AC32

6.3V
VSS_53 VSS_109 AVDD18_AVIF_PLL +1V8-AVIF VDD_CPU_4
AT12 W17 AJ48 AC34

C368T

C222T

C221T

C162T

C163T

C166T

C161T

C172T
VSS_54 VSS_110 AVDD_AVIF_1P8_1 VDD_CPU_5
AT15 W19 AT38 AC36
VSS_55 VSS_111 AVDD_AVIF_1P8_2 VDD_CPU_6
AT17 W21 BB47 AE32
VSS_56 VSS_112 AVDD_AVIF_1P8_3 VDD_CPU_7
W23 AE36
VSS_113 VDD_CPU_8
W28 AV12 N30
VSS_114 VDD_IO_1_1 +3V3-STANDBY VDD_CPU_9
W38 AV8 N34
VSS_115 VDD_IO_1_2 VDD_CPU_10
AY10 R28
VDD_IO_1_3 VDD_CPU_11
T2 AY12 R30
AVSS_ADAC VDD_IO_1_4 VDD_CPU_12 L008T I028T
BA13 R32 RES
VDD_IO_1_5 VDD_CPU_13 +1V8-MRV +1V8-AVDD
N10 BF3 R34
AVSS_VDAC_1 VDD_IO_1_6 VDD_CPU_14 30H
N12 BK7 R36
AVSS_VDAC_2 VDD_IO_1_7 VDD_CPU_15

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
2.2uF
10uF

10uF
N8 AY41 U36

1uF
AVSS_VDAC_3 VDD_IO_2 +3V3-MRV VDD_CPU_16
R12 AY43 W30
AVSS_VDAC_4 VDD_IO_3 VDD_CPU_17
U8 AV17 W32

C217T

C218T

C223T

C203T

C168T

C169T

C170T

C171T

C173T

C174T

C167T

C176T

C177T

C179T

C180T

C181T

C182T

C183T

C175T

C243T

C244T

C245T

C246T

C247T

C248T
AVSS_VDAC_5 VDD_IO_4_1 VDD_CPU_18
BA19 W34
VDD_IO_4_2 VDD_CPU_19
AV38 AV21 W36
AVSS_VGAFE_CLEAN VDD_IO_5_1 VDD_CPU_20
VDD_IO_5_2
AV23
VDD_CPU_FB
N41 SENSE-VCPU
AM32 AV25
AVSS_AVIF_1 VDD_IO_5_3
AM34 AV32 H13
AVSS_AVIF_2 VDD_IO_6_1 VDD_M_1 +1V5-MRV
AP32 BA32 H15
AVSS_AVIF_3 VDD_IO_6_2 VDD_M_2
AP34 BA23 H17
AVSS_AVIF_4 VDD_IO_7_1 VDD_M_3
HS1 AT32 BA25 H21
HS_1 AVSS_AVIF_5 VDD_IO_7_2 VDD_M_4
HS2 AT34 AT28 H23
HS_2 AVSS_AVIF_6 VDD_IO_8_1 VDD_M_5 L002T
AV36 AV28 H30 +1V8-AVDD
AVSS_AVIF_7 VDD_IO_8_2 VDD_M_6 +1V8-STANDBY
BB48 BA28 H34
AVSS_AVIF_8 VDD_IO_8_3 VDD_M_7 30H
AV34 K13
VDD_IO_9_1 VDD_M_8
BA34 K19
VDD_IO_9_2 VDD_M_9
BA36 K25
VDD_IO_9_3 VDD_M_10
C4 K26
VDD_IO_10_1 VDD_M_11 L003T I029T
E5 K28
VDD_IO_10_2 VDD_M_12 +3V3-MRV +3V3-AVDD
G3 K32
VDD_IO_10_3 +1V8-MRV VDD_M_13 30H
K1 K36
VDD_IO_11_1 VDD_M_14
100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF

100nF
2.2uF

2.2uF
L4 K38
1uF

1uF
VDD_IO_11_2 VDD_M_15
K40
VDD_M_16
L41
C241T

C242T

C253T

C224T

C225T

C204T

C185T

C186T

C187T

C188T

C189T

C190T

C191T

C184T
VDD_M_17

L006T
I056T
+3V3-MRV +3V3-VGAFE
30H

100nF

100nF

100nF

100nF
C272T

C273T

C274T

C271T
+3V3-STANDBY
100nF

100nF

100nF

100nF

100nF

100nF

100nF
1uF
C263T

C256T

C257T

C258T

C259T

C261T
C260T

C262T
5 2014-02-21

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19570_071_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 123

10-1-53 B, MARVELL - TRANSPORTSTREAM

MARVELL - TRANSPORTSTREAM
B B
+3V3-MRV

U001T

4.7K
88DE3100

SOC_CAM
BE36

R307T
CAM0_RESET
BC34
CAM0_WAIT_N
CAM0_IREQ_N
BH38 R267T 10 CIMAX-SPI-INT CIMAX-SPI-INT
BJ38
CAM0_CD1_N
BH39

4.7K
CAM0_CD2_N
BG38
CAM0_VS1_N

RES
BK38
CAM0_CE1_N
BJ41
CAM_OE_N
BH44

R308T
CAM_WE_N
BK41
CAM_IORD_N
BJ44
CAM_IOWR_N
BJ40
CAM_REG_N

CAM_MISTRT
BC36 R091T 33 TS-PI-SYNC
CAM_MIVAL
BH43 R092T 33 TS-PI-VALID
CAM_MCLKI
BH42 R093T 33 TS-PI-CLK
CAM_MDI[0]
BE38 R095T 33 TS-PI-DATA0
CAM_MDI[1]
BH46 R096T 33 TS-PI-DATA1
CAM_MDI[2]
BG40 R098T 33 TS-PI-DATA2
CAM_MDI[3]
BG44 R099T 33 TS-PI-DATA3
CAM_MDI[4]
BK44 R100T 33 TS-PI-DATA4
CAM_MDI[5]
BE40 R101T 33 TS-PI-DATA5
CAM_MDI[6]
BK47 R105T 33 TS-PI-DATA6
CAM_MDI[7]
BC38 R106T 33 TS-PI-DATA7

BG46
CAM_MOSTRT
BA38
CAM_MOVAL
BJ43
CAM_MCLKO
BJ46
CAM_MDO[0]
CAM_MDO[1]
BE42 R263T 10 TS-OUT2-CLK
CAM_MDO[2]
BJ48 R264T 10 TS-OUT2-SYNC
CAM_MDO[3]
BK49 R265T 10 TS-OUT2-VALID
CAM_MDO[4]
BJ47 R266T 10 TS-OUT2-DATA0
BJ49
CAM_MDO[5]
BH49
CAM_MDO[6]
BJ50
CAM_MDO[7]

BF47
CAM_A[0]
BF48
CAM_A[1]
BD45
CAM_A[2]
BE49
CAM_A[3]
BH50
CAM_A[4]
BC40
CAM_A[5]
CAM_A[6] BE50
CAM_A[7] BD48
CAM_A[8] BD46
CAM_A[9] BB43
CAM_A[10] BB45
CAM_A[11] AY45
CAM_A[12] BG48
CAM_A[13] BD43
CAM_A[14] BG49

CAM_D[0] BG34
CAM_D[1] BH36
CAM_D[2] BJ35
CAM_D[3] BJ34
CAM_D[4] BE34 +3V3-MRV
CAM_D[5] BH37
CAM_D[6] BJ37
BK35
RES

CAM_D[7]
RES
10K

10K

10K

U001T 10K
88DE3100
R291T

R292T

R293T

R369T

SOC_STS
STS0_CLK
BJ17 R255T 10 HDMI-ARC-SEL0
STS0_SOP
BK16 R256T 10 HDMI-ARC-SEL1
STS0_VALD
BH18 R257T 10 HDMI-ARC-SEL2
STS0_SD
BG19 R367T 10 HDCP-IRQn

STS1_CLK
BG15 R259T 10 TS-OUT1-CLK
STS1_SOP
BC17 R260T 10 TS-OUT1-SYNC
STS1_VALD
BH17 R261T 10 TS-OUT1-VALID
STS1_SD
BE17 R262T 10 TS-OUT1-DATA0
10K

10K

10K

10K
R299T

R300T

R301T

R368T
RES

5 2014-02-21

BG2-QTV FHD 2K14 715RLPCB000000005

19570_072_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 124

10-1-54 B, MARVELL - HDMI RX / TX

MARVELL - HDMI RX / TX
B B
U001T
+3V3-STANDBY
88DE3100

HDMI_RX HDMIRX_RX0_CLK_P
AG49 HDMI-SOC-RX0-C+

10K
HDMIRX_RX0_CLK_N
AH49 HDMI-SOC-RX0-C-
AF50 HDMI-SOC-RX0-D0+
HDMIRX_RX0_D0_P U001T

RES
HDMIRX_RX0_D0_N
AF49 HDMI-SOC-RX0-D0-
AD47 HDMI-SOC-RX0-D1+ 88DE3100
HDMIRX_RX0_D1_P

R249T
HDMIRX_RX0_D1_N
AD45 HDMI-SOC-RX0-D1-
AD41 HDMI-SOC-RX0-D2+ HDMI_TX
HDMIRX_RX0_D2_P AG2
AD43 HDMI-SOC-RX0-D2- HDMI_TX_CLK_P
HDMIRX_RX0_D2_N AG1
AG47 HDMI_TX_CLK_N
HDMI_RX0_HEAC_P
SM_RX0_EDDC_SCL
BJ10 R065T 10 HDMI-SOC-RX0-SCL AJ2
BG13 R074T 10 HDMI-SOC-RX0-SDA HDMI_TX_D0P
SM_RX0_EDDC_SDA AH2
BH9 D005T HDMI_TX_D0N
SM_HDMI_RX0_HPD
BG12 +3V3-STANDBY
SM_HDMI_RX0_PWR5V HDMI-SOC-RX0-5V AK2
HDMI_TX_D1P
AK1
AD49 HDMI_TX_D1N
HDMIRX_RX1_CLK_P
AD50 3

10K

10K
HDMIRX_RX1_CLK_N AJ4
AB43 HDMI_TX_D2P
HDMIRX_RX1_D0_P AJ6
AB45 1 U017T HDMI_TX_D2N
HDMIRX_RX1_D0_N
AB49 PDTC144EU
HDMIRX_RX1_D1_P AG6
AC49 RES HDMI_TX_HEACP

R371T

R370T
HDMIRX_RX1_D1_N AG4
Y45 2 HDMI_TX_HEACN
HDMIRX_RX1_D2_P
Y47
HDMIRX_RX1_D2_N
SM_HDMI_CEC
BC13 HDMI-CEC
AE50
HDMI_RX1_HEAC_P
SM_HDMI_HPD
BE13 R231T 10 HDMI-MUX-RESETn
SM_RX1_EDDC_SCL
BJ11 R279T 10 LED1
SM_RX1_EDDC_SDA
BH13 R076T 10 LED2

4.7K
BE15 D011T
SM_HDMI_RX1_HPD
BJ12
SM_HDMI_RX1_PWR5V HDMI-SOC-RX1-5V
Y49 +3V3-STANDBY
HDMIRX_RX2_CLK_P

R250T

RES
Y50
HDMIRX_RX2_CLK_N
V45
HDMIRX_RX2_D0_P

*
V43

*
10K

10K
HDMIRX_RX2_D0_N
V49
HDMIRX_RX2_D1_P
W49
HDMIRX_RX2_D1_N
U47
HDMIRX_RX2_D2_P
U49 * SEE DIVERSITY TABLE

R358T

R281T
HDMIRX_RX2_D2_N
AA50
HDMI_RX2_HEAC_P
SM_RX2_EDDC_SCL
BK13 D012T DIVERSITY-B0 +3V3-MRV
SM_RX2_EDDC_SDA
BJ14 D013T DIVERSITY-B1
BH14

10K
SM_HDMI_RX2_HPD

*
BK10
10K

10K
SM_HDMI_RX2_PWR5V HDMI-SOC-RX2-5V
U001T
U45
HDMIRX_RX3_CLK_P 88DE3100
U43

R077T
HDMIRX_RX3_CLK_N
R49
R359T

R282T
HDMIRX_RX3_D0_P SOC_DEMOD
HDMIRX_RX3_D0_N
T49
AGC_IF
BD49 STRAP I057T
R47 BB50
HDMIRX_RX3_D1_P IF_P
R45 BC50

10K
HDMIRX_RX3_D1_N IF_N
P50 AT49
HDMIRX_RX3_D2_P AVIF_ISET
P49

RES
HDMIRX_RX3_D2_N I037T
U50
HDMI_RX3_HEAC_P
BA15 X341T

R075T
SM_HDMI_RX3_HPD
SM_HDMI_RX3_PWR5V
BG10 HDMI-SOC-RX3-5V CIMAX-SPI-CLK 1
+3V3-STANDBY CIMAX-SPI-CSn 2
AG43 +3V3-STANDBY CIMAX-SPI-MOSI 3
HDMI_RX0_HSDAC_P
HDMI_RX0_HSDAC_N
AG45 STRAP STRAP CIMAX-SPI-MISO 4
CIMAX-SPI-INT 5
6 R097T 150K
RES
RES

RES
RES

RES

*
*

8 7
10K
10K

1%
10K
10K

10K
10K

10K

TYPE
U001T DBG
R361T
R360T

88DE3100
R154T
R155T

R158T
R159T

R160T

HDMI-SOC-RX0-5V
SM_SPI2
SM_SPI2_SS0N
BJ1 R094T 10 I030T CIMAX-SPI-CSn
BH5 R107T 10 I031T SPLASH-ON HDMI-SOC-RX1-5V
SM_SPI2_SS1N
SM_SPI2_SS2N
BC15 D014T DIVERSITY-B2
BG11 D015T DIVERSITY-B3 HDMI-SOC-RX2-5V
SM_SPI2_SS3N

BJ3 R108T 10 I034T CIMAX-SPI-CLK HDMI-SOC-RX3-5V


SM_SPI2_SCLK
SM_SPI2_SDO
BK2 R109T 10 I035T CIMAX-SPI-MOSI
SM_SPI2_SDI
BE11 R110T 10 I036T CIMAX-SPI-MISO

47K

47K

47K

47K
*
*
10K
10K

10K
10K

10K

10K
10K

R283T

R284T

R285T

R286T
R165T
R164T

R163T
R162T

R161T

R363T
R362T

5 2014-02-21

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14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 125

10-1-55 B, MARVELL - CONTROL

MARVELL - CONTROL
B B
+3V3-STANDBY

STRAP

4.7K
4.7K

4.7K
4.7K
4.7K
10K
10K
+3V3-STANDBY

R148T

R166T
R149T

R167T

R170T
R171T
R172T
U001T
88DE3100

RES

RES
RES
RES
RES
SM_MISC SOC-XTAL-IN
AY2

10K

10K

10K

10K

10K
SM_RCLKI
SM_RCLKO
AY1 SOC-XTAL-OUT

SM_RSTIN
BD2 I058T R153T 100 F044T MCU-RESET-INn
BB10 R111T 10 I039T MCU-RESET-OUTn U001T

R187T

R188T

R191T

R192T

R195T
SM_SOC_RSTON
88DE3100
BB6 R112T 10 F066T MCU-JTAG-TCK
SM_TCK SM_GPIO
SM_TRSTN
BB8 R114T 10 F067T MCU-JTAG-TRSTn SM_GPIO[0]
BF1 R143T 10 RC
SM_TMS
BD3 R115T 10 F068T MCU-JTAG-TMS SM_GPIO[1]
BH1 R144T 10 F075T SYSTEM-RESETn
SM_TDI
BD1 R116T 10 F069T MCU-JTAG-TDI SM_GPIO[2]
BB11 R145T 10 STANDBYn
SM_TDO
BF2 R113T 10 F070T MCU-JTAG-TDO SM_GPIO[3]
BD10 R146T 10 DETECT12V
SM_GPIO[4]
BJ2 R147T 10 DDR-ENABLE
SM_TEST_EN
BE2 F072T MCU-TEST-EN
SM_JTAG_SEL[0]
BD6 F073T JTAG-SEL0

RES

RES

RES

RES
SM_JTAG_SEL[1]
BH2 F074T JTAG-SEL1

BK4 R117T 10 I040T SOC-RXD-SERVICE

10K

10K

10K

10K

10K
SM_UART0_RXD
SM_UART0_TXD
BH6 R118T 10 I041T SOC-TXD-SERVICE
SM_UART0_CTSN
BJ6 R119T 10 SCL-PMIC
SM_UART0_RTSN
BF10 R120T 10 SDA-PMIC

R189T

R190T

R193T

R194T

R196T
SM_UART1_RXD
BH8 R121T 10 SOC-RXD-RF4CE
SM_UART1_TXD
BJ7 R122T 10 SOC-TXD-RF4CE

SM_ADCI[0]
BB3 R123T 5.6K KEYBOARD
SM_ADCI[1]
BB2 R124T 6.8K WOLAN-IRQn
SM_ADCI[2]
BA2 R125T 6.8K AMBI-TEMP
SM_ADCI[3]
BB1 R126T 10 POWER-OK
I043T
SM_0P9V_ENN
AY8 MCU-OP9V-ENn

SM_ISET
AW2 I060T MCU-ISET
I059T
R366T
10K
R365T

6.04K
4.7K

4.7K
4.7K
4.7K
1K
100nF

100nF

100nF

100nF

+3V3-STANDBY +3V3-STANDBY
R364T

C249T

C250T

C251T

C252T

R175T
R197T

R169T

R311T

R173T
R174T
10K

22K

10K

10K
F092T

R288T

R289T
X206 5
F040T
4
F041T
3 R341T 47 I014T SOC-RXD-SERVICE

2 F042T R342T 47 I012T SOC-TXD-SERVICE


1

D003T

D004T
S055T

S056T
+3V3-STANDBY

5.1V

5.1V
X310

470
1 SOC-XTAL-IN
2
3 X006T
4 5 1 3 SOC-XTAL-OUT

R346T
TYPE

2
4
10pF

10pF
50V

50V

GREEN
D002T
C269T

C268T
3
+3V3-STANDBY
MCU-RESET-INn 1 U009T
C270T 100nF PDTC144EU
U010T

3
16V
NCP803 2
VCC
RESET
2 MCU-RESET-INn

100
GND

MCU-RESET-OUTn R270T 100

R271T
X300T
SKHU
3 1 SOC-RESET-INn
4 2

5 2014-02-21

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19570_074_140523.eps
14-05-23

2014-Oct-22 back to
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Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 126

10-1-56 B, I2C MUX

I2C MUX
B +3V3-MRV +3V3-MRV
B

RES
4.7K

4.7K

4.7K

4.7K

10K

10K

10K

10K

10K
U001T

R176T

R177T

R178T

R179T

R180T

R181T

R182T

R183T

R184T
88DE3100

SOC_MISC
RSTIN
BH15 R127T 10 SOC-RESET-INn
BE25 R135T 10 I044T
ATP

GPIO_A
BJ16 R136T 10 HDMI-HPD0
GPIO_B
BE19 R137T 10 HDMI-HPD1
GPIO_C
BC19 R138T 10 HDMI-HPD2

TW0_SCL
BK26 R139T 10 SCL-BE
TW0_SDA
BJ26 R140T 10 SDA-BE

TW1_SCL
BH26 R141T 10 SCL-TW1
TW1_SDA
BE26 R142T 10 SDA-TW1

RES

RES

RES
RES
RES
10K

10K

10K

10K

10K
R185T

R186T

R150T

R151T

R152T
X322
SDA-TW1 RES S036T SDA-FE SCL-FE F078T 1
RES S037T SDA-SRF 2
RES S034T SDA-CYPRESS SDA-FE F079T 3
RES S035T SDA-HDMI 5 4

TYPE
X323B SCL-TW1 RES S040T SCL-FE
F057T
1 SCL-BE RES S041T SCL-SRF
2 F065T RES S038T SCL-CYPRESS X321
F058T
3 SDA-BE RES S039T SCL-HDMI SCL-SRF 1
4 5 2
SDA-SRF 3
TYPE 5 4

TYPE
X320
F064T
1 SCL-TW1
2 F059T
3 SDA-TW1 X328
4 5
F063T
+3V3 SCL-CYPRESS F082T 1
+3V3 2
TYPE SDA-CYPRESS F083T 3
X329 5 4 F081T
1 F060T SCL-PMIC
2 F061T +3V3 TYPE

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K

4.7K
3 F062T SDA-PMIC
S028T

S030T

S032T

4 5
RES

RES

U011T 16 X327
TYPE SCL-HDMI F084T 1

R333T

R334T

R335T

R336T

R337T

R338T

R339T

R340T
PCA9546APWR
2
SDA-HDMI
VCC

F085T 3
SDA-TW1 15
SDA SD0
4 S003T SDA-FE 5 4 F086T
SCL-TW1 14
SCL SC0
5 S020T SCL-FE
TYPE
SYSTEM-RESETn R276T 10 3
RESET SD1
6 S022T SDA-SRF
SC1
7 S023T SCL-SRF
I067T 1
A0
2
A1 SD2
9 S024T SDA-CYPRESS
I068T
I069T 13
A2 SC2
10 S025T SCL-CYPRESS

SD3
11 S026T SDA-HDMI
S029T

S031T

S033T

12 S027T SCL-HDMI
RES

SC3
GND
8

+3V3 +3V3 +3V3


100nF

16V
C371T

4.7K

4.7K

4.7K

4.7K
10K

10K

10K

U016T
14

PCA9543APWR
X330
R351T

R352T

R355T
R353T

R354T

R356T

R357T
VCC

SCL-PMIC0 1
SCL-PMIC 12
SCL SD0
5 SDA-PMIC0 2
SDA-PMIC 13
SDA SC0
6 SCL-PMIC0 SDA-PMIC0 3
4 5 4
INT0
11
INT
SD1
9 SDA-PMIC1 TYPE
SYSTEM-RESETn R350T 10 3
RESET SC1
10 SCL-PMIC1
8
INT1
1
A0
2 X332
A1
GND

SCL-PMIC1 1
2
SDA-PMIC1 3
7

5 4 5 2014-02-21

TYPE
BG2-QTV FHD 2K14 715RLPCB000000005

19570_075_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 127

10-1-57 B, HDMI MUX SiL9287B

HDMI MUX SiL9287B


B B
I015H
VCC33
MICOM-VCC33

10K
SBVCC33

1uF

16V
U003H

C027H

R005H
SII9287B

9
27
64

37

38
MICOM_VCC33

SBVCC33
VCC33

HPD0 31
CBUS_HPD0
32
+AIN-5VF R0PWR5V
R018H I027H
AIN-5V +AIN-5VF HDMI0-SDA 29
DSDA0
10
HDMI0-SCL 30
DSCL0 R4PWR5V
49
R4PWR5V

4,7K
1uF

16V
RX0-C- 65 48 R002H 10K

5%
N DSCL4
C039H

RX0-C+ 66
P
R0XC
DSDA4
47 R004H 10K

R032H RX0-0- 67 51
N CEC_D
RX0-0+ 68
P
R0X0
R019H I028H
BIN-5V +BIN-5VF RX0-1- 69
N N
57 HDMI-RX3-2-
10
RX0-1+ 70
P
R0X1 TX2
P
56 HDMI-RX3-2+
4,7K
1uF

16V

RX0-2- 71 59 HDMI-RX3-1-
5%

N N
C040H

RX0-2+ 72
P
R0X2 TX1
P
58 HDMI-RX3-1+
R033H

HPD1 35
CBUS_HPD1 N
61 HDMI-RX3-0-
36 TX0 60 HDMI-RX3-0+
+BIN-5VF R1PWR5V P
R020H I029H
CIN-5V +CIN-5VF HDMI1-SDA 33
DSDA1 N
63 HDMI-RX3-C-
10
HDMI1-SCL 34
DSCL1
TXC
P
62 HDMI-RX3-C+
4,7K
1uF

RES R039H
16V

RX1-C- 1 55 I033H
5%

N TPWR_CI2CA MICOM-VCC33
C041H

RX1-C+ 2
P
R1XC
4,7K
50
R034H

CEC_A
RX1-0- 3
N
RX1-0+ 4 R1X0 52 I026H R029H 10K
P INT +3V3
R021H I030H
DIN-5V +DIN-5VF RX1-1- 5
N
S001H I002H HDMI-MUX-IRQn
10
RX1-1+ 6
P
R1X1
CSCL
54 R043H 10 SCL-HDMI
4,7K

R044H 10 SDA-HDMI
1uF

53
CSDA
16V

RX1-2- 7
5%

N
C042H

RX1-2+ 8 R1X2 10

4,7K
P DB002H
RSVDL 28
R035H

HPD2 41
CBUS_HPD2
42
+CIN-5VF R2PWR5V

R040H
HDMI2-SDA 39
DSDA2
HDMI2-SCL 40
DSCL2

RX2-C- 11
N
RX2-C+ 12
P
R2XC

RX2-0- 13
N
RX2-0+ 14
P
R2X0

RX2-1- 15
N L007H I019H R017H I020H
RX2-1+ 16 R2X1 10
P +5V-FE R4PWR5V
30H 5%

100K
RX2-2- 17

RES
N
RX2-2+ 18
P
R2X2

6.3V

16V
C033H

C017H
HPD3 45
CBUS_HPD3

R001H

100nF
46
+DIN-5VF R3PWR5V

1uF
HDMI3-SDA 43
DSDA3
HDMI3-SCL 44
DSCL3

RX3-C- 19
N L011H I021H
RX3-C+ 20 R3XC
+3V3
P SBVCC33

RES

RES
30H
RX3-0- 21 RES
N
RX3-0+ 22 R3X0

16V
P

C034H

C018H
10uF
RX3-1-

100nF
23
N
RX3-1+ 24
P
R3X1

RX3-2- 25
N
R028H 10K HDMI-MUX-RESETn RX3-2+ 26 R3X2
+3V3-STANDBY P
EPAD
L008H I022H
(GND)
+3V3-HDMI VCC33

10uF

10uF
30H
73

16V

16V

16V
F016H

C035H
C036H

C019H

C020H

C021H
R007H 18K ATX-DDC-SDA
+5V-FE

100nF

100nF

100nF
F014H
R006H 18K ATX-DDC-SCL

F015H

U001H
F013H F011H AO3414
F017H
+3V3 +3V3-HDMI
2

F010H F012H

F001H
1

5 2014-02-21

+5V-FE
10K R003H
I001H BG2-QTV FHD 2K14 715RLPCB000000005

19570_076_140523.eps
14-05-23

2014-Oct-22 back to
div.table
Circuit Diagrams and PWB Layouts QV14.1E LA 10. EN 1

10-1-58 B, 715RLPCB0000000055 - LAYOUT TOP

X003
X002D X070 X003D X073 X001D X072 X008
X002 X031 X003 X008
X020 X025 X026
X002D X003D X001D
X031
X020 X026 X055 X051 X050
X025 C164T

C004U
1 6 40
11 1 1

U026B
1

8
C031T

U026B
X314B

R025T

X011U
C164T X055 X051 5 1 X050

C030T
R026T
R319B

C026T

C029T

R132T

C216B
X070 X073 X072
C202B
R001U

R133T

C038T
X313B

C303B
C213B
X312B

C018U
S002U R140B

C018U

5
C027T

C039T
C041T

R130T
R134T

C025T

C147T
S002T

R128T

C339B
R131T

C040T

C205B

R114B
X314B

R051T

C042T
1
X011U R121B

X313B X312B

R227B

R226B

R225B

R224B
X273

X273

R088B

R089B

R086B
C028T
C148T

R129T

C339B
C012T R123B R113B
R216T
C337B

C011T
R240B B
D006B C E
K A C358B

R064T
U017B

R064T
R370T

D045B

D031B
A K U017B
C069D C070D C068D C067D D008B

D038B D042B
R371T
E C

3
B

C023D

C010D

C009D
C024D

R245B
C072D C071D

R087B
U004B
C044B

C020D C002D C043B

D041B D043B
D040B

C020U
C042B

C020U
C041B

X017B

L003D

L002D
C040B

L001D
U019B AJ1 B1

L003D

L004D

L002D

L001D
L004D
C039B

G
D2
D1 C038B
AK2
D028B U004B
C037B
X017B A3 C071B

D039B
C227B
C036B R019B
U019B

X308B

D054B
C035B R018B

D044B
X274 S D4 C034B

C064D
D3 C067B

X011B
C033B

S001U
S017B
C064D
C032B GND

A22
X011B
INH VIN

A1
C021D
C031B

U003U
R051B

X308B

C013U
R045B R214B R052B

S018B
C030B
U003U

X274

C021D
R036D
C029B

R033B
R318B
C042D R215B
C219B
R107B
BYP VOUT
R027D

C012D
C004D C007D C016D
C003D C006D
R095B R108B
R316B
C019U C014U

R032B
R096B

R077B
R029D
D063B

R078B
R014D R038B

R079B
C007D
C004D
R043B

C003D

C006D
R042B

R082B
D005B
R041B
R048B

U023B

27
U023B
U030B

28
R080B
R015B
R047B

D014B

R081B
R050B

C029F D012B
R049B

R029B

R031B
C022D U031B

R072B
K A

C063D

R073B
D073B
U030B

R030B
R035D K A

D025B

D069B
R076B
C028D R040B

X090
D024B

D055B
D074B
K A

R074B
C029F C022D U031B D013B D075B
K A
R039B

U005B

X323B X325B

X323B

R075B
U004D
U021B D076B
K A

D056B
C063D
D072B

S002D

C207B

D059B
AK28 A28

AB22
8 5

C012U
C C

AB1
U005D

X090
C210B
U003D R012D

C210B
U004D C072B

U005B

D058B
B E B E
AJ30 B30 D057B R246B R021B

U003D E B R011D

C069U
R020B
C
U021B R046B

R017D
R131B

D033B
R013D C068B
U005D U001D

U001B
U001B

D060B
D032B
C
B E S007D S008D
R130B
R016D

U001D
C041D R028D R019D

1 4 X065B X065B

R037D

C048U
R038D DB020B
DB019B DB014BDB023B

C069U
DB026B DB024B DB016B DB009B DB004B
DB021B DB013B DB006B

R022B
R023B
R056F

L010U
DB027B DB025B DB017B DB011BDB008B

X325B
DB015B

8B
DB007B DB005B

01
DB012B DB022B
C098F C115F R039F

DB
R054F C107F DB010B
R092B

R094B

R090B
C208B

C041U

C042U
R055F C108F
C209B

R043F

R044F

R093B

R091B

4
U010U
U004F

C056U
C113F

1
R057F R047U C354B C353B

K
D001B
U009B
C355B C356B
R058F R059F R236B C343B

L010U

C116F
R292B

C058U
C114F

R250B
A
R045U R196B R197B
C201B R222B
L027B

R040F

C117F
C201B R036U C344B C345B
L028B

8
C068U
C

C095F

C045B
X013B 1 6 C386B

X296
C071U
U009B C299B C292B

1
2
16
X342B

1
C099F R046U
C057U

X015B

1
B E C372B

X006F
C367B

R053F

U028B
U010U
U004F C162U

X006F

C293B

C294B
C105F
1 6 L004U C064U
L027B
X342B C369B
L028B C371B

U028B
X344B

C073U

C074U

C096U
10
C148U
X013B

1
U013U
C009F

R048F

R061F

C096F

R016F

R047F
C368B C370B
X292

C002B
X344B

9
C182U X015B

L028F
D001T

L030F

S030F

6
C079U

6
C102F

C162U

S029F
C011F

C133F
C381B R120B

D044T

C077U

C076U

C075U
L029F

C352B

R184B

C357B

S010B
R238B R118B

K
D004B
C135F

C182U

S027F
C035F
L003U

L031F
R119B C378B
R015T R018T R019T
D043T C377B R112B

C129U
R008T R006T R007T R012T
C134F R153B

A
R233B
C040F

D027T D019T

X296
R045F

R010T
R060F S025F

L003U
D047T

C176U

C177U

R017T
X292 L017U

C314T

C350T

X071
D018T

C291T

R009T
D035T

R016T

C363T
C363T
C341T

C102U

C101U
C126F R190T

C292T
U006F

C130U

C310T
C132F

R011T

L012U
D036T

C342T

R320T
R020T

U004T

U005T

U003T

U002T
U006F

U003T
C290T

C301T
R278T
C109U C359T

D039T

1
L012U
C127F
L017U C266T

R095U

X071
C108U
D028T

C320T
C322T

C339T
R021T

D033T

C169U

C293T
R120U
R046F

U004T
R277T

U005T
D025T

C337T
L032F

C326T
C027U C168U C267T

C294T
C023F
L010F
C166U

D040T C052U

4
C055F 1 D032T D007T C265T

U002T
4
L014F

C285T
L015F 5 D034T D020T

L005T
C065F C068F
8

C165U

L002U
C144U
C141U

C178U

C179U
C055F D046T C051U

C026U
D038T

L002U
C123U

C053U

C054U
U017U U027U D024T D029T D030T D041T D021T C123U

X030
L015F L014F D031T D022T 4 1

C170U

C364T
C167U

C364T
5 8 1 4
U017U
R113U
B
C130F C E

C072T
C070F
C070F
C118F

U025U U027U C046U


U011U
IN
OUT_1
GND U025U
U018U U018U

1
1
C174U C005T

C233T
C073F 12 9

C039U
R121U

C181U

R117U

R119U
C066F C069F R114U

D037T

C107U
C025U E C
13 8

X029

X029
B R038U
R109U
C130F

U011U

C172U
5 8

C
R037U

C045U
L027F

D042T
R074U

R108U
16 5

U024U
R082U

C073F

X030
C065T

U005F C150U
1 4

R049T

R103T

R060T

R090T
R054T
R050T

R104T
U024U
R049U L007T

R055T
R110U

R115U

R116U

E
R218T R225T

5
R111U R112U R042U
C038U
X002T
C008T

R067U

R041U

C118U

C067U

C060U

C062U
OUT_2
C072F C072F U001T D017T
X329
C043U

C044U
R077U

C009T
U005F X002T

8
5.8mm

R167T

C074F X329

C270T
R166T
K A C074F

X304C
C071F R372T
C158T
C159T
L002T

D010T

1
D008F
D008F C071F X006C U017C
R223T R258T
C049T L006U

C243T

C245T
R024T

X304C

1
X001E
X001E
C183T

C175T

C246T
C165T L006U
U001T

C066C
C109C L007C

C018E
C014C

C037U

4
C116U

C155U
R162C R164C R165C R160C R161C
C165T C234T

C048C
C007T

R235T
R062T C016C
C015C
L008C R163C R155C R154C R156C R157C R152C R153C
C275T C222T

X261 C234T

C243C

C171C

C170C

L003T

C224T
S017C C020C C110C C069C C070C C071C C072C C068C C067C

C047C

S014C

S001C

19
R345T L001T

R062T S019C C017C C013C C076C C075C C077C C078C C073C C074C
C033U
1

R097T

C368T
X006T
R124T
S018C C018C

R222C

R140C

R139C

R138C

C169C
C104U
C019C
U007U C034U
X281

R036C C269T R311T C099U


R075T
R366T
C154U

8
C268T
R026C
R025C

X027
R221C

X027
R365T
C251T

R307T

R308T
R126T R077T R009E

C160U
R030U

R031U

C021U
C093C R115T R011E
R125T

U007U

X006T
U009C

R116T

R080U
R079U
X001C

C219T
R177C

C154T
R012E

R010E
C215C

R123T

1
R170T R153T
C252T C022U

C055C

C153T
R364T

X261
4

C250T R173T C249T


S003C R020C
~OE

VCC

R132C

C202T
L014U

R187T
X301T
X281

R189T
X310

C141T
R131C R143T C152U C153U
U009C

C216C
R172T
R144T
A

C220T
R130C R113T
C032U C035U

X006C
C092C R175T C316T
R129C R164T
GND

L014U
R147T C031U C036U

R367T

R368T
X310

C221C
S002C R128C R155T
R022C

R021C

2 2 D005T L013U

R268T
R075C 1 1 X001C R127C C065U
R196T
R281T R282T

D013T C055C

R117T
U008U
C121U

X301T

R118T

R305T
R358T R359T

D012T

R369T
R195T

R076T
R122T
C214C
R126C

R255T
R256T

R035T

R205T

R232T

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