CS-430 (MPI)_ _ Final Year (EE)

Instruction Encoding
Machine Language
• Native binary code microprocessor uses as its instructions to control its operation.
• For Intel microprocessors (till core 2) , instructions vary in length from 1 to 13 bytes
– Over 100,000 variations of machine language instructions.
– there is no complete list of these variations
• All information contained in an instruction are encoded in machine code.
• This information includes
– Opcode
– What operands are used
– Addressing mode
– Whether 8 or 16 bit operation
– Where the operands are located (reg/memory)
• For 8086/88 instruction length vary from 1 to 6 byte

Instruction Encoding
• Most instruction follow a general format, However, exceptions exist

General Instruction Format

Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6

LOW HIGH
Opcode D W MOD REG R/M LOW data HIGH data
disp/data disp/data

Register operand/registers to use in EA calculation

Register operand/ extension of opcode
Addressing mode with displacement length
Word (1) / Byte(0) size operation
Direction of data flow, 1→ R/M to REG , 0→ REG to R/M
Opcode

Page 1 of 8
CS-430 (MPI)_ _ Final Year (EE)
Byte 1:
Opcode
D W

• Opcode field specify operation to be performed.

• Opcode is usually 1 or 2 byte long for most machine language instructions
• 6 bit Opcode for MOV instruction
• Each instruction has 1 or more opcodes
• For example MOV has many different opcodes to specify and differentiate between the type of
operands used.
• 100010 is used when data transfer is between reg/reg or reg/memory.
• 1100011 (7 bit) is used when immediate value is transferred to reg/memory.
D (Direction) of data flow : D = 1 → R/M to REG D =0 → REG to R/M
W (word) : W = 1 (Word ) W = 0 (Byte) size operation

Byte 2:
MOD REG R/M

MOD field specifies the addressing mode (MOD) & whether a displacement is present
MODE (2 bits) Description
11 Register mode-specifies the second register operand along with W field
00 Memory operand addressing mode without displacement or direct displacement
01 Memory operand addressing mode and 8-bit displacement 1
10 Memory operand addressing mode and 16-bit displacement

MOD field for the 16-bit instruction mode

1 All 8 bit displacements are sign extended to 16-bit displacements

REG field in conjunction with D & W fields specifies the register operand (or sometimes used for opcode
extension)

Page 2 of 8
CS-430 (MPI)_ _ Final Year (EE)
R/M field is interpreted according to the MOD field and gives information about the second operand, or
specifies register to be used for EA calculation

For MOD = 11:

REG & R/M & is interpreted according to the given table

Code W=0 (Byte) W = 1 (word) W=1 (doubleword)
000 AL AX EAX
001 CL CX ECX
010 DL DX EDX
011 BL BX EBX
100 AH SP ESP
101 CH BP EBP
110 DH SI ESI
111 BH DI EDI

For MOD = 00 OR 01 OR 10

R/M selects memory operand addressing mode and specifies register to be used for EA calculation & is
interpreted according to the given table
R/M Code MOD = 00 MOD = 01 MOD = 10
000 DS : [BX + SI] DS : [BX + SI + D8] DS : [BX + SI + D16]
001 DS : [BX + DI] DS : [BX + DI + D8] DS : [BX + DI + D16]
010 SS : [BP + SI] SS : [BP + SI + D8] SS : [BP + SI + D16]
011 SS : [BP + DI] SS : [BP + DI + D8] SS : [BP + DI + D16]
100 DS : [SI] DS : [SI + D8] DS : [SI + D16]
101 DS : [DI] DS : [DI + D8] DS : [DI + D16]
110 SS : [BP]* SS : [BP + D8]* SS : [BP + D16]
111 DS : [BX] DS : [BX + D8] DS : [BX + D16]
Effective Address Calculation
* Special addressing mode

Page 3 of 8
CS-430 (MPI)_ _ Final Year (EE)

Byte 3,4,5 & 6:

Byte 3 Byte 4 Byte 5 Byte 6
LOW disp/data HIGH disp/data LOW data HIGH data

Example 1:
Encode the instruction MOV AL, BL. Assume that 6-bit Opcode for MOV is 100010.
Solution:
D decides direction of data flow from REG to R/M or vice versa, so two encodings are possible.

a. D= 1 (R/M to REG) [ code for AL = 000 , code for BL= 011 ]

MOV 8b Reg mode AL BL
1 0 0 0 1 0 1 0 1 1 0 0 0 0 1 1
Opcode D W MOD REG R/M
HEX code = 8A C3 H

b. D= 0 (REG to R/M) [ code for AL = 000 , code for BL= 011 ]

MOV 8b Reg mode BL AL
1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0
Opcode D W MOD REG R/M
HEX code = 88 D8 H
Example 2:
Encode the instruction ADD AX, [SI]. Assume that 6-bit Opcode for ADD is 000000.
Solution:
Direction of data flow is from R/M to REG so, D must be 1
ADD 16 b w/o disp AX [SI]
0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0
Opcode D W MOD REG R/M

HEX code = 03 04 H

Page 4 of 8
CS-430 (MPI)_ _ Final Year (EE)
Example 3:
Encode the instruction XOR CL, [1234 h]. Assume that Opcode for XOR is 001100.
Solution:
Direction of data flow is from R/M to REG so, D must be 1
XOR 8b Direct disp. CL direct
0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 0
Opcode D W MOD REG R/M

Byte 3 Byte 4
0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0
LOW displacement HIGH displacement

HEX code = 32 0E 34 12 H
Example 4:
Encode the instruction ADD [BX][DI] + 1234 h, AX. Assume that Opcode for ADD is 000000.
Solution:
Direction of data flow is from REG to R/M so, D must be 0
ADD 16 b 16b disp. AX [BX][DI]
0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1
Opcode D W MOD REG R/M

Byte 3 Byte 4
0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0
LOW data HIGH data

HEX code = 01 81 34 12 H

Page 5 of 8
CS-430 (MPI)_ _ Final Year (EE)
Example 5:
Encode the instruction MOV [BP + DI + 1234h] , ABCD H. Assume that Opcode for MOV is 1100011.
[Note: If immediate value is to be transferred to register or memory using base relative plus index

addressing mode, then REG field is fixed at 000 & Instruction follows a special format as given below.]

7 bit Opcode W
Solution:
MOV 16 b 16b disp BP + DI
1 1 0 0 0 1 1 1 1 0 0 0 0 0 1 1
Opcode W MOD REG R/M

Byte 3 Byte 4
0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0
LOW displacement = 34 h HIGH displacement = 12 h

Byte 5 Byte 6
1 1 0 0 1 1 0 1 1 0 1 0 1 0 1 1
LOW data = CD h HIGH data = AB h

HEX code = C7 83 34 12 CD AB H
Example 6:
Encode the instruction MOV [BP + DI + 1234 h] , DS
Note: For MOV from segment register to memory, format is
Byte 1 Byte 2 Byte 3 Byte 4

1 0 0 0 1 1 0 0
Opcode MOD 0 SR R/M LOW displacement HIGH displacement

Segment Register SR
ES 00
CS 01
SS 10
DS 11

Page 6 of 8
CS-430 (MPI)_ _ Final Year (EE)
Solution:
MOV 16b disp. DS BP + DI
1 0 0 0 1 1 0 0 1 0 0 1 1 0 1 1
Opcode MOD 0 SR R/M

Byte 3 Byte 4
0 0 1 1 0 1 0 0 0 0 0 1 0 0 1 0
LOW displacement = 34 h HIGH displacement = 12 h

HEX code = 8C 9B 34 12 H

Practice Problems (to be sent on group)

Question 1) Encode the given instructions.
1. MOV AX,2000 h 4. MOV DI, 120 h 7. MOV [DI], AH
2. MOV DS, AX 5. MOV CX, 10 h 8. PUSH AX
3. MOV SI, 100 h 6. MOV AH, [SI]

Question 2) Explore purpose of these instructions.

PUSHF, PUSHA, PUSH [SI], PUSH DATA, POPF, POPA, XCHG, XLAT

Note: MOV [SI], 5h will generate error as size of data transfer is not known.
Corrected Form is MOV BYTE PTR [SI], 5

************

Page 7 of 8