ADMV1014 (24 - 44 GHZ Downconverter)

24 GHz to 44 GHz,
Wideband, Microwave Downconverter

Data Sheet ADMV1014
FEATURES FUNCTIONAL BLOCK DIAGRAM
VCC_MIXER
Wideband RF input frequency range: 24 GHz to 44 GHz
2 downconversion modes
DVDD
SCLK
LO_N
LO_P
GND
GND
SDI
Direct conversion from RF to baseband I/Q
Image rejecting downconversion to complex IF
LO input frequency range: 5.4 GHz to 10.25 GHz ADMV1014
LO quadrupler for up to 41 GHz SEN VCC_QUAD
Matched 50 Ω, single-ended RF input, and complex IF outputs

I_P BG_RBIAS
Option between matched 100 Ω balanced or 50 Ω single- ×4
ended LO inputs I_N RST
100 Ω balanced baseband I/Q output impedance with
IF_I VCC_BG
adjustable output common-mode voltage level
Image rejection optimization GND
90°
VCC_LNA_1P5
0°
Square law power detector for setting mixer input power
Variable attenuator for receiver power control IF_Q GND
Programmable via a 4-wire SPI interface

Q_N RF_IN
32-terminal, 5 mm × 5 mm LGA package
Q_P DET GND
APPLICATIONS
Point to point microwave radios
Radar, electronic warfare systems
GND
VCTRL
SDO
VDET
VCC_VGA
VCC_IF_BB
VCC_VVA
VCC_LNA_3P3
Instrumentation, automatic test equipment (ATE)
17172-001
Figure 1.
GENERAL DESCRIPTION
The ADMV1014 is a silicon germanium (SiGe), wideband, provide two single-ended complex IF outputs anywhere between
microwave downconverter optimized for point to point microwave 800 MHz and 6000 MHz. When used as an image rejecting
radio designs operating in the 24 GHz to 44 GHz frequency range. downconverter, the unwanted image term is typically
The downconverter offers two modes of frequency translation. suppressed to better than 30 dBc below the wanted sideband.
The device is capable of direct quadrature demodulation to The ADMV1014 offers a flexible local oscillator (LO) system,
baseband inphase (I)/quadrature (Q) output signals, as well as including a frequency quadruple option allowing up to a 41 GHz
image rejection downconversion to a complex intermediate range of LO input frequencies to cover a radio frequency (RF)
frequency (IF) output carrier frequency. The baseband outputs input range as wide as 24 GHz to 44 GHz. A square law power
can be dc-coupled, or, more typically, the I/Q outputs are detector is provided to allow monitoring of the power levels at
ac-coupled with a sufficiently low high-pass corner frequency the mixer inputs. The detector output provides closed-loop
to ensure adequate demodulation accuracy. The serial port control of the RF input variable attenuator through an external
interface (SPI) allows fine adjustment of the quadrature phase op amp error integrator circuit option.
to allow the user to optimize I/Q demodulation performance. The ADMV1014 downconverter comes in a compact, thermally
Alternatively, the baseband I/Q outputs can be disabled, and the enhanced, 5 mm × 5 mm LGA package. The ADMV1014 operates
I/Q signals can be passed through an on-chip active balun to over the −40°C to +85°C case temperature range.
Rev. A Document Feedback

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ADMV1014 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1 Image Rejection Downconversion ........................................... 29
Applications ....................................................................................... 1 Detector ....................................................................................... 29
Functional Block Diagram .............................................................. 1 LO Input Path ............................................................................. 29
General Description ......................................................................... 1 Power-Down ............................................................................... 29
Revision History ............................................................................... 2 Serial Port Interface (SPI) ......................................................... 30
Specifications..................................................................................... 3 Applications Information .............................................................. 31
Serial Port Register Timing ......................................................... 5 Error Vector Magnitude (EVM) Performance ....................... 31
Absolute Maximum Ratings............................................................ 6 Baseband Quadrature Demodulation to Very Low
Thermal Resistance ...................................................................... 6 Frequencies ................................................................................. 32
ESD Caution .................................................................................. 6 Performance at Different Quad Filter Settings ....................... 32
Pin Configuration and Function Descriptions ............................. 7 VVA Temperature Compensation............................................ 33
Typical Performance Characteristics ............................................. 9 Performance Between Differential vs. Single-Ended LO Input
....................................................................................................... 33
I/Q Mode ....................................................................................... 9
Performance across RF Frequency at Fixed IF and Baseband
IF Mode........................................................................................ 17 Frequencies ................................................................................. 34
Output Detector Performance .................................................. 24 Recommended Land Pattern .................................................... 35
Return Loss and Isolations ........................................................ 25 Evaluation Board Information ................................................. 35
M × N Spurious Performance ................................................... 27 Register Summary .......................................................................... 36
Theory of Operation ...................................................................... 28 Register Details ............................................................................... 37
Start-Up Sequence ...................................................................... 28 Outline Dimensions ....................................................................... 42
Baseband Quadrature Demodulation (I/Q Mode) ................ 28 Ordering Guide .......................................................................... 42
REVISION HISTORY
4/2019—Rev. 0 to Rev. A Changes to Return Loss and Isolations Section, Figure 95, and
Changes to Figure 1 .......................................................................... 1 Figure 97 .......................................................................................... 25
Changes to Table 3 and Thermal Resistance Section................... 6 Changes to Figure 99 and Figure 101 .......................................... 26
Changes to Figure 3 and Table 5 ..................................................... 7 Changes to Start-Up Sequence Section and Baseband
Changes to Figure 14 ...................................................................... 10 Quadrature Demodulation (I/Q Mode) Section ....................... 28
Changes to Figure 19 Caption....................................................... 11 Changes to Image Rejection Downconversion Section
Changes to Figure 27 ...................................................................... 12 and LO Input Path Section ............................................................ 29
Changes to Figure 51 Caption and Figure 52 Caption .............. 17 Change to Serial Port Interface (SPI) Section............................. 30
Changes to Figure 63 Caption and Figure 64 Caption .............. 19 Changes to Figure 111 ................................................................... 32
Changes to Figure 69 Caption and Figure 70 Caption .............. 20 Changes to Table 18 and Table 19 ................................................ 41
Changes to Figure 75 ...................................................................... 21
Changes to Figure 79 ...................................................................... 22 10/2018—Revision 0: Initial Version
Rev. A | Page 2 of 42
Data Sheet ADMV1014
SPECIFICATIONS
RF amplitude = −30 dBm, measurements performed with a 0 mV dc bias. VCC_MIXER = VCC_QUAD = VCC_BG = VCC_LNA =
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B set to 0x727C, Register 0x03, Bits[12:13] set to 11, and
ambient temperature (TA) = 25°C, unless otherwise noted.
Measurements are in IF mode, performed with a 90° hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1, unless otherwise noted.
Measurements in I/Q mode are measured as a composite of the I and Q channel performance, common-mode voltage (VCM) = 1.15 V,
Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless otherwise noted.
Table 1.
Parameter Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGES
RF Input 24 44 GHz
LO Input 5.4 10.25 GHz
LO Quadrupler 21.6 41 GHz
IF Output 0.8 6.0 GHz
Baseband (BB) I/Q Output DC 6.0 GHz
LO AMPLITUDE RANGE −6 0 +6 dBm
I/Q DEMODULATOR PERFORMANCE
Conversion Gain At maximum gain
24 GHz to 42 GHz 12.5 17 dB
42 GHz to 44 GHz 12.5 17 dB
Voltage Variable Attenuator (VVA) Control Range 19 dB
Single Sideband (SSB) Noise Figure At maximum gain
24 GHz to 42 GHz 5.5 8 dB
42 GHz to 44 GHz 6 8.5 dB
Input Third-Order Intercept (IP3) At maximum gain
24 GHz to 42 GHz 0 dBm
42 GHz to 44 GHz −1 dBm
Input Second-Order Intercept (IP2) 24 GHz to 44 GHz, at maximum gain 45 dBm
Input 1 dB Compression Point (P1dB) At maximum gain
24 GHz to 42 GHz −14 −10 dBm
42 GHz to 44 GHz −15 −11 dBm
Amplitude Balance ±0.5 dB
Phase Balance DC < baseband frequency (fBB) < 2 GHz 1 Degrees
2 GHz < fBB < 4 GHz 2 Degrees
4 GHz < fBB < 6 GHz 4 Degrees
Image Rejection 24 GHz to 44 GHz, at maximum gain
Uncalibrated 45 dBc
Calibrated 52 dBc
IF DOWNCONVERTER PERFORMANCE
Conversion Gain At maximum gain
24 GHz to 42 GHz 12.5 17 dB
42 GHz to 44 GHz 11.5 16 dB
VVA Control Range 19 dB
SSB Noise Figure At maximum gain
24 GHz to 42 GHz 5.5 8 dB
42 GHz to 44 GHz 6 8.5 dB
Input IP3 At maximum gain
24 GHz to 42 GHz 0 dBm
42 GHz to 44 GHz 0.5 dBm
ADMV1014 Data Sheet
Parameter Test Conditions/Comments Min Typ Max Unit
Input P1dB At maximum gain
24 GHz to 42 GHz −14 −9 dBm
42 GHz to 44 GHz −15 −10 dBm
Amplitude Balance −0.5 dB
Phase Balance 800 MHz < IF frequency (fIF) < 2 GHz 0.5 Degrees
2 GHz < fIF < 4 GHz 1 Degrees
4 GHz < fIF < 6 GHz 2.5 Degrees
Image Rejection
Uncalibrated 30 dBc
Calibrated 35 dBc
RECEIVER (Rx) POWER DETECTOR PERFORMANCE
Input Level ±1 dB dynamic range
Minimum −35 dBm
Maximum −14 dBm
±1 dB Dynamic Range 20 dB
Output Voltage
Maximum DC Output 3.3 V
RETURN LOSS
RF Input 50 Ω single-ended −13 dB
LO Input 100 Ω differential −10 dB
IF Output 50 Ω single-ended −12 dB
BB Output 100 Ω differential −15 dB
BB I/Q Output Impedance 100 Ω
LEAKAGE At maximum gain
Fundamental LO to RF −70 dBm
4 × LO to RF −70 dBm
Fundamental LO to IF −60 dBm
Fundamental LO to I/Q −60 dBm
LOGIC INPUTS
Input Voltage Range
High, VINH DVDD − 0.4 1.8 V
Low, VINL 0 0.4 V
Input Current, IINH/IINL 100 μA
Input Capacitance, CIN 3 pF
LOGIC OUTPUTS
Output Voltage Range
High, VOH DVDD − 0.4 1.8 V
Low, VOL 0 0.4 V
Output High Current, IOH 500 μA
POWER INTERFACE
VCC_IF_BB, VCC_VGA, VCC_LNA_3P3, VCC_MIXER, 3.15 3.3 3.45 V
VCC_BG, VCC_QUAD
3.3 V Supply Current 437 mA
DVDD, VCC_VVA 1.7 1.8 1.9 V
1.8 V Supply Current 4.2 mA
VCC_LNA_1P5 1.43 1.5 1.57 V
1.5 V Supply Current 33 mA
Total Power Consumption 1.5 W
Power-Down 96 125 mW
Data Sheet ADMV1014
SERIAL PORT REGISTER TIMING
Table 2.
Parameter 䡟escription Min Typ Max Unit
tSDI, SETUP Data to clock setup time 10 ns
tSDI, HOLD Data to clock hold time 10 ns
tSCLK, HIGH Clock high duration 40 to 60 %
tSCLK, LOW Clock low duration 40 to 60 %
tSCLK, SEN_SETUP Clock to SEN setup time 30 ns
tSCLK, DOT Clock to data out transition time 10 ns
tSCLK, DOV Clock to data out valid time 10 ns
tSCLK, SEN_INACTIVE Clock to SEN inactive 20 ns
tSEN_INACTIVE Inactive SEN (between two operations) 80 ns
Timing Diagram
tSCLK, HIGH
tSCLK, LOW
SCLK
tSCLK, SEN_SETU P tSEN_INACTIVE

SEN
tSCLK, DOT tSCLK, SEN_INACTIVE
tSCLK, DOV
SDO
tSDI, HOLD
17172-106
tSDI, SETUP
SDI
Figure 2. Serial Port Register Timing Diagram
ADMV1014 Data Sheet
ABSOLUTE MAXIMUM RATINGS

TJ = (P × ѰJT) + TTOP (1)
Table 3.
Parameter Rating
where:
TTOP is package top temperature (°C). TTOP is measured at the
Supply Voltage
top center of the package.
VCC_IF_BB, VCC_VGA, VCC_LNA_3P3, 4.3 V
VCC_MIXER, VCC_BG, VCC_QUAD, DVDD ѰJT is the junction to top thermal characterization number.
VCC_VVA, VCC_LNA_1P5 2.3 V P is the total power dissipation in the chip (W).
RF Input Power 0 dBm TJ = (P × ѰJB) + TBOARD (2)
LO Input Power 9 dBm
where:
Maximum Junction Temperature 125°C
TBOARD is the board temperature measured on the midpoint of
Maximum Power Dissipation1 2.17 W
the longest side of the package no more than 1 mm from the
Lifetime at Maximum Junction Temperature (TJ) 1 ×106 hours
edge of the package body (°C).
Operating Case Temperature Range −40°C to +85°C
ѰJB is the junction to board thermal characterization number.
Storage Temperature Range −55°C to +125°C
P is the total power dissipation in the chip (W).
Lead Temperature (Soldering 60 sec) 260°C
Moisture Sensitivity Level (MSL) Rating2 MSL3 As stated in JEDEC51-12, only use Equation 1 and Equation 2
Electrostatic Discharge (ESD) Sensitivity when no heat sink or heat spreader is present. When a heat sink
Human Body Model (HBM) 3000 V or heat spreader is added, use θJC_TOP to estimate or calculate the
Field Induced Charged Device Model 750 V junction temperature.
(FICDM)
Table 4. Thermal Resistance
1
The maximum power dissipation is a theoretical number calculated by Package
(TJ − 85°C)/θJC_TOP. Type1 θJA2 θJC_TOP3 θJB4 ΨJT5 ΨJB6 Unit
2
Based on IPC/JEDEC J-STD-20 MSL classifications.
CC-32-6 33.6 18.4 13.3 4.9 12.6 °C/W
Stresses at or above those listed under Absolute Maximum
1
Ratings may cause permanent damage to the product. This is a The thermal resistance values specified in Table 4 are simulated based on
JEDEC specifications, unless specified otherwise, and must be used in
stress rating only; functional operation of the product at these compliance with JESD51-12.
2
or any other conditions above those indicated in the operational θJA is the junction to ambient thermal resistance in a natural convection,
JEDEC environment.
section of this specification is not implied. Operation beyond 3
θJC_TOP is the junction to case (top) JEDEC thermal resistance.
4
the maximum operating conditions for extended periods may θJB is the junction to board JEDEC thermal resistance.
5
ΨJT is the junction to top JEDEC thermal characterization parameter.
affect product reliability. 6
ΨJB is the junction to board JEDEC thermal characterization parameter
THERMAL RESISTANCE ESD CAUTION
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Only use θJA and θJC to compare the thermal performance of
different packages when all test conditions listed are similar to
JEDEC specifications. Otherwise, use ѰJT and ѰJB to calculate
the device junction temperature using the following equations:
Data Sheet ADMV1014
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

ADMV1014
TOP VIEW
(Not to Scale)
VCC_MIXER
DVDD
SCLK
LO_N
LO_P
GND
GND
SDI
32 31 30 29 28 27 26 25
SEN 1 24 VCC_QUAD
I_P 2 23 BG_RBIAS
I_N 3 22 RST
IF_I 4 21 VCC_BG
GND 5 20 VCC_LNA_1P5
IF_Q 6 19 GND
Q_N 7 18 RF_IN
Q_P 8 17 GND
9 10 11 12 13 14 15 16
GND
SDO
VDET
VCTRL
VCC_VGA
VCC_IF_BB
VCC_VVA
VCC_LNA_3P3
17172-002
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED PAD
TO A LOW IMPEDANCE GROUND PLANE.
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions

Pin No. Mnemonic Description
1 SEN SPI Serial Enable. SEN is a high impedance pin with a logic of 1.8 V.
2, 3 I_P, I_N Negative (I_N) and Positive (I_P) Differential BB I Outputs. These pins are dc-coupled.
4, 6 IF_I, IF_Q IF I and IF Q Single-Ended Complex Quadrature Outputs. These pins are dc-coupled to GND, and
each pin is matched to 50 Ω.
5, 13, 17, 19, 25, 28 GND Ground.
7, 8 Q_N, Q_P Positive (Q_P) and Negative (Q_N) Differential Baseband Q Outputs. These pins are dc-coupled.
9 SDO SPI Serial Data Output.

10 VCC_IF_BB 3.3 V Power Supply for BB and IF Section. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this
pin.
11 VDET Square Law Detector Output Voltage.
12 VCC_VGA 3.3 V Power Supply for RF Amplifier. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
14 VCTRL RF VVA Control Voltage. The voltage on this pin ranges from 1.8 V (minimum gain) to 0 V (maximum
gain). Refer to the ADMV1014-EVALZ user guide for the external component requirements.
15 VCC_VVA 1.8 V Power Supply for VVA Control Circuit. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to
this pin.
16 VCC_LNA_3P3 3.3 V Power Supply for LNA. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
18 RF_IN RF Input. This pin is dc-coupled internally with a choke to GND, and matched to 50 Ω, single-
ended. A dc input above 0 V requires external ac coupling.
20 VCC_LNA_1P5 1.5 V Power Supply for Low Noise Amplifier (LNA). Place a 100 pF, 0.01 μF, and a 10 μF capacitor
close to this pin.
21 VCC_BG 3.3 V Power Supply for Band Gap Circuit. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this
pin.
22 RST SPI Reset. Connect this pin to logic high for normal operation.
23 BG_RBIAS Bang Gap Circuit External High Precision Resistor. Place a 1.1 kΩ, high precision resistor shunt to
ground close to this pin.
24 VCC_QUAD 3.3 V Power Supply for Quadruple. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
ADMV1014 Data Sheet
Pin No. Mnemonic Description
26, 27 LO_N, LO_P Negative (LO_N) and Positive (LO_P) Differential Local Oscillator Input. These pins are dc-coupled
internally with a choke to GND and matched to 100 Ω differential or 50 Ω single-ended. A dc input
above 0 V requires external ac coupling. When using the LO input as single-ended, terminate the
unused LO port with a 50 Ω impedance to ground.
29 VCC_MIXER 3.3 V Power Supply for the Mixer. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
30 DVDD 1.8 V SPI Digital Supply. Place a 100 pF, 0.01 μF, and a 10 μF capacitor close to this pin.
31 SCLK SPI Clock Digital Input. SCLK is a high impedance pin.
32 SDI SPI Serial Data Input. SDI is a high impedance pin.
EPAD Exposed Pad. Solder the exposed pad to a low impedance ground plane.
Data Sheet ADMV1014
TYPICAL PERFORMANCE CHARACTERISTICS

I/Q MODE
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, and TA = 25°C, unless otherwise noted. Register 0x0B is set to 0x727C,
Register 0x03, Bits[13:12] are set to 11, VCM = 1.15 V, Register 0x03, Bit 11 = 1, Register 0x03, Bit 8 = 0, and measurements are a composite
of the I and Q channels. VATT is the attenuation voltage at the VCTRL pin. VATT = 0 V, unless otherwise specified.
25
25
20 +85°C AT 39GHz
+25°C AT 39GHz
15 20 –40°C AT 39GHz
+85°C AT 28GHz
+25°C AT 28GHz
CONVERSION GAIN (dB)
10

–40°C AT 28GHz
5 15
0
10
–5
+85°C AT 1.8V
–10 +25°C AT 1.8V
–40°C AT 1.8V 5
–15 +85°C AT 0.8V
+25°C AT 0.8V
–20 –40°C AT 0.8V
+85°C AT 0V 0
–25 +25°C AT 0V
–40°C AT 0V
–30
17172-003
–5
17172-006
23 25 27 29 31 33 35 37 39 41 43 45
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
RF FREQUENCY (GHz)
VATT (V)
Figure 4. Conversion Gain vs. RF Frequency at Three Different Gain Settings Figure 7. Conversion Gain vs. VATT for Various RF Frequencies (fRF),
for Various Temperatures, fBB = 100 MHz (Upper Sideband) fBB = 100 MHz at fRF = 28 GHz and 39 GHz
25 25
20
20
15
15
10
5
10
3.5V UPPER SIDEBAND
3.3V UPPER SIDEBAND 39GHz UPPER SIDEBAND
0 28GHz UPPER SIDEBAND
3.1V UPPER SIDEBAND
5
–5
–10 0
17172-004
17172-007
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz) BASEBAND FREQUENCY (GHz)
Figure 5. Conversion Gain vs. RF Frequency for Various Supply Voltages, Figure 8. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and
fBB = 100 MHz 39 GHz (Upper Sideband)
25 25
20
20
15
15
10
5
10
0 39GHz LOWER SIDEBAND

+6dBm UPPER SIDEBAND 28GHz LOWER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND 5
–5
–10 0
17172-005
17172-008
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 6. Conversion Gain vs. RF Frequency for Various LO Inputs, fBB = 100 MHz Figure 9. Conversion Gain vs. Baseband Frequency at fRF = 28 GHz and
39 GHz (Lower Sideband)
ADMV1014 Data Sheet
10 10.0
8 +85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND 39GHz UPPER SIDEBAND
–40°C UPPER SIDEBAND 7.5 28GHz UPPER SIDEBAND
6
4
5.0
INPUT IP3 (dBm)
INPUT IP3 (dBm)

2
0 2.5
–2
0
–4
–6
–2.5
–8
–10 –5.0
17172-009
17172-012
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
RF FREQUENCY (GHz) VATT (V)
Figure 10. Input IP3 vs. RF Frequency at Maximum Gain for Various Figure 13. Input IP3 vs. VATT for Various RF Frequencies (fRF),
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper
fBB = 100 MHz (Upper Sideband) Sideband) at fRF = 28 GHz and 39 GHz
10 10.0
8 3.5V UPPER SIDEBAND 7.5 39GHz UPPER SIDEBAND

3.3V UPPER SIDEBAND
5.0 28GHz LOWER SIDEBAND
4
INPUT IP3 (dBm)
INPUT IP3 (dBm)
2.5
2
0 0
–2
–2.5
–4
–5.0
–6
–7.5
–8
–10 –10.0
17172-010
17172-013
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 11. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply Figure 14. Input IP3 vs. Baseband Frequency at Maximum Gain, RF
Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, Amplitude = −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and
fBB = 100 MHz (Upper Sideband) 39 GHz, Upper Sideband and Lower Sideband
10 5
8 +6dBm UPPER SIDEBAND 4

0dBm UPPER SIDEBAND 39GHz UPPER SIDEBAND
–6dBm UPPER SIDEBAND 28GHz UPPER SIDEBAND
6 3
4 2
INPUT IP3 (dBm)
INPUT IP3 (dBm)
2 1
0 0
–2 –1
–4 –2
–6 –3
–8 –4
–10 –5
17172-014
17172-011
23 25 27 29 31 33 35 37 39 41 43 45 –30 –29 –28 –27 –26 –25 –24 –23 –22 –21 –20
RF FREQUENCY (GHz) INPUT POWER (dBm)
Figure 12. Input IP3 vs. RF Frequency at Maximum Gain for Various LO Figure 15. Input IP3 vs. Input Power for Various RF Frequencies (fRF) at 20 MHz
Inputs, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz
(Upper Sideband)
Data Sheet ADMV1014
12 25
+85°C AT 39GHz
+85°C UPPER SIDEBAND +25°C AT 39GHz
+25°C UPPER SIDEBAND –40°C AT 39GHz
10 –40°C UPPER SIDEBAND 20 +85°C AT 28GHz
+25°C AT 28GHz
–40°C AT 28GHz
NOISE FIGURE (dB)

NOISE FIGURE (dB)
8
15
10
4
5
2
0 0
17172-015
17172-018
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 16. Noise Figure vs. RF Frequency at Maximum Gain for Various Figure 19. Noise Figure vs. VATT for Various RF Frequencies and Temperatures,
Temperatures, fBB = 100 MHz fBB = 100 MHz at fRF = 28 GHz and 39 GHz
12 9
3.5V UPPER SIDEBAND 8

3.3V UPPER SIDEBAND
10 3.1V UPPER SIDEBAND
7
NOISE FIGURE (dB)
NOISE FIGURE (dB)

8 6
5
6
4
4 3 39GHz UPPER SIDEBAND

28GHz UPPER SIDEBAND
2
2
1
0 0
17172-016
17172-019
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 17. Noise Figure vs. RF Frequency for Various Supply Voltages, Figure 20. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
fBB = 100 MHz (Upper Sideband)
12 9
+6dBm UPPER SIDEBAND 8

0dBm UPPER SIDEBAND
10 –6dBm UPPER SIDEBAND
7
NOISE FIGURE (dB)
NOISE FIGURE (dB)
8 6
5
6
4
4 3 39GHz LOWER SIDEBAND

28GHz LOWER SIDEBAND
2
2
1
0 0
17172-017
17172-020
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 18. Noise Figure vs. RF Frequency for Various LO Inputs, fBB = 100 MHz Figure 21. Noise Figure vs. Baseband Frequency at fRF = 28 GHz and 39 GHz
(Lower Sideband)
ADMV1014 Data Sheet
80 80
+85°C UPPER SIDEBAND

70 +25°C UPPER SIDEBAND 70
–40°C UPPER SIDEBAND
60 60
IMAGE REJECTION (dBc)

50 50
40 40
30 30
+6dBm UPPER SIDEBAND

20 20 0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND
10 10
0 0
17172-021
17172-024
23 25 27 29 31 33 35 37 39 41 43 45 23 25 27 29 31 33 35 37 39 41 43 45
RF INPUT FREQUENCY (GHz) RF INPUT FREQUENCY (GHz)
Figure 22. Image Rejection vs. RF Input Frequency at Maximum Gain for Figure 25. Image Rejection vs. RF Input Frequency for Various LO Inputs,
Various Temperatures, fBB = 100 MHz, Uncalibrated fBB = 100 MHz
80 80

70 +25°C UPPER SIDEBAND 70 39GHz UPPER SIDEBAND
–40°C UPPER SIDEBAND 28GHz UPPER SIDEBAND
60 60
50 50
40 40
30 30
20 20
10 10
0 0
17172-022
17172-025
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
RF INPUT FREQUENCY (GHz) VATT (V)
Figure 23. Image Rejection vs. RF Input Frequency at Maximum Gain for Figure 26. Image Rejection vs. VATT for Various RF Frequencies (fRF),
Various Temperatures, fBB = 100 MHz, Calibrated fBB = 100 MHz at fRF = 28 GHz and 39 GHz
80 80

60

50 50
40 40
30 30
3.5V UPPER SIDEBAND
20 3.3V UPPER SIDEBAND 20
3.1V UPPER SIDEBAND
10 10
0 0
17172-023
17172-026
23 25 27 29 31 33 35 37 39 41 43 45 0 1 2 3 4 5 6 7
RF INPUT FREQUENCY (GHz) BASEBAND FREQUENCY (GHz)
Figure 24. Image Rejection vs. RF Input Frequency for Various Supply Figure 27. Image Rejection vs. Baseband Frequency at fRF = 28 GHz and
Voltages, fBB = 100 MHz 39 GHz (Upper Sideband and Lower Sideband)
Data Sheet ADMV1014
60 60
50 50
40 40
INPUT IP2 (dBm)
INPUT IP2 (dBm)

30 30

20 +25°C UPPER SIDEBAND 20 39GHz UPPER SIDEBAND
–40°C UPPER SIDEBAND 28GHz UPPER SIDEBAND
10 10
0 0
17172-027
17172-030
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 28. Input IP2 vs. RF Frequency at Maximum Gain for Various Figure 31. Input IP2 vs. VATT for Various RF Frequencies (fRF), RF Amplitude = −30
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, dBm per Tone at 20 MHz Spacing, fBB = 100 MHz (Upper Sideband) at
fBB = 100 MHz (Upper Sideband) fRF = 28 GHz and 39 GHz
60 55
50
50 45
40
40
INPUT IP2 (dBm)
INPUT IP2 (dBm) 35
30
30
25
20
20 3.5V UPPER SIDEBAND
3.1V UPPER SIDEBAND 15 28GHz UPPER SIDEBAND
10 10
0 0
17172-028
17172-031
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 29. Input IP2 vs. RF Frequency (fRF) at Maximum Gain for Various Figure 32. Input IP2 vs. Baseband Frequency at Maximum Gain, RF
Supply Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, Amplitude = −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and
fBB = 100 MHz (Upper Sideband) 39 GHz, Upper Sideband
60 55
50
50 45
40
40
INPUT IP2 (dBm)
INPUT IP2 (dBm)
35
30
30
25
20
+6dBm UPPER SIDEBAND 15 28GHz LOWER SIDEBAND
0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND 10
10
5
0 0
17172-029
17172-032
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 30. Input IP2 vs. RF Frequency at Maximum Gain for Various LO Figure 33. Input IP2 vs. Baseband Frequency for Various RF Frequencies (fRF)
Inputs, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fBB = 100 MHz at 20 MHz Spacing, fBB = 100 MHz, fRF = 28 GHz and 39 GHz
(Upper Sideband)
ADMV1014 Data Sheet
0 0
–2 +85°C UPPER SIDEBAND

+25°C UPPER SIDEBAND –2
–4 –40°C UPPER SIDEBAND
–6 –4
INPUT P1dB (dBm)

INPUT P1dB (dBm)
–8
–6
–10
–8
–12
+85°C AT 39GHz
–14 –10 +25°C AT 39GHz
–40°C AT 39GHz
–16 +85°C AT 28GHz
+25°C AT 28GHz
–12 –40°C AT 28GHz
–18
–20 –14
17172-033
17172-036
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 34. Input P1dB vs. RF Frequency at Maximum Gain for Various Figure 37. Input P1dB vs. VATT for Various RF Frequencies (fRF),
Temperatures, fBB = 100 MHz fBB = 100 MHz at fRF = 28 GHz and 39 GHz
0 0
–2 3.5V UPPER SIDEBAND –2

3.3V UPPER SIDEBAND
–4 3.1V UPPER SIDEBAND –4
–6 INPUT P1dB (dBm) –6

INPUT P1dB (dBm)
–8 –8
–10 –10
–12 –12
–14 –14 39GHz UPPER SIDEBAND

–16 –16
–18 –18
–20 –20
17172-034
17172-037
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 35. Input P1dB vs. RF Frequency for Various Supply Voltages, Figure 38. Input P1dB vs. Baseband Output Frequency at
fBB = 100 MHz fRF = 28 GHz and 39 GHz (Upper Sideband)
0 0
–2 +6dBm UPPER SIDEBAND –2

0dBm UPPER SIDEBAND
–4 –6dBm UPPER SIDEBAND –4
–6 –6
INPUT P1dB (dBm)
INPUT P1dB (dBm)
–8 –8
–10 –10
–12 –12
–14 –14 39GHz LOWER SIDEBAND

–16 –16
–18 –18
–20 –20
17172-035
17172-038
23 25 27 29 31 33 35 37 39 41 43 45 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 36. Input P1dB vs. RF Frequency for Various LO Inputs, fBB = 100 MHz Figure 39. Input P1dB vs. Baseband Output Frequency at
fRF = 28 GHz and 39 GHz (Lower Sideband)
Data Sheet ADMV1014
1.0 1.0
0.8 0.8
0.6 0.6
MAGNITUDE ERROR (dB)
MAGNITUDE ERROR (dB)

0.4 0.4
0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 –0.6
BB I_N +85°C BB Q_N +85°C BB Q_P +85°C BB I_N +85°C BB Q_N +85°C BB Q_P +85°C
–0.8 BB I_N +25°C BB Q_N +25°C BB Q_P +25°C –0.8 BB I_N +25°C BB Q_N +25°C BB Q_P +25°C
BB I_N –40°C BB Q_N –40°C BB Q_P –40°C BB I_N –40°C BB Q_N –40°C BB Q_P –40°C
–1.0 –1.0
17172-045
17172-047
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
BASEBAND OUTPUT FREQUENCY (GHz) BASEBAND OUTPUT FREQUENCY (GHz)
Figure 40. Magnitude Error vs. Baseband Output Frequency, Referenced to Figure 42. Magnitude Error vs. Baseband Output Frequency, Referenced to
I_P Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain I_P Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
8 8
6 6
4 4
PHASE ERROR (Degrees)
PHASE ERROR (Degrees)

2 2
0 0
–2 –2
–4 –4
BB I_N +85°C BB Q_N +85°C BB Q_P +85°C
–6 BB I_N +25°C BB Q_N +25°C BB Q_P +25°C –6 BB I_N +85°C BB Q_N +85°C BB Q_P +85°C
BB I_N –40°C BB Q_N –40°C BB Q_P –40°C BB I_N +25°C BB Q_N +25°C BB Q_P +25°C
BB I_N –40°C BB Q_N –40°C BB Q_P –40°C
–8 –8
17172-046
17172-048
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
BASEBAND OUTPUT FREQUENCY (GHz) BASEBAND OUTPUT FREQUENCY (GHz)
Figure 41. Phase Error vs. Baseband Output Frequency, Referenced to I_P Figure 43. Phase Error vs. Baseband Output Frequency, Referenced to I_P
Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
ADMV1014 Data Sheet
25 12
10
20
NOISE FIGURE (dB)

8
15
10
0 4 0
1 1
2 2
5 3 3
2
0 0
17172-042
17172-044
23 25 27 29 31 33 35 37 39 41 43 45 23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUENCY (GHz) RF FREQUENCY (GHz)
Figure 44. Conversion Gain vs. RF Frequency at Four Different Figure 46. Noise Figure vs. RF Frequency Four Different BB_AMP_GAIN_CTRL
BB_AMP_GAIN_CTRL (Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz (Register 0x0A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband)
(Upper Sideband)
2
INPUT IP3 (dBm)
–1
–2 0
1
2
–3 3
–4
–5
17172-043
23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUENCY (GHz)
Figure 45. Input IP3 vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL

(Register A, Bits[2:1]) Settings, fBB = 100 MHz (Upper Sideband)
Data Sheet ADMV1014
IF MODE
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, TA = 25°C unless otherwise specified. Register 0x0B set to 0x727C,
Register 0x03, Bits[12:13] set to 11, measurements performed with a 90° hybrid, Register 0x03, Bit 11 = 0, and Register 0x03, Bit 8 = 1.
25 25


10
5
15
0
–5
10
–10

–20 –40°C UPPER SIDEBAND 5
+85°C LOWER SIDEBAND
–25 –40°C LOWER SIDEBAND
–30 0
17172-049
17172-052
23 25 27 29 31 33 35 37 39 41 43 45 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz) IF FREQUENCY
Figure 47. Conversion Gain vs. RF Frequency at Maximum Gain for Various Figure 50. Conversion Gain vs. IF Frequency (fIF) at Maximum Gain,
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
25 25
+85°C AT 28GHz
20 +25°C AT 28GHz
20
–40°C AT 28GHz
15 +85°C AT 39GHz
15 +25°C AT 39GHz
10 –40°C AT 39GHz
5 10
0
5
–5
–10 0
–15 3.5V UPPER SIDEBAND

3.3V UPPER SIDEBAND –5
3.5V LOWER SIDEBAND
3.3V LOWER SIDEBAND –10
–25 3.1V LOWER SIDEBAND
–30 –15
17172-050
17172-053
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 48. Conversion Gain vs. RF Frequency at Maximum Gain for Various Figure 51. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz,
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) fRF = 28 GHz and 39 GHz (Upper Sideband)
25 25
20 +85°C AT 28GHz
20 +25°C AT 28GHz
15 –40°C AT 28GHz
+85°C AT 39GHz
15 +25°C AT 39GHz
10
–40°C AT 39GHz
5
10
0
5
–5
–10 0
–15 +6dBm UPPER SIDEBAND

0dBm UPPER SIDEBAND –5
–20 –6dBm UPPER SIDEBAND
+6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND –10
–25 –6dBm LOWER SIDEBAND
–30 –15
17172-051
17172-054
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

Figure 49. Conversion Gain vs. RF Frequency at Maximum Gain for Various
LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) Figure 52. Conversion Gain vs. VATT at Various Temperatures, fIF = 3.5 GHz ,
fRF = 28 GHz and 39 GHz (Lower Sideband)
ADMV1014 Data Sheet
12 10
10 +25°C UPPER SIDEBAND
–40°C UPPER SIDEBAND 8
8 +85°C LOWER SIDEBAND
6 –40°C LOWER SIDEBAND 6
4
INPUT IP3 (dBm)
INPUT IP3 (dBm)

4
2
0 2
–2 39GHz UPPER SIDEBAND
–4 39GHz LOWER SIDEBAND
–6 –2
–8
–4
–10
–12 –6
17172-055
17172-058
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 53. Input IP3 vs. RF Frequency at Maximum Gain for Various Figure 56. Input IP3 vs. VATT for Various RF Frequencies (fRF), RF Amplitude =
Temperatures, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz at fRF = 28 GHz and
fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 39 GHz (Upper Sideband and Lower Sideband)
12 10
6
4
4
INPUT IP3 (dBm)
INPUT IP3 (dBm)
2 2
0 0
–2 –2
–4
3.3V LOWER SIDEBAND –8
–12 –10
17172-056
17172-059
23 25 27 29 31 33 35 37 39 41 43 45 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
RF FREQUENCY (GHz) IF FREQUENCY (GHz)
Figure 54. Input IP3 vs. RF Frequency at Maximum Gain for Various Supply Figure 57. Input IP3 vs. IF Frequency at Maximum Gain, RF Amplitude =
Voltages, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz −30 dBm per Tone at 20 MHz Spacing at fRF = 28 GHz and 39 GHz
(Upper Sideband and Lower Sideband) (Upper Sideband and Lower Sideband)
12 5

6
2
4
INPUT IP3 (dBm)
INPUT IP3 (dBm)
1
2
0 0
–2 –1
–4
–2
–6 0dBm UPPER SIDEBAND
–6dBm UPPER SIDEBAND –3
–8 +6dBm LOWER SIDEBAND
0dBm LOWER SIDEBAND –4
–10 –6dBm LOWER SIDEBAND
–12 –5
17172-060
17172-057
23 25 27 29 31 33 35 37 39 41 43 45 –30 –29 –28 –27 –26 –25 –24 –23 –22 –21 –20
RF FREQUENCY (GHz) INPUT POWER (dBm)
Figure 55. Input IP3 vs. RF Frequency at Maximum gain for Various LO Inputs, Figure 58. Input IP3 vs. Input Power for Various RF Frequencies (fRF), at
RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz 20 MHz Spacing, fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz
(Upper Sideband and Lower Sideband) (Upper Sideband and Lower Sideband)
Data Sheet ADMV1014
12 9
+25°C UPPER SIDEBAND 8
10 +85°C LOWER SIDEBAND
+25°C LOWER SIDEBAND 7
–40°C LOWER SIDEBAND
NOISE FIGURE (dB)

NOISE FIGURE (dB)
8 6
5
6
4
4 3 39GHz LOWER SIDEBAND
2
2
1
0 0
17172-061
17172-064
23 25 27 29 31 33 35 37 39 41 43 45 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 59. Noise Figure vs. RF Frequency at Maximum Gain for Various Figure 62. Noise Figure vs. IF Frequency at Maximum Gain, fRF = 28 GHz and
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) 39 GHz (Upper Sideband and Lower Sideband)
12 22
+85°C AT 28GHz
20 +25°C AT 28GHz
10 –40°C AT 28GHz
18 +85°C AT 39GHz
+25°C AT 39GHz
16 –40°C AT 39GHz
NOISE FIGURE (dB)

NOISE FIGURE (dB)
8
14
12
6
10
8
4
3.3V UPPER SIDEBAND
2 3.5V LOWER SIDEBAND
3.3V LOWER SIDEBAND
3.1V LOWER SIDEBAND 2
0 0
17172-062
17172-065
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 60. Noise Figure vs. RF Frequency at Maximum Gain for Various Figure 63. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz,
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) fRF = 28 GHz and 39 GHz (Upper Sideband)
22
12 +85°C AT 28GHz
20 +25°C AT 28GHz
–40°C AT 28GHz
18 +85°C AT 39GHz
10 +25°C AT 39GHz
16 –40°C AT 39GHz
NOISE FIGURE (dB)
14
NOISE FIGURE (dB)
8
12
10
6
8
4 6
0dBm UPPER SIDEBAND 4
–6dBm UPPER SIDEBAND
2 +6dBm LOWER SIDEBAND 2
0dBm LOWER SIDEBAND
–6dBm LOWER SIDEBAND 0
17172-066
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

0
17172-063
23 25 27 29 31 33 35 37 39 41 43 45 VATT (V)
RF FREQUENCY (GHz)
Figure 64. Noise Figure vs. VATT at Various Temperatures, fIF = 3.5 GHz,
Figure 61. Noise Figure vs. RF Frequency at Maximum Gain for Various LO fRF = 28 GHz and 39 GHz (Lower Sideband)
Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
ADMV1014 Data Sheet
0 1
–40°C UPPER SIDEBAND –1 39GHz UPPER SIDEBAND
+85°C LOWER SIDEBAND 28GHz UPPER SIDEBAND
–4 +25°C LOWER SIDEBAND 39GHz LOWER SIDEBAND
–40°C LOWER SIDEBAND –3 28GHz LOWER SIDEBAND
–6
INPUT P1dB (dBm)

INPUT P1dB (dBm)
–5
–8
–10 –7
–12
–9
–14
–11
–16
–13
–18
–20 –15
17172-067
17172-070
23 25 27 29 31 33 35 37 39 41 43 45 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0
Figure 65. Input P1dB vs. RF Frequency at Maximum Gain for Various Figure 68. Input P1dB vs. IF Frequency at Maximum Gain,
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
0 2
–2 0
–4
–2
–6 INPUT P1dB (dBm)
INPUT P1dB (dBm)
–4
–8
–6
–10
–8
–12
–10
–14 3.5V UPPER SIDEBAND +85°C AT 28GHz
3.3V UPPER SIDEBAND –12 +25°C AT 28GHz
–16 3.1V UPPER SIDEBAND –40°C AT 28GHz
3.5V LOWER SIDEBAND +85°C AT 39GHz
–18 3.3V LOWER SIDEBAND –14 +25°C AT 39GHz
3.1V LOWER SIDEBAND –40°C AT 39GHz
–20 –16
17172-068
17172-071
23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
Figure 66. Input P1dB vs. RF Frequency at Maximum Gain for Various Supply Figure 69. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz,
Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) fRF = 28 GHz and 39 GHz (Upper Sideband)
2
0
0
–2
–2
–4
INPUT P1dB (dBm)
–6 –4
INPUT P1dB (dBm)
–8 –6
–10 –8
–12
–10
+85°C AT 28GHz
–14 +6dBm UPPER SIDEBAND +25°C AT 28GHz
–12
0dBm UPPER SIDEBAND –40°C AT 28GHz
–16 –6dBm UPPER SIDEBAND +85°C AT 39GHz
+6dBm LOWER SIDEBAND –14 +25°C AT 39GHz
–18 0dBm LOWER SIDEBAND –40°C AT 39GHz
–6dBm LOWER SIDEBAND
–16
17172-072
–20 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
17172-069
24 26 28 30 32 34 36 38 40 42 44
VATT (V)
RF FREQUENCY (GHz)
Figure 70. Input P1dB vs. VATT at Various Temperatures, fIF = 3.5 GHz,
Figure 67. Input P1dB vs. RF Frequency at Maximum Gain for Various LO fRF = 28 GHz and 39 GHz (Lower Sideband)
Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
Data Sheet ADMV1014
60 60
+85°C UPPER SIDEBAND +6dBm UPPER SIDEBAND

+25°C UPPER SIDEBAND 50 0dBm UPPER SIDEBAND
50 –40°C UPPER SIDEBAND –6dBm UPPER SIDEBAND
+85°C LOWER SIDEBAND +6dBm LOWER SIDEBAND

+25°C LOWER SIDEBAND 0dBm LOWER SIDEBAND

40 –40°C LOWER SIDEBAND 40 –6dBm LOWER SIDEBAND
30 30
20 20
10 10
0 0
17172-076
17172-073
23 25 27 29 31 33 35 37 39 41 43 45 23 25 27 29 31 33 35 37 39 41 43 45
RF INPUT FREQUENCY (GHz) RF INPUT FREQUENCY (GHz)
Figure 71. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Figure 74. Image Rejection vs. RF Input Frequency at Maximum Gain for
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Uncalibrated Various LO Inputs, fIF = 3.5 GHz (Upper Sideband and Lower Sideband)
60 60

+25°C UPPER SIDEBAND 39GHz UPPER SIDEBAND
+85°C LOWER SIDEBAND 39GHz LOWER SIDEBAND


40 –40°C LOWER SIDEBAND 40
30 30
20 20
10 10
0 0
17172-077
17172-074
23 25 27 29 31 33 35 37 39 41 43 45 0 1 2 3 4 5 6 7
RF INPUT FREQUENCY (GHz) IF INPUT FREQUENCY (GHz)
Figure 72. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Figure 75. Image Rejection vs. IF Input Frequency at Maximum Gain,
Temperatures, fIF = 3.5 GHz (Upper Sideband and Lower Sideband), Calibrated fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
60 60
3.5V UPPER SIDEBAND

50 3.3V UPPER SIDEBAND 39GHz UPPER SIDEBAND
3.1V UPPER SIDEBAND 50 28GHz UPPER SIDEBAND
3.5V LOWER SIDEBAND 39GHz LOWER SIDEBAND
3.3V LOWER SIDEBAND 28GHz LOWER SIDEBAND

40 3.1V LOWER SIDEBAND

40
30 30
20 20
10
10
0
17172-075
0
17172-078
23 25 27 29 31 33 35 37 39 41 43 45
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
RF INPUT FREQUENCY (GHz)
VATT (V)
Figure 73. Image Rejection vs. RF Input Frequency at Maximum Gain for Various Figure 76. Image Rejection vs. VATT at Various RF Frequencies (fRF),
Supply Voltages, fIF = 3.5 GHz (Upper Sideband and Lower Sideband) fIF = 3.5 GHz, fRF = 28 GHz and 39 GHz (Upper Sideband and Lower Sideband)
ADMV1014 Data Sheet
20 20
18 18
16 16

14 14
12 12
10 10
8 8
6 6 0 4 8 12
1 5 9 13
0 2 6 10 14
4 4 3 7 11 15
1
3
2 7 2
15
0 0
17172-079
17172-082
23 25 27 29 31 33 35 37 39 41 43 45 23 25 27 29 31 33 35 37 39 41 43 45
Figure 77. Conversion Gain vs. RF Frequency at Different Figure 80. Conversion Gain vs. RF Frequency at Different IF_AMP_
IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for FINE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Register 0x08, Bits[7:4]
Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same and Bits[3:0] Are the Same
5 5
4 4
3 3
2 2
INPUT IP3 (dBm)
INPUT IP3 (dBm)
1 1
0 0
–1 –1
0 0 4 8 12
–2 1 –2
1 5 9 13
3 2 6 10 14
–3 7 –3 3 7 11 15
15
–4 –4
–5 –5
17172-080
17172-083
23 25 27 29 31 33 35 37 39 41 43 45 23 25 27 29 31 33 35 37 39 41 43 45
Figure 78. Input IP3 vs. RF Frequency at Different IF_AMP_COARSE_GAIN_x Figure 81. Input IP3 vs. RF Frequency at Different IF_AMP_FINE_GAIN_x
Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[11:8] Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4]
and Register 0x09, Bits[15:12] Are the Same and Bits[3:0] Are the Same
10
10
9
9
8
8
7
NOISE FIGURE (dB)
7
NOISE FIGURE (dB)
6
6
5
5
4
4
3
3 0 4 8 12
0 1 5 9 13
2 1 2 6 10 14
3 2 3 7 11 15
1 7
15 1
0
17172-081
23 25 27 29 31 33 35 37 39 41 43 45 0
17172-084
RF FREQUENCY (GHz) 23 25 27 29 31 33 35 37 39 41 43 45
RF FREQUENCY (GHz)
Figure 79. Noise Figure vs. RF Frequency at Different
IF_AMP_COARSE_GAIN_x Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Figure 82. Noise Figure vs. RF Frequency at Different IF_AMP_FINE_GAIN_x
Register 0x08, Bits[11:8] and Register 0x09, Bits[15:12] Are the Same Settings, fIF = 3.5 GHz (Upper Sideband); Settings for Register 0x08, Bits[7:4]
and Bits[3:0] Are the Same
Data Sheet ADMV1014
1.0 1.0
0.8 +85°C 0.8

+25°C +85°C
0.6 –40°C 0.6 +25°C
I/Q MAGNITUDE ERROR (dB)
I/Q MAGNITUDE ERROR (dB)

–40°C
0.4 0.4
0.2 0.2
0 0
–0.2 –0.2
–0.4 –0.4
–0.6 –0.6
–0.8 –0.8
–1.0 –1.0
17172-085
17172-087
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
IF OUTPUT FREQUENCY (GHz) IF OUTPUT FREQUENCY (GHz)
Figure 83. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I Figure 85. I/Q Magnitude Error vs. IF Output Frequency, Referenced to IF_I
Output, fRF = 28 GHz, for Various Temperatures, at Maximum Gain Output, fRF = 39 GHz, for Various Temperatures, at Maximum Gain
5 5
4 4
3 3
I/Q PHASE ERROR (dB)
I/Q PHASE ERROR (dB)

2 2
1 1
0 0
–1 –1
–2 +85°C –2 +85°C
+25°C +25°C
–3 –40°C –3 –40°C
–4 –4
–5 –5
17172-086
17172-088
0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
IF OUTPUT FREQUENCY (GHz) IF OUTPUT FREQUENCY (GHz)
Figure 84. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output, Figure 86. I/Q Phase Error vs. IF Output Frequency, Referenced to IF_I Output,
fRF = 28 GHz, for Various Temperatures, at Maximum Gain fRF = 39 GHz, for Various Temperatures, at Maximum Gain
ADMV1014 Data Sheet
OUTPUT DETECTOR PERFORMANCE
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bit 6 = 0, Register 0x03,
Bits[13:12] set to 11, and TA = 25°C, unless otherwise noted.
3.5 3.0
–22
–27
3.0 –32
2.5
2.5
2.0
VDET (V)
VDET (V)
2.0
1.5
1.5
1.0
1.0
0.5 +85°C = 64 +25°C = 64 –40°C = 64
+85°C = 8 +25°C = 8 –40°C = 8
+85°C = 0 +25°C = 0 –40°C = 0
0 0.5
17172-090
17172-089
–40 –35 –30 –25 –20 –15 –10 23 25 27 29 31 33 35 37 39 41 43 45
RF INPUT POWER (dBm) RF INPUT FREQUENCY (GHz)
Figure 87. VDET vs. RF Input Power, fRF = 28 GHz for Various Temperatures Figure 89. VDET vs. RF Input Frequency at Various Input Power Levels,
and DET_PROG Settings DET_PROG = 8
3.5 5
4
3.0
3
VDET LINEARITY ERROR (dB)
2.5 2
1
VDET (V)
2.0
0
1.5 +85°C = 64 –40°C = 64
–1 +85°C = 8 –40°C = 8
+85°C = 0 –40°C = 0
1.0 –2 +25°C = 64
+25°C = 8
+25°C = 0
–3
0.5 +85°C = 64 +25°C = 64 –40°C = 64
+85°C = 8 +25°C = 8 –40°C = 8 –4
+85°C = 0 +25°C = 0 –40°C = 0
0 –5
17172-091
17172-093
–40 –35 –30 –25 –20 –15 –10 –40 –35 –30 –25 –20 –15 –10
RF INPUT POWER (dBm) RF INPUT POWER (dBm)
Figure 88. VDET vs. RF Input Power, fRF = 39 GHz for Various Temperatures Figure 90. VDET Linearity Error vs. RF Input Power, fRF = 28 GHz for Various
and DET_PROG Settings Temperatures and DET_PROG Settings
3
VDET LINEARITY ERROR (dB)
–1 +85°C = 64 –40°C = 64
+85°C = 8 –40°C = 8
–2 +85°C = 0 –40°C = 0
+25°C = 64
+25°C = 8
–3 +25°C = 0
–4
–5
17172-094
–40 –35 –30 –25 –20 –15 –10

RF INPUT POWER (dBm)
Figure 91. VDET Linearity Error vs. RF Input Power, fRF = 39 GHz for Various
Temperatures and DET_PROG Settings
Data Sheet ADMV1014
RETURN LOSS AND ISOLATIONS
VCC_VGA = VCC_IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set to 0x727C, Register 0x03, Bits[13:12] are set to 11,
and TA = 25°C, unless otherwise noted.
Measurements in IF mode performed with a 90° hybrid, Register 0x03, Bit 11 = 0, Register 0x03, Bit 8 = 1, unless otherwise noted.
Measurements in I/Q mode are measured as a composite of the I and Q channel performed, VCM = 1.15 V, Register 0x03, Bit 11 = 1, and
Register 0x03, Bit 8 = 0, unless otherwise noted.
0 0
I
Q
I/Q DIFFERENTIAL RETURN LOSS (dB)

–5 –5
RF RETURN LOSS (dB)
–10 –10
–15 –15
–20 –20
–25 –25
–30 –30
–35 –35
17172-095
17172-098
23 25 27 29 31 33 35 37 39 41 43 45 0 1 2 3 4 5 6 7
RF FREQUENCY (GHz) I/Q FREQUENCY (GHz)
Figure 92. RF Input Return Loss vs. RF Frequency Figure 95. I/Q Differential Return Loss vs. I/Q Frequency (Taken Without
Hybrids or Baluns)
0 0
–5 –5
LO RETURN LOSS (dB)
–10 –10
IF RETURN LOSS (dB)
–15 –15
–20 –20
LON IF_I
–25 LOP –25 IF_Q
LODIFF
–30 –30
–35 –35
17172-096
17172-099
4 5 6 7 8 9 10 11 12 0 1 2 3 4 5 6 7
LO FREQUENCY (GHz) IF FREQUENCY (GHz)
Figure 93. LO Return Loss vs. LO Frequency Figure 96. IF Return Loss vs. IF Frequency (Taken Without Hybrid)
–50 –50
LOx1 = 1.8
LOx1 = +85°C LOx1 = 0.9
–55 LOx1 = +25°C –55 LOx1 = 0
LOx1 = –40°C LOx4 = 1.8
–60 LOx4 = +85°C –60 LOx4 = 0.9
LO TO RF LEAKAGE (dBm)
LOx4 = +25°C LOx4 = 0

LO TO IF LEAKAGE (dBm)
–65 LOx4 = –40°C –65
–70 –70
–75 –75
–80 –80
–85 –85
–90 –90
–95 –95
–100 –100
17172-097
17172-100
4 5 6 7 8 9 10 11 12 4 5 6 7 8 9 10 11 12
LO INPUT FREQUENCY (GHz) LO INPUT FREQUENCY (GHz)
Figure 94. LO to RF Leakage vs. LO Input Frequency for Various Temperatures Figure 97. LO to IF Leakage vs. LO Input Frequency at Different VCTRL Settings
at Different Gain Settings
ADMV1014 Data Sheet
–30 –30
I = +85°C I =0 Q =0
–35 I = +25°C –35 I =1 Q =1
I = –40°C I =3 Q =3
–40 Q = +85°C –40 I =7 Q =7
Q = +25°C I = 15 Q = 15
–45 Q = –40°C –45
–50 –50
–55 –55
–60 –60
–65 –65
–70 –70
–75 –75
–80 –80
17172-101
17172-103
4 5 6 7 8 9 10 11 12 4 5 6 7 8 9 10 11 12
Figure 98. LO to IF Leakage vs. LO Input Frequency at Various Temperatures Figure 100. LO to IF Leakage, vs. LO Input Frequency at Different IF Amplifier
Gain Settings (Taken Without Hybrid)
–40 –40
FUNDAMENTAL LO TO I/Q LEAKAGE (dBm)

–45 –45
–50 –50
LO TO I/Q LEAKAGE (dBm)
–55 –55
–60 –60
–65 –65
–70 –70
–75 –75
I_P = +85°C Q_P = +85°C I_P = 0 Q_P = 0
–80 I_P = +25°C Q_P = +25°C –80 I_P = 3 Q_P = 3
I_P = –40°C Q_P = –40°C I_N = 0 Q_N = 0
–85 I_N = +85°C Q_N = +85°C –85 I_N = 3 Q_N = 3
I_N = +25°C Q_N = +25°C
I_N = –40°C Q_N = –40°C
–90 –90
17172-104
17172-102
4 6 8 10 12 4 5 6 7 8 9 10 11 12
Figure 99. LO to I/Q Leakage vs. LO Input Frequency at Various Temperatures Figure 101. Fundamental LO to I/Q Leakage vs. LO Input Frequency at
(Taken Without Hybrid) Different Baseband Amplifier Gain Settings
Data Sheet ADMV1014
M × N SPURIOUS PERFORMANCE IF Mode
Mixer spurious products are measured in dBc from the IF Measurements are made on the IF_I port. Data is taken without
output power level. Spurious values are measured using the any 90° hybrid.
following equation:
IF frequency (fIF) = 3.5 GHz, LO= 6.125 GHz at 0 dBm, and
|(M × RF)+ (N × LO)| fRF = 28 GHz at −30 dBm.
N/A means not applicable. Blank cells in the spurious N × LO
performance tables indicate that the frequency is above 50 GHz 0 1 2 3 4 5 6 7 8
and is not measured. −2 81 93 85 93 93 99 96 Ĥ䤁
The LO frequencies are referred from the frequencies applied −1 66 94 89 63 0 44 46 92 78
M × RF
to the LO_x pin of the ADMV1014. RF amplitude = −30 dBm, 0 N/A 45 43 65 54 71 64 80 58
measurements performed with a 0 mV dc bias. VCC_MIXER = +1 66 84 84 81
VCC_QUAD = VCC_BG = VCC_LNA = VCC_VGA = VCC_
fIF = 3.5 GHz, LO= 8.875 GHz at 0 dBm, and fRF = 39 GHz at
IF_BB = 3.3 V, DVDD = VCC_VVA = 1.8 V, Register 0x0B is set
−30 dBm.
to 0x727C, Register 0x03, Bits[13:12] are set to 11, and TA =
25°C, unless otherwise noted. N × LO
Measurements in IF mode performed with Register 0x03, Bit 11 = 0 0 1 2 3 4 5 6 7 8
and Register 0x03, Bit 8 = 1, unless otherwise noted. −2 84 92 91 93 59
−1 62 93 81 71 0 39 91 92 89
The measurements in I/Q mode are as follows: VCM = 1.15 V, M × RF
0 N/A 47 68 75 50 75
Register 0x03, Bit 11 = 1, and Register 0x03, Bit 8 = 0, unless
+1 62 89
otherwise noted.
fIF = 3.5 GHz, LO= 7.875 GHz at 0 dBm, and fRF = 28 GHz at
I/Q Mode
−30 dBm.
Measurements are made on the I_P port. Data is taken without
any hybrids or baluns. N × LO
0 1 2 3 4 5 6 7 8
BB frequency (fBB) =100 MHz, LO= 6.975 GHz at 0 dBm, and
−2 90 86 83 95 94 83 89 58
fRF = 28 GHz at −30 dBm.
−1 70 93 70 41 0 65 90 89 83
N × LO M × RF
0 N/A 47 62 66 49 74 86
0 1 2 3 4 5 6 7 8 +1 70 90 88
−2 85 87 87 82 86 103 96 59
fIF = 3.5 GHz, LO= 10.5 GHz at 0 dBm, and fRF =39 GHz at
−1 61 90 54 46 0 45 52 106 82
M × RF −30 dBm
0 N/A 43 55 65 48 76 78 81
+1 61 91 80 82 N × LO
0 1 2 3 4 5 6 7 8
fBB = 100 MHz, LO= 9.725 GHz at 0 dBm, and fRF = 39 GHz at
−2 85 87 94 94 90 58
−30 dBm.
−1 61 91 81 35 0 87 84 84 82
N × LO M × RF
0 N/A 39 51 62 53
0 1 2 3 4 5 6 7 8 +1 61 89
−2 85 88 87 92 87 60
−1 63 92 56 47 0 51 61 85 84
M × RF
0 N/A 42 48 67 51 85
+1 42 48
ADMV1014 Data Sheet
THEORY OF OPERATION
The ADMV1014 is a wideband microwave downconverter The baseband I/Q ports are designed to operate from dc to
optimized for microwave radio designs operating in the 24 GHz 6.0 GHz at each I and Q channel.
to 44 GHz frequency range. See Figure 1 for a functional block The BB output VCM can be changed from 1.05 V to 1.85 V. To
diagram of the device. The ADMV1014 digital settings are change the VCM, set BB_SWITCH_HIGH_LOW_COMMMON
controlled via the SPI. The ADMV1014 has two modes of (Register 0x0A, Bit 0) to be the opposite of Register 0x0A, Bit 6.
operation: Also, set the MIXER_VGATE bit field (Register 0x07, Bits[15:9])
 Baseband quadrature demodulation (I/Q mode) and the BB_AMP_REF_GEN bit field (Register 0x0A, Bits[6:3])
 Image reject I/Q downconversion (IF mode) based on Table 6.
Table 6 provides the correct setting for these bit fields vs. the
START-UP SEQUENCE
required common-mode voltage.
The ADMV1014 SPI settings require its default settings to be
changed during startup for optimum performance. To use the The VCM can be further adjusted on each I or Q channel by
SPI, toggle the RST pin to logic low and then logic high to ±15 mV by setting the BB_AMP_OFFSET_I bit field
perform a hard reset before starting up the device. (Register 0x09, Bits[4:0]) and the BB_AMP_OFFSET_Q bit field
(Register 0x09, Bits[9:5]) for each VCM setting shown in Table 6.
Set Register 0x0B to 0x727C after every power-up or reset. Set
Register 0x03, Bits[13:12] to 11 after every power-up or reset. The most significant bit (MSB) for each bit field is the sign bit.
When the MSB is 1, the values of the four lower bits are
BASEBAND QUADRATURE DEMODULATION (I/Q positive. When the MSB is 0, the values of the four lower bits
MODE) are negative. These bits also offer input IP2 and common-mode
In I/Q mode, the output impedance of the baseband I/Q ports is rejection optimization.
100 Ω differential. These outputs are designed to be loaded to a The BB I/Q section of the ADMV1014 also features a baseband
dc-coupled, differential, 100 Ω load. I_P and I_N are the amplifier with a digital attenuator that is controlled by setting
differential baseband I outputs. Q_P and Q_N are the the BB_AMP_GAIN_CTRL bit field (Register 0x0A, Bits[2:1]).
differential baseband Q outputs. Figure 44, Figure 45, and Figure 46 show the performance of the
To set the ADMV1014 in I/Q mode, set BB_AMP_PD baseband digital attenuator.
(Register 0x03, Bit 8) to 0 and set IF_AMP_PD (Register 0x03, The Baseband Quadrature Demodulation to Very Low
Bit 11) to 1. Frequencies section shows the baseband performance to very
low demodulation frequencies.
Table 6. Common-Mode Voltage Settings

MIXER_VGATE BB_AMP_REF_GEN BB_SWITCH_HIGH_LOW_COMMON_MODE
VCM (V) (Register 0x07, Bits[15:9]) (Register 0x0A, Bits[6:3]) (Register 0x0A, Bit 0)
1.05 1101010 0000 1
1.10 1101011 0001 1
1.15 1101100 0010 1
1.20 1101110 0011 1
1.25 1101111 0100 1
1.30 1110000 0101 1
1.35 1110001 0110 1
1.40 1110010 0111 1
1.50 1110101 1000 0
1.55 1110110 1001 0
1.60 1110111 1010 0
1.65 1111000 1011 0
1.70 1111010 1100 0
1.75 1111011 1101 0
1.80 0101100 1110 0
1.85 0101101 1111 0
Data Sheet ADMV1014
IMAGE REJECTION DOWNCONVERSION path can switch from differential to single-ended operation by
The ADMV1014 features the ability to downconvert to a real IF setting the QUAD_SE_MODE bits (Register 0x04, Bits[9:6]).
output anywhere from 800 MHz to 6000 MHz, while suppressing See the Performance Between Differential vs. Single-Ended LO
the unwanted image sideband by typically better than 30 dBc. Input section for more information.
The IF outputs are quadrature to each other, 50 Ω single-ended, Figure 102 shows a block diagram of the LO path.
and are internally ac coupled. IF_I and IF_Q are the quadrature IF
outputs. An external 90° hybrid is required to select the appropriate
sideband.
To configure the ADMV1014 in IF mode, set BB_AMP_PD LO_N 4 × LO_N
AMP ×4
(Register 0x03, Bit 8) to 1 and set IF_AMP_PD (Register 0x03, LO_P 4 × LO_P
Bit 11) to 0
Each IF output features an amplifier with a digital attenuator.
17172-105
The digital attenuator can be adjusted using fine or coarse steps.
The coarse steps for the IF_I can be adjusted using the IF_AMP_ Figure 102. LO Path Block Diagram
COARSE_GAIN_I bit field (Register 0x08, Bits[11:8]). The coarse
steps for the IF_Q can be adjusted using the IF_AMP_COARSE_ Enable the quadrupler by setting the QUAD_IBIAS_PD bit
GAIN_Q bit field (Register 0x09, Bits[15:12]). Each course gain (Register 0x03, Bit 7) to 0 and the QUAD_BG_PD bit
bit field has five settings. The fine steps for IF_I can be adjusted (Register 0x03, Bit 9) to 0. To power down the quadrupler, set
using the IF_AMP_FINE_GAIN_I bit field (Register 0x08, both of these bits to 1.
Bits[3:0]). The fine steps for the IF_Q can be adjusted using the An unwanted image can be downconverted from the
IF_AMP_FINE_GAIN_Q bit field (Register 0x08, Bits[7:4]). quadrature error in generating the quadrature LO signals.
Figure 77 to Figure 82 show the performance of these four bit Deviation from ideal quadrature (that is, total image rejection
fields. and no image tone is downconverted) on these signals limits the
amount of achievable image rejection.
DETECTOR
The ADMV1014 offers about 25° of quadrature phase
The ADMV1014 features a square law detector that produces a
adjustment in the LO path quadrature signals. Make these
voltage linearly, according to the square of the RF voltage
adjustments through the LOAMP_PH_ADJ_I_FINE bits
output from the low noise amplifier. The detector can be
(Register 0x05, Bits[15:9]) and the LOAMP_PH_ADJ_Q_FINE
enabled by setting the DET_EN bit (Register 0x03, Bit 6) to 0. The
(Register 0x05, Bits[8:2]) bits. These bits reject the unwanted
detector can be turned off by setting this bit to 1. The detector
sideband signal. In IF mode amplitude adjustments can be made
linear range can be adjusted by setting the DET_PROG bit field
to the complex outputs via IF_AMP_FINE_GAIN_Q
(Register 0x07, Bits[6:0]). These ranges are specified based on
(Register 0x08, Bits[7:4]) and IF_AMP_FINE_GAIN_I
the input power into the detector coming from the output of the
(Register 0x08, Bits[3:0]) to further reduce the unwanted
low noise amplifier. Each DET_PROG setting offers an
sideband.
approximate 20 dB of ±1 dB dynamic range based on a two-
point linear regression from an ideal line for one temperature at POWER-DOWN
each DET_PROG setting. See Figure 89 to Figure 91 for more The SPI of the ADMV1014 allows the user to power down
performance information of the detector. device circuits and reduce power consumption. There are two
LO INPUT PATH power-down modes: band gap power-down mode (BG_PD)
and individual power-down circuits mode. The BG_PD bit
The LO input path operates from 5.4 GHz to 10.25 GHz with an
(Register 0x03, Bit 5) and the QUAD_BG_PD bit (Register 0x03,
LO amplitude range of −6 dBm to +6 dBm. The LO has an
Bit 9) power down the band gap circuit. The QUAD_IBIAS_PD
internal quadrupler (×4) and a programmable band-pass filter.
bit (Register 0x03, Bit 7) and the IBIAS_PD bit (Register 0x03,
The LO band-pass filter is programmable using QUAD_FILTERS
Bit 14) power down the specific circuits.
(Register 0x04 Bits[3:0]). See the Performance at Different
Quad Filter Settings section for more information on the Table 7 shows the circuits that are controlled by their related
QUAD_FILTERS settings. power-down bit, the typical power savings, and the latency
requirement to power the circuits back up.
The LO path can operate either differentially or single-ended
(SE). LOIP and LOIN are the inputs to the LO path. The LO
ADMV1014 Data Sheet
Table 7. Power-Down Power and Latency Requirements
Typical Power Power-Up Power-Down
Bit Name Circuit Savings (mW) Latency (μs) Latency (μs)
IBIAS_PD Receiver bias current (IBIAS) 1172 5 <1
QUAD_IBIAS_PD LO path 238 4 <1
BG_PD and QUAD_BG_PD Band gap 1423 4.5 <1
IBIAS_PD, IF_AMP_PD, QUAD_BG_PD, Entire chip 1435 5 <1
BB_AMP_PD, QUAD_IBIAS_PD, BG_PD
SEN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
17172-107
SDI R/W A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
Figure 103. Write Serial Port Timing Diagram
SEN
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
SDI R/W A5 A4 A3 A2 A1 A0
17172-108
SDO D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 P
Figure 104. Read Serial Port Timing Diagram
Sideband. The ADMV1014 input logic level for the write cycle
SERIAL PORT INTERFACE (SPI) supports an 1.8 V interface.
The SPI of the ADMV1014 allows the user to configure the device
For a read cycle, up to 16 bits of serial read data are shifted out,
for specific functions or operations via a 4-pin SPI port. This
MSB first. After the 16 bits of data shift out, the parity bit shifts
interface provides users with added flexibility and customization.
out. The output logic level for a read cycle is 1.8 V.
The SPI consists of four control lines: SCLK, SDIN, SDO, and
SEN. The parity bit always follows the direction of the data. If parity
is not used, the transmitting end transmits zero instead of parity.
The ADMV1014 protocol consists of a write/read bit followed The parity is odd, which means that the total number of ones
by six register address bits, 16 data bits, and a parity bit. Both transmitted during a command, including the read/write bit,
the address and data fields are organized most significant bit the address bit, the data bit, and the parity bit, must be odd.
(MSB) first and end with the least significant bit. For a write, set
the first bit to 0. For a read, set the first bit to 1. Figure 103 and Figure 104 show the SPI write and read
protocol, respectively.
The write cycle sampling must be performed on the rising edge.
The 16 bits of the serial write data are shifted in, MSB to Lower
Data Sheet ADMV1014
APPLICATIONS INFORMATION
1.8
ERROR VECTOR MAGNITUDE (EVM)
PERFORMANCE 1.6
Figure 105 shows the EVM vs. input power performance of the 1.4
ADMV1014 in IF mode at maximum gain, upper sideband, 1.2

25°C and 0 dBm LO input power. The EVM measurement was
EVM (%)
1.0
performed using four 100 MHz, 5G-NR, 256QAM waveforms.
The EVM shown is the average of the four channels. The EVM 0.8
of the test equipment was not de-embedded. 0.6
Figure 106 shows the constellation diagram and EVM statistics 0.4
of each of the four channels at −30 dBm input power.
0.2
17172-109
–45 –40 –35 –30 –25 –20 –15
PIN (dBm)
Figure 105. EVM vs. Input Power at 28 GHz, VCTRL = 0 V, TA = 25°C,

LO = 0 dBm, Upper Sideband (Low-Side LO), IF = 3.5 GHz
17172-110
Figure 106. Constellation Diagram and EVM Statistics per Channel
ADMV1014 Data Sheet
50
BASEBAND QUADRATURE DEMODULATION TO
VERY LOW FREQUENCIES 45
40
Figure 107 to Figure 111 show the I/Q mode performance at

low baseband frequencies. The measurements were performed 35
at 28 GHz, −25 dBm input power, VCM = 1.15 V, Register 0x03, 30

Bit 11 = 1, Register 0x03, Bit 8 = 0, 6 dBm LO input power, and 25
TA = 25°C. 20
350
I AND Q DIFFERENTIAL PEAK-TO-PEAK VOLTAGE
15
300 10 IMAGE REJECT
5
250
0
17172-114
1 10 100 1k 10k 100k 1M 10M 100M
200 BASEBAND FREQUENCY (Hz)
Q DIFFERENTIAL Figure 110. Image Rejection vs. Baseband Frequency

150 I DIFFERENTIAL
350
100
300
50
DC OFFSET ERROR (mV)

250
0
17172-111
1 10 100 1k 10k 100k 1M 10M 100M 200

BASEBAND FREQUENCY (Hz)
Q DIFFERENTIAL
Figure 107. I and Q Differential Peak-to-Peak Voltage vs. Baseband Frequency 150 I DIFFERENTIAL
20
100
18
16 50
14
0
17172-111
12 1 10 100 1k 10k 100k 1M 10M 100M
10
Figure 111. DC Offset Error vs. Baseband Frequency
8 Q GAIN
I GAIN PERFORMANCE AT DIFFERENT QUAD FILTER
7
SETTINGS
6
Figure 112 shows the conversion gain vs. RF frequency in IF
5
mode at 25°C and LO input power = 6 dBm, for different
0
QUAD_FILTERS settings. Figure 113 shows the LO to IF_I and
17172-112
1 10 100 1k 10k 100k 1M 10M 100M

BASEBAND FREQUENCY (Hz) LO to IF_Q leakage vs. LO frequency at different quad filter
Figure 108. Conversion Gain vs. Baseband Frequency settings.
5 25
20
AMPLITUDE IMBALANCE 15
4 PHASE IMBALANCE
AMPLITUDE IMBALANCE (dB)/
PHASE IMBALANCE (Degrees)
10
5
3
0
–5
2 –10
QUAD_FILTERS = 0
–15 QUAD_FILTERS = 5
QUAD_FILTERS = 10
1 –20 QUAD_FILTERS = 15
–25
–30
17172-116
0
17172-113
23 25 27 29 31 33 35 37 39 41 43 45
1 10 100 1k 10k 100k 1M 10M 100M
RF FREQUENCY (GHz)
Figure 109. Amplitude Imbalance and Phase Imbalance vs. Baseband Frequency Figure 112. Conversion Gain vs. RF Frequency for Four Different
QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband)
Data Sheet ADMV1014
–40
IF I: QUAD_FILTERS = 0
PERFORMANCE BETWEEN DIFFERENTIAL vs.
–45
IF
IF
I: QUAD_FILTERS = 5
I: QUAD_FILTERS = 10
SINGLE-ENDED LO INPUT
IF I: QUAD_FILTERS = 15
Figure 115 to Figure 117 show the conversion gain, input IP3
–50
and image rejection performance for operating the ADMV1014
–55 LO input as differential vs. SE. The measurements were
–60 performed with 0 dBm LO input power, IF mode, with an IF
frequency of 3.5 GHz, upper sideband, and TA = 25°C.
–65
25
–70
IF Q: QUAD_FILTERS = 0
–75 IF Q: QUAD_FILTERS = 5 20

–80
17172-117
4 5 6 7 8 9 10 11 12 15
LO FREQUENCY (GHz)
Figure 113. LO To IF Leakage vs. RF Frequency for Four Different

QUAD_FILTERS Settings, fIF = 3.5 GHz (Upper Sideband) 10
VVA TEMPERATURE COMPENSATION LO DIFF

LO SE P SIDE
5 LO SE N SIDE
Figure 114 shows the conversion gain vs. RF frequency at two
different Register 0x0B settings and three different temperatures
for IF mode. The recommended value suggested in the Start-Up 0
17172-119
23 25 27 29 31 33 35 37 39 41 43 45
Sequence section provides the highest conversion gain. If the RF FREQUENCY (GHz)
priority is to decrease the conversion gain variation across Figure 115. Conversion Gain vs. RF Frequency for Three Different LO Mode
temperature, Register 0x0B can be set to 0x726C. However, at Settings, fIF = 3.5 GHz (Upper Sideband)
this value, the conversion gain is lower at each temperature. 10
25 8
6
20
4
INPUT IP3 (dBm)
15
2
10 0
–2
5
–4 LO DIFF
+85°C AT REG 0x0B = 0x727C
+25°C AT REG 0x0B = 0x727C LO SE P SIDE
0 –40°C AT REG 0x0B = 0x727C –6 LO SE N SIDE
+85°C AT REG 0x0B = 0x726C
+25°C AT REG 0x0B = 0x726C –8
–5 –40°C AT REG 0x0B = 0x726C
–10
17172-120
23 25 27 29 31 33 35 37 39 41 43 45
–10
17172-118
23 25 27 29 31 33 35 37 39 41 43 45 RF FREQUENCY (GHz)
RF FREQUENCY (GHz) Figure 116. Input IP3 vs. RF Frequency for Three Different LO Mode Settings,
Figure 114. Conversion Gain vs. RF Frequency at Maximum Gain for Various RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, fIF = 3.5 GHz
Register 0x0B Settings and Various Temperatures (Upper Sideband)
ADMV1014 Data Sheet
40 30
20
35
10
30

0
25
–10
20 –20
–30
15
–40 0.8GHz LOWER SIDEBAND
1.0GHz LOWER SIDEBAND
10 2.0GHz LOWER SIDEBAND
LO DIFF
LO SE P SIDE –50 3.0GHz LOWER SIDEBAND
LO SE N SIDE 4.0GHz LOWER SIDEBAND
5 5.0GHz LOWER SIDEBAND
–60
0 –70
17172-121
17172-123
24 26 28 30 32 34 36 38 40 42 44 23 25 27 29 31 33 35 37 39 41 43 45
RF INPUT FREQUENCY (GHz) RF FREQUENCY (GHz)
Figure 117. Image Rejection vs. RF Input Frequency for Three Different LO Figure 119. Conversion Gain vs. RF Frequency at Multiple IF Frequency
Mode Settings, RF Amplitude = −30 dBm per Tone at 20 MHz Spacing, Settings (Lower Sideband)
fIF = 3.5 GHz (Upper Sideband)
25
PERFORMANCE ACROSS RF FREQUENCY AT FIXED 20
IF AND BASEBAND FREQUENCIES 15

The ADMV1014 quadrupler operates from 21.6 GHz to 10
41 GHz. When using high-side LO injection, the conversion 5
gain starts rolling off gradually after the quadrupler frequency 0
reaches 41 GHz. When using low-side LO, the conversion gain –5

starts rolling off when the quadrupler frequency is 21.6 GHz. –10 0.8GHz UPPER SIDEBAND
1.0GHz UPPER SIDEBAND
Figure 118 and Figure 119 show the conversion gain vs. RF –15 2.0GHz UPPER SIDEBAND
frequency in IF mode for fixed IF frequencies (TA = 25°C, LO = –20 4.0GHz UPPER SIDEBAND
6 dBm) for upper sideband and lower sideband, respectively. –25 6.0GHz UPPER SIDEBAND
Figure 120 and Figure 121 show the conversion gain vs. RF –30
17172-124
23 25 27 29 31 33 35 37 39 41 43 45
frequency in IQ mode for fixed BB frequencies (TA = 25°C, LO = RF FREQUENCY (GHz)
6 dBm) for upper sideband and lower sideband, respectively.
Figure 120. Conversion Gain vs. RF Frequency at Multiple I/Q Frequency
25 Settings (Upper Sideband)
20 30
15
20
10
10
5
0 0
–5 –10
–10 1.0GHz UPPER SIDEBAND
2.0GHz UPPER SIDEBAND –20
–15 3.0GHz UPPER SIDEBAND
4.0GHz UPPER SIDEBAND –30 0.8GHz LOWER SIDEBAND
–20 5.0GHz UPPER SIDEBAND 1.0GHz LOWER SIDEBAND
6.0GHz UPPER SIDEBAND 2.0GHz LOWER SIDEBAND
–40 3.0GHz LOWER SIDEBAND
–25
–30 –50 5.0GHz LOWER SIDEBAND
17172-122
23 25 27 29 31 33 35 37 39 41 43 45 6.0GHz LOWER SIDEBAND
RF FREQUENCY (GHz) –60

17172-125
23 25 27 29 31 33 35 37 39 41 43 45
Figure 118. Conversion Gain vs. RF Frequency for Multiple IF Frequency RF FREQUENCY (GHz)
Settings (Upper Sideband)
Figure 121. Conversion Gain vs. RF Frequency at Multiple IQ Frequency
Settings (Lower Sideband)
Data Sheet ADMV1014
RECOMMENDED LAND PATTERN EVALUATION BOARD INFORMATION
Solder the exposed pad on the underside of the ADMV1014 to a For more information about the ADMV1014 evaluation board,
low thermal and electrical impedance ground plane. This pad is refer to the ADMV1014-EVALZ user guide.
typically soldered to an exposed opening in the solder mask on
the evaluation board. Connect these ground vias to all other
ground layers on the evaluation board to maximize heat
dissipation from the device package.
17172-126
Figure 122. Evaluation Board Layout for the LGA package
ADMV1014 Data Sheet
REGISTER SUMMARY
Table 8. Register Summary
Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8
Reg. Name Bits Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset R/W
0x00 SPI_CONTROL [15:8] PARITY_EN SPI_SOFT_ RESERVED CHIP_ID[7:4] 0x0093 R/W
RESET
[7:0] CHIP_ID[3:0] REVISION
0x01 ALARM [15:8] PARITY_ TOO_FEW_ TOO_MANY_ ADDRESS RESERVED 0x0000 R
ERROR ERRORS ERRORS _RANGE_
ERROR
[7:0] RESERVED
0x02 ALARM_MASKS [15:8] PARITY_ TOO_ TOO_MANY_ ADDRESS RESERVED 0xFFFF R/W
ERROR_MASK FEW_ ERRORS_ _RANGE_
ERRORS_ MASK ERROR_
MASK MASK
[7:0] RESERVED
0x03 ENABLE [15:8] RESERVED IBIAS_PD P1DB_COMPENSATION IF_AMP_ RESERVED QUAD_ BB_AMP_ 0x0157 R/W
PD BG_PD PD
[7:0] QUAD_IBIAS_ DET_EN BG_PD RESERVED
PD
0x04 QUAD [15:8] RESERVED QUAD_SE_MODE[3:2] 0x5700 R/W
[7:0] QUAD_SE_MODE[1:0] RESERVED QUAD_FILTERS
0x05 LO_AMP_ [15:8] LOAMP_PH_ADJ_I_FINE LOAMP_ 0x4101 R/W
PHASE_ PH_ADJ_
ADJUST1 Q_FINE[6]
[7:0] LOAMP_PH_ADJ_Q_FINE[5:0] RESERVED
0x07 MIXER [15:8] MIXER_VGATE RESERVED 0xD808 R/W
[7:0] RESERVED DET_PROG
0x08 IF_AMP [15:8] RESERVED IF_AMP_COARSE_GAIN_I 0x0000 R/W
[7:0] IF_AMP_FINE_GAIN_Q IF_AMP_FINE_GAIN_I
0x09 IF_AMP_BB_ [15:8] IF_AMP_COARSE_GAIN_Q RESERVED BB_AMP_OFFSET_Q[4:3] 0x0000 R/W
AMP
[7:0] BB_AMP_OFFSET_Q[2:0] BB_AMP_OFFSET_I
0x0A BB_AMP__AGC [15:8] RESERVED 0x2390 R/W
[7:0] RESERVED BB_AMP_REF_GEN BB_AMP_GAIN_CTRL BB_
SWITCH_
HIGH_
LOW_
COMMON_
MODE
0x0B VVA_TEMP_ [15:8] VVA_TEMPERATURE_COMPENSATION[15:8] 0x4A5C R/W
COMP
[7:0] VVA_TEMPERATURE_COMPENSATION[7:0]
Data Sheet ADMV1014
REGISTER DETAILS
Address: 0x00, Reset: 0x0093, Name: SPI_CONTROL
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1
[15] PARITY_EN (R/W) [3:0] REVISION (R)

Enable the Parity for Write Execution Revis ion ID
[14] SPI_SOFT_RESET (R/W) [11:4] CHIP_ID (R)

SPI Soft Reset Chip ID
[13:12] RESERVED
Table 9. Bit Descriptions for SPI_CONTROL

Bits Bit Name Settings Description Reset Access
15 PARITY_EN Enable the Parity for Write Execution 0x0 R/W
14 SPI_SOFT_RESET SPI Soft Reset 0x0 R/W
[13:12] RESERVED Reserved 0x0 R
[11:4] CHIP_ID Chip ID 0x9 R
[3:0] REVISION Revision ID 0x3 R
Address: 0x01, Reset: 0x0000, Name: ALARM

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15] PARITY_ERROR (R) [11:0] RESERVED

Parity Error
[12] ADDRESS_RANGE_ERROR (R)
[14] TOO_FEW_ERRORS (R) Address Range Error
Too Few Errors
[13] TOO_MANY_ERRORS (R)

Too_Many_Errors
Table 10. Bit Descriptions for ALARM

15 PARITY_ERROR Parity Error 0x0 R
14 TOO_FEW_ERRORS Too Few Errors 0x0 R
13 TOO_MANY_ERRORS Too Many Errors 0x0 R
12 ADDRESS_RANGE_ERROR Address Range Error 0x0 R
Address: 0x02, Reset: 0xFFFF, Name: ALARM_MASKS

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
[15] PARITY_ERROR_MASK (R/W) [11:0] RESERVED

Parity Error Mas k
[12] ADDRESS_RANGE_ERROR_MASK (R/W)
[14] TOO_FEW_ERRORS_MASK (R/W) Address Range Error Mask
Too Few Errors Mask
[13] TOO_MANY_ERRORS_MASK (R/W)

Too Many Errors Mas k
Table 11. Bit Descriptions for ALARM_MASKS

15 PARITY_ERROR_MASK Parity Error Mask 0x1 R/W
14 TOO_FEW_ERRORS_MASK Too Few Errors Mask 0x1 R/W
13 TOO_MANY_ERRORS_MASK Too Many Errors Mask 0x1 R/W
12 ADDRESS_RANGE_ERROR_MASK Address Range Error Mask 0x1 R/W
[11:0] RESERVED Reserved 0xFFF R
ADMV1014 Data Sheet
Address: 0x03, Reset: 0x0157, Name: ENABLE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1
[15] RESERVED [4:0] RESERVED
[14] IBIAS_PD (R/W) [5] BG_PD (R/W)

Power Down the RX Ibias Power Down the RX BG
[13:12] P1DB_COMPENSATION (R/W) [6] DET_EN (R/W)

Turn on bits to optim ize P1dB Digital RX Detector Enable
[11] IF_AMP_PD (R/W) [7] QUAD_IBIAS_PD (R/W)

Power Down the IF Am p Power Down the Quadrupler Bias
Current.
[10] RESERVED
[8] BB_AMP_PD (R/W)
[9] QUAD_BG_PD (R/W)
Power Down the Base-Band Am p
Power Down the Quadrupler BandGap
Table 12. Bit Descriptions for ENABLE

15 RESERVED Reserved 0x0 R
14 IBIAS_PD Power Down the Rx IBIAS 0x0 R/W
[13:12] P1DB_COMPENSATION Turn on bits to optimize P1dB 0x0 R/W
11 IF_AMP_PD Power Down the IF Amp 0x0 R/W
10 RESERVED Reserved 0x0 R
9 QUAD_BG_PD Power Down the Quadrupler Band Gap 0x0 R/W
8 BB_AMP_PD Power Down the Baseband Amp 0x1 R/W
7 QUAD_IBIAS_PD Power Down the Quadrupler Bias Current 0x0 R/W
6 DET_EN Digital Rx Detector Enable 0x1 R/W
5 BG_PD Power Down the Rx BG 0x0 R/W
Address: 0x04, Reset: 0x5700, Name: QUAD

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 1 0 1 1 1 0 0 0 0 0 0 0 0
[15:10] RESERVED [3:0] QUAD_FILTERS (R/W)

LO Filters BW Selection
[9:6] QUAD_SE_MODE (R/W)
0000: LO Frequency BW: 8.625 to 10.25GHz.
Switch Differential/SE Modes
0101: LO Frequency BW: 6.6 to 9.2GHz.
0110: SE_Mode_N_Side.
1010: LO Frequency BW: 5.4 to 8GHz.
1001: SE_Mode_P_Side.
1111: LO Frequency BW: 5.4 to 7GHz.
1100: Differential Mode.
[5:4] RESERVED
Table 13. Bit Descriptions for QUAD

[9:6] QUAD_SE_MODE Switch Differential/SE Modes 0xC R/W
0110 SE Mode N Side
1001 SE Mode P Side
1100 Differential Mode
[5:4] RESERVED Reserved. 0x0 R
[3:0] QUAD_FILTERS LO Filters BW Selection 0x0 R/W
0000 LO Frequency BW: 8.625 GHz to 10.25 GHz
0101 LO Frequency BW: 6.6 GHz to 9.2 GHz
1010 LO Frequency BW: 5.4 GHz to 8 GHz
1111 LO Frequency BW: 5.4 GHz to 7 GHz
Data Sheet ADMV1014
Address: 0x05, Reset: 0x4101, Name: LO_AMP_PHASE_ADJUST1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1
[15:9] LOAMP_PH_ADJ_I_FINE (R/W) [1:0] RESERVED

Mixer Im age Rejection Calibration
0x00:Maximum Phase, 0x7F: Minim um
Phase
[8:2] LOAMP_PH_ADJ_Q_FINE (R/W)

Mixer Im age Rejection Calibration
0x00:Maximum Phase, 0x7F: Minim um
Phase
Table 14. Bit Descriptions for LO_AMP_PHASE_ADJUST1

[15:9] LOAMP_PH_ADJ_I_FINE Mixer Image Rejection Calibration 0x00: Maximum Phase, 0x7F: 0x20 R/W
Minimum Phase
[8:2] LOAMP_PH_ADJ_Q_FINE Mixer Image Rejection Calibration 0x0: Maximum Phase, 0x7F: 0x40 R/W
Minimum Phase
Address: 0x07, Reset: 0xD808, Name: MIXER

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0
[15:9] MIXER_VGATE (R/W) [6:0] DET_PROG (R/W)

Control BB Comm on Mode Voltage Digital RX Detector Program
(Please see the application section 0: From -12 to +4dBm .
for more Inform ation) 1: From -13 to +3dBm .
10: From -14 to +2dBm .
[8:7] RESERVED
100: From -15 to +1dBm .
1000: From -15.5 to +0.5dBm.
10000: From -16.25 to -0.25dBm .
100000: From -17 to -1dBm .
1000000: From -18 to -2dBm .
Table 15. Bit Descriptions for MIXER

[15:9] MIXER_VGATE Control BB Common Mode Voltage. See the Applications Information section for 0x6C R/W
more information)
[6:0] DET_PROG Digital Rx Detector Program. 0x8 R/W
0 From −12 dBm to +4 dBm.
1000 From −15.5 dBm to +0.5 dBm.
10000 From −16.25 dBm to −0.25 dBm.
100000 From −17 dBm to −1 dBm.
1000000 From −18 dBm to −2 dBm.
ADMV1014 Data Sheet
Address: 0x08, Reset: 0x0000, Name: IF_AMP
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] RESERVED [3:0] IF_AMP_FINE_GAIN_I (R/W)

IF Amp I, 10 Fine Steps from 0x0 to
[11:8] IF_AMP_COARSE_GAIN_I (R/W)
0xA (Total attenuation ~1dB). Refer
Digital IF Am p 1dB Step Gain_I
to Figure 80 to Figure 82.
0: Refer to Figure 77 to Figure 79.
1: Refer to Figure 77 to Figure 79. [7:4] IF_AMP_FINE_GAIN_Q (R/W)
11: Refer to Figure 77 to Figure 79. IF Amp Q, 10 Fine Steps from 0x0
111: Refer to Figure 77 to Figure 79. to 0xA (Total attenuation ~1dB). Refer
1111: Refer to Figure 77 to Figure 79. to Figure 80 to Figure 82.
Table 16. Bit Descriptions for IF_AMP

[11:8] IF_AMP_COARSE_GAIN_I Digital IF Amp Step Gain I. 0x0 R/W
0 Refer to Figure 77 to Figure 79.
[7:4] IF_AMP_FINE_GAIN_Q IF Amp Q, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82. 0x0 R/W
[3:0] IF_AMP_FINE_GAIN_I IF Amp I, 10 Fine Steps from 0x0 to 0xA. Refer to Figure 80 to Figure 82. 0x0 R/W
Address: 0x9, Reset: 0x0000, Name: IF_AMP__BB_AMP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
[15:12] IF_AMP_COARSE_GAIN_Q (R/W) [4:0] BB_AMP_OFFSET_I (R/W)

Digital IF Am p 1dB Step Gain_Q BB Am p I. Bit 4: Use as Sign Bit, b’1
0: Refer to Figure 77 to Figure 79. is for positive values and b’0 is for
1: Refer to Figure 77 to Figure 79. negative values; Bits [3:0] Minim um
11: Refer to Figure 77 to Figure 79. Offset, 0xF: Maxim um Offset.
[9:5] BB_AMP_OFFSET_Q (R/W)
BB Am p Q. Bit 9: Use as Sign Bit,
[11:10] RESERVED b’1is for positive values and b’0 is
for negative values; Bit [8:5] Minim um
Offset, 0xF: Maxim um Offset.
Table 17. Bit Descriptions for IF_AMP__BB_AMP

[15:12] IF_AMP_COARSE_GAIN_Q Digital IF Amp 1 dB Step Gain Q 0x0 R/W
0 Refer to Figure 77 to Figure 79
[9:5] BB_AMP_OFFSET_Q BB Amp Q (Bit 9: Use as Sign Bit, 1 is for positive values and 0 is for 0x0 R/W
negative values; Bits[8:5]: Minimum Offset, 0xF: Maximum Offset)
[4:0] BB_AMP_OFFSET_I BB Amp I (Bit 4: Use as Sign Bit, 1 is for positive values and 0 is for 0x0 R/W
negative values; Bits[3:0]: Minimum Offset, 0xF: Maximum Offset)
Data Sheet ADMV1014
Address: 0x0A, Reset: 0x2390, Name: BB_AMP_AGC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 1 0 0 0 1 1 1 0 0 1 0 0 0 0
[15:7] RESERVED [0] BB_SWITCH_HIGH_LOW_COMMON_MODE (R/W)

Setting between High and Low Output
[6:3] BB_AMP_REF_GEN (R/W)
Com mon Mode Voltage; Should Be
Control BB Com m on Mode Voltage
Set to Oppos ite from RegA<bit6>
See the Baseband Quadrature Dem odulation
(I/Q Mode) s ection for m ore inform ation. [2:1] BB_AMP_GAIN_CTRL (R/W)
See Figure 44 to Figure 46.
Table 18. Bit Descriptions for BB_AMP_AGC

[6:3] BB_AMP_REF_GEN Control BB Common-Mode Voltage. See the 0x2 R/W
Baseband Quadrature Demodulation (I/Q Mode)
section for more information.
[2:1] BB_AMP_GAIN_CTRL See Figure 44 to Figure 46. 0x0 R/W
0 BB_SWITCH_HIGH_LOW_COMMON_MODE Setting between High and Low Output Common- 0x0 R/W
Mode Voltage. This bit must be set to opposite from
Register 0x0A, Bit 6. See the Baseband Quadrature
Demodulation (I/Q Mode) section for more
information.
Address: 0x0B, Reset: 0x4A5C, Name: VVA_TEMP_COMP

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 1 0 0 1 0 1 0 0 1 0 1 1 1 0 0
[15:0] VVA_TEMPPERATURE_COMPENSATION (R/W)

VVA Temperature Compensation
Table 19. Bit Descriptions for VVA_TEMP_COMP

[15:0] VVA_TEMPERATURE_COMPENSATION VVA Temperature Compensation. Set to 0x727C. See the 0x4A5C R/W
Start-Up Sequence section and the VVA Temperature
Compensation section for more information. Disable
PARITY_EN when updating the VVA temperature
compensation.
ADMV1014 Data Sheet
OUTLINE DIMENSIONS
5.10 0.32
5.00 0.27 0.81 BSC
0.40 SQ
4.90 0.22
PIN 1 0.35 PIN 1
CORNER AREA INDICATOR
0.30 25 32
24 1
3.50 REF
SQ 3.57 BSC
SQ
0.50
BSC
17 8
16 9
TOP VIEW
0.75 BOTTOM VIEW
BSC 0.165
0.52 0.275 3.77 BSC BSC
0.45 REF
0.75 MAX FOR PROPER CONNECTION OF
SIDE VIEW 0.38
0.67 NOM THE EXPOSED PADS, REFER TO
0.25 THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING 0.22
02-12-2018-A
SECTION OF THIS DATA SHEET.
PLANE
PKG-005727
0.19
Figure 123. 32-Terminal Land Grid Array [LGA]

(CC-32-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADMV1014ACCZ −40°C to +85°C 32-Terminal Land Grid Array Package [LGA] CC-32-6
ADMV1014ACCZ-R7 −40°C to +85°C 32-Terminal Land Grid Array Package [LGA] CC-32-6
ADMV1014-EVALZ Evaluation Board
1
Z = RoHS-Compliant Part.
©2018–2019 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D17172-0-4/19(A)

ADMV1014 (24 - 44 GHZ Downconverter)

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ADMV1014 (24 - 44 GHZ Downconverter)

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24 GHz to 44 GHz,

Wideband, Microwave Downconverter

Matched 50 Ω, single-ended RF input, and complex IF outputs

Programmable via a 4-wire SPI interface

Rev. A Document Feedback

tSCLK, SEN_SETU P tSEN_INACTIVE

Figure 2. Serial Port Register Timing Diagram

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

9 SDO SPI Serial Data Output.

TYPICAL PERFORMANCE CHARACTERISTICS

CONVERSION GAIN (dB)

CONVERSION GAIN (dB)

CONVERSION GAIN (dB)

0 39GHz LOWER SIDEBAND

8 +85°C UPPER SIDEBAND

INPUT IP3 (dBm)

8 3.5V UPPER SIDEBAND 7.5 39GHz UPPER SIDEBAND

8 +6dBm UPPER SIDEBAND 4

INPUT IP3 (dBm)

NOISE FIGURE (dB)

3.5V UPPER SIDEBAND 8

NOISE FIGURE (dB)

4 3 39GHz UPPER SIDEBAND

+6dBm UPPER SIDEBAND 8

NOISE FIGURE (dB)

4 3 39GHz LOWER SIDEBAND

+85°C UPPER SIDEBAND

IMAGE REJECTION (dBc)

+6dBm UPPER SIDEBAND

+85°C UPPER SIDEBAND

70 70 39GHz UPPER SIDEBAND

60 28GHz LOWER SIDEBAND

INPUT IP2 (dBm)

+85°C UPPER SIDEBAND

INPUT IP2 (dBm) 35

–2 +85°C UPPER SIDEBAND

INPUT P1dB (dBm)

–2 3.5V UPPER SIDEBAND –2

–6 INPUT P1dB (dBm) –6

–14 –14 39GHz UPPER SIDEBAND

–2 +6dBm UPPER SIDEBAND –2

–14 –14 39GHz LOWER SIDEBAND

MAGNITUDE ERROR (dB)

PHASE ERROR (Degrees)

NOISE FIGURE (dB)

Figure 45. Input IP3 vs. RF Frequency at Four Different BB_AMP_GAIN_CTRL

20 39GHz UPPER SIDEBAND

CONVERSION GAIN (dB)

–15 +85°C UPPER SIDEBAND

–15 3.5V UPPER SIDEBAND

–15 +6dBm UPPER SIDEBAND

23 25 27 29 31 33 35 37 39 41 43 45 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

INPUT IP3 (dBm)

INPUT IP3 (dBm)

10 39GHz UPPER SIDEBAND

NOISE FIGURE (dB)

NOISE FIGURE (dB)

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

INPUT P1dB (dBm)

+85°C UPPER SIDEBAND +6dBm UPPER SIDEBAND