Introduction To Introduction To 8085 8085: Microprocessor

12/19/2018
 A microprocessor is a multipurpose,
INTRODUCTION TO programmable, clock-driven,
8085 register-based electronic device that
reads binary instructions from a
storage device called memory,
accepts binary data as input and
processes data according to those
-NAVEEN BHAT
instructions, and provides results as
output
Naveen Bhat 1 NAVEEN BHAT 2
A Programmable Machine
Memory
Microprocessor
I/O
Introduction to 8085 Introduction to 8085

 It was introduced in 1977.  It has three advanced
 It is 8-bit microprocessor. versions:
 Its actual name is 8085 A. ◦ 8085 AH
 It is single NMOS device. ◦ 8085 AH2
 It contains 6200 transistors ◦ 8085 AH1
approx.
 Its dimensions are  These advanced
164 mm x 222 mm. versions are designed
 It is having 40 pins Dual- using HMOS
Inline-Package (DIP). technology.
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Introduction to 8085
 The advanced versions Address Bus
consume 20% less power
supply.
Memory
Real world
Input
 The clock frequencies of 8085 Output
8085 are: MPU
◦ 8085 A 3 MHz
◦ 8085 AH3 MHz Data Bus
◦ 8085 AH2 5 MHz Control Bus

◦ 8085 AH1 6 MHz
Address Bus Data Bus

The address bus is a group of 16 lines generally
identified as A0 to A15. Data bus is a group of 8 lines used for data
The address bus is Unidirectional flow.
These lines are Bi-directional
The MPU uses the address bus to perform the first
function: identifying a peripheral or a memory location.
The MPU uses the data bus to perform the
second function: transferring binary
In a computer system, each peripheral or memory
location is identified by a binary number, called
information.
Address, and the address bus is used to carry a 16- The 8 data lines enable the MPU to
bit address. manipulate 8-bit data ranging from 00 to
Since it has 16 address lines, it can address 64K FF.
memory
Control Bus
Pin Diagram of 8085
The control bus is comprised of various
single lines that carry synchronization signals.
The MPU uses these lines to perform third

function: providing timing signals.
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X1 & X2 RESET IN and RESET OUT

Pin 1 and Pin 2 (Input) Pin 36 (Input) and Pin 3 (Output)
 These are also called  RESET IN:
Crystal Input Pins.
◦ It is used to reset the
microprocessor.
 8085 can generate clock
signals internally. ◦ It is active low signal.
 To generate clock ◦ When the signal on this

pin is low for at least 3
signals internally, 8085 clocking cycles, it forces
requires external inputs the microprocessor to
from X1 and X2. reset itself.
13 14
RESET IN and RESET OUT RESET IN and RESET OUT

Pin 36 (Input) and Pin 3 (Output) Pin 36 (Input) and Pin 3 (Output)
 Resetting the  RESET OUT:
microprocessor means:
◦ It is used to reset the peripheral
devices and other ICs on the
circuit.
◦ Clearing the PC and IR.
◦ Disabling all interrupts ◦ It is an output signal.
(except TRAP).
◦ Disabling the SOD pin. ◦ It is an active high signal.
◦ All the buses (data,
address, control) are tri- ◦ The output on this pin goes high
stated. whenever RESET IN is given low
signal.
◦ Gives HIGH output to
RESET OUT pin. ◦ The output remains high as long
as RESET IN is kept low.
15 16
SID and SOD SID and SOD

Pin 4 (Input) and Pin 5 (Output) Pin 4 (Input) and Pin 5 (Output)
 SID (Serial Input  SOD (Serial Output
Data): Data):
o It takes 1 bit input from o It takes 1 bit from

serial port of 8085. Accumulator to serial port
of 8085.
o Stores the bit at the 8th o Takes the bit from the 8th
position (MSB) of the position (MSB) of the
Accumulator. Accumulator.
o RIM (Read Interrupt o SIM (Set Interrupt Mask)

Mask) instruction is used instruction is used to
to transfer the bit. transfer the bit.
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Sequence of Steps Whenever There is

Interrupt Pins an Interrupt
 Interrupt:  Microprocessor completes execution of current
instruction of the program.
• It means interrupting the normal execution of the
microprocessor.
 PC contents are stored in stack.
• When microprocessor receives interrupt signal, it discontinues
whatever it was executing.  PC is loaded with address of the new program.
• It starts executing new program indicated by the interrupt
signal.  After executing the new program, the
microprocessor returns back to the previous
• Interrupt signals are generated by external peripheral devices. program.
• After execution of the new program, microprocessor goes  It goes to the previous program by reading the top
back to the previous program. value of stack.
19 20
Five Hardware Interrupts in 8085 Classification of Interrupts

 TRAP  Maskable and Non-Maskable
 RST 7.5  Vectored and Non-Vectored
 RST 6.5
 Edge Triggered and Level Triggered
 RST 5.5
 Priority Based Interrupts
 INTR
21 22
Maskable Interrupts Maskable Interrupts

 Maskable interrupts are those interrupts  List of Maskable Interrupts:
which can be enabled or disabled.
• RST 7.5
 Enabling and Disabling is done by
software instructions. • RST 6.5
• RST 5.5
• INTR
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Non--Maskable Interrupts
Non Vectored Interrupts
 The interrupts which are always in  The interrupts which have fixed memory
enabled mode are called non-maskable location for transfer of control from
interrupts. normal execution.
 These interrupts can never be disabled  Each vectored interrupt points to the
by any software instruction. particular location in memory.
 TRAP is a non-maskable interrupt.
25 26
Vectored Interrupts Vectored Interrupts

 List of vectored interrupts:  The addresses to which program control
goes:
• RST 7.5 Name Vectored Address
RST 7.5 003C H (7.5 x 0008 H)
RST 6.5 0034 H (6.5 x 0008 H)
• RST 6.5
RST 5.5 002C H (5.5 x 0008 H)
TRAP 0024 H (4.5 x 0008 H)
• RST 5.5
 Absolute address is calculated by
• TRAP multiplying the RST value with 0008 H.
27 28
Non--Vectored Interrupts
Non Edge Triggered Interrupts
 The interrupts which don't have fixed  The interrupts which are triggered at
memory location for transfer of control leading or trailing edge are called edge
from normal execution. triggered interrupts.
 The address of the memory location is  RST 7.5 is an edge triggered interrupt.
sent along with the interrupt.
 It is triggered during the leading
 INTR is a non-vectored interrupt. (positive) edge.
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Level Triggered Interrupts Priority Based Interrupts

 The interrupts which are triggered at high  Whenever there exists a simultaneous
or low level are called level triggered request at two or more pins then the
interrupts. pin with higher priority is selected by the
microprocessor.
 RST 6.5
 RST 5.5  Priority is considered only when there
 INTR are simultaneous requests.
 TRAP is edge and level triggered interrupt.

31 32
Priority Based Interrupts TRAP

Pin 6 (Input)
 It is an non-maskable interrupt.
 Priority of interrupts:
 It has the highest priority.
 It cannot be disabled.
Interrupt Priority
 It is both edge and level
TRAP 1 triggered.
RST 7.5 2
 It means TRAP signal must go
RST 6.5 3 from low to high.
RST 5.5 4  And must remain high for a
INTR 5 certain period of time.
 TRAP is usually used for power
failure and emergency shutoff.
33 34
RST 7.5 RST 6.5

Pin 7 (Input) Pin 8 (Input)
 It is a maskable interrupt.  It is a maskable interrupt.
 It has the second highest  It has the third highest
priority. priority.
 It is positive edge triggered  It is level triggered only.
only.  The pin has to be held high
for a specific period of
 The internal flip-flop is time.
triggered by the rising
 RST 6.5 can be enabled by
edge. EI instruction.
 The flip-flop remains high  It can be disabled by DI
until it is cleared by RESET instruction.
IN.
Gursharan Singh Tatla Gursharan Singh Tatla
professorgstatla@gmail.com www.eazynotes.com 35 professorgstatla@gmail.com www.eazynotes.com 36
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RST 5.5 INTR

 It is a maskable  It is a maskable interrupt.
interrupt.  It has the lowest priority.
 It has the fourth highest  It is also level triggered.
priority.  It is a general purpose
 It is also level triggered. interrupt.
 The pin has to be held  By general purpose we
mean that it can be used to
high for a specific period vector microprocessor to
of time. any specific subroutine
 This interrupt is very having any address.
similar to RST 6.5.

INTA Address and Data Pins

Pin 11 (Output)
 It stands for interrupt  Address Bus:
acknowledge.
 It is an out going signal. • The address bus is used to send address to
 It is an active low signal. memory.
 Low output on this pin • It selects one of the many locations in
indicates that memory.
microprocessor has • Its size is 16-bit.
acknowledged the INTR
request.
Address and Data Pins AD0 – AD7

Pin 19-
19-12 (Bidirectional)
 These pins serve the dual
 Data Bus: purpose of transmitting lower
order address and data byte.
• It is used to transfer data between  During 1st clock cycle, these pins
act as lower half of address.
microprocessor and memory.
• Data bus is of 8-bit.  In remaining clock cycles, these
pins act as data bus.
 The separation of lower order

address and data is done by
address latch.

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A8 – A15 ALE
Pin 21-
21-28 (Unidirectional) Pin 30 (Output)
 These pins carry the  It is used to enable Address
higher order of address Latch.
bus.
 It indicates whether bus
functions as address bus or data
 The address is sent from bus.
microprocessor to
memory.  If ALE = 1 then
◦ Bus functions as address bus.
 These 8 pins are switched
to high impedance state  If ALE = 0 then
during HOLD and RESET ◦ Bus functions as data bus.
mode.
Procedure For DeMultiplexing AD0–

AD0–AD7 Bus
DeMultiplexing AD0–
AD0–AD7 Bus
 Whenever an instruction is executed by MPU first of
all MPU sends ALE signal to address latch IC to
enable all D Latches to receive new address from
MPU.
 In first T state Microprocessor generates the address
on Address Bus, half portion of address (lower order
address) is generated on AD0-AD7 . This Address bits
are captured by D latches and stored in.
 During next cycles say T2, T3 and so on, MP can use
AD0-AD7 as Data Bus to send receives data. During
this period the initially generated Address is also
available at output pins of D Latches .The IC
74LS373is used as Address Latch it contains 8 D
Latches to store lower half of address.(8 bits).
S0 and S1 IO/M
Pin 29 (Output) and Pin 33 (Output) Pin 34 (Output)
 S0 and S1 are called Status  This pin tells whether I/O
Pins. or memory operation is
being performed.
 They tell the current

 If IO/M = 1 then
operation which is in progress
in 8085. ◦ I/O operation is being
performed.
S0 S1 Operation
0 0 Halt  If IO/M = 0 then
0 1 Write
◦ Memory operation is being
1 0 Read performed.
1 1 Opcode Fetch
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IO/M Table Showing IO/M, S0, S1 and

Pin 34 (Output) Corresponding Operations
 The operation being performed is indicated by
S0 and S1.
Operations IO/M S0 S1
Opcode Fetch 0 1 1
 If S0 = 0 and S1 = 1 then Memory Read 0 1 0
Memory Write 0 0 1
◦ It indicates WRITE operation.
I/O Read 1 1 0
I/O Write 1 0 1
 If IO/M = 0 then Interrupt Ack. 1 1 1
◦ It indicates Memory operation. Halt High Impedance 0 0
 Combining these two we get Memory Write

Operation.
RD WR
Pin 32 (Output) Pin 31 (Output)
 RD stands for Read.  WR stands for Write.
 It is an active low signal.  It is also active low signal.
 It is a control signal used  It is a control signal used
for Read operation either for Write operation either
from memory or from into memory or into
Input device. output device.
 A low signal indicates that  A low signal indicates that
data on the data bus must data on the data bus must
be placed either from be written into selected
selected memory location memory location or into
or from input device. output device.
READY HOLD
 This pin is used to  HOLD pin is used to request
synchronize slower the microprocessor for DMA
transfer.
peripheral devices with
fast microprocessor.  A high signal on this pin is a
request to microprocessor
 A low value causes the to relinquish the hold on
microprocessor to buses.
enter into wait state.
 This request is sent by DMA
controller.
 The microprocessor
remains in wait state  Intel 8257 and Intel 8237 are
until the input at this pin two DMA controllers.
goes high.
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HLDA HLDA
Pin 39 (Output) Pin 39 (Output)
 HLDA stands for Hold  The control of these
Acknowledge. buses goes to DMA
 The microprocessor uses Controller.
this pin to acknowledge the
receipt of HOLD signal.  Control remains at
DMA Controller until
 When HLDA signal goes high, HOLD is held high.
address bus, data bus, RD,
WR, IO/M pins are tri-  When HOLD goes low,
stated.
HLDA also goes low
 This means they are cut-off and the microprocessor
from external environment. takes control of the
buses.
8085 Microprocessor Architecture

VSS and VCC
Pin 20 (Input) and Pin 40 (Input)
 +5V power supply is
connected to VCC.
 Ground signal is
connected to VSS.
Gursharan Singh Tatla

professorgstatla@gmail.com www.eazynotes.com 57
Internal structure and basic operation of

microprocessor
The ALU
 In addition to the arithmetic & logic circuits, the ALU
includes an accumulator, which is a part of every
arithmetic & logic operation.
Address bus
ALU Register
Section  Also, the ALU includes a temporary register used for
Data bus holding data temporarily during the execution of the
operation. This temporary register is not accessible by
Control and timing the programmer.
section Control bus
Block diagram of a microprocessor

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The 8085 programmable model Accumulator:

•The accumulator is an 8-bit register then is part
Accumulator Flag register of the arithmetic/logic unit(ALU).
B C •
D E
•This register is used to store to store 8-bit data this data
H L
is used to perform arithmetic & logical operation.
Stack pointer (SP)
•The result of an operation is stored in the accumulator.
Program counter (PC)
Data B us Address Bus •The accumulator is also identified as register A.
•The accumulator is used for data transfer between an

I/O port and memory location.
Bi-directional Unidirectional
Registers Flag Register

The 8085 has six general-purpose registers The ALU includes five flip-flops (flags) that are
to perform the 1st operation: to store 8-bit data set or reset according to the result of an
during program execution operation. The microprocessor uses them to
The six general-purpose registers are – B, perform third operation: testing the data
C, D, E, H & L. And these can be combined as conditions
register pairs -BC, DE and HL – to perform • Carry flag
some 16-bit operations.
• Zero flag
These registers are programmable, • Sign flag
means , a programmer can use them to
• Parity flag
load or copy data from the registers by
using instructions. • Auxiliary flag
Flag Name Description PROGRAM COUNTER (PC)

Indicates that the result of a mathematical or logical operation was
Z Zero flag
zero.
 a 16 bit register, used to store the next address
of the operation code to be fetched by the CPU.
Indicates that the result of an operation produced an answer greater
C Carry flag
than the number of available bits. (This flag may also be set before a  Not much use in programming, but as an
mathematical operation as an extra operand to certain instructions,
e.g. "add with carry".) indicator to user only.
 Purpose of PC in a Microprocessor
◦ to store address of tos (top of stack)
This flag is set when a carry is generated from bit D3 and passed to
AC Auxiliary Carry Flag D4 .This flag is used only internally for BCD operations. ◦ to store address of next instruction to be
executed.
◦ to store base address of the stack.
After an ALU operation, if the result has an even # of 1s, the p-flag is
set. Otherwise it is cleared. So, the flag can be used to indicate even
P Parity flag
parity.
The sign flag is set if bit D7 of the accumulator is set after an

arithmetic or logic operation.
S Sign flag
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STACK POINTER (SP)

Instruction resister or Decoder:-
 The stack is configured as a data structure that
Once the instruction is fetch from the
grows downward from high memory to low memory, it is reloaded in the
memory. instruction resistor for some time,
after the decoder decode the
 At any given time, the SP holds the 16-bit instruction performing some event or
address of the next free location in the stack. task.
Address buffer:
The remaining higher order address
lines form the address buffer ranging
from[A15-18].This is having the
unidirectional buffer
67
Address/data buffer:
The address bus will be having 16 address
lines[A15-A0] .In which A7-A0 are called as
lower addressing lines and these are
multiplexed with data lines[D7-D0] to form
multiplexed address /data buffer .The
address/data buffer is the bidirectional bus.
Timing and Control Unit:
The timing and control unit accepts information
from the instruction decoder and
generates different control signal. This unit
synchronizes all the microprocessor operation
and generates control and status signal
necessary for communication between the
microprocessor and peripherals.
12

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12/19/2018

Naveen Bhat 1 NAVEEN BHAT 2

Introduction to 8085 Introduction to 8085

◦ 8085 AH2 5 MHz Control Bus

Address Bus Data Bus

The MPU uses these lines to perform third

X1 & X2 RESET IN and RESET OUT

 To generate clock ◦ When the signal on this

RESET IN and RESET OUT RESET IN and RESET OUT

SID and SOD SID and SOD

o It takes 1 bit input from o It takes 1 bit from

o RIM (Read Interrupt o SIM (Set Interrupt Mask)

Sequence of Steps Whenever There is

Five Hardware Interrupts in 8085 Classification of Interrupts

 RST 7.5  Vectored and Non-Vectored

Maskable Interrupts Maskable Interrupts

 TRAP is a non-maskable interrupt.

Vectored Interrupts Vectored Interrupts

Level Triggered Interrupts Priority Based Interrupts

 TRAP is edge and level triggered interrupt.

Priority Based Interrupts TRAP

RST 7.5 RST 6.5

RST 5.5 INTR

Gursharan Singh Tatla Gursharan Singh Tatla

INTA Address and Data Pins

Address and Data Pins AD0 – AD7

 The separation of lower order

Gursharan Singh Tatla Gursharan Singh Tatla

Procedure For DeMultiplexing AD0–

 They tell the current

IO/M Table Showing IO/M, S0, S1 and

 Combining these two we get Memory Write

8085 Microprocessor Architecture

Gursharan Singh Tatla

Internal structure and basic operation of

Block diagram of a microprocessor

The 8085 programmable model Accumulator:

Data B us Address Bus •The accumulator is also identified as register A.

•The accumulator is used for data transfer between an

Registers Flag Register

Flag Name Description PROGRAM COUNTER (PC)

The sign flag is set if bit D7 of the accumulator is set after an

STACK POINTER (SP)

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