FABRICATION AND ELECTRICAL MEASURMENTS OF MIS BASED MEMORY DEVICES. Maximum Marks = 100 (25 % towards module total marks) Lab report -2 INTRODUCTION MEMORY devices are playing an increasingly important role in microelectronics technology and considered as the technology drivers, whereas electronic memories cover about 20% of semiconductors market. Memory devices can be divided into different categories as shown in Fig. 1 wos [—~|Merares| ——1 rans rows L Lt ‘SRAM DRAM | ROM ee re Figure- 1. Different types of solid-state memories. Basically, these memory devices are divided into two types, i.e. volatile memories and non-volatile memories. The speed of write-erase operations in volatile memories such as SRAM and DRAM are very high, while these memories will lose data when the supply voltage is removed. In contrast, non- volatile memories have a very low write-erase speed with the need for high voltage and a longer retention time, usually more than 10 years. These different types of memories have different functions or in other words, fila particular function in a particular system. For example, SRAM memories are used by microprocessors of computers as off-chip or on-chip cache to store copies of the most frequently used main memory locations, to reduce the average time to access memory. SRAM memories are expensive and have a very high write-erase speed compared to the other type of volatile memories such as DRAM memories. DRAM memories are used as the main memory in computers and provide a random-access storage that is relatively large and cheap as compared to SRAM and relatively fast as compared to non-volatile memories. Magnetic disks are considered as a storage device and have the advantage of providing high storage capacity at extremely low cost, but with a poor energy consumption and a low access speed capabilities compared to other memory devices. For example, ‘nine million instructions can be executed by a 3-GHz microprocessor while waiting for the data from the magnetic disk. A broad range of computing systems was designed to conceal the disagreeable performance of magnetic disks . Because of critical computing applications are becoming data-centric, a high performance, high density and low cost NVM technology, which access time falls between of that of HDD and DRAM will increase the overall system performance. Flash memories technology promises to provide Hard Disks with costs lower than Magnetic disk cost. In Flash memories, the elapsed time between data storage and the first invalid readout of the data is the retention time, Each non-volatile storage technology employs a particular storage mechanism and properties related to that mechanism. Its implementation format will verify the retention features of the device. For Flash,the storage mechanism is to represent data by quantities of charge held on a floating gate. Each technology can be expected to have some natural processes where the data representation changes with time. Flash has some intrinsic charge decay characteristics that define the ultimate retention potential of the approach. At the present time, a typical retention specification is 10 years. 2. Aim and Objective: The aim of the experiment is to fabricate and electrically characterise Metal-nsular-Semiconductor structures containing silicon nano-structures fabricated from a selected catalyst (tin) as a charge- storing element. (a) (b) ———— pre Ineaiator > rovtrcne Semiconductor senleondctr Figure-2 Schematic diagram of MIS structure (a) a reference device without containing any nano- structures (b) a memory device containing nano-structure as a floating gate. 3. Fabrication of MIS structures: All the fabrication steps will be carried out using various equipment available in the EMTERC research group. A p-type silicon substrate, having a thin native oxide (1-2 nm) will be provided. Cleaning of the silicon wafer is performed using a standard organic solvents cleaning procedure. The bottom contact is performed by evaporating Aluminium and annealing in N2 gas at 500°C to establish an ohmic contact. The polished side of Si wafer is coated with Sn, of thickness 3 nm (approximately), by thermal evaporation. This is then followed by deposition of Si nanostructures (a floating gate in the above schematic diagram). The Device is completed by deposition of silicon nitride layer and top aluminium contact. A reference sample, without the deposition Sn and silicon nano-structures, will also be fabricated at the same time. Tremal Msplasma catalyst Figure-3: Overview of Vapour-liquid-Solid (VLS) growth of silicon nano-structures: (left) deposition of ‘metal catalyst (Sn in your case) on polished surface of Si substrate by thermal evaporation, (middle) ‘formation of nanoparticle, removal of surface oxide of catalyst and density control by atomic hydrogen plasma treatment and (right) VLS growth of Si nano-structures by assisted catalyst under SiH and H). You would like to stop the PECVD process within a few minutes, otherwise you will end up with growth of silicon nanowires.Silicon Nitride (Insulator — blocking layer) deposition parameters Silane flow rate = 20 sccm, Ammonia flow rate = 40 sccm, Nitrogen flow rat = 300°C, Pressure = 350 mTorr, RF power 11mW/cm?, Duration- 20 minutes. 100 sccm, Temperature Deposition conditions for Silicon Nanostructures Silane flow rate = 20 sccm, Hydrogen flow rate = 100 sccm, Temperature = 400 °C, Pressure = 500 mTorr, RF power 11mW/cm?, Duration = 120 sec. 4, Capacitance-Voltage (CV) behaviour of MIS structures: CV behaviour for the MIS structures (with and without floating gate) determines the presence of electronic charge in the insulating material (SiaNs) and floating gate (silicon nano-structures). Ideally, you would like to have no electronic charge stored in the insulating layer. However, the real insulator, specifically deposited by Plasma-Enhanced Chemical Deposition (PECVD) system does contain defect states, which give rise to a certain amount of charge stored. Your reference sample will help you to understand the quality of the insulating layer. Top contact (Al) }———SisN4_ — Blocking layer | <—— Native SiO (1-2 nm) —Tunneling layer ~ Bottom ohmic contact (Al) Figure-4: Schematic diagram of MIS structure. This device can help you to understand if Si nano- structures are storing the electronic charge or not. This structure is easy to fabricate and relatively straight forward to test. The electronic charge tunnel through the tunnelling layer and stores in Si nano-structures when a certain value of positive voltage is applied at the top contact. The tunnel layer also helps to retain the charge in Si nano-structures when there is no bias voltage (non-volatile memory). The thick blocking layer helps the stored electronic charge not to leak to the top metal electrode and prevent any charging of Si nano-structures from the top-electrode.stance) Figure-5: A schematic illustration using the energy band diagrams of a flash MIS to describe the tunnelling of high energy electrons (usually called hot-electrons as they possess energy in the order of Jew eV and the corresponding temperature will be the order of thousands of Kelvin thus the name hot- electrons). aes 8 Capacitance (pF) f Gate Votage (Vy Figure-6: capacitance-voltage behaviour of MIS structure containing Si nano-structures. The flat band voltage (Via) is the external voltage that is required to remove band bending in order to achieve a flat band. The change in the flat band voltage (VFB) is significant in the MIS structure containing Sinano- structures, The high value of AVFB is the determining factor in realising the Flash memory devices. Ideally, the change in fiat band voltage (AVFB) should be zero in the reference devices. The charging of nano-structures during the inversion mode (state) of MIS diode as there are unfilled lower energy states in Si nano-structures and no unfilled energy states during the accumulation mode (state); this is clearly illustrated in the satellite images. saxo aoe Wantage numberof puso Figure-7: The amount of time that information con be retained, in Si nano-structures, is another important factor of realising memory devices. In light of this, you will study data retention ‘measurements, which involved the monitoring of two states over a period of time. A typical example of such measurements is shown in this plot.Electrical Measurements to be performed in this work: Initially, carry out the leakage current measurements using HP4140B pico-ammeter. If the leakage current value is less than 10 nA at a specified voltage (say x), then continue measurements using an LCR bridge HP4192A, to measure capacitance-voltage behaviour of MIS diode: i Set Vins = 0.150 Set frequency f= 1 kHz, 1OkHz, SOkHz, 100KHZ and 30OkHZ. Capacitance-Voltage Measurements: Set the values of start and end voltages in such a ‘way that the value of leakage current is less than 10 nA. The measurements will be carried out using a HP4192A impedance analyzer in a shielded box for avoiding any electro- magnetic (e-m) interference with the electrical measurements. The voltage will be swept forth and back between +x V and -x V. This meant that bias swept from the inversion region to the accumulation region for a p-type MIS structure. Measure C-V behaviour for both memory sample with different frequencies. iv. Retention measurements. Select the appropriate write, read and erase voltages on the basis of step iii C-V measurements, Measure both the states ("0” and 1”) for a large number of 0.1-second pulses. 6. Weekly tasks: Cleaning of p-type | Catalyst Wand Cv Discussion on the | Data analysis and silicon & Evaporation | deposition measurements | results obtained, | calculations of Aluminium and etc making back ohmic | silicon nano- contact by Annealing | structures, SINx and Top contact, 7. Report write-up: Do not write too much! Individual report on the experiment performed and conclusions reached. This report should follow the format of the IEEE journal article (maximum 4 pages)- An example is provided {please go to the BB-shell of the module and look for Lab-2 MOS Memory folder). Minimum of 10 references should be cited. The journal paper/article should be submitted in Turnitin through the blackboard. Your report should answer and discuss questions mentioned below in the results and discussion section Q1. MIS Diode can be used to understand the electrical charging mechanism in Flash memory. Explain. Q2. Calculate the area enclosed by C-V curves for memory device for C-V measured at different frequencies. Is there any difference among the enclosed areas of memory device measured at different frequencies? Explain the observation in your own words. 3. Use the CV data, to calculate the charge storage in your memory devices. Q4, Plot the retention data for “O” and “1” states. What do you observe? Explain the observation in your own words.Q5. Explain the working principle of Flash Memory and problems associated with current Flash technology. Will the use of nano-structures, as a storage element, eliminate the problems associated with the Flash memory? Justify your answer. 8, Marks distribution In jual Components | Maximum score (%) © Abstract 10 * Introduction 10 © Experimental Section 10 © Results and Discussion 50 © Conclusions and 10 Future Scope * Referencing and Acknowledgements 10 9. Useful references for further reading (available in the BB-shell): 1. Charge-Trap-Non-volatile Memory and Focus on Flexible Flash Memory Devices Konstantina Sarant, Shashi Paul January 2017, Springer Science, Charge-Trap Memory, DOI: 10.1007/978-3- 319-48705-2_2 2. Konstantina Saran, Sultan Alotalbi, Shashi Paul, A new approach for two-terminal electronic memory devices - Storing information on silicon nanowires, Scientific Reports, June 2016, Nature Publishing Group, DO!: 10,1038/srep27506 3. Paul, ., Kanal, A. & Chhowalla, M. 2006, "Memory effect in thin Fims of insulating polymer and C60 nanocomposites", Nanotechnology, vol. 17, no. 1, pp. 145-152, 4. Paul, , Pearson, C, Molloy, A., Cousins, M.A, Green, M., Kolliopoulou, S, Dimitrak’s,P., Normand, P, Tsoukala, 1. & Petty, M.C. 203, "Langmuir-Blodgett film deposition of metallic nanoparticles and their application to electronic memory structures", Nono Letters, vol. 3, no. 4, pp. 533-536. 5. S. Tiwari, F. Rana, H, Hanafi, A. Hartstein, E.F. Crabbe, and K. Chan, A silicon nanocrystals based memory, Appl Phys. Let. 68, 1377 (1996).