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OMAPL138 Based Image Acquisition and Display System Development

Conference Paper · November 2018

DOI: 10.1109/ICAM.2018.8596541

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 2018 3rd International Conference on Integrated Circuits and Microsystems
OMAPL138 Based Image Acquisition and Display System Development
Yangqing Sun
School of Computer and Software
Nanjing Institute of Industry Technology
Nanjing, China
e-mail: sunyangqing@gmail.com
Abstract—An OMAPL38 based high sensitive CMOS image
acquisition and display system has been developed. This system
is designed for iris recognition which requires high speed and
high sensitive raw images. The image size of the system is
752×480 (10bit) and the experimental results indicate that the
readout speed exceeds 60fps with the peak quantum efficiency
over 50%. This system opens new possibilities for the real-time
biometric matching of eye images. The hardware and software
details are described in this paper.
Keywords-OMAPL138; CMOS image sensor; hardware
design; software design; frame rate; iris recognition
I. INTRODUCTION
Since now, Optical image detector has been widely used
in many fields like security system, military, traffic and so on.
It has contributed greatly for the efficiency and convenience
of our life [1]. As to the biometric matching, especially iris
recognition system, high speed and sensitivity are the two
critical characters for the achievable level of performances
[2]. The system we designed considerably decreases the time
demanded to read the image, and significant improved the
sensitivity compared with the traditional iris recognition
structure.
Image sensor is the core component of the iris
recognition system. With the advantages of low power
consumption, high integration and small volume, CMOS
image sensor dominates the Optical image detector market
for these years. It integrates the analog to digital (A/D)
conversion circuit and registers in a little chip which
provides a friend interface to DSP, ARM and other kinds of
processors. There are many companies producing CMOS
image sensor, like Omni Vision and Aptina [1].
OMAPL38 is a dual-core processor which integrates
ARM926EJ-S and DSP TMS320C6748 in it. It also includes
a series of peripherals. ARM and DSP can operate these
peripherals independently. With standardized interface, this
chip can be transplanted with programs and functions from
the third party [3]. And its standardized interface also allows
programs to be easily transplanted to different platforms. The
two microprocessor cores in OMAPL138 are all
programmable, and rewriting either one can completely
change the function of the system. The clock management of
each part is independent and the power consumption of this
chip is effectively controlled.
978-1-5386-8311-8/18/$31.00 ©2018 IEEE
Yuanyuan Hua
Purple Mountain Observatory, CAS
Key Lab of Space Object and Debris Observation, CAS
Nanjing, China
e-mail: huayuanyuan@outlook.com
The system is based on embedded Linux operating
system, taking ARM926EJ-S as the main control unit, and 7-
inch LCD screen as the image display unit.
II. SYEYTEM HARDWARE DESIGN
Fig. 1 is the architectural structure of the overall system.
It is composed of image acquisition, image processing,
image display and storage. The CMOS image sensor receives
the timing control from OMAPL138 and sends the image
data to the processor. The processor gets the parallel data and
sends it to the LCD to display. Here SD card is used to
storage the image files of the Linux system. RS232 is used to
get order and give feedback information to the PC.
LCD
TIMING
OMAPL138 DB9 to USB
CMOS Image Sensor
DSP
SYSLINK
ARM
SD CARD
PC
OBJECT
NAND FLASH DDR SDRAM
Figure 1. System architecture.
A. CMOS Image Sensor Control
In this project, Aptina’s MT9V034 is chosen as the
image sensor. It is a 1/3-Inch wide-VGA CMOS digital
image sensor with the 10-bit On-chip ADC and high
dynamic range. The active imager size is 4.51mm(H) *
2.88mm(v), with 5.35mm diagonal. The pixel size is
6.0*6.0um which provides a deep well depth[4]. The chip
can work on a high frame rate of up to 60 fps at full
resolution. The system is working on progressive scan
readout modes, and it can operate in a wide temperature
range (-30°C to +70°C) [4].
Fig. 2 is the block diagram of MT9V034. The sensor is
composed of active-pixel sensor array, analog processing,
ADCs, Control register for sdata/sclk to control the chip,
timing and control, and digital processing for parallel video
data out.
The quantum efficiency value indicates the amount of
current that the pixel will produce when irradiated by
photons of a particular wavelength. In order to achieve
higher quantum efficiency, we choose the monochrome chip
391
[4]. This system can achieve the quantum efficiency as high
as 50% at the wavelength of 550nm to 700nm, which is a
good parameter for the iris recognition system. we can see
that from Fig. 3.
Figure 2. Block diagram of MT9V034.
Figure 3. Monochrome quantum efficiency.
The image sensor can work in master, snapshot, or slave
mode. This system works in the master mode when the
sensor generates the readout timing. The integration time can
be programmed through the two-wire serial interface.[4] In
the simultaneous master mode, the exposure time is decided
by the sensor itself during the readout time. Fig. 4 show the
waveforms of the three signals when the readout
time >exposure time.
Figure 4. Master mode synchronization waveforms.
The data output of the MT9V034 is synchronized with
the PIXCLK output. When the LINE_VALID goes high,
every 10bit pixel data is transferred to the output port at the
falling edge of the PIXCLK edge. Fig. 5 shows the pixel
readout timing.
392
Figure 5. Pixel readout timing.
The image sensor is designed with a separate interface
board to connect to the OMAPL38 board. In order to reduce
the readout noise, serpentine line is designed to send the
control signals and 10bit data to the OMAPL38 board. Fig. 6
is the interface board schematic design, with the power
supply of 3.3V.
Figure 6. Interface circuits design.
B. VPIF Control
The core processor of the system is the OMAPL38 which
has multiple on/off chip memories and some external device
interfaces. In this system, ARM is used to receive the image
data and display it. The configuration for the ARM internal
memory is 8kB local RAM, 64kB local ROM, 16kB
instruction Cache and 16kB Data cache, which is only
accessible by ARM [3]. The DSP side is left to process the
captured image data. The shared on-chip RAM Memory is
128KB which can be accessible not only by the ARM and
DSP, but also several master peripherals.
The VPIF in the chip can support ITU-BT.656 format,
VBI data storage, Clipping of output data, Raw data
capture[3]. It can accept up to 16bit parallel data. The VPIF
module has two input channels and two output channels.
Each channel has 1 clock input and the clock edge can be
controlled by the CLKEDGE bit in the channel n control
register. And it can provide output clock for the external
device. So the image sensor can be connected to the input
channel and the LCD can be connected to the output
channel[5].
Table I and Table II describe the pin assignment on the
VPIF for receiving image data and the data transmitted to the
LCD. Table I is the receive pin arrangement. Shadowed
raw_v_valid can be connected to VSINC for the frame signal,
and raw_h_valid can be connected to line signal for the line
data transmission.
In this system, the ADC is 10bit. DIN[9]..DIN[0] are
connect to the parallel output of the sensor. The data is read
and saved directly by the processor. DOUT[15]..DIN[0] are
connected to LCD for display.
 TABLE I. RECEIVE PIN ARRANGEMENT terms of security and reliability. Moreover, its kernel source
code is open. Users can develop an embedded operating
system that meets their own requirements [8].
An efficient driver can support the stability of the whole
system. Fig. 9 is the software structure [5].

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TABLE II. OUTPUT PIN ARRANGEMENT

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In this system, a 7.0 inch, 800×480 TFT LCD is chosen ,PDJH6HQVRU

for the image display. The active area is 152.4mm(W) ×
91.44mm(H) [4]. The panel power consumption is about
0.825w. Fig. 7 is the input vertical timing. Figure 9. Software structure.

The driver and the capture structure are based on V4L2.

It is a collection of device drivers and API for supporting of
video capture on Linux systems. It supports many kinds of
optical sensors, USB webcams, TV tuners, and so on. The
driver is compiled in the Linux system and the video device
is as the /dev/video0, which can be read and write by the
Figure 7. Input vertical timing.
users just like the ordinary file.
A. Image Sensor Driver Design
The mt9v034 Linux 3.3 driver is based on I2C,
VIDEO_V4L2, VIDEO_V4L2_SUBDEV_API. The main
work is to set the register and read data from it through I2C.
Each device in the system has it unique ID. The device driver
will be automatically loaded when the system is powered on.
The function design includes the following functions in
Table III.

TABLE III. FUNCTION FOR THE SENSOR

Function Notes
Mt9v034_read Read data from the register
Mt9v034_write Write data to set the register
Mt9v034_power_on Reset and acquire the data
Mt9v034_power_off Stop the output data
Mt9v034_s_stram Column/row/window_width…
Mt9v034_set_format Set the output data format
Mt9v034_set_crop Clamp the crop rectangle
Mt9v034_registered Register the device to the OS
Mt9v034_subdev_core_op Interface for the V4L2
s
Figure 8. LCD VPIF interface.

III. SYSTEM SOFTWARE DESIGN

This system is based on embedded operating
system(EOS). There are kinds of EOS system, like Windows
CE, Palm OS, LynxOS, pSOS, VxWorks. Compared with
other kinds of operating system, Linux OS is excellent in Figure 10. Mt9v034’s driver registered by Linux 3.3.

393
 After the system being turned on, the U-Boot, image and
hardware/software information will be printed on the screen.
Fig. 10 is the device mt9v034 which is registered and
installed by the OS.
B. Application for Image Acquisition and Display
A complete image acquisition and display includes
several parts: open the device, initiate the device, get the
ability of the device, set the video format, request for buffers,
memory mapping, put the buffers into the queen, start
capture, get captured buffer, put a vane buffer to the buffer
line, stop capture, release capture data. Fig. 11 is the flow
chart.
frame rate CMOS image sensor, the system can reach a
frame rate of 60 fps with a 752 × 480 image format.
Compared with the traditional iris image capturing system,
this system improves the resolution from 8bit to 10bit [7], [8],
and the peak quantum efficiency exceeds 50%. The dual-
core processor OMAPL38 provides more possibility for the
iris recognition development. The ARM+DSP architecture,
provides an low power and accurate platform for iris image
processing [9], [10]. In the next step, we will add iris codes
matching algorithm to the DSP to test the performance of
data processing.

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Figure 11. Flow chart of the capture and display application.

Parameters setting for the test:

1. Max Buffer for captured image: 4
2. Image sensor ID: /dev/video0
3. Initial mode:0_RDWR
4. Pixel format: V4L2_PIX_FMT_STRBG10

Figure 13. Image capture and dispay system.

Figure 12. Lens used in the system.
Fig. 12 is a 3MP, M12, F1.4, 1/2.7’’ lens used in the
system, and Fig. 13 is the image capture and display system.
Compared with other similar system, The advantage of this
one: ADC resolution (10bit), quantum efficiency (≥50%)ˈ
frame rate 60fps (27Mp/s).
IV. CONCLUSION
This program has designed a high-sensitive image
acquisition and display system. With the use of the high
ACKNOWLEDGMENT
This research was funded by the Intelligent Sensor
Network Foundation of Jiangsu (grant No. ZK14-04-01) and
the Research Fund of Nanjing Institute of Industry
Technology (grant No. YK15-04-07).
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Multi-patch deep sparse histograms for iris recognition in visible
spectrum using collaborative subspace for robust verification. Pattern
Recognition Letter, 2017, 91:27-36.
[3] Texas Instruments. OMAPL38 C6000 DSP+ARM Processor
Technical Reference Manual (Rev.A). America: Texas Instruments,
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394
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